CN102386188B - Memory architecture of 3D array with diode in memory string - Google Patents
Memory architecture of 3D array with diode in memory string Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The invention discloses a memory architecture of a 3D array with a diode in a memory string. The 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
Description
Technical field
The invention relates to high density memory Set, particularly about the storage device with multilayer planar memory cell so that cubical array to be provided.
Background technology
The critical dimension of the device in integrated circuit is during to the limit of common memory cell technologies, designer then the multiple lamination planar technique of seeking memory cell to reach higher storage density, and each lower cost.For example, thin-film transistor technologies has been applied among charge capturing memory, can consult the paper " A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory " as Lai Dengren, IEEE Int ' l Electron Device Meeting, on December 11st～13,2006; And the people's such as Jung paper " Three Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm Node ", IEEE Int ' l Electron Device Meeting, on December 11st～13,2006.
In addition, plotted point array technique has also been applied among anti-fuse memory, can consult as the people's such as Johnson paper " 512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells ", IEEE J.of Solid-state Circuits, vol.38, no.11, in November, 2003.In the described design of the people such as Johnson, multilayer word line and bit line are used, and it has memory element in plotted point.This memory element comprises p+ polysilicon anode and is connected with word line, and n+ polysilicon negative electrode is connected with bit line, and by anti-fuse materials, is separated between negative electrode and positive electrode.
By relying, Jung, etc. in the described technique of people, each accumulation layer is used the crucial lithography step of multiple tracks.Therefore, manufacturing this number that installs required crucial lithography step can be its multiple that uses accumulation layer number.Therefore, though can reach higher density by use cubical array, higher manufacturing cost has also limited the scope of application of this technology.
The another kind of technology of vertical NAND gate memory cell structure in charge capturing memory of using is also at the people's such as Tanaka paper " Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory ", 2007Symposium on VLSI Technology Digest of Technical Papers, pp.14～15, on June 12nd～14,2007, describe to some extent.In the structure of describing in people such as Tanaka, comprise multiple-grid utmost point field effect transistor structure, the vertical channel that it has similar NAND gate operation, is used silica nitrogen-oxygen-silicon (SONOS) kenel charge capturing storage unit structure, to produce storage location at each grid/vertical channel interface.This storage organization is as the columnar semiconductor material of vertical channel, to form many gate memory cells based on arranging, and has a lower selection grid near substrate, and higher selection grid side thereon.It is to use the plane electrode layer crossing with column and form that a plurality of levels are controlled grids.The plane electrode layer of controlling grid as level does not need crucial photoetching, and therefore saves cost.Yet each vertical memory cell is still and needs many crucial lithography steps.In addition, the number of controlling grid in the sandwich construction of the method is still restriction to some extent, and it is to be decided by factors such as the programming such as being vertical channel conductivity, using and erase operations.
Therefore need to provide a kind of three dimensional integrated circuits memory construction of low manufacturing cost, it comprises reliably, very little memory element.
Summary of the invention
Technology described herein is a kind of storage device, comprises an ic substrate, a plurality of rectangular semi-conducting material laminations, many word lines, memory element and diodes.These a plurality of rectangular semi-conducting material laminations extend this ic substrate, and the plurality of lamination has ridge shape and comprises that at least two rectangular semi-conducting materials are separated as the Different Plane position in a plurality of plan position approachs by insulating barrier.These many word lines are arranged to and are orthogonal on the plurality of lamination, and with the plurality of lamination along shape, the intersection region of so setting up a cubical array in surface and this many word line plotted points of the plurality of lamination.This memory element is in this intersection region, and it sets up the memory cell of accessible this cubical array via this rectangular semi-conducting material and this many word lines, and this memory element is arranged to serial between bit line structure and source electrode line.This diode and this serial couple, and are between memory cell serial and bit line structure and source electrode line wherein between one.
In certain embodiments, this serial right and wrong door serial.
In certain embodiments, the combination of the particular word line in the particular source polar curve in the specific bit line in this bit line structure, this source electrode and this many word lines is selected, and can pick out the particular memory location in the memory cell of this cubical array.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this bit line structure.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this source electrode line.
Some embodiment comprises a serial selection line and ground connection selection line.This serial selection line is arranged to and is orthogonal on the plurality of lamination, and with the plurality of lamination along shape, so in surface and this serial selection line plotted point of the plurality of lamination, set up serial choice device.This ground connection is selected line to be arranged to be orthogonal on the plurality of lamination, and with the plurality of lamination along shape, so in the surface of the plurality of lamination, set up grounding selection device with this ground connection selection line plotted point.
In certain embodiments, this diode is coupled between this serial choice device and this bit line structure.In certain embodiments, this diode is coupled between this grounding selection device and this source electrode line.
In certain embodiments, the memory element in this intersection region comprises respectively a tunnel layer, an electric charge capture layer and a barrier layer.
In certain embodiments, this rectangular semi-conducting material comprises N-shaped silicon and this diode comprises a p-type region in this rectangular semi-conducting material.In certain embodiments, this rectangular semi-conducting material comprises N-shaped silicon and this diode comprises a p-type embolism contacts with this rectangular semi-conducting material.
Some embodiment comprises that logic do not choose the diode in serial to apply reverse biased to this memory cell in programming during this memory cell.
Another object of the present invention is for providing a kind of storage device, and the memory cell that comprises an ic substrate and a cubical array is in this ic substrate.The lamination that this cubical array comprises NAND gate serial memory cell; And diode and this serial couple, be between memory cell serial and bit line structure and source electrode line wherein between one.
In some embodiment, the combination of the particular word line in the particular source polar curve in the specific bit line in this bit line structure, this source electrode and this many word lines is selected, and can pick out the particular memory location in the memory cell of this cubical array.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this bit line structure.In certain embodiments, this diode and this serial couple, and are between memory cell serial and this source electrode line.
Some embodiment comprises that a serial choice device is between this bit line structure and this memory cell serial; And one grounding selection device between this source electrode line and this memory cell serial.
In certain embodiments, this diode is coupled between this serial choice device and this bit line structure.In certain embodiments, this diode is coupled between this grounding selection device and this source electrode line.
In certain embodiments, the charge-trapping structure in this intersection region comprises respectively a tunnel layer, an electric charge capture layer and a barrier layer.
A further object of the present invention is for providing a kind of method that operates three-dimensional NAND gate flash memory.Its step comprises and applies a programming and adjust bias voltage sequence to this three-dimensional NAND gate flash memory, and this cubical array comprises diode and this serial couples, and making this diode is between memory cell serial and bit line structure and source electrode line structure wherein between one.
One or more serial of not choosing is recharged, and wherein this is not chosen serial and does not comprise soon the memory cell of being adjusted bias voltage programming by this programming.In different embodiment, this charging is to carry out from source electrode line structure or from bit line structure.In different embodiment, this charging is via diode or via diode, does not carry out.This bit line structure and source electrode line structure are not chosen to serial and comprised soon one or more one choose serial and remove and couple of being adjusted the memory cell of bias voltage programming by this programming from this.Program voltage will be applied to this and will not choose serial and this chooses serial via being about to be adjusted one or more word line of the memory cell that bias voltage programme by this programming.
This memory element is arranged to serial between bit line structure is together with source electrode line, and comprises that diode and this serial couple, and is between the memory cell serial of serial separately and bit line structure and source electrode line wherein between one.First selects grid (for example grid SSL is selected in serial) can be coupled between corresponding bit line structure and this memory cell serial, and second selects grid (for example ground connection is selected grid G SL) can be coupled between corresponding common source line and this memory cell serial.This diode can couple between the first selection grid bit line structure corresponding with this.This diode can couple between the second selection grid common source line corresponding with this.
This three-dimensional memory devices comprises a plurality of ridge shape laminations, and it is to be separated by insulating barrier by a plurality of rectangular semi-conducting materials, is arranged to serial herein in described example, and it can couple with sensing amplifier via decoding circuit.The plurality of rectangular semi-conducting material has side surface in the side of the plurality of lamination.In this example, these the many wires as word line can couple with column decoder, are arranged to and are orthogonal on the plurality of lamination.This wire has and the surface (for example basal surface) of the plurality of lamination along shape.So along the surperficial configuration of shape, cause setting up at the side surface with this rectangular semi-conducting material and many wire plotted points the intersection region of a multilayer.This memory element is placed in the side surface of rectangular semi-conducting material and the intersection region between wire.Memory element is programmable, is similar to programmable resistance structure or charge-trapping structure described in following examples.This in lamination in specific intersection region is along a lamination that constitutes memory cell of shape wire, memory element and this rectangular semi-conducting material.The result of this array structure can provide the memory cell of this cubical array.
These a plurality of ridge shape laminations and many wires are to utilize self-aligning mode to form memory cell.For example, rectangular semi-conducting material in a plurality of ridge shape laminations can be used single etching mask definition, cause forming staggered raceway groove, it can be that the side surface of the rectangular semi-conducting material in relatively dark and lamination is vertically or with the side that forms the ridge inclination of raceway groove to aim at.This memory element can be used one or more layers material being comprehensively deposited on lamination to form, and uses other technique that does not need critical alignment step to form.In addition, many wires can utilize direct motion to be deposited on one or more layers material as memory element, use afterwards this single etching mask to define the etching technics of wire again.Consequently, only use an alignment procedures to define the rectangular semi-conducting material in lamination, and an alignment procedures define many wires.
In addition, a kind of three-dimensional of energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) technology, NAND gate flash structures of burying passage, nothing knot of being based on also described herein.
To three-dimensional perpendicular grid NAND gate quick flashing, design provides a kind of very efficient array decoded mode in the present invention.Its crystallite dimension goes in current floating grid NAND gate quick flashing design and density can be extended to megabit.
Also to super-high density, three-dimensional NAND gate quick flashing design provides a kind of feasible circuit design framework in the present invention.
Object of the present invention, feature, and embodiment, graphic being described of can arranging in pairs or groups in the chapters and sections of following execution mode.
Accompanying drawing explanation
Fig. 1 shows the schematic diagram of a three-dimensional storage organization described herein, it comprises that a plurality of rectangular semi-conducting material planes are parallel with Y-axis and is arranged to a plurality of ridge shape laminations, one accumulation layer is in the side of rectangular semi-conducting material, and many have with its under a plurality of ridge shape laminations along the wire of the basal surface of shape.
Fig. 2 shows that the memory cell structure of Fig. 1 is at the profile along Z-X plane.
Fig. 3 shows that the memory cell structure of Fig. 1 is at the profile along Y-X plane.
Fig. 4 shows to have the schematic diagram that the anti-fuse of Fig. 1 structure is basic memory.
Fig. 5 shows the schematic diagram of a three-dimensional NAND gate flash structure described herein, it comprises that a plurality of rectangular semi-conducting material planes are parallel with Y-axis and is arranged to a plurality of ridge shape laminations, one charge-trapping accumulation layer is in the side of rectangular semi-conducting material, and many have with its under the wire of basal surface of a plurality of ridge shape lamination cisoids.
Fig. 6 shows that the memory cell structure of Fig. 5 is at the profile along Z-X plane.
Fig. 7 shows that the memory cell structure of Fig. 5 is at the profile along Y-X plane.
Fig. 8 shows the schematic diagram of the NAND gate flash memory with Fig. 5 and Figure 23 structure.
Fig. 9 shows the schematic diagram of the alternate embodiment of a three-dimensional NAND gate flash structure that is similar to Fig. 5, and wherein storage material layer removes between wire.
Figure 10 shows that the memory cell structure of Fig. 9 is at the profile along Z-X plane.
Figure 11 shows that the memory cell structure of Fig. 9 is at the profile along Y-X plane.
Figure 12 shows that enforcement manufacture is as the generalized section of the technique first stage of the storage device in Fig. 1, Fig. 5 and Fig. 9.
Figure 13 shows that enforcement manufacture is as the generalized section of the technique second stage of the storage device in Fig. 1, Fig. 5 and Fig. 9.
Figure 14 A shows that enforcement manufacture is as the generalized section of the technique phase III of the storage device in Fig. 1.
Figure 14 B shows that enforcement manufacture is as the generalized section of the technique phase III of the storage device in Fig. 5.
Figure 15 shows that enforcement manufacture is as the generalized section of the technique phase III of the storage device in Fig. 1, Fig. 5 and Fig. 9.
Figure 16 shows that enforcement manufacture is as the generalized section of the technique fourth stage of the storage device in Fig. 1, Fig. 5 and Fig. 9.
Figure 17 shows the fast schematic diagram in simplification side of integrated circuit according to an embodiment of the invention, and wherein integrated circuit comprises the three-dimensional programmable resistance read-only memory array with row, column and plane decoding circuit.
Figure 18 shows the fast schematic diagram in simplification side of integrated circuit according to another embodiment of the present invention, and wherein integrated circuit comprises the three-dimensional NAND gate flash array with row, column and plane decoding circuit.
Figure 19 is the tunnelling electron microscope picture of three-dimensional NAND gate flash array some.
Figure 20 shows in a three-dimensional NAND gate flash structure to have diode in the bit line structure of this serial and store the profile between serial.
Figure 21 shows in a three-dimensional NAND gate flash structure to have the schematic diagram of diode between the bit line structure of this serial and storage serial, and it shows two memory cell planes, and each plane has 6 charge capturing storage units and is arranged to NAND gate configuration.
Figure 22 shows the sequential schematic diagram of the programming operation that is similar to the array in Figure 20.
Figure 23 shows in a three-dimensional NAND gate flash structure to have diode in the bit line structure of this serial and store the profile when carrying out read operation between serial.
Figure 24 shows in a three-dimensional NAND gate flash structure to have diode in the bit line structure of this serial and store the profile when carrying out programming operation between serial.
Figure 25 shows in a three-dimensional NAND gate flash structure to have the schematic diagram of diode between the bit line structure of this serial and storage serial, and it is to use polysilicon plug as diode.
Figure 26 shows in a three-dimensional NAND gate flash structure to have diode in the source electrode line structure of this serial and store the profile between serial.
Figure 27 shows in a three-dimensional NAND gate flash structure to have the schematic diagram of diode between the source electrode line structure of this serial and storage serial, and it shows two memory cell planes.
Figure 28 is shown in the sequential schematic diagram of the first example of the programming operation of the array in Figure 21.
Figure 29 is shown in the sequential schematic diagram of the second example of the programming operation of the array in Figure 21.
Figure 30 is shown in the sequential schematic diagram of another example of the programming operation of the array in Figure 21.
Figure 31 shows a schematic diagram that is similar to the three-dimensional NAND gate flash structure in Figure 27, shows that this serial comprises that diode is formed between source electrode line structure and storage serial in this icon.
Figure 32 is shown in the sequential schematic diagram of an example of the programming operation of the array in Figure 31.
Figure 33 A and Figure 33 B are the photograph of the tunnelling electron microscope of three-dimensional NAND gate flash memory some.
Figure 34 is current/voltage (IV) performance plot of the polysilicon diode of experiment measuring.
Figure 35 is the reading current performance plot of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
Figure 36 is the programming suppression characteristic figure of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
Figure 37 be experiment measuring the polysilicon diode being connected with three-dimensional NAND gate memory source electrode bias effect for programming interference effect.
Figure 38 be experiment measuring the polysilicon diode being connected with three-dimensional NAND gate memory turn-on grid electrode voltage effects for programming interference effect.
Figure 39 is the block erase switching current schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
Figure 40 is programming and the erase status current-voltage characteristic schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring, and this memory has different number mark program/erase cycle.
Figure 41 is the critical voltage distribution schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring, and this memory has the program/erase memory cell that check table distributes.
[main element symbol description]
10,110: insulating barrier
11～14,111～114: rectangular semi-conducting material
15,115: storage medium
16,17,116,117: wire
18,19,118,119: metal silicide
20,120: raceway groove
21～24,121～124: insulating material
25,26,125,126: active area
30～35,40～45,70～78,80,82,84: memory cell
51～56: rectangular semi-conducting material lamination
60 (60-1,60-2,60-3), 61,160～162: word line
86,87: source electrode line
90～95: zone-block selected transistor
97,397: tunnel dielectric layer
98,398: electric charge storage layer
99,399: stop dielectric layer
83: serial selection line
85,88,89: string row selecting transistor
106,107,108: bit line
128,129,130: source/drain region
210,212,214: insulating barrier
211,213: semiconductor
215: storage material layer
250: ridge shape lamination
315: electric charge capture layer
225: wire
226,1426: metal silicide
875,975: integrated circuit
860: there is the three-dimensional programmable resistance read-only memory array of diode in storage serial
960: have the three-dimensional NAND gate flash array of diode in storage serial
858,958: plane decoder
859,959: serial selection line
861,961: column decoder
862,962: word line
863,963: row decoder
864,964: bit line
865,965,867,967: bus
866,966: sensing amplifier/data input structure
874,974: other circuit
869,969: state machine
868,968: bias voltage adjustment supply voltage
871,971: Data In-Line
872,972: DOL Data Output Line
410,1410: substrate
1412～1414: rectangular semi-conducting material
1415,1515: region
1425-1 is to 1425-n: wire
1427: serial selection line SSL
1428: whole source electrode line GSL
1449:P+ injection zone
1450,1451,1550,1551: embolism
1491: electric conducting material
1492,1592: diode
1106: serial selection line
1110～1113: diode
1160～1162: wire
1170～1175,1180,1182: memory cell
1190,1191: ground connection is selected transistor
1196,1197: string row selecting transistor
Embodiment
It is that collocation Fig. 1 describes to Figure 41 that embodiment below the present invention describes.
Fig. 1 shows the schematic diagram of 2 * 2 memory cell parts of a three-dimensional programmable resistance storage array, in the drawings packing material is omitted clearly to represent to form the lamination of rectangular semi-conducting material and the wire of quadrature of this cubical array.In this is graphic, only show two planes.Yet the number of plane can extend to very large number.As shown in fig. 1, this storage array is formed at and has on the semiconductor or the ic substrate above other structure (not shown) of an insulating barrier 10 under it.This storage array comprises that the lamination 11,12,13,14 of a plurality of rectangular semi-conducting materials is each other by insulating material 21,22,23,24 separations.This lamination is that ridge shape and the Y direction in figure are extended, so rectangular semi-conducting material 11～14 can configuration be bit line, and extends substrate.The bit line that rectangular semi-conducting material 11,13 can be used as on the first memory plane, and the bit line that rectangular semi-conducting material 12,14 can be used as on the second memory plane.One deck storage medium 15, for example, be anti-fuse materials, is coated on rectangular semi-conducting material, and in other example, is at least formed at the sidewall of rectangular semi-conducting material in this example.Many wires 16,17 and these rectangular semi-conducting material lamination quadratures.Many wire 16,17 has and the surface of these rectangular semi-conducting material laminations along shape, and for example insert, by among the defined raceway groove of these laminations (20), and in the interface area of the definition of side surface plotted point part between rectangular semi-conducting material 11～14 laminations and many wires 16,17 multiple tier array.Layer of metal silicide (for example tungsten silicide, cobalt silicide, titanium silicide) 18,19 is formed at the upper surface of many wires 16,17.
Fig. 2 is presented at wire 16 and the profile of rectangular semi-conducting material 14 confluces along memory cell Z-X plane. Active area 25,26 forms the both sides of rectangular semi-conducting material 14 and between wire 16 and rectangular semi-conducting material 14.In nature, anti-fuse storage material layer 15 has high resistance.After programming, this anti-fuse storage medium collapse, causes one of active area 25,26 in anti-fuse storage medium or both to get back to a low resistance state.In described embodiment, each memory cell has the both sides that two active areas 25,26 form rectangular semi-conducting material 14 herein.Fig. 3 is presented at wire 16,17 and rectangular semi-conducting material 14 confluces along the profile of memory cell X-Y plane.In figure, show that the anti-fuse storage material layer 15 of word line process of arbitrary routing of line 16 definition is to the current path of rectangular semi-conducting material 14.
Electronics mobile is that the dotted line in Fig. 3 shows, from n+ wire 16, enter the rectangular semi-conducting material 14 of p-type, and along rectangular semi-conducting material 14 (dotted arrow) to sensing amplifier, at sensing amplifier place, can measure to indicate the state of selected memory cell.In an exemplary embodiments, be to use the silica of approximately 1 nanometer thickness as anti-fuse materials, and utilize chip inner control circuit in Figure 17 to apply to comprise 5～7 volts of pulses and pulse duration to be about the programming pulse of 1 microsecond.And read pulse, be to utilize chip inner control circuit in Figure 17 to apply to comprise 1～2 volt of pulse and the pulse duration relevant to configuration.This reads pulse can far be shorter than programming pulse.
Fig. 4 shows two memory cell planes, and each plane has six memory cell.These memory cell are indicated to represent by the diode with the anti-fuse materials layer (dotted line representative) between negative electrode and positive electrode.These two memory cell planes are by the wire 60 as the first word line WLn and the second word line WLn+1 and 61 and define first and second layers of this array as the first, second, and third rectangular semi-conducting material lamination 51,52,53,54 of bit line BLn, BLn+1 and BLn+2 and 55,56 confluces respectively.The first plane of memory cell is included in the memory cell 30,31 on rectangular semi-conducting material lamination 52, the memory cell 32,33 on rectangular semi-conducting material lamination 54 and the memory cell on rectangular semi-conducting material lamination 56 34,35.The second plane of memory cell is included in the memory cell 40,41 on rectangular semi-conducting material lamination 51, the memory cell 42,43 on rectangular semi-conducting material lamination 53 and the memory cell on rectangular semi-conducting material lamination 55 44,45.As shown in FIG., wire 60 is as word line WLn, and it comprises that vertically extending 60-1,60-2,60-3 are corresponding with the material in the raceway groove between between lamination in Fig. 1, so that wire 60 and the rectangular semi-conducting material lamination of 3 illustrations in each plane are coupled.An array may be embodied to as described herein has many layers, to form the very highdensity memory that approaches or arrive every chip megabit.
Fig. 5 shows the schematic diagram of 2 * 2 memory cell parts of a three-dimensional programmable resistance storage array, has in the drawings packing material clearly to represent and the lamination of rectangular semi-conducting material and the wire relativeness of quadrature that form this cubical array.In this is graphic, only show two-layer.Yet the number of level can extend to very large number.As shown in Figure 5, this storage array is formed at and has on the semiconductor or the ic substrate above other structure (not shown) of an insulating barrier 110 under it.This storage array comprises that the lamination 111,112,113,114 of a plurality of rectangular semi-conducting materials is each other by insulating material 121,122,123,124 separations.This lamination is that ridge shape and the Y direction in figure are extended, so rectangular semi-conducting material 111～114 can configuration be bit line, and extends substrate.The bit line that rectangular semi-conducting material 111,113 can be used as on the first memory plane, and the bit line that rectangular semi-conducting material 112,114 can be used as on the second memory plane.
In the first lamination between the insulating material 121 between rectangular semi-conducting material 111 and 112 and in the second lamination the insulating material 123 between rectangular semi-conducting material 113 and 114 there is the equivalent oxide thickness (EOT) that is more than or equal to approximately 40 nanometers, wherein equivalent oxide thickness (EOT) is that the thickness of this insulating material is multiplied by the oxidated layer thickness that the dielectric constant ratio of silica and insulating barrier is changed.Noun as used herein " approximately 40 nanometer " is the result of considering approximately 10% order of magnitude change in typical case's technique of installing like this.The thickness of this insulating barrier has important impact for reducing the interference between consecutive storage unit in this structure.In certain embodiments, the equivalent oxide thickness of insulating material (EOT) can minimum reach 30 nanometers and still can between adjacent layer, have enough isolation.
One deck storage medium 115, for example, be dielectric charge capturing structure, in this example, is coated on rectangular semi-conducting material.Many wires 116,117 and these rectangular semi-conducting material lamination quadratures.Many wire 116,117 has and the surface of these rectangular semi-conducting material laminations along shape, and for example insert, by among the defined raceway groove of these laminations (120), and in the interface area of the definition of side surface plotted point part between rectangular semi-conducting material 111～114 laminations and many wires 116,117 multiple tier array.Layer of metal silicide (for example tungsten silicide, cobalt silicide, titanium silicide) 118,119 is formed at the upper surface of many wires 116,117.
The metal oxide semiconductcor field effect transistor kenel of nano wire is by providing passage area on wire 111～114 of nano wire or nano tube structure and also being become this kind of mode by configuration, paper " Impact of a Process Variation on Nanowire and Nanotube Device Performance " as people such as Paul, IEEE Transactions on Electron Device, Vo1.54, No.9, on September 11st～13,2007, at this, be incorporated by reference data.
Therefore, can form the SONOS kenel memory cell that configuration is the cubical array of NAND gate flash array.Source electrode, drain electrode and tunnel-shaped are formed in the rectangular semi-conducting material 111～114 of silicon, and storage material layer 115 comprises the tunnel dielectric layer 97 of silica (O), the wire 116,117 that stops dielectric layer 99 and polysilicon (S) of the electric charge storage layer 98 of silicon nitride (N), silica (O).
Rectangular semi-conducting material 111～114 can be p-type semi-conducting material and wire 116,117 can be used identical or different semi-conducting material (for example p+ kenel).For example, rectangular semi-conducting material 111～114 can be p-type polysilicon, or p-type epitaxial monocrystalline silicon, and wire 116,117 can be used the p+ polysilicon of relatively dense doping.
Alternatively, rectangular semi-conducting material 111～114 can be N-shaped semi-conducting material and wire 116,117 can be used the semi-conducting material (for example p+ kenel) of identical or different conductivity.This N-shaped semi-conducting material arrangement causes the charge capturing storage unit of the vague and general kenel of bury-passage.For example, rectangular semi-conducting material 111～114 can be N-shaped polysilicon, or N-shaped epitaxial monocrystalline silicon, and wire 116,117 can be used the p+ polysilicon of relatively dense doping.The doping content of the rectangular semi-conducting material of typical case's N-shaped is about 10
18/ cm
3, can use the scope of embodiment greatly about 10
17/ cm
3to 10
19/ cm
3between.Use the rectangular semi-conducting material of N-shaped preferably to select for the embodiment without knot, because can improve along the conductance of NAND gate serial and therefore allow higher reading current.
Therefore this memory cell that, comprises field-effect transistor has in the cubical array structure that charge storing structure is formed at this plotted point.Use rectangular semi-conducting material and the conductor thickness of approximately 25 nanometer scale, and the spacing with ridge shape lamination is also approximately 25 nanometer scale, the device for example, with tens of layers (30 layers) can reach million (10 in single-chip
12) position capacity.
This storage material layer 115 can comprise other charge storing structure.For example, can use the SONOS charge storing structure of energy gap engineering (BE) to replace, it comprises dielectric tunnel layer 97, and when 0V bias voltage, has inverted U valence band between level.In one embodiment, this multilayer tunnel layer comprises that ground floor is called tunneled holes layer, and the second layer is called can be with layer of compensation and the 3rd layer to be called separator.In this embodiment, tunneled holes layer 97 comprises that silicon dioxide layer is formed at the side surface of rectangular semi-conducting material, it can utilize as on-site steam generation (in-situ steam generation, ISSG) method forms, and after optionally utilizing deposition, nitric oxide is annealed or in deposition process, adds nitric oxide production mode to carry out nitrogenize.The thickness of the silicon dioxide in ground floor is to be less than 20 dusts, and is preferably less than 15 dusts, is 10 or 12 dusts in an exemplary embodiment.
In this embodiment, can be with layer of compensation to comprise silicon nitride layer is to be positioned on tunneled holes layer, and it is that utilization similarly is the technology of low-pressure chemical vapor deposition LPCVD, at 680 ℃, use dichlorosilane (dichlorosilane, DCS) and the predecessor of ammonia to form.In other technique, can be with layer of compensation to comprise silicon oxynitride, it is to utilize similar technique and nitrous oxide predecessor to form.Can with the thickness of the silicon nitride layer in layer of compensation, be to be less than 30 dusts, and be preferably 25 dusts or less.
In this embodiment, it is to be positioned to be with on layer of compensation that separator comprises silicon dioxide layer, and it is that utilization similarly is that the mode that LPCVD high-temperature oxide HTO deposits forms.Silicon dioxide layer thickness in separator is to be less than 35 dusts, and is preferably 25 dusts or less.So three layers of tunnel dielectric layer have produced " fall U " the valence band energy rank of shape.
The valence band energy rank at the first place can make electric field be enough to bring out tunneled holes by the thin region between this first place and semiconductor body (or rectangular semi-conducting material) interface, and it is also enough to promote the valence band energy rank behind the first place, effectively to eliminate the tunneled holes phenomenon in the composite tunnel dielectric layer behind the first place.This kind of structure, except setting up this three layers of tunnel dielectric layer " fall U " valence band of shape, also can reach the auxiliary high speed tunneled holes of electric field, it also can not exist or only bring out the situation of little electric field for other operation object (similarly being from memory cell reading out data or the contiguous memory cell of programming) at electric field, effectively prevents charge loss to pass through through composite tunnel dielectric layer structure.
In a representational device, storage material layer 115 comprises energy gap engineering (BE) composite tunnel dielectric layer, the thickness of the silicon dioxide that it comprises ground floor is to be less than 2 nanometers, and the thickness of one deck silicon nitride layer is that the silicon dioxide layer thickness that is less than 3 nanometers and a second layer is to be less than 4 nanometers.In one embodiment; this composite tunnel dielectric layer comprises ultra-thin silicon oxide layer O1 (being for example less than or equal to 15 dusts), ultra-thin silicon nitride layer N1 (being for example less than or equal to 30 dusts) and ultra-thin silicon oxide layer O2 (being for example less than or equal to 35 dusts) forms; and it can, under 15 dust of starting at the interface of semiconductor body or rectangular semi-conducting material or less compensation, increase the valence band energy rank of approximately 2.6 electron-volts.By a region, low valence band energy rank (high hole tunneling barrier) and high conduction band energy rank, O2 layer can separate N1 layer and electric charge capture layer one second compensation (for example starting at approximately 30 dust to 45 dusts from interface).Because second place's distance interface is far away, the electric field that is enough to bring out tunneled holes can improve the valence band energy rank behind the second place, so that it eliminates tunneled holes potential barrier effectively.Therefore, O2 layer can't the auxiliary tunneled holes of severe jamming electric field, can promote again the ability that blocks charge loss through engineering tunnelling dielectric structure during at low electric field simultaneously.
The thickness that electric charge capture layer in storage material layer 115 comprises silicon nitride layer is in this embodiment to be greater than 50 dusts, comprises for example, and the silicon nitride of thickness approximately 70 dusts, and it is to utilize to form as LPCVD mode.The present invention also can use other charge-trapping material and structure, comprises similarly being silicon oxynitride (Si
xo
yn
z), the nitride of high silicon content is, the oxide of high silicon content comprises seizure layer of embedded nano particle etc.
The dielectric layer that stops in storage material layer 115 is silica in this embodiment, and its thickness is to be greater than 50 dusts, and is included in this embodiment Chinese style 90 dusts, and can use the wet furnace oxidation technique of silicon nitride being carried out to wet method conversion.The silica that can use in other embodiments high-temperature oxide (HTO) or LPCVD depositional mode to form.Also can use other the dielectric layer material that stops is for example the high-k material of aluminium oxide.
In an exemplary embodiment, the thickness of the silicon dioxide in tunneled holes layer is 13 dusts; Can with the silicon nitride layer thickness of layer of compensation, be 20 dusts; The silicon dioxide layer layer thickness of separator is 25 dusts; The silicon nitride layer thickness of electric charge capture layer is 70 dusts; And stop that dielectric layer can be the silica of thickness 90 dusts.The grid material of wire 116,117 can be p+ polysilicon (its work function is 5.1 electron-volts).
Fig. 6 is presented at the charge capturing storage unit of wire 116 and the 114 confluces formation of rectangular semi-conducting material along the profile of memory cell Z-X plane.Active area 125,126 forms the both sides of rectangular semi-conducting material 114 between wire 116 and rectangular semi-conducting material 114.In the described embodiment of Fig. 6, each memory cell is that double gate field-effect transistor has the both sides that two active areas 125,126 form rectangular semi-conducting material 114.
Fig. 7 is presented at the charge capturing storage unit of wire 116 and the 114 confluces formation of rectangular semi-conducting material along the profile of memory cell X-Y plane.In figure, also show the current path that flow to rectangular semi-conducting material 114.Flowing as shown in phantom in FIG. of electronics, is to flow to sensing amplifier along the rectangular semi-conducting material of p-type, and it can measure to indicate the state of selected memory cell.Source/drain region 128,129,130 between the wire 116,117 as word line can be " without knot ", and namely the dopant profile of source/drain electrode does not need different from the dopant profile of passage area under word line.In the embodiment of this " without knot ", charge-trapping field-effect transistor can have p-type channel design.In addition, in certain embodiments, the mode that the doping of source/drain electrode can utilize auto-alignment to inject after defined word line forms.
In alternate embodiment, rectangular semi-conducting material 111～114 can be used shallow Doped n-type semiconductor body in the arrangement of " without knot ", cause forming the bury-channel field effect transistor that can operate under depletion-mode, this charge capturing storage unit has nature and is offset to lower critical voltage distribution.
Fig. 8 shows two memory cell planes, and each plane has 9 charge capturing storage units and is arranged to NAND gate configuration, and it is the illustration that represents of a square, can comprise many planes and many word lines.These two memory cell planes are by the wire 160,161 and 162 as word line WLn-1, WLn and WLn+1, and it is respectively first, second, and third rectangular semi-conducting material lamination.
The first plane of memory cell comprises that memory cell 70,71 and 72 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination, and memory cell 73,74 and 75 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination, and memory cell 76,77 and 78 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination.In this illustration, the second plane of memory cell is corresponding with cubical baseplane, and comprises that the mode that memory cell (for example 80,82 and 84) utilization is similar to the first plane is arranged in NAND gate serial.
As shown in FIG., wire 161 as word line WLn comprises that vertical stretch divides, it is corresponding with the interior material of the raceway groove between lamination 120 in Fig. 5, for example, so that the memory cell of the interface area in the raceway groove between between rectangular semi-conducting material in wire 161 and all planes (in the first plane 71,74 and 77 of memory cell) is coupled.
Bit line and source electrode line are the opposite ends that is positioned at this storage serial.Bit line 106,107 and 108 controls by bit line signal BLn-1, BLn and BLn+1 are connected to the different laminations in storage serial.The NAND gate serial of the source electrode line 86 termination poincare half planes of being controlled by signal SLn in this arranges.The NAND gate serial of the source electrode line 87 termination lower half-planes of being controlled by signal SLn+1 in this arranges similarly.
In this arranges, string row selecting transistor 85,88 and 89 connects between NAND gate serial and bit line BLn-1, BLn and BLn+1 separately.Serial selection line 83 and word line parallel.
In this arranges, zone-block selected transistor 90～95 couples one of NAND gate serial and source electrode line.In this example, ground connection selects line GSL to be connected with zone-block selected transistor 90～95, and can use the mode that is similar to wire 160,161 and 162 to implement.In certain embodiments, this string row selecting transistor and zone-block selected transistor can be used the dielectric lamination identical with gate oxide in memory cell.In other embodiments, can replace with typical gate oxide.In addition, passage length and width can be depending on the needs of design and the handoff functionality that provides these transistors suitable are provided.
Fig. 9 shows an alternative structure schematic diagram that is similar to Fig. 5, uses in the drawings identical reference number, and no longer described in similar structures.The part that Fig. 9 is different from Fig. 5 is that the surperficial 110A of insulating barrier 110 and side surface 113A, the 114A of rectangular semi-conducting material 113,114 are for example, out exposed between the wire as word line (160) after etching forms word line.Therefore, storage material layer 115 etching and can not have influence on operation wholly or in part between word line.Yet, in some structure, do not need general etching as described herein to form dielectric charge capturing structure by storage material layer 115.
Figure 10 shows that the memory cell of similar Fig. 6 is along the profile of Z-X plane.Figure 10 is identical with Fig. 6, shows the structure in Fig. 9 memory cell, and the profile of the structure of implementing with Fig. 5 in this profile is identical.Figure 11 shows that the memory cell of similar Fig. 7 is along the profile of X-Y plane.The part that Figure 11 is different from Fig. 7 is for example, to be removed along region 128a, the 129a of the side surface of rectangular semi-conducting material 114 (114A) and the storage medium in 130a.
Figure 12 shows the basic technology stage flow chart of implementing three-dimensional storage array as described herein to Figure 16, it only uses 2 pair arrays to form the pattern mask step of aiming at very crucial impact.In Figure 12, show intertonguing insulating barrier 210,212,214 and semiconductor layer 211,213 structure afterwards, for example semiconductor layer can be used the doped semiconductor of comprehensive deposition to be formed at the array region of chip.According to the difference of embodiment, semiconductor layer can be used polysilicon or the epitaxial monocrystalline silicon with N-shaped or p-type doping.Interlayer insulating film 210,212,214 can for example be used silicon dioxide, other silica or silicon nitride.These layers can be used many different modes to form, and comprise the technology such as low-pressure chemical vapor deposition (LPCVD) that industry is known.
Figure 13 shows the result of the first lithographic patterning step, and it is used for defining the rectangular semi-conducting material lamination 250 of a plurality of ridge shapes, and wherein this rectangular semi-conducting material is formed and separated by insulating barrier 210,212,214 by semiconductor layer 211,213.The raceway groove with very dark and very high depth-to-width ratio can be formed at multilayer laminated between, it is to use to be lithographically basic technique and to apply carbon containing hard mask and reaction equation ion etching.
Figure 14 A and Figure 14 B show respectively and comprise to be for example the programmable resistance storage organization of anti-fuse storage unit structure and to comprise it being for example the profile in next stage in the charge-trapping storage organization embodiment able to programme of silica nitrogen-oxygen-silicon (SONOS) kenel memory cell structure.
Figure 14 A shows that the programmable resistance storage organization embodiment that comprises single-layer back fuse storage unit structure as shown in Figure 1 deposits the result after a storage medium 215 comprehensively.Alternatively, can carry out oxidation technology and do not use comprehensive deposition to form oxide in the exposed side of rectangular semi-conducting material, wherein oxide is as storage medium.
Figure 14 B shows that the programmable resistance storage organization embodiment that comprises multilayer charge-trapping structure as shown in Figure 4 deposits the result after a storage medium 315 comprehensively, and this multilayer charge-trapping structure comprises a tunnel layer 397, an electric charge capture layer 398 and a barrier layer 399.As shown in Figure 14 A and Figure 14 B, storage material layer the 235, the 315th, utilizes along shape mode and is deposited on the rectangular semi-conducting material lamination (250 in Figure 13) of ridge shape.
Figure 15 shows the result after electric conducting material filling high-aspect-ratio raceway groove step, and this electric conducting material can be for example to have N-shaped or p-type doping, is used as the wire of word line, is deposited to form layer 225.In addition,, in using the embodiment of polysilicon, one deck silicide 226 is formed on layer 225.As shown in FIG., the high-aspect-ratio deposition techniques such as polysilicon such as low-pressure chemical vapor deposition (LPCVD) are used to fill the raceway groove between between ridge shape lamination in this embodiment, and even the 10 nanometer scale raceway grooves very narrow with high-aspect-ratio are also feasible.
Figure 16 figure shows the result of the second lithographic patterning step, and it is used for defining in this three-dimensional storage array the many wires 260 as word line.This second lithographic patterning step is used single mask to define the critical dimension of etching high-aspect-ratio raceway groove between between wire in this array, and do not need to execute, does not carve by the lamination of ridge shape.Polysilicon can carry out etching with the etching technics having polysilicon and silica or silicon nitride high selectivity.Therefore, alternatively etching technics can carry out by the use mask identical with etching semiconductor and insulating barrier, and this technique can stop at bottom insulation layer 210.
One optionally processing step comprise and form hard mask on many wires, these wires comprise that word line, ground connection selects line and serial selection line.The material that this hard mask can be used relatively thick nitride or other can blocks ions to inject forms.After hard mask forms, can carry out Implantation to increase the doping content in rectangular semi-conducting material, and therefore reduce along the resistance on rectangular semi-conducting material current path.By use, control Implantation Energy, injection can cause through the rectangular semi-conducting material in the end, and each in lamination above rectangular semi-conducting material.
Afterwards, remove hard mask the silicide of many wires top is out exposed.After an interlayer dielectric layer is formed at array top, interlayer hole is formed and for example uses the embolism of tungsten to be filled in wherein.Upper metal line as bit line BL is patterned and is connected with decoding circuit.A three-dimensional decoding circuit is set up in the mode in scheming, and with a word line, a bit line and one source pole line, comes access one to choose memory cell.Can consult title for No. 6906940th, the United States Patent (USP) of " Plane Decoding Method and Device for Three Dimensional Memories ".
For the selected negate fuse-type state memory cell of programming, selected be biased to-7V of word line in this embodiment, do not choose word line and can be set as 0V, selected bit line also can be set as 0V, do not choose bit line and can be set as 0V, can be set as-3.3V of selected source electrode line, can not be set as 0V and choose source electrode line.In order to read a selected memory cell, selected be biased to-1.5V of word line in this embodiment, do not choose word line and can be set as 0V, selected bit line also can be set as 0V, do not choose bit line and can be set as 0V, selected can be set as-3.3V of source electrode line SL, can not be set as 0V and choose source electrode line.
Figure 17 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 875 comprises using to have three-dimensional programmable resistance read-only memory described herein (RRAM) array 860 on semiconductor substrate.One column decoder 861 couples and electrically links up with the many word lines 862 along storage array 860 column direction arrangements.Row decoder 863 and the multiple bit lines 864 arranging along storage array 860 line directions (or before described serial selection line) electrically ditch pass to the memory cell from array 860 are read and programming data operation.One plane decoder 858 therewith in array 860 planes before described source serial selection line 859 (or before described bit line) couple.Address is to offer row decoder 863, column decoder 861 and plane decoder 858 by bus 865.Sensing amplifier in square 866 and data input structure couple via data/address bus 867 and row decoder 863.Data offer Data In-Line 871 by the input/output end port on integrated circuit 875, or by the data source of integrated circuit 875 other inner/outer, input to the data input structure in square 866.Within other circuit 874 is contained in integrated circuit 875, for example general with object processor or specific purposes application circuit, or module combines to provide the system single chip of being supported by programmable resistance memory cell array function.The sensing amplifier of data in square 866, via DOL Data Output Line 872, provides to integrated circuit 875, or provides to other data terminal of integrated circuit 875 inner/outer.
The controller that used is in the present embodiment to have used bias voltage to adjust state machine 869, and has controlled by voltage source of supply or square 868 and produce or the application of the bias voltage adjustment supply voltage that provides, for example, read and program voltage.This controller can utilize specific purposes logical circuit and apply, as well known to the skilled person.In alternate embodiment, this controller has comprised general object processor, and it can make in same integrated circuit, the operation of control device to carry out a computer program.In another embodiment, this controller is to be combined by specific purposes logical circuit and general object processor.
Figure 18 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 975 comprises using to have three-dimensional NAND gate flash array array 960 described herein on semiconductor substrate.One column decoder 961 couples and electrically links up with the many word lines 962 along storage array 960 column direction arrangements.Row decoder 963 and the multiple bit lines 964 arranging along storage array 960 line directions (or before described serial selection line) electrically ditch pass to the memory cell from array 960 are read and programming data operation.One plane decoder 958 therewith in array 960 planes before described serial selection line 959 (or before described bit line) couple.Address is to offer row decoder 963, column decoder 961 and plane decoder 958 by bus 965.Sensing amplifier in square 966 and data input structure couple via data/address bus 967 and row decoder 963.Data offer Data In-Line 971 by the input/output end port on integrated circuit 975, or by the data source of integrated circuit 975 other inner/outer, input to the data input structure in square 966.In this illustrative embodiments, within other circuit 974 is contained in integrated circuit 975, for example general with object processor or specific purposes application circuit, or module combines to provide the system single chip of being supported by NAND gate flash array function.The sensing amplifier of data in square 966, via DOL Data Output Line 972, provides to integrated circuit 975, or provides to other data terminal of integrated circuit 975 inner/outer.
The controller that used is in the present embodiment to have used bias voltage to adjust state machine 969, and controlled by voltage source of supply or square 868 and produce or the application of the bias voltage adjustment supply voltage that provides, for example read, programme, wipe, erase verification and program verification voltage.This controller can utilize specific purposes logical circuit and apply, as well known to the skilled person.In alternate embodiment, this controller has comprised general object processor, and it can make in same integrated circuit, the operation of control device to carry out a computer program.In another embodiment, this controller is to be combined by specific purposes logical circuit and general object processor.
Figure 19 is the profile of the tunnelling electron microscope of 8 layers of vertical channel thin-film transistor energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) charge-trapping NAND gate device some, and it is into, and the mode of Fig. 8 and Figure 23 is manufactured, test and arrange decoding.This device is to utilize half spacing of 75 nanometers to form.Its passage is the N-shaped polysilicon of about 18 nanometer thickness.Do not carry out extra knot to inject and form without junction structure.Between semiconductor strips, being used for the insulating material of channel isolation is in Z-direction, and it is the silica that thickness is about 40 nanometers.The grid providing is P+ polysilicon lines.This serial selection and grounding selection device have the passage length longer compared with memory cell.This testing apparatus has the NAND gate serial of 32 word lines, nothing knot.Because the channel etching that shown in forming, structure is used has the shape of inclination, in the bottom of raceway groove, have apart from wide silicon line, and the insulating material between fine rule is etched manyly apart from polysilicon, so the width system of below fine rule is also wider than the width of top fine rule in Figure 19.
Figure 20 shows in an embodiment, to have the memory cell profile of diode (for example diode 1492) in this NAND gate serial semiconductor body.This structure comprises a plurality of ridge shape laminations, and it comprises that rectangular semi-conducting material 1414,1413,1412 is on the substrate of ridge shape lamination plane separately.Suitable shape many wire 1425-1 as word line passes through with lamination quadrature and extension to 1425-n (only showing two in figure for simplicity), and to be formed on accumulation layer as previously described.As the wire 1427 of serial selection line SSL and wire 1428 and other the line like this of source electrode line GSL are arranged to parallel with the many wires as word line as a whole.It is for example that the electric conducting material 1491 with N-shaped or p-type doped polycrystalline silicon forms that these wires can utilize, and for the wire that is used as word line, uses.Silicide layer 1426 can be formed on the many wires as word line, serial selection line SSL and whole source electrode line GSL.
In region 1415, rectangular semi-conducting material 1414,1413,1412 is connected with other the rectangular semi-conducting material in same level via whole source electrode line interconnect, and is connected with a plane decoder (not shown).Rectangular semi-conducting material be use before described ladder contact area and extending in whole source electrode line interconnect.
Diode (for example 1492) be positioned over the memory cell that is connected to 1425-n with wire 1425-1 and embolism 1450,1451 that bit line BLn and BLn+1 are connected with rectangular semi-conducting material 1414,1413,1412 between.In this example illustrated, diode is that P+ injection zone in rectangular semi-conducting material (for example 1449) forms.Embolism 1450,1451 can comprise doped polycrystalline silicon, tungsten or other vertical interior interconnection technique.Top bit line BLn and BLn+1 connect between embolism 1450,1451 and column decode circuitry (not shown).
In the structure shown in Figure 20, need to the serial in array not select grid and common source to select to form and contact on grid.
Figure 21 shows two memory cell planes, and each plane has 6 charge capturing storage units and is arranged to NAND gate configuration, and it is the illustration that represents of a square, can comprise many planes and many word lines.These two memory cell planes are by the wire 1160,1161 and 1162 as word line WLn-1, WLn and WLn+1, and it is respectively first, second, and third rectangular semi-conducting material lamination.
The first plane of memory cell comprises that memory cell 1170,1171 and 1172 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination, and memory cell 1173,1174 and 1175 is in a NAND gate serial, and be positioned on rectangular semi-conducting material lamination.In this illustration, the second plane of memory cell is corresponding with cubical baseplane, and comprises that the mode that memory cell (for example 1182 and 1184) utilization is similar to the first plane is arranged in NAND gate serial.
As shown in FIG., wire 1161 as word line WLn comprises that vertical stretch divides, it is corresponding with the interior material of the raceway groove between lamination 120 in Fig. 5, for example, so that the memory cell of the interface area in the raceway groove between between rectangular semi-conducting material in wire 1161 and all planes (in the first plane 1171,1174 of memory cell) is coupled.
String row selecting transistor 1196,1197 connects between NAND gate serial and bit line BL1 and BL2 separately.Similarly, in this arranges, the similar string row selecting transistor in this square baseplane connects between NAND gate serial and bit line BL1 and BL2 separately, makes row separate Code and puts on these bit lines.Serial selection line 1106 with string row selecting transistor 1196,1197 be connected, and with word line parallel, as shown in Figure 20.
In this example, diode 1110,1111,1112,1113 is connected between this serial and corresponding bit line.
Ground connection selects transistor 1190,1191 be arranged in the opposite side in this NAND gate serial and be used for coupling at this NAND gate serial and a common source reference line of choosing in layer.This common source reference line is the plane decoder for decoding in structure thus.Ground connection selects line GSL can use the mode that is similar to wire 1160,1161 and 1162 to implement.In certain embodiments, this string row selecting transistor and ground connection select transistor can use the dielectric lamination identical with gate oxide in memory cell.In other embodiments, can replace with typical gate oxide.In addition, passage length and width can be depending on the needs of design and the handoff functionality that provides these transistors suitable are provided.Below programming operation will be described, wherein Destination Storage Unit is the storage unit A in Figure 21, and respectively can be to representing with Destination Storage Unit A at same level/source electrode line and same column/word line, but the memory cell B of different rows/bit line, to with Destination Storage Unit A at go together mutually/bit line and same column/word line, but the memory cell C of Different Plane/source electrode line, to with Destination Storage Unit A at same column/word line, but the memory cell D of different rows/bit line and Different Plane/source electrode line, to with Destination Storage Unit A at same level/source electrode line and go together mutually/bit line, but the memory cell E of different lines/word line, consider the disturbed condition of memory cell.
According to this, arrange, this serial selection line and common source select line can in a cube, take cube as basic mode decoding.This word line can be to classify basic mode decoding as in row.This common source line can be take plane as basic mode decoding in a plane.This bit line can be in a line with the mode decoding of behavior base.
Figure 22 shows the sequential schematic diagram of the programming operation that is similar to the array in Figure 20.Between this programming area, be divided into three main sections that are denoted as T1, T2 and T3.When the first of T1, ground connection in this cube selects line GSL and the common source line CSL that do not choose (be shown in figure be denoted as SL) is set to VCC, and its common source line CSL that is approximately 3.3V chooses is retained in about 0V.In addition, this serial selection line SSL is also retained in about 0V.So can reach the coupling effect of selected plane and 0V and the plane do not chosen is suspension joint, causes between the common source line of not choosing and common source and selects the difference between line to be not enough to open the grid that common source is selected line.After a bit of change-over time, do not choose word line and other turn-on grid electrode (for example false word line and select grid) in this circuit are coupled to a turn-on voltage that is about 10V.Similarly, this chooses word line and is coupled to identical or approaching magnitude of voltage, and ground connection is selected line GSL and the common source line CSL that do not choose is retained in VCC.So can cause this square not choose the self-voltage rise effect of the body region in plane.Refer to Figure 21, memory cell C and D in interval T1 because of for this reason operation result there is voltage rise region.
In T2 section, ground connection selection line GSL and the common source line CSL not choosing change back to 0V, and word line and turn-on grid electrode are retained in conducting voltage.In ground connection, select line GSL and after the common source line CSL that do not choose changes back to a bit of time of 0V, the serial selection line SSL in this cube is converted to VCC, it can be about 3.3V as previously described.Similarly, the bit line of not choosing is also converted to VCC.The bias voltage result of T2 in the time can cause at same level/source electrode line and same column/word line, but the passage of the memory cell of different rows/bit line (as memory cell B) and at same column/word line, but the passage of the memory cell of different rows/bit line and Different Plane/source electrode line (as memory cell D) is boosted by self-voltage rise.The channel voltage that boosts of memory cell C can not leaked by bit line BL because of this diode of meeting.After T2 paragraph, serial selection line SSL and the bit line of not choosing change back to 0V.
In T3 section, in ground connection, select line GSL and after the common source line CSL that do not choose changes back to 0V, it is for example the read/program potential of 20V that the voltage of choosing word line is promoted to one, and serial selection line SSL, ground connection select line GSL, choose bit line, do not choose bit line, the common source line CSL choosing and the common source line CSL not choosing remain on 0V.In the time of T1 and T2 section, in selected memory cell, can form the passage of a reversion, even and therefore also can reach programming in the situation that grid is selected in serial and select common source grid all to close.Should be noted that with Destination Storage Unit A at same level/source electrode line and go together mutually/bit line, but the memory cell E of different lines/word line only can be applied to and not choose word line and be interfered because of conducting voltage.For example, so the conducting voltage applying enough low (being less than 10V) is interfered to prevent the data that are stored in these memory cell.
After between programming area, all voltage is all got back to about 0V.
In Figure 20, the different embodiment of structure are used drain electrode end (bit line) forward-sense.In different embodiment, this diode suppresses lost current path when reading and programme inhibition operation.
Figure 23 shows the bias condition schematic diagram of the read operation that is similar to the array in Figure 20.According to Figure 23, show the bias condition put on structure on substrate 410, the bias voltage that reads of the memory cell in a cube in a plane is not extremely chosen word line for applying conducting voltage, and one reads reference voltage and is applied to one and chooses word line.The common source line CSL and the about 0V that choose couple, and the common source line CSL and the about VCC that do not choose couple, and ground connection in this cube selects line GSL and serial selection line SSL all to couple with about 3.3V.Bit line BLn in this cube and BLn+1 couple with the precharge class that is about 1.5V.
Page decoding in this example can be by being used the plane decoding of common source line to reach.Therefore, to a given bias condition, because the common source line that in cube, each is chosen or plane have the page that the bit line that can be read has identical bits number.The common source line CSL and the about 0V that choose couple or are set as reference voltage, and other common source line CSL is set as about 3.3V.In the case, the common source line of not choosing is suspension joint.To choosing the diode in plane up line path, do not prevent divergence.
In page read operation, each the word line in each plane in a cube is read once.Similarly, take the page in basic programming operation in one, this programming rejection condition must be enough to the programming number of times that this page of the program of bearing is programmed required, and each plane once.Therefore,, for a cube that comprises 8 memory cell, the programming rejection condition of not choosing memory cell must be enough to bear 8 program cycles.
Must be noted that the diode in this bit line serial need to slightly promote the online bias voltage in position about 0.7V with the typical pressure drop of compensation diode.
Figure 24 shows the bias condition schematic diagram of a cubical erase operation.The bias condition showing according to Figure 24, word line and is for example-negative voltage of 5V couples, common source line CSL and bit line and one be for example+positive voltage of 8V couples, and ground connection selection line GSL and be for example+the suitable high break-over voltage of 8V couples.The yardstick that punctures that so can suppress source electrode line bias voltage.The ground connection of other block selects line GSL and serial selection line SSL to close.The required high voltage of bit line can be met by bit line driver design.Alternatively, word line and serial selection line can ground connection common source line CSL and ground connection select line GSL with one be for example+high voltage of 13V couples.
Figure 25 shows an alternate embodiment, and wherein diode 1492 is that the polysilicon plug 1550,1551 that application is formed by the coordination p+ doping of using when forming embolism forms.In the case, diode is self-aligning and can reduce processing step.Other structure is identical with shown in Figure 20.When being less than 40 nanometer, can use and reverse contact structures layouts (as Figure 27).
When self-voltage rise, this PN diode must bear the channeling potential that boosts of an about 8V in tens of milliseconds.Estimation leakage current when 8V reverse biased should be less than 100pA to bear this current potential that boosts.Certainly, disruptive potential should be far above 8V.A difficulty that helps prevent sensing compared with low turn-on voltage (being approximately less than 0.7V).
Figure 26 shows an alternate embodiment, and wherein diode is the common source line CSL end that is placed on memory cell serial.Therefore, in region 1515, the source electrode line in each plane is coupled in together by p+ line or doping, in common source line decoder and the ground connection of each string line, selects to form PN diode between line GSL.Other structure is identical with shown in Figure 20.
In Figure 26, the different embodiment of structure are used oppositely sensing of source terminal (source electrode line).In different embodiment, this diode suppresses lost current path when reading and programme inhibition operation.
Figure 27 shows a cubical schematic diagram, shows two planes of memory cell in this icon, corresponding common source line CSL0 and common source line CSL1, two row of memory cell, corresponding bit line BL0 and bit line BL1, four row of memory cell, correspond respectively to the word line in graphic.Serial selection line SSL in this cube and serial select grid to couple, and ground connection selects line GSL and ground connection to select grid to couple.Before being similar to, described self-voltage rise programming operation is used for programming, its have two stage program voltages be applied to selected word line can be in describing in more detail below.Diode is coupled to corresponding memory cell serial together with between source electrode line CSL0 or common source line CSL1.
In the following discussion, region bit line means another noun in a serial.In this structure, all common source line CSL can apply high voltage to suppress programming.When the common source line CSL choosing becomes low level, the high voltage of region bit line can not become low level.Page buffer can determine which memory cell should be programmed.When bit-line voltage is VDD, can not programme.When bit-line voltage is ground connection, can programme.
For a NAND gate flash memory cell, can use Fu Le-Nuo Dehan electron tunneling to programme to selected memory cell.In order to suppress the non-programming of choosing memory cell, should apply high voltage so far region bit line or the passage of memory cell.In order to reach programming, suppress, can apply as the programmed sequence of Figure 28 and Figure 29.
This programming operation comprises and applies high voltage to the common source line do not chosen, and applies VCC (about 3.3V) to not choosing bit line.When word line changes to VCC or high-tension conducting voltage, the region bit line of not choosing bit line is promoted to high voltage.The region bit line of choosing bit line can be forced and is pulled to high voltage or is forced to leave behind to ground common source line by bit line by common source line.When the word line of selected memory cell changes to read/program potential, all region bit lines are suspension joint all.The electric energy applying when programming operation must be enough to make any electric current (from VCC/ high voltage extremely) being caused by an online voltage class in a position, region that does not choose bit line can not impact or cause programming disturbed condition generation programming.
Figure 28 shows the programmed sequence of a five-stage.In step 1, ground connection is selected line to open ground connection and is selected grid, and serial selection line is closed serial selection grid.The high voltage of not choosing common source line charges to high voltage to the region bit line of not choosing in this cube in plane.The word line voltage of all word lines is raised to one first word line voltage.In step 2, the region bit line of not choosing in row applies supply current potential to not choosing bit line and choosing bit line ground connection by serial being selected grid open and being selected grid to close ground connection.In step 3, word line is biased to next conducting voltage and serial selects grid to be held open and ground connection selects grid to keep closing.So cause region bit line and high voltage in chosen area bit line not to couple.In step 4, share and choose bit line and and do not choose the region bit line of common source line and charge to high voltage.In this stage, serial selection line is closed and the unlatching of ground connection selection line.In step 5, word line voltage is biased to program voltage and serial selection line and ground connection select line to keep closing.
Figure 29 shows an alternative five-stage programmed sequence.In step 1, all region bit lines are charged to high voltage via the common source line in bias voltage cube to high voltage, and the ground connection of opening in this cube is selected grid, and close serial and select grid.Afterwards, close ground connection in this cube and select grid, and open serial and select grid, it can drive region bit line in chosen area bit line to ground voltage.
In step 3, word line is biased to a conducting voltage and serial selects grid to be held open and ground connection selects grid to keep closing.So cause region bit line in chosen area bit line to keep ground connection and the region bit line suspension joint in chosen area bit line and by boosting word line not.In step 4, by opening ground connection in this cube, select grid, and close serial and select grid to not choosing common source line bias voltage, the region bit line of choosing bit line and and do not choose common source line is charged to high voltage.In step 5, choose that word line receives program voltage and serial selects grid and ground connection to select grid to keep closing.Algorithm in Figure 29 can have and preferably promotes suppression characteristic and consume more power compared to Figure 28.From lifting region bit line LBL3, from high voltage, can improve and promote suppress result, so region bit-line voltage can be higher and improved inhibition.By common source line change to high voltage and be discharged to ground result can increase power consumption.
Therefore,, in this operating technology, the high voltage applying from source electrode line can suppress programming.When program voltage is applied in selected bit line and does not choose source electrode line and left behind to ground, this bit line being programmed is suspension joint.In addition, this bias voltage sequence is to maintain the mode of correctly boosting to suppress to programme to apply.When programming, be to prevent electric current, to get back to common source with the current path of diode.
Because common source line is whole, common source line can be to whole array decoding once.Relative, decoding serial selection line needs extra serial selection line driver and contact area.
In different embodiment, number to each block that the storage array of this diode decoding reduces serial selection line grid only has a serial selection line structure, or each NAND gate serial only has a serial selection line grid.So structure significantly reduces difficulty in process degree, and has high symmetry and micro.During the memory cell number of layers of this framework in increasing three-dimensional storage array, do not need a large amount of serial selection lines.Similarly, in a block, also only need a ground connection to select line.
This three-dimensional perpendicular gate devices is preferably used thin-film transistor energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) device.On the other hand, also can the anti-fuse of application or the similar device of other memory technology (for example using other the charge trapping devices with high-dielectric coefficient dielectric layer).
Figure 30 shows the sequential schematic diagram of another example programming operation that is similar to the array in Figure 21.
When T1 phase place, this source electrode line is selected line GSL by ground connection and is not chosen the online Vcc of source electrode and boosted by oneself.
When T2 phase place, this does not choose bit line by serial selection line SSL and does not choose position online high voltage HV and boosted to high voltage HV.The channel voltage Vch of memory cell B is also raised.The channel voltage Vch that memory cell C is raised can not leak because of the diode on bit line BL for this reason.
When T3 phase place, storage unit A is programmed.Its inverting channel just forms when T1 phase place.
Figure 31 shows a schematic diagram that is similar to the three-dimensional NAND gate flash structure in Figure 27, shows that this serial comprises that diode is formed between source electrode line structure and storage serial in this icon.The position of these diodes can be used for supporting that programming suppresses.
Destination Storage Unit is the storage unit A in figure, and can consider that the disturbed condition of following memory cell: memory cell B representative and Destination Storage Unit A are at same level/source electrode line and same column/word line, but the memory cell of different rows/bit line, memory cell C represents with Destination Storage Unit A at go together mutually/bit line and same column/word line, but the memory cell of Different Plane/source electrode line, memory cell D representative and Destination Storage Unit A are at same column/word line, but the memory cell of different rows/bit line and Different Plane/source electrode line, memory cell E representative with Destination Storage Unit A at same level/source electrode line and go together mutually/bit line, but the memory cell of different lines/word line.Memory cell E is switched on voltage Vpass and disturbs and can ignore in many examples.
Figure 32 shows the sequential schematic diagram of an example programming operation that is similar to the array in Figure 31.
When T1 phase place, this does not choose bit line (memory cell B and D) by serial selection line SSL and does not choose position online voltage vcc and being boosted by oneself.
When T2 phase place, this does not choose source electrode line and by ground connection, selects line GSL and do not choose the online high voltage HV of source electrode and boosted to high voltage HV.For example the channel voltage Vch that does not choose source electrode line of memory cell C is also directly promoted.When the voltage of source electrode line SL is 0V and ground connection while selecting line GSL to open, for example the channel voltage Vch being raised of memory cell B goes up can not leaking compared with little electric leakage of the diode of reverse biased because of source electrode line SL for this reason.
When T3 phase place, although serial selection line SSL is closed storage unit A, is still and is programmed.Its inverting channel just forms when T1 phase place.
Figure 33 A and Figure 33 B are the photograph of the tunnelling electron microscope of three-dimensional NAND gate flash memory some.
Be shown in figure is the tunnelling electron micrograph of the virtual ground device of 75 nanometer half spacing (4F2).Its channel width and length are respectively 30 and 40 nanometers, and channel height is 30 nanometers.Each device is the vertical channel device of bigrid (vertical gate), and wherein passage (burying lane device) is that the N-shaped of shallow doping is to increase reading current.The profile of this bit line BL is the shape that is applicable to using plane ONO.By this technique of suitable allotment to obtain less side walls collapse.And form a very smooth ONO at the sidewall of this bit line BL.
Figure 33 A is the profile of array in X-direction for this reason.In figure, show that two charge-trapping energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) device is formed at the sidewall of each passage.Each device is double gate device.Channel current is flatly to flow, and grid is vertically to arrange.There is minimum ONO side walls collapse.
Figure 33 B is the profile of array in Y direction for this reason.Due to the spacing tightening and less bitline width, the tunnelling electron micrograph of focused ion beam shows the Dual Images that comprises polysilicon gate and spacing upper in bit line (horizontal semiconductor strips).Its passage length of device in icon is approximately 40 nanometers.
Figure 34 is current/voltage (IV) performance plot of the polysilicon diode of experiment measuring.
The forward of polysilicon PN diode and reverse current voltage (IV) characteristic are directly from the PN diode measurement being connected with the three-dimensional NAND gate array of virtual ground NAND gate vertical gate.The height/width of this polysilicon is of a size of 30/30 nanometer.Leakage current-8 is far below 10pA, and it has met oneself and has boosted and help to eliminate the demand that programming is disturbed.Apply source electrode bias voltage Vs, and the conducting voltage Vpass of 7V is on all word lines.This P+-N diode (30 nano-widths and 30 nanometer height) shows over 6 quantity and above successful On/Off ratio.This forward current is clamped down on by NAND gate serial series resistance.
Figure 35 is the reading current performance plot of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
This three-dimensional NAND gate memory has 32 word lines.The Vpass of word line and Vread voltage are all 7V.Source electrode line voltage Vsl changes in following numerical value: 2.5V, 2.0V, 1.0V, 0.5V and 0.1V.In this icon, source electrode line voltage Vsl causes suitable current sensor while surpassing 1.0V.What be applied to source terminal reads voltage (source terminal detection technology), is a positive voltage in the case.Required bias voltage thus PN diode promotes, and it needs enough cut-in voltages, makes the source electrode bias voltage that surpasses 1.5V just can produce enough reading currents.
Figure 36 is the programming suppression characteristic figure of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
The typically programming suppression characteristic that shows storage unit A, B, C, D in figure.In the case, Vcc=3.3V, HV=8V, Vpass=9V.In storage unit A, be to apply to increase progressively step-by-step impulse ISSP method.Between this graphic interference-free coverage area demonstrating over 5V.By Diode Insulation Properties, caused.
Figure 37 be experiment measuring the polysilicon diode being connected with three-dimensional NAND gate memory source electrode bias effect for programming interference effect.
Source electrode line suppresses bias voltage (HV) for having impact between programming interference range.By HV > 7V, the interference of memory cell C can be down to minimum.
Figure 38 be experiment measuring the polysilicon diode being connected with three-dimensional NAND gate memory turn-on grid electrode voltage effects for programming interference effect.
Turn-on grid electrode voltage disturbs and has impact for programming.By Vpass > 6V, can reduce the interference of memory cell C.
Figure 39 is the block erase switching current schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring.
The upper different bias voltage of source electrode line SL can change block erase transfer characteristic.Wipe is by applying a positive source electrode line bias voltage and all word line WL ground connection being reached.So represent the main body suspension joint of this three-dimensional NAND gate array.Drain selection line SSL/ ground connection selects line GSL to apply suitable positive voltage to avoid interference.In Figure 10, also show that this wipes transformation.This array is not used electric field enhancement effect (because cause of smooth ONO) in certain embodiments, this is wiped mainly and by energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) tunneled holes, injected and supported.
Figure 40 is programming and the erase status current-voltage characteristic schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring, and this memory has different number mark program/erase cycle.
This i-v curve shows and carries out less deteriorated lower than in 10,000 erase operations, particularly when 1000 times and one time.The deteriorated cause normally producing because of Interface status (Dit) of endurance makes subcritical slope variation, and can't change between memory block.By adjust this device of energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) lamination demonstrate carry out after 10,000 erase operations with huge device compare rationally less deteriorated.
Figure 41 is the critical voltage distribution schematic diagram of the polysilicon diode being connected with three-dimensional NAND gate memory of experiment measuring, and this memory has the program/erase memory cell that check table distributes.
The check table of one single class memory cell is distributed in this PN polysilicon diode being connected with three-dimensional NAND gate memory and uses.(in this three-dimensional sensing) immediate memory cell is programmed to inverse state with the poorest disturbed condition of representative.In every one deck, be to use traditional page programming and programming inhibition method, and then other do not chosen to source electrode line (memory cell C and D) and suppress.At other layer, carry out page programming successively.In a cubical array, do not choose memory cell and be subject to row stress many times and the injury of row stress.
In many different embodiment, the diode of alternate embodiment is to be connected with drain electrode end (bit line) or source terminal (source electrode line), and has the role exchange of drain selection line SSL/ ground connection being selected to line GSL and bit line/source electrode line.These substitute operation is to verify in device class.Yet in circuit design, source electrode line has very little capacitive load, performance that so can be in speed and power consumption when applying high voltage HV in source electrode line is better.
Preferred embodiment of the present invention and example disclose as above in detail, but are to be appreciated that above-mentioned example is only as example, non-in order to limit the scope of patent.With regard to those skilled in the art, from modifying to correlation technique and combine according to the claim scope of enclosing easily.
Claims (25)
1. a storage device, comprises:
One ic substrate;
A plurality of rectangular semi-conducting material laminations extend this ic substrate, and the plurality of lamination has ridge shape and comprises that at least two rectangular semi-conducting materials are separated as the Different Plane position in a plurality of plan position approachs by insulating barrier;
Many word lines are arranged to and are orthogonal on the plurality of lamination, and have and the surface of the plurality of lamination along shape, so in the plotted point on the plurality of lamination and these many word line surfaces, set up the intersection region of a cubical array;
Memory element is in this intersection region, and it sets up the memory cell of accessible this cubical array via the plurality of rectangular semi-conducting material and this many word lines, and this memory element is arranged to serial between bit line structure and source electrode line; And
Diode and this serial couple, between memory cell serial and bit line structure and source electrode line wherein between one.
2. storage device according to claim 1, wherein this serial right and wrong door serial.
3. storage device according to claim 1, wherein the combination of the particular word line in the particular source polar curve in the specific bit line in this bit line structure, this source electrode line and this many word lines is selected, and can pick out the particular memory location in the memory cell of this cubical array.
4. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.
5. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.
6. storage device according to claim 1, more comprises:
One serial selection line is arranged to and is orthogonal on the plurality of lamination, and has and the surface of the plurality of lamination along shape, so in the plotted point on the plurality of lamination and this serial selection line surface, sets up serial choice device; And
One ground connection selection line is arranged to and is orthogonal on the plurality of lamination, and has and the surface of the plurality of lamination along shape, so in the plurality of lamination and this ground connection, selects the plotted point on line surface to set up grounding selection device.
7. storage device according to claim 6, wherein this diode is coupled between this serial choice device and this bit line structure.
8. storage device according to claim 6, wherein this diode is coupled between this grounding selection device and this source electrode line.
9. storage device according to claim 1, wherein this memory element comprises respectively a tunnel layer, an electric charge capture layer and a barrier layer.
10. storage device according to claim 1, wherein this rectangular semi-conducting material comprises N-shaped silicon and this diode comprises a p-type region in this rectangular semi-conducting material.
11. storage devices according to claim 1, wherein this rectangular semi-conducting material comprises N-shaped silicon and this diode comprises a p-type embolism contacts with this rectangular semi-conducting material.
12. storage devices according to claim 1, more comprise logic and do not choose the diode in serial to apply reverse biased to this memory cell when programming this memory cell.
13. 1 kinds of storage devices, comprise:
One ic substrate;
The memory cell of a cubical array is in this ic substrate, and this cubical array comprises:
The lamination of NAND gate serial memory cell;
Be arranged to and be orthogonal on the plurality of lamination and have and the surperficial many bar word lines of the plurality of lamination along shape; And
Diode and this serial couple, and are between memory cell serial and bit line structure and source electrode line wherein between one.
14. storage devices according to claim 13, wherein the combination of the particular word line in the particular source polar curve in the specific bit line in this bit line structure, this source electrode line and this many word lines is selected, and can pick out the particular memory location in the memory cell of this cubical array.
15. storage devices according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.
16. storage devices according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.
17. storage devices according to claim 13, more comprise:
One serial choice device is between this bit line structure and this memory cell serial; And
One grounding selection device is between this source electrode line and this memory cell serial.
18. storage devices according to claim 17, wherein this diode is coupled between this serial choice device and this bit line structure.
19. storage devices according to claim 17, wherein this diode is coupled between this grounding selection device and this source electrode line.
20. storage devices according to claim 13, wherein this memory element comprises respectively a tunnel layer, an electric charge capture layer and a barrier layer.
21. 1 kinds of methods that operate three-dimensional NAND gate flash memory, the memory cell that this three-dimensional NAND gate flash memory comprises an ic substrate and a cubical array is in this ic substrate, the lamination that wherein this cubical array comprises NAND gate serial memory cell, be arranged to and be orthogonal on the plurality of lamination and have and the surperficial many bar word lines of the plurality of lamination along shape, and diode, this diode and this serial couple, be between memory cell serial and bit line structure and source electrode line wherein between one, the method comprises:
Apply a programming and adjust bias voltage sequence to this three-dimensional NAND gate flash memory, this cubical array comprises diode and this serial couples, and making this diode is between memory cell serial and bit line structure and source electrode line structure wherein between one.
22. methods according to claim 21, wherein this applies this programming and adjusts bias voltage sequence and comprise:
From one or more of source electrode line structure by one or more of this diode to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon by this programming and adjust the memory cell that bias voltage will be programmed;
This bit line structure and source electrode line structure are not chosen to serial and comprised soon one or more one choose serial and remove and couple of being adjusted the memory cell of bias voltage programming by this programming from this;
Via the one or more word line that is about to be adjusted by this programming the memory cell that bias voltage programme, apply a program voltage and do not choose serial and this chooses serial to this.
23. methods according to claim 21, wherein this applies this programming and adjusts bias voltage sequence and comprise:
Not by this diode one or more and from one or more of source electrode line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise and soon by this programming, adjusted the memory cell that bias voltage will be programmed;
This bit line structure and source electrode line structure are not chosen to serial and comprised soon one or more one choose serial and remove and couple of being adjusted the memory cell of bias voltage programming by this programming from this; And
Via the one or more word line that is about to be adjusted by this programming the memory cell that bias voltage programme, apply a program voltage and do not choose serial and this chooses serial to this.
24. methods according to claim 21, wherein this applies this programming and adjusts bias voltage sequence and comprise:
By this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon and to be adjusted by this programming the memory cell that bias voltage will be programmed;
This bit line structure and source electrode line structure are not chosen to serial and comprised soon one or more one choose serial and remove and couple of being adjusted the memory cell of bias voltage programming by this programming from this; And
Via the one or more word line that is about to be adjusted by this programming the memory cell that bias voltage programme, apply a program voltage and do not choose serial and this chooses serial to this.
25. methods according to claim 21, wherein this applies this programming and adjusts bias voltage sequence and comprise:
Not by this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise and soon by this programming, adjusted the memory cell that bias voltage will be programmed;
This bit line structure and source electrode line structure are not chosen to serial and comprised soon one or more one choose serial and remove and couple of being adjusted the memory cell of bias voltage programming by this programming from this; And
Via the one or more word line that is about to be adjusted by this programming the memory cell that bias voltage programme, apply a program voltage and do not choose serial and this chooses serial to this.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US37929710P | 2010-09-01 | 2010-09-01 | |
| US61/379,297 | 2010-09-01 | ||
| US13/011,717 US8659944B2 (en) | 2010-09-01 | 2011-01-21 | Memory architecture of 3D array with diode in memory string |
| US13/011,717 | 2011-01-21 |
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| Publication Number | Publication Date |
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| CN102386188A CN102386188A (en) | 2012-03-21 |
| CN102386188B true CN102386188B (en) | 2014-01-22 |
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| KR (1) | KR20120022676A (en) |
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| JP2020087495A (en) * | 2018-11-29 | 2020-06-04 | キオクシア株式会社 | Semiconductor memory |
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| CN102386188A (en) | 2012-03-21 |
| JP2012054550A (en) | 2012-03-15 |
| TWI427744B (en) | 2014-02-21 |
| KR20120022676A (en) | 2012-03-12 |
| TW201212168A (en) | 2012-03-16 |
| JP5977003B2 (en) | 2016-08-24 |
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