CN104347635B - The semiconductor array arrangement supplied including carrier - Google Patents

Abstract

It is that the thin film transistor (TFT) base material storage device for a memory is supplied through a hole carrier the invention discloses a kind of semiconductor array arrangement supplied including carrier.Hole carrier supply may include the diode with a first end and one second end.The second switch that one NAND string row is coupled in a bit line, a second end by the first switch in a first end is coupled to the first end of the diode.One first source electrode line and one second source electrode line that can be driven individually are respectively coupled to the first end and second end of the diode.The circuit for being coupled to first, second source electrode line is, with different bias conditions, including forward bias voltage drop condition or reverse bias condition, first, second source electrode line to be biased according to operator scheme.

Description

The semiconductor array arrangement supplied including carrier

Technical field

The invention relates to a kind of high density memory Set, and it may include in particular to a kind of storage device multiple Three-dimensional (3D) array of film crystal transistor memory unit arrangement form one, includes the semiconductor array arrangement of carrier supply, is to pass through One hole carrier supplies the thin film transistor (TFT) base material storage device for a memory.

Background technology

The design of high density memory Set include multiple flash memory cells (flash memory cells) or it is multiple its Multiple arrays of the memory cell of his type.In some instances, including multiple memory cell of multiple thin film transistor (TFT)s can be arranged Arrange into three-dimensional structure (3D architectures).

Three-dimensional memory devices have developed into a variety of structures, including multiple films and are spaced apart by insulating materials Multiple bit lines.Known three-dimensional perpendicular grid structure is the three-dimensional for using multiple thin film transistor (TFT)s as multiple Storage Unit Types Storage device, is e.g. recorded in the 13/078th, No. 311 case of U.S. Patent Application No., applies on April 1st, 2011, invention name Referred to as " there is stored interleaved string to configure and go here and there 3D storage array bodies structure (the Memory Architecture of for selecting structure 3D Array With Alternating Memory String Orientation and String Select Structures) " (U.S. Patent Publication No. US 2012/0182806A1 are disclosed on July 19th, 2012), inventor is old The great two pieces United States Patent (USP) with Lv Hanting of scholar is co-owned by the assignee of present application, can be as reference.Three-dimensional perpendicular grid Pole structure includes multiple film tape laminations and the word line structure being covered on lamination so that word line structure part is vertically extended Between multiple laminations, the part of word line structure extension and the intersection of multiple film tapes are used as a plurality of word in memory cell Line.A plurality of film bit line can be that main body be lightly doped and no connects in this structure or other kinds of storage organization Touch, therefore the source of a plurality of film bit line and electric charge carrier is insulated in the operation of device.The insufficient situation of carrier in hole It is lower to injure the operating efficiency of structure.

Therefore, related dealer expects to provide a kind of array junctions for being used in three dimensional integrated circuits have higher operating efficiency Structure.

The content of the invention

The present invention is to provide for that can meet the structure of hole carrier supply requirement in thin film transistor (TFT) base material storage device.

In one embodiment, a memory may include a diode, a series arrangement, one first source electrode line, one second source electrode Line, a plurality of wordline and a circuit.Diode has a first end and one second end.Series arrangement includes multiple memory cell, Series arrangement is, for example, to be coupled to a bit line by the first switch in a first end in NAND string row, by a second end On a second switch be coupled to the first end of diode.The first source electrode line and the second source electrode line that can be driven individually are respectively coupled to First end and the second end in diode.A plurality of wordline is coupled to corresponding memory cell.Circuit is coupled to first, second source electrode Line, circuit is to bias first, second source electrode line according to operator scheme with different bias conditions.

In another embodiment, circuit is configuration to use in a block of the memory cell of selection or multiple memory cell One erasing bias arrangement (erase bias arrangement) is produced with inducing hole.Erasing for N-shaped passage biases row Row are included in the source side bias on the second source electrode line, and the source side biases the forward bias voltage drop diode to provide coming for hole Source make it that one or more bit line is wiped free of.Erasing bias arrangement also may include that the first source electrode line keeps floating, in a plurality of wordline Apply erasing voltage to induce hole generation.

In another embodiment, circuit is that configuration can be used during program bias arrangement (program bias arrangement) A source side on the first source electrode line is biased so that in programming operation, the second source electrode line keeps floating or being subjected to bias With reverse bias diode.

Be the same as Example is not to include the three-dimensional storage arrangement of a three-dimensional perpendicular grid structure, wherein diode described above can For providing carrier supply in the certain operations pattern of device.In general there is provided embodiment be used for semiconductor material One hole carrier supply of the multiple bit lines of material, bit line may insulate with a conductivity substrate and may not have a body contact.

More preferably understand to have to other aspects of the present invention with advantage, preferred embodiment cited below particularly, and coordinate institute Accompanying drawings, are described in detail below：

Brief description of the drawings

Fig. 1 illustrates the perspective view of a three-dimensional perpendicular grid NAND array, and wherein three-dimensional perpendicular grid NAND is deposited Storing up array is included without film bit line of the body contact without knot.

Fig. 2 illustrates the layout of three-dimensional perpendicular Gate Memory of the one embodiment of the invention including diode structure.

Fig. 2A, Fig. 2 B, Fig. 2 C illustrate the diode structure in the three-dimensional storage suitable for such as Fig. 2.

Fig. 3 illustrates the layout of the intermediate structure in a technique, and the wherein technique is for manufacturing with two such as Fig. 2A Similar Fig. 2 of pole pipe structure memory construction.

Fig. 3 A, Fig. 3 B are the profiles according to depicted in the operation stage of Fig. 3 layout.

Fig. 4 illustrates the layout of another intermediate structure in a technique, and wherein the technique is to be used to manufacture to have as schemed Similar Fig. 2 of 2A diode structure memory construction.

Fig. 4 A, Fig. 4 B are the profiles that the extra stage is illustrated according to the operation stage of Fig. 4 layout.

Fig. 5 illustrates the layout of another intermediate structure in a technique, and wherein the technique is to be used to manufacture in similar Fig. 2 Structure.

Fig. 5 A, Fig. 5 B are the profiles that the extra stage is illustrated according to the operation stage of Fig. 5 layout.

Fig. 6 illustrates the layout of another intermediate structure in a technique, and wherein the technique is to be used to manufacture in similar Fig. 2 Structure.

Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D are the profiles that the extra stage is illustrated according to the operation stage of Fig. 6 layout.

Fig. 7 illustrates the layout that an intermediate structure after Fig. 6 technique is carried out for the structure manufactured in similar Fig. 2.

Fig. 7 A, Fig. 7 B are the profiles that the extra stage is illustrated according to the operation stage of Fig. 7 layout.

Fig. 8 illustrates the layout of another intermediate structure in a technique, and wherein the technique is to be used to manufacture to have as schemed Similar Fig. 2 of 2B diode structure memory construction.

Fig. 8 A, Fig. 8 B are the profiles that the extra stage is illustrated according to the operation stage of Fig. 8 layout.

Fig. 9 illustrates the technique for manufacturing the structure in similar Fig. 2, an intermediate structure after Fig. 8 technique is carried out Layout.

Fig. 9 A, Fig. 9 B are the profiles that the extra stage is illustrated according to the operation stage of Fig. 9 layout.

Figure 10 illustrates the layout of another intermediate structure in a technique, and wherein the technique is to be used to manufacture to have as schemed Similar Fig. 2 of 2C diode structure memory construction.

Figure 10 A, Figure 10 B are the profiles that the extra stage is illustrated according to the operation stage of Figure 10 layout.

Figure 11 illustrates the technique for manufacturing the structure in similar Fig. 2, carries out another middle knot after Figure 10 technique The layout of structure.

Figure 11 A, Figure 11 B are the profiles that the extra stage is illustrated according to the operation stage of Figure 11 layout.

Figure 12 is that the bias arrangement for a programming operation is illustrated in the schematic diagram of similar Fig. 2 three dimensional NAND structure, figure.

Figure 13 is that the bias arrangement for an erasing operation is illustrated in the schematic diagram of similar Fig. 2 three dimensional NAND structure, figure.

Figure 14 is the erasing bias arrangement that a replacement is illustrated in the schematic diagram of similar Fig. 2 three dimensional NAND structure, figure.

Figure 15 is that reading bias arrangement is illustrated in the schematic diagram of similar Fig. 2 three dimensional NAND structure, figure.

Figure 16 is the schematic diagram of another three dimensional NAND structure, and its each bit line lamination for illustrating a circuit has one or two One embodiment of pole pipe, three dimensional NAND structure is to impose to be biased to carry out a programming operation.

Figure 17 is a simplification block diagram of the integrated circuit for including three-dimensional storage, and wherein three-dimensional storage is to include implementing The carrier supply of example.

【Symbol description】

10：Array

11：Column decoder

12：Bit line

13：Page buffer

14：Global bit lines

15、17：Bus

16、18、20：Square

19：State machine

23：Data In-Line

24：Other circuits

25：Integrated circuit

102、103、104、105、112、113、114、115、202、202-1、202-2、202-8、203、203-2：Bit line

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A, 202-A~202-D, 203-A~203-D, 220、223、330、331：Engagement pad

109、119、119-A1、119-A2、119-D1、119-D2：Serial selection line grid structure

125-0~125-N, WL：Wordline

126、127、GSL：It is grounded selection line

128：Source electrode line

205-1~205-8,210-A~210-D, 211-A~211-D：Serial selection connection

219-1~219-8：First source line contact

221-1~221-8：Second source line contact

220A~220D, 605,606,607,650-1~650-8,651-1~651-8,850-1~850-8：Opening

224、351、557、558、724、824：P+ regions

302：Substrate

225、350：Knot

305：Insulating barrier

320、345、346、355、550-1、550-2、550-8、651、660、665：Cylinder

321、524-1、524-2、524-3、590、591、725-1、725-2、725-3、825-1、825-2、825-3：N+ Region

325、326、327、356、610、611、612、859-1、859-2、859-8、869-1、869-2、869-8：Interlayer Conductor

332、333、342、343、353、592、593、655、656、：PN junction

410、410A、420、420A、430：Stepped contact

500：Upper strata

501、502、503：Through hole

509：Top insulator material layer

510：Second active material

511：First active material

512：Semi-conducting material

519：Charge storing structure layer

524：N+ injects

555、579：Mask

556：P+ injects

565：Polysilicon layer

598：Silicide layer

600、855：Insulation fill stratum

601、650：Interlayer dielectric packed layer

651：N+ cylinders

652：N+ parts

653、654：P+ parts

661：P+ cylinders

750-1~750-8,751-1~751-8：Interlayer articulamentum

800：Diode

801：Diode N-type end

804-1~804-4：Contact

824-1、824-2、825-1、825-2：Serial selecting switch

814-1~814-4：It is grounded selecting switch

840、842、845、847：Memory cell

859-1、859-2、859-8、869-1、869-2、869-8：Interlayer conductor

861、866：First end

860、865：Second end

SSL：Serial selection line

BLL1、BLL2：Bit line layer

GSL：It is grounded selection line

SC：Source contact end

PNS、PNS1、PNS2：PN junction source terminal

P1PNS：Upper strata diode source is extreme

P2PNS：Lower diodes source terminal

X、Y、Z：Direction

ML1、ML2、ML3：Metal level

A、B、C、D：Block

Embodiment

Various embodiments are that the appended diagram of collocation is described in detail.

Fig. 1 illustrates the perspective view of three-dimensional NAND gate storage array (3D NAND memory array) structure, three-dimensional NAND structures are that to see, for example be that the assignee of above-mentioned present application co-owns U.S. patent application case number the 13/078th, No. 311 cases.In order to preferably represent additional structure, insulating materials is by being removed in diagram.For example remove to be located at and fold Multiple insulating barriers between multiple bit lines (being, for example, 112-115) in layer and between multiple bit line laminations.

Multiple tier array is formed on an insulating barrier, and including a plurality of wordline (Word Line, WL) 125-0 to 125- N, a plurality of wordline and multiple lamination systems are conformal.Multiple laminations include multiple bit lines 112,113,114,115, and multiple bit lines include It is multiple that there is a relatively low intensity of impurity doping or other extrinsic semiconductors (intrinsic semiconductor) Semiconductor material thin film bar, semiconductor material thin film bar can be made as passage in NAND string row.Multiple storage devices can configure For N-shaped passage or p-type channel operation.In the structure of some illustrations, multiple bit lines do not include being located between a plurality of wordline Source/drain is connected, therefore is referred to as " no knot " bit line.And multiple bit lines be nor connected to semi-conductive substrate or other half Conductor main body, therefore ought not apply electricity via string selection (string select) or ground connection selection (ground select) switch When being pressed on multiple bit lines, multiple bit lines can be considered as " floating (floating) ".

Multiple bit lines in same level be by an engagement pad (pad) electric property coupling together, engagement pad have and one A touch-down zone (landing area) for interlayer conductor (interlayer conductor) contact.As shown in Figure 1 multiple layers Multiple engagement pads can be arranged in stepped construction, each sequentially to configure and suffer from land area in the engagement pad on the single order of structure. For special manufacture setting that is desired or needing, for multiple touch-down zones of the connection of multiple engagement pads, and multiple engagement pads On multiple touch-down zones multiple interlayer conductors can be arranged in it is simple it is stepped beyond pattern.

It is used for the word line numbers of even number memory page (even memory pages) shown in figure from the rear end of total It is to be incremented by by 0 to N to front end.Word line numbers for odd number memory page (odd memory pages) are after total It is to be successively decreased by N to 0 to hold to front end.

Engagement pad 112A, 113A, 114A and 115A terminate the multiple bit lines that (terminate) interlocks, in this example Engagement pad 112A, 113A, 114A and 115A are, for example, to terminate the bit line 112,113,114 and 115 in each layer.As shown in FIG., In order to be connected to decoding circuit (decoding circuitry) to select plane in an array, these engagement pads 112A, 113A, 114A and 115A are electrically connected at different wordline.These engagement pads 112A, 113A, 114A and 115A can define multiple fold It is patterned while layer.

Engagement pad 102B, 103B, 104B and 105B terminate multiple bit lines staggeredly, are, for example, to terminate respectively in this example Bit line 102,103,104 and 105 in layer.As shown in FIG., in order to be connected to decoding circuit to select plane in an array, this A little engagement pad 102B, 103B, 104B and 105B are electrically connected at different wordline.These engagement pads 102B, 103B, 104B and 105B can be patterned with multiple through holes in touch-down zone while multiple laminations are defined.

In other examples, all bit lines in a block may terminate on the bit line contact pad on same end.

In the example illustrated, all bit line laminations are coupled to engagement pad 112A, 113A, 114A and 115A or connect Touch pad 102B, 103B, 104B and 105B, but both can not be coupled to simultaneously.The position of one lamination of multiple bit lines is to for from position Line end to source electrode line end (bit line end-to-source line end) or from source electrode line end to bit line end Two one of them of opposite position in of (source line end-to-bit line end).For example, multiple bit lines 112nd, 113,114 and 115 lamination has from bit line end to the position of source electrode line end to the and of multiple bit lines 102,103,104 105 lamination have from source electrode line end to the position of bit line end to.

One end of the lamination of multiple bit lines 112,113,114 and 115 is to pass through serial selection line (String Select Line, SSL) grid structure 119, ground connection selection line (Ground Select Line, GSL) 126, wordline 125-0 extremely 125-N and ground connection selection line 127 simultaneously terminate at engagement pad 112A, 113A, 114A and 115A, and another end terminates at source electrode Line 128.The lamination of multiple bit lines 112,113,114 and 115 does not extend to engagement pad 102B, 103B, 104B and 105B.

One end of the lamination of multiple bit lines 102,103,104 and 105 be pass through serial selection line grid structure 109, Ground connection selection line 127, wordline 125-N to 125-0 and ground connection selection line 126 and terminate at engagement pad 102B, 103B, 104B and 105B, and another end terminates at source electrode line (being covered by another part in figure).Bit line 102,103,104 and 105 it is folded Layer does not extend to engagement pad 112A, 113A, 114A and 115A.

One layer of storage material separates wordline 125-0 to 125-N with bit line 112-115 and 102-105.It is grounded selection line 126 and 127, it is conformal with bit line similar in appearance to serial selection line grid structure.

One end of each lamination of multiple bit lines is to terminate at multiple engagement pads, and another end terminates at a source electrode Line.For example, an end of multiple bit lines 112,113,114 and 115 terminate at engagement pad 112A, 113A, 114A and 115A, another end terminates at source electrode line 128.In the near-end of schema, the lamination of multiple bit lines at interval is to terminate at contact 102B, 103B, 104B and 105B are padded, the lamination of multiple bit lines at interval is to terminate at a different source electrode line.In the remote of schema Journey, the lamination of multiple bit lines at interval is to terminate at engagement pad 112A, 113A, 114A and 115A, multiple bit lines at interval it is folded Layer is to terminate at a different source electrode line.

Multiple bit lines and a plurality of serial selection line are formed at multiple patterning conductor layers, e.g. metal level (Metal Layer, ML) ML 1, ML 2 and ML 3.Multiple transistors are formed at multiple bit lines (being, for example, 112-115) and wordline 125-0 To the crosspoint between 125-N.In multiple transistors, bit line (being, for example, 113) is as the channel region in device.

Serial selection structure (being, for example, 119,109) can define wordline 125-0 to 125-N (as shown in Figure 2) process In be patterned simultaneously.Multiple transistors are formed at multiple bit lines (being, for example, 112-115) 119th, 109) between crosspoint.In order to select specific multiple laminations in array, multiple crystal of serial selecting switch are used as Pipe is coupled to decoding circuit.

One charge storing structure (charge storage structure) layer is formed at least provided with memory cell Intersection.Charge storing structure may include multilayer dielectric charge storing structure, and e.g. eka-silicon O-N-Si oxygen (SONOS) is tied Structure.Known dielectric charge storage structure is energy gap engineering silica nitrogen silica (bandgap engineered SONOS) or " BE- SONOS」.BE-SONOS charge storing structures may include a multilayer tunnel layer, and an e.g. thickness is about 2 nanometers of silica Layer, a thickness are about 2-3 nanometers of silicon nitride layer and a thickness is about 2-3 nanometers of silicon oxide layer.BE-SONOS electric charges are stored Structure may include to be located at the dielectric layer for being used for storing electric charge above multilayer tunnel layer, and an e.g. thickness is 5-7 nanometers of nitrogen SiClx layer.Charge storing structure also may include to be located at the dielectric layer for being used for stopping electric leakage (leakage) on electric charge storage layer, example A thickness is 5-8 nanometers of silicon oxide layer in this way.Other kinds of material can be also used in BE-SONOS laminations.

In the device including BE-SONOS electric charge storage layers, an erasing operation (erasing operation) may include F-N tunnellings (Fowler Nordheim tunneling) hole from passage to electric charge storage layer is to neutralize in electric charge storage layer The electronics caught.

However, for as the structure shown in Fig. 1, it is whole it is serial in not P+ areas.May be via Gate Induced Drain (Gate Induced Drain Leakage, the GIDL) mechanism of electric leakage induces an energy band extremely can band hot hole electric current (band-to- band hot hole current).However, it may be desirable to an extra or other hole source.Such as present invention institute State, a carrier supply for including diode can produce hole source to solve this problem.

Fig. 2 illustrates three-dimensional finger vertical gate NAND memory device (finger VG (vertical gate) 3D NAND Memory device) the first array arrangement layout.For reference, " X " axle is to be located parallel to wordline (example in structure 125-0,125-5,125-15 in this way) direction, " Y " axle is to be located parallel to structure neutrality line (being, for example, 202-1,202-8) Direction, " Z " axle is to be located at the direction for being orthogonal to bit line and bit line in structure.

In Fig. 2 layout, array arrangement includes multiple bit lines.Memory cell be disposed on bit line (be, for example, 202-1, 202-2,202-8) and wordline (be, for example, 125-0,125-5,125-15) crosspoint.In the embodiment illustrated, there is sign For A, B, C, D four blocks, to put it more simply, each block of embodiment has two bit line laminations of two layer depths.In other realities Apply in example, may have a more layers, e.g. 4,8, may have multiple bit line laminations in 16 or more, and each block, for example It is 4,8,16 or more.In this embodiment, the shared carrier supply of four blocks A, B, C, D illustrated, below will It is described in more detail.

Multiple bit lines in the horizontal plane of upper strata prolong from a corresponding engagement pad (upper water plane contact pad 202-A, 202-D) Extend the top of source electrode line and carrier Supply Structure.Carrier Supply Structure is included in the N+ regions 524-3 of multiple bit lines First source line contact 219-1 to 219-8, engagement pad 220 includes the second source electrode in the P+ regions of a P+ regions and engagement pad Linear contact lay 221-1 to 221-8.N+ regions 524-3 establishes the source terminal of bit line.Positioned at N+ regions 524-3 and source line contact A knot 225 on pad 220 between P+ regions 224 provides the PN junction of a diode.In a p-type channel embodiment, region 224 Doping type with 524-3 is in turn.

Bit line in lower floor's horizontal plane extends from a corresponding engagement pad (lower floor's horizontal plane engagement pad 203-A, 203-D), As shown in FIG., the bit line in lower floor's horizontal plane can be obtained by the stepped opening of engagement pad in the horizontal plane of upper strata.In a pattern During the conductor layer of change is, for example, the metal level ML3 shown in Fig. 1, serial selection connection 210-A to 210-D and 211-A to 211-D Couple engagement pad and superincumbent bit line.

The wordline (being, for example, 202-1,202-2,202-8) and the ground connection selection line 127 of level of level are covered in bit line (example 125-0,125-5,125-15 in this way) on.Serial selection line grid structure is also covered in positioned at line, including for couple bit line with Serial selection line grid structure 119-A1,119-A2 of engagement pad 202-A, 203-A, for couple bit line and engagement pad 202-D, Similar multiple serial selection line grid structures in 203-D serial selection line grid structure 119-D1,119-D2, block B, C Reference symbol is not indicated.Serial selection line grid structure controls any one bit line engagement pad corresponding with the bit line (e.g. 202-A, 203-A) between electric connection.In a conductor layer patterned is, for example, the metal level ML2 shown in Fig. 1, string Row selection connection 205-1 to 205-8 couples multiple serial selection line grid structures and superincumbent serial selection line.

Three dimensional NAND storage device includes multiple memory cell planes.In multiple memory cell planes multiple bit lines via Multiple engagement pad (being, for example, 202-A and 202-B) one specific plane of selection.The specific plane is tied by multiple serial selections Structure, multiple horizontal grounding selection lines and multiple bit lines are decoded.Apply a positive serial selection line voltage (VSSL) to serial selection Structure (119-A1) is to select a specific lamination (e.g. including upper horizontal plane bit line 202-1).For example one is applied For voltage to multiple serial selection structures of 0 volt (V) other multiple laminations are selected to cancel.

Fig. 2A-Fig. 2 C illustrate the structure for substituting carrier supply in the layout available for similar Fig. 2.

Fig. 2A is the side view in Z-Y plane direction, is illustrated positioned at bit line 202,203 laminations for being similar to Fig. 2 structures One carrier Supply Structure of end.The lamination of bit line 202,203 is disposed on the insulating barrier 305 on a substrate 302 On.Ground connection selection line 127 is that configuration is adjacent on bit line 125-N, 125-N-1 etc. side.In this example, bit line 202, 203 extend to a N+ end regions 321 in bit line by ground connection selection line 127.N+ end regions 321 are the N+ for being contacted with semi-conducting material A part for the N+ cylinders 320 of cylinder (column) 320 or semi-conducting material, the N+ cylinders 320 of semi-conducting material provide position The N+ ends of line.One interlayer conductor 325 is coupled to the top of N+ cylinders 320 and to connect one first source electrode line (not shown). Bit line 202,203 is from vertical cylinder 320 extends to the P+ regions of source line contact pad 330,331.Positioned at source line contact The PN junction 332,333 between the N+ regions on P+ regions and N+ cylinders 320 in pad 330,331 establishes diode.Interlayer is led Body 326,327, for example may include tungsten plug (tungsten plugs), is connect in a stair-stepping structure from source electrode line P+ regions extension in touch pad 330,331, and provide to be connected to one second source electrode line (not shown) or in each level Multiple second source electrode lines are separated in face.P1PNS shown in Fig. 2A is that upper strata diode source is extreme, P2PNS is lower diodes Source terminal, SC are source contact end (function is the source electrode of traditional NAND string row).

Fig. 2 B illustrate the side view of the carrier Supply Structure of a replacement, and similar element is with reference to identical component symbol. In this structure, bit line 202,203 extension semiconductor interface touch pad, including be connected to one first source electrode line (not shown) one hang down Straight N+ semi-conducting materials cylinder 345.Semiconductor interface touch pad also includes the vertical P+ semi-conducting materials being connected with engagement pad Cylinder 346, and produce PN junction 342,343.Vertical cylinder 346 is used for connecting one second source electrode line (not shown).

Fig. 2 C illustrate the side view of the carrier Supply Structure of another replacement.In this example, bit line (is e.g. terminated In the bit line 202 of knot 350) terminate at the vertical N+ semi-conducting material cylinders of one be connected with one first source electrode line (not shown) 355.Vertical cylinder is coupled to a P+ regions 351 in Semiconductor substrate 302, and a PN junction 353 is set up at interface.One layer Between conductor 356, for example may include that there is provided for connecting the source electrode line (not shown) of P+ regions 351 and 1 second for a tungsten plug. Multiple diode carrier Supply Structures that Fig. 2A-Fig. 2 C are illustrated can be used together with three-dimensional storage.Suitable storage can also be used The other structures of device and the practising way of other elements.

Fig. 3, Fig. 3 A, Fig. 3 B, Fig. 4, Fig. 4 A, Fig. 4 B, Fig. 5, Fig. 5 A, Fig. 5 B, Fig. 6, Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D, figure 7th, Fig. 7 A and Fig. 7 B illustrate the different phase of the technique for manufacturing the storage organization such as Fig. 2, and storage organization has such as Fig. 2A One carrier Supply Structure.Fig. 3 illustrates a plan for being used for manufacturing the material upper strata 500 of bit line, as foregoing upper strata 500 can be covered Above the active material and the lamination of insulating materials that Gai Yi interlocks.Can be semiconductor for manufacturing the material of multiple bit lines Material is, for example, the polysilicon layer of siliceous deposits.Alternatively, material can be a single-crystal semiconductor material or other kinds of half Conductor material.Material can be adapted to being relatively lightly doped as passage in thin film transistor (TFT), or suitable specific demand Constitutionally (intrinsically) doping.For N-shaped channel thin film transistors, there is material a p types to be lightly doped or essence Doping.

As shown in Figure 3, formed after active material staggeredly and insulating materials, form multiple through holes through lamination (vias) (being, for example, 501,502,503), multiple through holes at least extend to the bottom of active material.With multiple bit line laminations Structure, forms multiple through holes, one bit line of each hole correspondence.Multiple through holes (such as 501,502,503) are interlocked by patterning The lamination of active material and insulating materials is directed at the position of multiple bit lines.

Fig. 3 A illustrate the side view diagram of the lamination of active material and insulating materials staggeredly.At this visual angle, one can be with It is to be covered with an insulation material layer 305 above the substrate 302 of semiconductor or other kinds of material.One first active material 511 and one second active material 510 be to be separated by an insulating barrier.One top insulator material layer 509 is covered on lamination.One leads to Hole 501 forms through top insulator material layer 509 and at least extends to the first active material 511.

Fig. 3 B illustrate the side view with the lamination after a filling through hole 501 of semi-conducting material 512 with N+ doping.Can A planarisation step is carried out so that a surface of the top alignment top insulator material layer 509 of semi-conducting material.

The structure that Fig. 4 is illustrated in Fig. 3 carries out the plan after pattern etched technique.Pattern etched defines multiple positions Linear contact lay pad (be, for example, 202-A, 202-B, 202-C and 202-D) with as shown in Figure 2 be used in each three-dimensional block A, B, In C, D.Pattern etched also defines source line engagement pad (be, for example, 220), and source line contact pad is (for example in this example It is 220) to be shared by four blocks.Multiple semi-conducting material bit lines (being, for example, 202-1,202-2,202-8) are from source line contact Pad (being, for example, 220) extends to a corresponding bit line contact pad (being, for example, 202-A, 202-B, 202-C and 202-D).

As shown in Figure 4, pattern etched is also etched through the semiconductor material of filling through hole (being, for example, 501,502,503) Material 512, through hole is illustrated in Fig. 3.Therefore, N+ types semi-conducting material cylinder (being, for example, 550-1,550-2,550-8) connection first The bit line in bit line and upper layer in layer, and the width of N+ types semi-conducting material cylinder meets the width of bit line in this example Degree.In other embodiments, can there can be a variety of width according to the pattern in the region of desired multiple cylinders.

Fig. 4 also illustrates the region 224 that P+ doping is carried out in source line contact pad (being, for example, 220).

Fig. 4 A illustrate the lamination side view along wherein one bit line (being, for example, 202-2).Therefore, the first semi-conducting material Layer and the second semiconductor material layer have been patterned to define the lamination of bit line, in the lamination of this two layers of example neutrality line Including lower floor bit line 203-2 and upper level bitline 202-2.Fig. 4 A illustrate charge storing structure layer 519 and are deposited on patterning On bit line.One mask is, for example, that photolithographic mask 555 is also covered in structure, and photolithographic mask 555 has an opening exposed region 224 To carry out P+ injections 556.Injected with enough energy progress P+ under make it that P+ is doped into first, second active material Layer, upper strata source line contact pad.

Fig. 4 B illustrate the structure injected and removed after mask 555.Fig. 4 B structure includes the second source contact pads In with the P+ areas in the source contact pads of P+ areas 557 and second of upper level bitline 202-2 same layers with lower floor bit line 203-2 same layers 558。

Fig. 5 illustrates the plan after the technique to form wordline, ground connection selection line and serial selection line.Technique may include with One filling is located at the mode of multiple raceway grooves between multiple bit lines, and one P+ or N+ DOPOS doped polycrystalline silicons of deposition are in charge storing structure On (Fig. 5 is not illustrated), thus between multiple bit lines (be, for example, 202-1,202-2,202-8) form vertical gate structure.

This technique make it that horizontal wordline (being, for example, 125-0,125-5,125-15) and horizontal grounding selection line 127 are covered On bit line (being, for example, 202-1,202-2,202-8).Serial selection line grid structure also covers bit line, including for coupling position Serial selection line grid structure 119-A1,119-A2 of line and engagement pad 202-A, for coupling bit line and engagement pad 202-D's Similar serial selection line grid structure is not indicated with reference to symbol in serial selection line grid structure 119-D1,119-D2, block B, C Number.Flash memory cell is formed between the vertical gate structure in multiple bit lines and on a plurality of wordline 125-0 to 125-15 Crosspoint, flash memory cell is made up of film, bigrid and charge-stroage transistor.Double gate transistor is formed at a plurality of Bit line and the crosspoint between ground connection selection line 127 and the serial vertical gate structure selected in structure, double grid polar crystal Pipe optionally couples serial in bit line contact pad or carrier Supply Structure along the memory cell of bit line as switch.Figure 5A, Fig. 5 B figures illustrate wordline, the side view of ground connection selection Wiring technology, a P+ or N+ doped polysilicon layers are deposited as shown in Figure 5 A 565 in charge storing structure layer 519 on, then as shown in Figure 5 B in after patterned polysilicon layer 565 formed wordline (for example It is 125-N, 125-N-1,125-N-2) with being grounded selection line (being, for example, 127), serial selection line (figure is not illustrated) is also walked herein It is rapid to be formed.

Fig. 6, which is shown in source line contact pad 220, forms opening 220A, 220B, 220C and 220D and in bit line contact pad The plan formed in (being, for example, 202-A, 202-B, 202-C and 202-D) after the technique of corresponding opening.These openings The bit line contact pad of source line contact pad (being, for example, 223) and lower section below exposure (is, for example, 203-A, 203-B, 203-C And 203-D) therefore interlayer contact (interlayer contacts) can be formed.Also one is illustrated in figure is used for the pattern of N+ doped regions, Including positioned at multiple bit line contact pad Shang N+ area 524-1, positioned at multiple serial selection structures (being, for example, 119-A1) and first N+ areas 542-2 between wordline 125-0 and the N+ areas on multiple N+ cylinders in multiple bit lines (being, for example, 550-2) 524-3.Also part is covered on source line contact pad 220 and extends upwardly to or connect along multiple bit lines N+ areas 524-3 Proximity ground selection line 127.

Fig. 6 A illustrate the structure in similar Fig. 5 B, and the structure has a mask being covered in (photolithographic mask) 579, mask 579 has the opening corresponding to region 524-3.Opening allows N-type The injection 524 of dopant, and lower floor bit line 203-2 is injected into as shown in FIG..

Fig. 6 B form stair-stepping opening 220A after being shown in removal mask 579 (see Fig. 6).As depicted in figure 6b, one PN junction 592 is to be formed between upper strata Zhong N+ areas 590 and upper strata Zhong P+ areas 557.Similarly, a PN junction 593 is to be formed Between Zhong N+ areas of lower floor 591 and Zhong P+ areas of lower floor 558.

Fig. 6 C illustrate the formation positioned at superstructure insulation fill stratum 600, can carry out planarization insulation fill stratum 600 and expose Upper surface of a plurality of wordline (being, for example, 125-N) with ground connection selection line 127.Then, silicide layer 598, e.g. cobalt silicide are It is formed on ground connection selection line and a plurality of wordline.In the preferred embodiment, silicide layer 598 is also formed in serially selecting structure On (not showing in Fig. 6 C).

Fig. 6 D illustrate another interlayer dielectric packed layer 601 being formed on silicide layer.Interlayer dielectric packed layer 601 is exhausted The patterning conductor layer of edge wordline, ground connection selection grid and serial selection grid structure and overlying.

Fig. 7 illustrates the plan after the technique for forming interlayer contact in the structure.Structure includes source line contact pad 220th, in 223 the rank in stepped contact (being, for example, 410,410A) and bit line contact pad (being, for example, 202-A, 203-A) Scalariform contact (being, for example, 420,420A).Structure also includes being located at stepped above serially selection structure (being, for example, 119-D1) Contact (being, for example, 430).Fig. 7 incorporates many features being set forth in Fig. 4, Fig. 5, Fig. 6.

Fig. 7 A illustrate the side view of opening 605,606,607, and the opening 605,606,607 of formation passes through packed layer (for example It is 601,600) with charge storing structure layer 519 with formation and N+ cylinders 550-2 contact, formation and upper strata source line contact pad P+ regions 557 contact and the formation contact with the P+ regions 558 of lower floor source line contact pad.

Fig. 7 B are illustrated after the conductor filled opening of interlayer, form interlayer conductor 610,611,612, e.g. tungsten plug or its His conductive structure, planarizes obtained structure so that body structure surface suitably forms one or more overlying patterned conductive layers.

As shown in fig.7b, carrier Supply Structure include by N+ areas 550-2, be each located at the corresponding N+ areas of line with along source Pole engagement pad Zhong P+ areas 557,558 form PN junction 592,593.Carrier Supply Structure also includes interlayer conductor 610,611,612. These interlayer conductors provide first, second source line contact being used for overlying, will be further described below.

Fig. 8, Fig. 8 A, Fig. 8 B, Fig. 9, Fig. 9 A and Fig. 9 B illustrate multiple techniques of the carrier Supply Structure in manufacture such as Fig. 2 B Stage.The pattern etched after the cross laminates formation that active material and insulating materials are illustrated by Fig. 8, in figure.At this In etching, bit line 202-1,202-2,202-8 of formation a first end be connected to bit line contact pad (be, for example, 202-A, 202-B、202-C、202-D).One second end of bit line is to be connected to source line contact pad (being, for example, 220).In this example In, opening 650-1 to 650-8,651-1 to 651-8 is formed in source line contact pad (being, for example, 220).In this example In, two opening (being, for example, 650-2,651-2) wherein one bit lines of alignment (being, for example, 202-2).

Fig. 8 A are shown in opening 650-2,651-2 along bit line 202-2 formation in bit line contact pad, the 650-2 that is open, 651-2 extends into lower floor bit line 203-2.

Illustrated in Fig. 8 B with semi-conducting material filling opening 650-2,651-2, formed with active material (be, for example, 510, 511) cylinder 665,666 of the bit line contact in.Surface can be planarized then charge storing structure layer 519 and is formed at On the lamination of multiple bit lines.

Fig. 9 illustrates the plan for the structure that the above-mentioned multiple steps relevant with the first manufacturing process are made.Therefore, plan In illustrate stepped contact in bit line contact pad, the contact in serial selection structure and two groups of contact (750-1 to 750-8 With 751-1 to 751-8).Interlayer connection 750-1 to 750-8 is connected to the cylinder formed in source line contact pad, e.g. reference The cylinder formed in Fig. 8 A, Fig. 8 B.Fig. 9 plan, which is also illustrated, is covered in the neighbouring ground connection selection line 127 of source line contact pad Partial N+ injection regions 725-1, the N+ injection regions 725-2 between the first wordline and serial selection structure and covering are in place The N+ injection regions 725-3 in linear contact lay pad area.Fig. 9, which also illustrates to be covered in source line contact pad (being, for example, 220), offs normal line farther out Region P+ injection regions 724.

Result of the injection close to the region of source line contact pad is illustrated in Fig. 9 A, injection formation is carried out in the 725-1 of region N+ cylinders 651 and N+ parts (being, for example, 652) in the source line contact bed course of upper strata and lower floor, are noted in region 724 The P+ cylinders 661 entered to be formed in the source line contact bed course of upper strata and lower floor and P+ parts 653,654.Therefore formed in the structure PN junction 656,655.

Fig. 9 B, which are shown in structure, forms silicide layer 598, interlayer dielectric filling 650 and interlayer connection 751-2,750- The structure of 2 technique.It can be seen that carrier Supply Structure as shown in Figure 2 B is formed by this flow.

Figure 10, Figure 10 A, Figure 10 B, Figure 11, Figure 11 A and Figure 11 B illustrate many of the carrier structure of manufacture as shown in FIG. 2 C Individual operation stage.The pattern etched after the cross laminates formation that active material and insulating materials are illustrated by Figure 10, in figure. In this etching, bit line 202-1,202-2,202-8 of formation a first end are to be connected to bit line contact pad (to be, for example, 202-A、202-B、202-C、202-D).One second end of bit line is to be connected to source line contact pad (being, for example, 220).At this In individual example, etching upper strata source line contact pad (being, for example, 220) is with a part for exposing semiconductor substrate.Also formed through upper Layer source line contact pad is until the opening 850-1 to 850-8 of the horizontal plane of lower floor's source line contact pad.This plan is also illustrated It is used for the region 824 of P+ injections for forming P+ regions 351 in substrate 302.

Figure 10 A are the side views of the lamination along bit line 202-2,203-2, illustrate to extend through and are stacked in substrate 302 P+ regions 351 opening 850-2.

Figure 10 B illustrate the side view after the formation of semiconductor material N+ cylinders (cylinder 355), semi-conducting material N+ posts Body extends through source line contact pad 220 and is coupled to multiple bit lines.PN junction is formed at being located at N+ cylinders (cylinder body 355) and P+ Interface between area 351, sets up the diode of carrier Supply Structure.Also charge storing structure layer 519 is illustrated in 10B figures in figure Formation above the bit line of case.

Figure 11 illustrates the plan for the structure that the above-mentioned multiple steps relevant with the first manufacturing process are made.Therefore, plane Stepped contact in bit line contact pad, the contact in serial selection structure are illustrated in figure, positioned at source line contact pad 220 The interlayer conductor (859-1,859-2,859-8) and one that one group forms in the way of with reference to above-mentioned Figure 10 A, Figure 10 B in region Group is used for the interlayer conductor (869-1,869-2,869-8) for being connected to substrate Zhong P+ areas 351.Figure 11 also illustrates the area of P+ injections Domain 824, the N+ injection regions 825-1 on source line contact pad 220, the N+ between the first wordline and serial selection structure The injection region 825-2 and N+ injection regions 825-3 on bit line contact pad.

Figure 11 A are analogous to Fig. 6 C side view, illustrate the charge storing structure 519 to form covering bit line, horizontal wordline (being, for example, 125-N, 125-N-1,125-N-2) and the result of horizontal grounding selection line 127.

Figure 11 B illustrate silicide layer 598, insulation filling 855, connection N+ cylinders (cylinder 355) interlayer conductor 859-2 with And the result of the interlayer conductor 869-2 in connection substrate 302 Zhong P+ areas 351 formation.It can be seen that PN junction 353 is by shape Into and set up the diode of carrier Supply Structure.

Figure 12 to Figure 15 is the wherein block in two layers of cubical array, e.g. illustrates the knot of block A in fig. 2 Structure schematic diagram, block can have any one in Fig. 2A-Fig. 2 C carrier Supply Structure.Although being accorded with herein using regular transistor Number, but the embodiment of the present invention is included without knot NAND string row (junction-free NAND strings).

In order to clearly represent, the term " programming " that the present invention is used is related to the threshold voltage of increase memory cell One operation of (threshold voltage).Logical zero can be expressed as or patrol by being stored in the data of memory cells Collect " 1 ".The term " erasing " that the present invention is used is related to an operation of the threshold voltage of reduction memory cell.Erasing is stored in deposit The data utilogic " 1 " or logical zero of storage unit is represented.Multi-bit cell (multibit cells) also can be according to designer Expectation programming and have one single minimum or most with multiple different critical levels (threshold levels) or erasing High critical level.In addition, term " write-in " description that the present invention is used changes an operation of the threshold voltage of memory cell, and Expect the combination comprising both programmed and eraseds or programming and erasing operation.

The programming operation that the present invention is described include be biased in the memory cell of selection with inject electrons into one selection Charge storing structure in memory cell, therefore increase threshold voltage.One programming operation can be carried out to program e.g. one page (page), a character or the memory cell of one or more selections in a hyte.In programming operation, non-selected deposit is biased in Storage unit is to avoid or reduce the upset (disturbance) of the electric charge of storage.

The present invention describes the block erasing operation for N-shaped channel memory, including is biased in an area of multiple units In charge storing structure unit in block of the block to inject holes into selection, therefore reduction threshold voltage, block is at least Multiple units threshold voltage not low at the beginning.Other programmed and erased biased operations may be used.

By taking two layers of 3-D stacks structure as an example, as shown in Figure 12, it will include up and down according to double-layer structure block such as Fig. 2 Totally four NAND string rows, upper strata dual serial is coupled to bit line layer BLL1, and lower floor's dual serial is coupled to bit line layer BLL2.It is multiple The serial selection structure of one first lamination in the lamination of bit line includes being connected to the serial selection of a serial selection line SSL1 Switch 824-1,824-2.Similarly, the serial selection structure of one second lamination in the lamination of multiple bit lines includes being connected to One serial selection line SSL2 serial selecting switch 825-1,825-2.Ground connection selection line GSL is covered in a plurality of positioned at line, formation Four grounded selecting switch 814-1,814-2,814-3 and 814-4.Bit line is also coupled to the N-type end 801 of PN diodes 800, and It is sequentially that one first source electrode line 803 is first coupled to by contact 804-1,804-2,804-3 and 804-4.The P of PN diodes 800 Type end is coupled to one second source electrode line 802.Identical circuit structure is illustrated in 12-15 figures.

Figure 12 illustrates a bias arrangement of the unit for programming a selection.Figure 13 is illustrated for wiping multiple memory cell In a block one bias arrangement.Another bias that Figure 14 illustrates for wiping the block in multiple memory cell is arranged Row.Figure 15 illustrates a bias arrangement of the unit for reading the selection in block.

Therefore, storage circuit includes a series arrangement (series arrangement) for multiple memory cell, is, for example, Including the serial of memory cell 840,842,845 and 847.A second switch in one second end of series arrangement is (e.g. 814-1) it is coupled to a first end of diode.Storage circuit also includes a plurality of wordline WL.Circuit is coupled to a plurality of wordline, One and second source electrode line, ground connection selection line GSL, sequence selection line SSL and the bit line for controlling storage circuit to operate.Herein In structure, circuit is configured to different first, second source electrode lines of bias condition driving or bias.Controller may include configuration For applying the arrangement of erasing bias, program bias arrangement and a reading bias arrangement of induction hole generation.Controller The narration in Figure 17 is referred to as after.

Figure 12 illustrates program bias arrangement.In this bias arrangement, apply a source side and be biased in the first source electrode line 803 (such as the first source contact end SC=0), when the second source electrode line 802 receives a bias or the second source of reverse bias diode When polar curve 802 is in the state of floating (floating) so that diode is closed and can not transmit electric current to the second source electrode line 802, now the diode of source terminal do not interfere with the programming of element.

Program bias arrangement as illustrated in Figure 12, is to be described as follows in one embodiment：

The wordline BL of selection：0V

Non-selected wordline BL：3.3V

The serial selection line SSL of selection：3.3V

Non-selected serial selection line SSL：0V

The wordline WL of selection：Vpgm

Non-selected wordline WL：Vpass

It is grounded selection line GSL：0V

Source contact end SC：0V

PN junction source terminal PNS：0V (closing of PN diodes)

The arrangement of this program bias can represent the programming pulse in a programming operation, e.g. increase rank type pulse program (Incremental Step Pulsed Programming, ISPP) method, for more traditional flash memory, it is not necessary to Extra carrier supply, and what diode system closed.

Figure 13 illustrates the erasing bias arrangement of an induction tunneled holes.In one embodiment, erasing is inclined as illustrated in Figure 13 Pressure is arranged, and is to be described as follows：

All bit line BL：Float

All serial selection line SSL：0V

All wordline WL：-8V

It is grounded selection line GSL：-2V

Source contact end SC：Float

PN junction source terminal PNS：V ＞ Vbi (unlatching of PN diodes)

PN diodes are to open in this erasing operation, it is possible to provide the one of hole originates to carry out tunneled holes wiping Remove.Gate Induced Drain electric leakage can also provide hole to bit line in ground connection selection wiretap.

Figure 14, which is illustrated, utilizes the another of the serial Gate Induced Drain electric leakage for selecting structure and ground connection to select both structures Erasing bias arrangement.Erasing bias arrangement as illustrated in Figure 14, is to be described as follows in one embodiment：

All bit line BL：-8V

All serial selection line SSL：-2V

All wordline WL：-8V

It is grounded selection line GSL：-2V

Source contact end SC：Float

PN junction source terminal PNS：V ＞ Vbi (unlatching of PN diodes)

Diode is to open in this erasing bias arrangement, source contact is kept in a reference voltage, when the first source When polar curve is in quick condition, the first source electrode line is not involved in bias.In order to induce the formation in hole, serial selecting switch receives one Suitable negative-gate voltage so that Gate Induced Drain leaks electricity.The memory cell for being biased in selection produces FN tunneled holes.

Figure 15 illustrates reading bias arrangement.In this reading bias arrangement, diode is what is closed, and signal can be by the Source-side is spread out of, it is allowed to according to the operation of more typical read method.In one embodiment, bias is read as illustrated in Figure 15 Arrangement system is described as follows：

The wordline BL of selection：1V

Non-selected wordline BL：0V

The serial selection line SSL of selection：3.3V

Non-selected serial selection line SSL：0V

The wordline WL of selection：Vref

Non-selected wordline WL：Vpass

It is grounded selection line GSL：3.3V

Source contact end SC：0V

PN junction source terminal PNS：0V (closing of PN diodes)

Diode is biased in reading process so that diode two ends do not have pressure drop, in order to be read with efficient at a high speed Take, the bias voltage of diode keeps load.

The schematic diagram of the alternative circuit of Figure 16 marks one, represents enforceable different another structure.In this structure, often One layer there is respective carrier to supply diode.Therefore being coupled to bit line layer BLL1 layer, there is a diode to include a first end 866 and one second end 865.Being coupled to bit line layer BLL2 layer, there is a diode to include a first end 861 and one second end 860.Single second source electrode line 862 and 867 is the second end for being connected to diode.Can be as discussed above and with reference to 12- The mode of 15 figures applies different bias arrangements to the circuit shown in Figure 16.

Figure 17 is the simplification block diagram of an integrated circuit 25, and integrated circuit 25 includes a p-type passage, can implemented by the present invention The nand flash memory array 10 of example operation.In certain embodiments, array 10 is to include the three-dimensional storage of multilayered memory unit.One Column decoder 11 is coupled to multiple bit lines 12 along the row arrangement in storage array 10.Multiple line decoders in square 16 are by coupling One group of page buffer (page buffers) 13 is connected to, is to be coupled via data/address bus (data bus) 17 in this embodiment. Global bit lines (global bit lines) 14 are coupled to local bitline (local bit along the row arrangement in memory Lines) (not shown).Position (addresses) is sent to line decoder (square 16) and column decoder (square via bus 15 11).In addition, can be derived from circuit by square 20 includes the driver for the first and second source electrode lines so that the first and second sources Polar curve can be separately or independently biased.

Data are from other circuits 24 (including being, for example, input/output end port) on integrated circuit via Data In-Line 23 To provide, integrated circuit is, for example, a general processor (general purpose processor), special-purpose applications circuit (special purpose application circuitry) or provide the system single chip supported by the feature of array 10 (system-on-a-chip) combination of module.Data are sent to input/output end port, inside other via Data In-Line 23 Data destination or to outside integrated circuit 25.

One controller, in one embodiment e.g. state machine (state machine) 19 there is provided signal with control via The bias arrangement that one or more voltage controllers in square 18 are provided or produced supplies the application of voltage to implement in the present invention Different operations include the reading and write operation in array.These operations include erasing, programming or read.Controller can be by Know the special purpose logic circuitry (special-purpose logic circuitry) of technology to carry out.In another embodiment In, controller includes the general processor that may be implemented on same integrated circuit, and general processor performs computer program to control The operation of device processed.In another embodiment, special purpose logic circuitry and general processor can be used in the implementation of controller Combination.

Controller may include the circuit for performing a program, and program includes being biased in forward bias voltage drop condition in operation Diode changes a threshold voltage of one or more memory cell in memory to provide minority carrier to series arrangement, is reading Diode is biased in reverse bias condition during taking.For example, the program performed by the circuit in controller may include Diode is biased in a forward bias voltage drop condition during erasing operation.The program performed by the circuit in controller can also be wrapped Include and diode is biased in a reverse bias condition during programming operation.

Described structure includes the three-dimensional in an additional PN diodes source in the source side of NAND string row in an array The performance of erasing can be improved in memory.

In one embodiment, carrier Supply Structure is disposed in vertical gate nand flash memory.During operation, because film is brilliant The electronic tunnelling erasing of body pipe (TFT) structure and shortage body contact three-dimensional perpendicular Gate Memory may have with traditional NAND Very big difference.In that case, hole source can improve device erasing.

In summary, although the present invention it is disclosed above with preferred embodiment and detailed example, so itself and be not used to limit The fixed present invention.It will be appreciated that persond having ordinary knowledge in the technical field of the present invention, is not departing from the spirit of the present invention In scope, when can be used for a variety of modifications and variations.Therefore, protection scope of the present invention is when regarding appended claims scope institute That defines is defined.

Claims (24)

1. a kind of semiconductor array arrangement supplied including carrier, including：

One diode, with a first end and one second end；

One series arrangement (series arrangement), including multiple memory cell, the series arrangement is by a first end A first switch be coupled to a bit line, the first end of the diode is coupled to by the second switch in a second end；

One first source electrode line and one second source electrode line, are connected to the first end and second end of the diode；

A plurality of wordline, these wordline are coupled to these corresponding memory cell in multiple memory cell；And

One circuit, is coupled to these wordline, first source electrode line and second source electrode line, and the circuit is configuration with different biass Under the conditions of bias first source electrode line and second source electrode line.

2. semiconductor array arrangement according to claim 1, the wherein circuit are configurations with an erasing bias arrangement (erase bias arrangement), to induce tunneled holes, erasing bias arrangement is included in one on second source electrode line Source side is biased, and source side bias is the forward bias voltage drop diode, when first source electrode line keeps floating, in these wordline Erasing voltage induce tunneled holes.

3. semiconductor array arrangement according to claim 1, the wherein circuit are configurations with program bias arrangement (program bias arrangement), program bias arrangement includes the source side bias on first source electrode line, should Second source electrode line keeps floating or being subjected to being biased to the reverse bias diode.

4. semiconductor array arrangement according to claim 1, wherein these memory cell include multiple thin film transistor (TFT) lists Member.

5. semiconductor array arrangement according to claim 1, wherein these memory cell include being arranged in one single half Multiple film crystal pipe units on conductor bar, the first end of the diode includes a doping in the single semiconductor bar Area.

6. semiconductor array arrangement according to claim 1, wherein these memory cell include being arranged in one single half Multiple film crystal pipe units on conductor bar, the first end of the diode and second end in the single semiconductor bar Each include a doped region.

7. semiconductor array arrangement according to claim 1, wherein these memory cell include being arranged in being covered in half Multiple film crystal pipe units on a single semiconductor bar above conductor substrate, first end of the diode includes coupling A doped semiconductor materials of the single semiconductor bar and the Semiconductor substrate are connected to, second end of the diode is included in A doped region in the Semiconductor substrate.

8. semiconductor array arrangement according to claim 1, the wherein series arrangement are that a NAND gate (NAND) is serial, should At least one extra NAND gate that semiconductor array arrangement includes being coupled to the first end of the diode is serial.

9. semiconductor array arrangement according to claim 1, wherein these memory cell are configuration in a read mode For a N-shaped channel operation, the first end of the diode has N-shaped doping, and there is p-type to mix at second end of the diode It is miscellaneous.

10. semiconductor array arrangement according to claim 1, wherein these memory cell are configuration in a read mode For a p-type channel operation, the first end of the diode has p-type doping, and there is N-shaped to mix at second end of the diode It is miscellaneous.

11. semiconductor array according to claim 1 arrangement, wherein these memory cell include a film, multiple vertical Grid unit.

12. a kind of semiconductor array arrangement supplied including carrier, including：

Each in one cubical array, including multiple horizontal planes, these horizontal planes includes an engagement pad and prolonged from the engagement pad The multiple bar of semiconductor material stretched；

Multiple first diode ends, one of these the first diode ends are one or more these semiconductor materials on long-range One contact point of material strip；

One in one second diode end, these the first diode ends of the second diode end in contact；

One first source electrode line, is connected to these the first diode ends；

One second source electrode line, is connected to the second diode end；

A plurality of wordline, is coupled to these bar of semiconductor material in these horizontal planes；

One charge-trapping element and a data storage elements, between these wordline and these bar of semiconductor material, wherein many Individual memory cell is provided on the crosspoint of these bar of semiconductor material and these wordline；And

One circuit, is coupled to first source electrode line and second source electrode line, and the circuit is to be used to bias under different bias conditions First source electrode line and second source electrode line.

13. semiconductor array arrangement according to claim 12, the wherein circuit are configurations with an erasing bias row Row are to induce tunneled holes, and erasing bias arrangement is included in the source side bias on second source electrode line, the source electrode lateral deviation Pressure is the diode of forward bias voltage drop one, when first source electrode line keeps floating, and the erasing voltage in these wordline induces hole tunnel Wear.

14. semiconductor array arrangement according to claim 12, the wherein circuit are configurations with program bias row Row are to close diode end, and program bias arrangement includes the source side bias on first source electrode line, when second source electrode When line keeps floating or being pressurized to the reverse bias diode, now diode end does not influence element programs.

15. semiconductor array arrangement according to claim 12, further includes a plurality of first choice line and one second selection line, These first choice lines are coupled to these corresponding semiconductors in these bar of semiconductor material of a near-end of these engagement pads The lamination of material strips, second selection line is covered in these semiconductors between these the first diode ends and these wordline Above material strips.

16. semiconductor array arrangement according to claim 12, wherein these the first diode ends include being located at these partly Multiple doped regions in conductor material strips.

17. semiconductor array arrangement according to claim 12, wherein these the first diode ends and second diode End includes the multiple doped regions being located in these bar of semiconductor material.

18. semiconductor array according to claim 12 arrangement, wherein these horizontal planes be covered in semi-conductive substrate, this On a little first diode ends and the second diode end, these the first diode ends include being coupled to these bar of semiconductor material A doped semiconductor materials, the second diode end include be located at the Semiconductor substrate in a doped region.

19. semiconductor array arrangement according to claim 12, wherein these memory cell are to match somebody with somebody in a read mode Put for a N-shaped channel operation, these the first diode ends include n-type semiconductor, the second diode end includes p-type half Conductor material.

20. semiconductor array arrangement according to claim 12, wherein these memory cell are to match somebody with somebody in a read mode Put for a p-type channel operation, these the first diode ends include p-type semiconductor material, the second diode end includes N-shaped half Conductor material.

21. semiconductor array according to claim 12 arrangement, wherein these memory cell include a film, multiple vertical Grid unit.

22. a kind of method for operating the three-dimensional flash memory (3D flash memory) for including carrier supply, the three-dimensional flash memory includes One series arrangement of multiple memory cell, and one first source electrode line and one second source electrode line, are connected to a diode One first end and one second end, a first end function of the series arrangement are the source-side of traditional NAND memory element, And a second end of the series arrangement is an operating side of the diode PN junction, the first end of the series arrangement is coupled to The diode, second end of the series arrangement is coupled to a bit line, and this method includes：

Under the conditions of a forward bias voltage drop diode is biased in operating process to provide the series arrangement minority carrier to change one Or a threshold voltage of multiple memory cell, the diode is biased under the conditions of a reverse bias in reading process.

23. method according to claim 22, including：During erasing operation, biased under the conditions of a forward bias voltage drop The diode.

24. method according to claim 22, including：During procedure operation, biased under the conditions of a reverse bias The diode.