TWI574266B - And-type sgvc architecture for 3d nand flash - Google Patents

Description

AND type SGVC structure for three-dimensional anti-gate flash memory [related application]

The present application claims priority to US Provision No. 62/117,958 patent provisional patent application, filed on Feb. 9, 2015, which is incorporated by reference. The full text of this patent is included in the disclosure.

The present invention relates to a high density memory device, and more particularly to a memory device in which a complex plane of a plurality of memory cells is arranged in a three-dimensional 3D array.

A high density memory device is designed to include multiple arrays of flash memory cells or other types of memory cells. In some embodiments, the memory cells comprise thin film transistors that can be arranged in a three-dimensional structure.

A three-dimensional memory device can include a memory cell and a gate string (NAND An array of strings). The memory device can include a stack of integrated circuit substrates and a plurality of conductive strips separated by an insulating material, the stacks including at least as a ground select line (GSL) a bottom plane of the conductive strip, a plurality of intermediate planes for the conductive strips of the word line (WL), and a conductive strip for use as a string select line (SSL) A top plane of the belt. Active strips are disposed over these stacks and are orthogonally aligned above these stacks. A memory cell including a charge storage structure forms a cross-point of the side surface of the active strip on the stacks with the word lines.

A three-dimensional memory device can include different metal layers to routing word lines, string select lines, ground select lines, bit lines connected to active strips, and the like. For example, a first metal layer on a stack of the conductive strips may include a plurality of conductor lines for wiring local source lines, located first A second metal layer on the metal layer may include a plurality of wires for wiring the bit lines, and a second metal layer on the second metal layer may include Multiple wires of the wiring word line, the string selection line, and the ground selection line. A tandem select line (SSL) in the top plane of the conductive strip is routed to a row of decoders in the three dimensional memory device. The column decoder decodes the serial select line and the ground select line to perform read, write, and erase operations of the memory cells in the three-dimensional memory device. The third metal layer includes individual wires of respective string select lines in the three dimensional memory device. For example, for 32 serial select lines in 32 anti-gate trains, the third metal layer includes 32 wire traces to 32 string select lines. Serial selection in a metal layer (eg, a third metal layer) The wiring efficiency of the line selection is affected by the string select structure.

Therefore, there is a need to provide an efficient serial selection structure for three-dimensional integrated circuit memory.

The present disclosure provides an efficient tandem structure that improves wiring efficiency by reducing the number of traces of a tandem select line on a metal layer to a column decoder. In one embodiment, for (N times K) string select lines, the number of wires on the metal layer used to route the select line to column decoder is reduced from (N x K) to (N+ K), where N and K are positive integers. For example, if N=4 and K=8, the number of wires on the metal layer is reduced from (N x K=4 x 8=32) to (N+K=4+8=12).

A memory device includes a plurality of strings of a plurality of conductive strips. a plurality of stacks of a plurality of conductive strips, including a plurality of first upper strips, a plurality of second upper strips, and a plurality of intermediate strips, The first upper strips are used as a plurality of first string select lines in the series, and the second upper strips are used as the second plurality of strings in the series A second string select line, which is a plurality of word lines in the series. The second upper strips may be disposed between the first upper strips and the intermediate strips.

The memory device includes a first series of select lines coupled to the first a control circuit of the second series of select lines, and by applying a first turn-on voltage to one of the first series of select lines coupled to a particular string, And applying a second turn-on voltage to one of the second series of select lines coupled to the particular string for selecting the particular string. The second starting voltage is lower than the first starting voltage.

The control circuit is configured to apply a turn-off voltage to one or both of the first series select lines of one of the first series select lines and one of the second series select lines Deselecting a particular one of the series of strings, the first series of select lines being coupled to the particular series, the second series of select lines being coupled to the particular series.

Such strings of such memory cells include complex arrays of strings. The memory device includes a plurality of first string select structures, wherein each first column select structure is coupled to the first string of the respective one of the plurality of string groups a selection line, and a plurality of second string select structures, wherein each of the second string selection structures is coupled to a respective second string of each of the plurality of strings in the complex array string Select the line. Combining a first serial column selection structure of the first serial column selection structure with one of the second serial column selection structures of the second serial column selection structures to select a column in the complex array string . Each of the second series selection structures is coupled to the plurality of strings in the respective string groups in the complex array string.

Such series of such memory cells include K sets of N strings. The memory device can include K first serial selection structures. Each of the K first series selection structures is coupled to N first series selection lines in a respective one of the N series of the K groups, and N second serial selection structures, wherein each N The second string selection structure is coupled to one of the N series of the K groups. Selecting a first string selection structure of the K first series selection structures and a second string selection structure of the N second series selection structures to select N of the K groups A list of columns in a string.

The K first series selection structures may include K first linking elements in a first patterned conductor layer, the first patterned conductor layer being located on the conductive strips Above the stack of strips, wherein each of the K first joining elements connects N first string select lines in a respective one of the N series of the K sets. The N second series selection structures may include N second linking elements in the first patterned conductor layer, wherein each N second linking elements are connected to the N series of the K group A separate second string selection line in each of the groups.

The K first series selection structures may include a plurality of first interlayer connectors, wherein the first interlayer connectors respectively connect K first patterned conductor lines to The K first joining elements. The N second series selection structures include a plurality of second interlayer connectors, and the second interlayer connectors are respectively connected with N second patterned conductor lines to the Nth Two connecting elements. The K first patterned wires and the N second patterned wires are disposed at one or more patterned conductor layers of the first patterned conductor layer The K first patterned wires and the N second patterned wires connect the N series of the K groups to a string decoder.

In an embodiment, the stacks comprise a plurality of even stacks and a plurality of odd stacks. The memory device includes a plurality of data storage structures located on a plurality of even-numbered stacks and a plurality of odd-numbered stacked sidewalls of a plurality of conductive strips corresponding to the stacks, and a plurality of data storage structures The semiconductor films are disposed on the data storage structures, the data storage structures are on the sidewalls of the corresponding even stacks and odd stacks, and the semiconductor films are connected to form a current path, the current path The upper end to the lower end of the semiconductor films on the corresponding even numbers are stacked, and thus the lower ends to the upper ends of the semiconductor films on the corresponding odd-numbered stacks.

The even stack of the conductive strips includes the first upper strips and the second upper strips, and the first upper strips are used as the first series of select lines, and the second upper strips The band is used as the second string selection line. The odd stack of such conductive strips includes a plurality of upper strips for use as a plurality of ground select lines. At least one of the even stacks and the odd stacks of the plurality of conductive strips includes a plurality of bottom strips, the bottom strips being used as a plurality of auxiliary gates disposed under the intermediate strips (assist gates) ).

In another embodiment, a plurality of data storage structures are disposed on sidewalls of the stack of a plurality of conductive strips in the stack. A plurality of semiconductor films are disposed on the data storage structures on the sidewalls of the stacks to form the stacks A current path from one upper end to the lower end of the semiconductor films.

Other aspects and advantages of the present disclosure can be found in the following detailed description of the drawings and the scope of the patent application.

101‧‧‧Insulation

105‧‧‧layer of tantalum nitride

111, 113, 115, 117‧‧‧ odd stack

112, 114, 116, 118‧‧‧ even stacking

121~125‧‧‧Insulation material layer

130‧‧‧Data storage structure

131‧‧‧Charge storage layer

132‧‧‧Through tunnel

133‧‧‧Block

140‧‧‧Semiconductor film

145‧‧‧ Current path

150‧‧‧Insulation materials

161‧‧‧Air gap

173~175‧‧‧Electrical Department

177~179‧‧‧Electrical Department

183~185‧‧‧Electrical Department

187, 188‧‧‧Electrical Department

2040, 2044, 2048, 2049‧‧‧ source reference wire

2070, 2071, 2080, 2081‧‧‧Electrical Department

210‧‧‧First tandem selector switch

220‧‧‧Second serial selector switch

230‧‧‧ memory cells

310‧‧‧First landing zone

311‧‧‧Interlayer connector

390‧‧‧Second landing zone

391‧‧‧Interlayer connector

405‧‧‧block selection switch

411, 412‧‧‧ first interlayer connector

421, 422‧‧‧Second interlayer connector

431, 432‧‧‧ first patterned wire

441, 441b‧‧‧ odd stack

442, 442b‧‧‧ even stack

443‧‧‧odd stacking

443b‧‧‧Stacking

444‧‧‧ even stack

444b‧‧‧Stacking

445, 445b‧‧‧ odd stack

446, 446b‧‧‧ even stack

447, 447b‧‧‧ odd stack

448, 448b‧‧‧ even stack

451, 452‧‧‧Second patterned wire

460‧‧‧SSL/ASSL/GSL decoder

470‧‧‧ state machine

480‧‧‧ page buffer

612, 612b, 656, 656b, 678, 678b‧‧‧ reverse gate series

705‧‧‧block selection switch

711, 712‧‧‧ first interlayer connector

731, 732‧‧‧ first patterned wire

742, 742b, 744, 744b, 746, 746b, 748, 748b‧‧‧ reverse gate series

751, 752‧‧‧ second patterned wire

760‧‧‧Serial decoder

770‧‧‧ state machine

780‧‧‧ page buffer

800‧‧‧ integrated circuit

805‧‧‧ data bus

810‧‧‧Control circuit

820‧‧‧bias circuit

830‧‧ ‧ busbar

840‧‧‧SSL/ASSL/GSL decoder

845‧‧‧SSL/ASSL/GSL line

850‧‧‧ even/odd level decoder

855‧‧‧ even/odd digital lines

860‧‧‧ memory array

865‧‧‧Global bit line

870‧‧‧Global Bit Line Line Decoder

875‧‧‧First data line

880‧‧‧Sense Amplifier and Program Buffer Circuit

885‧‧‧Second data line

890‧‧‧Multi-level data buffer

891‧‧‧Input/Output Circuit

893‧‧‧data channel

AG‧‧‧Auxiliary gate

WL‧‧‧ character line

DG0‧‧‧ pseudo strip

SSL0~SSL3‧‧‧ first string selection line

ASSL0~ASSL3‧‧‧Second serial selection line

GSL, GSL0~GSL4‧‧‧ Grounding selection line

BL0~BL2‧‧‧ bit line

SSL _N , SSL _N+1 ‧‧‧ first link component

ASSL _N , ASSL _N+1 ‧‧‧Second link component

G0, G1, G7, G8, G14, G15‧‧‧ gate

CSL‧‧‧Common source line

V _SSL1 ‧‧‧First start voltage

V _{ASSL1 ‧‧‧second} starting voltage

V _SSL2 , V _ASSL2 ‧‧‧ Turn off the voltage

Vpgm‧‧‧ stylized voltage

Figure 1 is a simplified perspective view of one of the three-dimensional NAND memory devices described herein.

Figure 2 is a more detailed illustration of the stack of conductive strips shown in Figure 1.

3 is a layout view of the first connecting element and the second connecting element for the first series selection line and the second series selection line in the three-dimensional inverse gate memory device described herein.

Figure 4 is a simplified schematic diagram of one of the three-dimensional anti-gate memory devices described herein.

Fig. 5 is a partially simplified diagram showing the bias voltage for selecting and deselecting the strings of the memory cells on the first tandem selection line and the second serial selection line along the Y direction in Fig. 4.

6A, 6B, and 6C are diagrams showing the portion of the first string selection line and the second string selection line along the X direction for selecting and deselecting the bias voltage of the string of memory cells in FIG. Simplify the schematic.

Figure 7 is a simplified schematic diagram of another embodiment of the disclosed technology.

Figure 8 is a simplified diagram of an integrated circuit including a three-dimensional vertical thin-channel film NAND array (3D). Block diagram.

The details of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following description is not intended to limit the technical means of the invention to a particular structure or method embodiment. Conversely, the technical means of the present invention can be implemented in combination with other features, elements, methods or embodiments. The preferred embodiment is intended to be illustrative only and not to limit the scope of the invention, and the scope of the invention is defined by the scope of the appended claims. Anyone having ordinary knowledge in the field can make some changes and refinements without departing from the spirit and scope of the invention. The same elements in different embodiments will be denoted by the same reference numerals.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified perspective view of one of the three dimensional inverse gate memory devices described herein. The memory device includes a series of a plurality of conductive strips. The stack of the plurality of conductive strips includes a first upper strip, a second upper strip, and an intermediate strip, the first upper strip being used as a plurality of series a first string select line, the second upper strip is used as a second string select line in the plurality of series, and the middle strip is used as a plurality of The word line in the string.

The stack of a plurality of conductive strips includes even stacks (eg, 112, 114, 116, and 118) and odd stacks (eg, 111, 113, 115, and 117). The even stacks 112, 114, 116, and 118 of the conductive strips are included as a first string select line (eg, SSL0, SSL1, SSL2) And a first upper strip of SSL3), a second upper strip for use as a second tandem select line (eg, ASSL0, ASSL1, ASSL2, and ASSL3), and an intermediate strip for use as a word line (eg, WL) The belt, wherein the second upper strip is disposed between the first upper strip and the middle strip. The first series selection line and the second series selection line will be described in detail in FIGS. 3 and 4.

Stacks of conductive strips (eg, 111, 113, 115, and 117) in these memory devices may include upper strips as ground select lines (eg, GSL0, GSL1, GSL2, and GSL3). An odd-numbered stack (eg, 111) may also include a dummy strip (eg, DG0) between the upper strip (eg, GSL0) and those intermediate strips (eg, WLs) in the odd stack, the pseudo strip The band is not used to form a memory cell for data storage, but to avoid gate induced drain leakage (GIDL) of the ground select line (eg, GSL0) in this odd stack. At least one of the even stacks and the odd stacks of the conductive strips may include a bottom strip disposed as an auxiliary gate (AG) under the intermediate strip.

The stack of conductive strips may be disposed on an insulating layer 101 or other dielectric layer on a semiconductor substrate, which may include silicon oxide. Stacks 111 through 118 include layers of insulating material 121, 122, 123, 124, and 125 that separate the conductive strips within the stack from each other. In the embodiments described herein, the electrically conductive material can be P-type polysilicon (P+ polysilicon) or other materials that are compatible with the data storage structure. In this embodiment, a layer of tantalum nitride 105, which provides tensile stress, can be deposited on the top layer. This tantalum nitride layer improves stack uniformity and reduces bending. These layers of insulating material may comprise cerium oxide deposited in different ways as is known in the art. Furthermore, these layers of insulating material may comprise other insulating materials, as well as mixtures of insulating materials. In the present embodiment, all the insulating layers except the tantalum nitride layer 105 are composed of the same material. In other embodiments, different Materials can be used in different layers to suit specific design goals.

The data storage structure 130 is disposed on the sidewalls of the corresponding even and odd stacks of the conductive strips. The semiconductor film 140 is disposed on the data storage structure 130 corresponding to the sidewalls of the even stack and the odd stack. An insulating material 150, such as hafnium oxide, is filled between the stacks and on the inner side surface of the semiconductor film 140. The data storage structure 130, the semiconductor film 140, and the insulating material 150 will be described in detail in FIG.

The semiconductor film 140 includes conductive portions 2070, 2071, 2080, and 2081 that are overlaid on the odd stacks 111, 113, 115, and 117, respectively. The conductive portions 173, 174 and 175 are overlaid on the even stack 112, the conductive portions 177, 178 and 179 are over the even stack 114, the conductive portions 183, 184 and 185 are over the even stack 116, and the conductive portions 187 and 188 are over the even Stack 118. The conductive portions 2070, 2071, 2080, and 2081 are connected together with a semiconductor film having an outer surface on the data storage structure and a landing area providing an interlayer connector to be connected to a common source line (common source) Line), the data storage structure is on the sidewalls of the odd stacks 111, 113, 115, and 117, and the odd stacks are on the common source side of the reverse gate train. The conductive portions 173, 174, 175, 177, 178, 179, 183, 184, 185, 187, and 188 are separate and provide a landing zone for the interlayer connector that is independently connected to the bit line.

One or a plurality of patterned conductor layers are overlaid on the stacks. A first interlayer connector connects a first conductor (eg, bit lines BL0, BL1, BL2) to a top surface of a first semiconductor film, an even stack of the first semiconductor film in the plurality of stacks (eg: 112, 114, 116, and 118) on the data storage structure on the sidewalls. a second interlayer connector is connected to a second conductor (eg, source reference wire (source reference) Conductor lines 2040, 2044, 2048, and 2049) to a top surface of a second semiconductor film, a corresponding stack of the second semiconductor film in a plurality of stacks (eg, 111, 113, 115, and 117) The data storage structure on the side wall.

Figure 2 is a more detailed illustration of the stack of conductive strips shown in Figure 1. The description of Fig. 1 generally applies to Fig. 2. The same elements in Fig. 2 will be denoted by the same reference numerals in Fig. 1.

The data storage structure 130 includes a tunneling layer 132, a charge storage layer 131, and a blocking layer 133. For example, the data storage structure 130 can include oxide-nitride-oxide (ONO), oxide-nitride-oxide-nitride-oxidation as known in the flash memory technology. (oxide-nitride-oxide-nitride-oxide, ONONO), silicon-oxide-nitride-oxide-silicon (SONOS), band gap engineering 矽-oxide- Bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS), tantalum nitride-aluminum oxide, silicon nitride, Silicon oxide, silicon, TANOS), metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE) -SONOS).

The semiconductor film 140 has an outer side surface and an inner side surface. The outer side surfaces are disposed on the data storage structures on the sidewalls of the corresponding even stack and the odd stack, and the corresponding even stacks and odd stacks are stacked in a plurality of stacks forming a three dimensional array of memory cells (eg, 230). The semiconductor film 140 is connected to form a current path 145 from an upper end to a lower end of the semiconductor film on the corresponding even stack, and from the lower end to the upper end of the semiconductor film on the corresponding odd stack. insulation Material 150 may leave at least an air gap 161 in the region of the intermediate strip (e.g., WL) adjacent the conductive strip.

An even stack (eg, 114) of the plurality of stacks includes a first string select switch (eg, 210) coupled to the first string select line (eg, SSL1) and coupled to the second string Select a second string select switch (eg, 220) for the line (eg, ASSL1). The first and second tandem select switches include a data storage structure 130 on the sidewalls of the even stack (e.g., 114) of the plurality of stacks. The data storage structure 130 includes a charge trapping nitride material, such as the ONO described above. The initial threshold voltage distribution of the first and second series select switches including the charge trapping nitride material can be relatively wide and thus affect read and program operations. For example, the wider threshold voltage distribution of the first and second series select switches can increase the minimum required voltage on the first and second series select switches. To better control read and program operations, the initial threshold voltage distribution can be controlled by trimming the first and second series select switches to narrowen their threshold voltage distribution. This adjustment operation can be performed with a typical incremental step pulsed programming (ISPP), but with a lower bias voltage (e.g., approximately 16V). The adjusting operation may result in a narrower threshold voltage distribution of the first and second string select switches, and thus reduce the minimum required voltage on the first and second string select switches.

3 is a layout view of the first connecting element and the second connecting element for the first series selection line and the second series selection line in the three-dimensional inverse gate memory described herein. The first connecting component (eg, SSL _N and SSL _N+1 ) and the second bonding component (eg, ASSL _N and ASSL _N+1 ) may be disposed in one of the plurality of stacked first patterned conductor layers (eg, metal layer 1) For example, the same metal layer level (FIG. 1) as the source reference lines 2040 and 2044, and a metal layer level lower than the word line (eg, FIGS. 1B0, BL1, and BL2) (eg, Metal layer 2).

An upper layer pattern in a stack of a plurality of conductive strips depicts a stacked block of conductive strips in a stack of a plurality of conductive strips. The conductive strips are extended by a landing area that is shared with other conductive strips in the block. The middle and lower layers of the plurality of stacks have the same layout and can be formed in the same patterning step. Each block includes a strip extending from a first landing zone (e.g., 310) for use as a first tandem select line (SSL) and a second tandem select line (ASSL), and in a conductive strip The lower even digital line in the even stack, and the strip extending from the second landing zone (eg, 390), the strip is used as a ground select line (GSL) and below the odd stack in the conductive strip Digital element line.

In an embodiment, the first landing zone (eg, 310) may include a single MiLC (minimal incremental) for the first tandem select line (SSL), the second tandem select line (ASSL), and the lower even digital line below. Layer cost process) module. In another embodiment, the first landing zone (eg, 310) can include a first MiLC module for the first serial selection line and the second serial selection line and a first for the lower even digital line Two MiLC modules.

The stack of a plurality of conductive strips may comprise N even stacks of K groups, wherein a current channel may be formed from one of the upper ends of the semiconductor films on each of the N even-numbered stacks to the lower end, and the semiconductors on the corresponding odd-numbered stack One of the lower ends of the membrane to an upper end. The memory device may include K first connection elements (eg, SSL _N and SSL _N+1 ) in a first patterned conductor layer (eg, metal layer 1) on a plurality of stacks, wherein each of the K first links The component joins the first tandem select line of the N even stacks of the set of K groups. The memory device may include N second connection elements (eg, ASSL _N and ASSL _N+1 ) in the first patterned conductor layer (eg, metal layer ₁ ), wherein each N second connection elements are connected to K second The column select lines, the K second string select lines include a second string select line in one of the N even stacks in each K group.

Therefore, for (K x N) even stacks, the number of first and second link elements required for SSL/ASSL decoding is (K+N). Furthermore, as shown in FIG. 4, the number of patterned wires connecting the first connecting member and the second connecting member via the first interlayer connector and the second interlayer connector is also (K+N), wherein the patterning The wires are disposed in one or more patterned conductor layers (eg, metal layer 3) that are higher than the first patterned conductor layer (eg, metal layer 1). In contrast, if each of the (K x N) even-numbered stacks requires a patterned wire, the number of patterned wires required for (K x N) even stacks is (K x N). Accordingly, the present invention discloses a pitch of a patterned conductor layer (e.g., metal layer 3).

For example, a stack of a plurality of conductive strips may include 32 even stacks of 32 first series select lines arranged in 8 groups with 4 even stacks in each group (K=8, N= 4). Therefore, the memory device includes eight first connecting elements, wherein each of the eight first connecting elements connects four of the first series of selectable lines in one of the four even stacks of the eight sets. The memory device also includes four second connecting elements, wherein each of the four second connecting elements connects one of each of the four even stacks of the eight sets of respective second tandem select lines.

As shown in the embodiments of Figures 1 to 3, where K = 2 and N = 2, there are 4 even stacks of 4 first series select lines (for example: SSL0, SSL1, SSL2, and SSL3) (for example) 112, 114, 116 and 118), arranged in 2 groups, each group of 2 even stacks. The first group has a first string selection line SSL0 and SSL1 and a second string selection line ASSL0 and ASSL1 (Fig. 1). The second group has first string selection lines SSL2 and SSL3 and second string selection lines ASSL2 and ASSL3 (Fig. 1). Therefore, the memory device includes two first connection elements (eg, SSL _N , SSL _N+1 ), wherein the first connection element SSL _{N is} coupled to the first series of select lines SSL0 and SSL1 of the even stacks 112 and 114, and A link element SSL _N+1 connects the first tandem select lines SSL2 and SSL3 of the even stacks 116 and 118. The memory device also includes two second connecting elements (for example, ASSL _N , ASSL _N+1 ), wherein the second connecting element ASSL _{N is} connected to the second serial selection lines ASSL0 and ASSL2, and the second connecting element ASSL _{N+1 is} connected. The second string selects lines ASSL1 and ASSL3.

For example, this figure schematically illustrates an interlayer connector that is individually connected to each underlying layer in a stair step fashion via the upper layer of the stack. The second landing zone (eg, 390) may include eight inter-layer connectors (eg, 391), one for the top layer, six for the intermediate layer including the odd-numbered meta-lines in the odd stack, and one for including the auxiliary gate The bottom layer of a pole or other word line.

The first landing zone (e.g., 310) can include an inter-layer connector for each of the first link elements of the first tandem select line (e.g., SSL _N and SSL _N+1 ) for the second string select line (e.g., ASSL) _The interlayer connector of each of the second connecting elements of _N and ASSL _N+1 ), and the six interlayer connectors (for example, 311) connected to the lower layer, for example, including six even-numbered elements including the even-numbered stack The middle layer of the line, and one bottom layer for the auxiliary gate or other word line.

Conductive strips extending from the second landing zone (e.g., 390) and conductive strips extending from the SSL/ASSL region (e.g., 310) are laid out in an interdigitated fashion. As shown, the upper layer of the stack includes five GSL lines GSL0-GSL4 and four SSL lines SSL0-SSL3. In addition, four ASSL lines ASSL0-ASSL3 (Fig. 1 and Fig. 2) are placed under the four corresponding SSL lines SSL0-SSL3. In this arrangement, all of the GSL lines GSL0-GSL4 are commonly connected to one of the landing zones on the top layer of a GSL stack, such as the heap on the second landing zone 390. Stack.

Figure 4 is a simplified schematic diagram of one of the three-dimensional anti-gate memory devices described herein. In this embodiment, eight memory cell and gate trains are illustrated, wherein each of the reverse gate trains includes a memory cell even stack and a memory cell odd stack connected to form a current channel (eg, FIG. 2 145). The current path is from the upper end to the lower end of the semiconductor film on the even stack, and from the lower end to the upper end of the semiconductor film on the odd stack. The AND gate sequence is connected to a bit line (eg, BL0, BL1) at the upper end of the even stack, and to a common source line (eg, CSL) at the upper end of the odd stack.

As shown in the embodiment of FIG. 4, a first reverse gate sequence includes an even stack 442 and an odd stack 441. The even stack 442 includes a first upper strip as a first string select line SSL0 and a second upper strip as a second string select line ASSL0 for use as a word line (eg, a gate) The middle strip of the character line at the poles G15, G14, ..., G8, and a bottom strip (such as the bottom strip at the gate AG), wherein the second upper strip is disposed at Between the first upper strip and the middle strip. The odd stack 441 includes an intermediate strip for use as a word line (e.g., a word line at gates G7, ..., G1, G0), an upper strip for a ground selection line GSL, and a bottom A strip (for example, a bottom strip at the gate AG), wherein the middle strip is disposed between the ground selection line GSL and the bottom strip AG.

Similarly, a second reverse gate train includes an even stack 444 including a first upper strip for use as a first string select line SSL1 and a second string select line ASSL1 a second strip. A third reverse gate train includes an even stack 446 including a first upper strip for use as a first string select line SSL2 and a first strip select line ASSL2 Two strips. a fourth reverse gate sequence includes an even stack The stack 448 includes a first upper strip for use as a first tandem select line SSL3 and a second upper strip for use as a second tandem select line ASSL3.

The inverse of the plurality of memory cells may include N series of K groups. The memory device may include K first serial column selection structures, wherein each K first serial column selection structures are coupled to N first string selection lines in a respective one of the N series of K groups, And N second serial column selection structures, wherein each of the N second serial column selection structures are coupled to a respective second string selection line of the N series of the K groups. Selecting a combination of a first string selection structure and a second string selection structure of the K second series selection structures in the N series of K groups a series of columns.

As shown in the embodiment of FIG. 4, where K=2 and N=2, there are four first, second, third and fourth opposites of the first serial selection lines SSL0, SSL1, SSL2 and SSL3. The gate series are arranged in two groups, and each group has two reverse gate series. The first group separately includes first and second reverse gate trains, first tandem select lines SSL0 and SSL1, and second tandem select lines ASSL0 and ASSL1. The second group separately includes third and fourth reverse gate trains, first tandem select lines SSL2 and SSL3, and second tandem select lines ASSL2 and ASSL3.

A first serial selection structure is coupled to the two first serial selection lines (eg, SSL0 and SSL1) in the first group, wherein the first serial selection structure includes a first connection element SSL _N and a first layer Interconnector 411. Another first serial selection structure is coupled to the two first serial selection lines (eg, SSL2 and SSL3) in the second group, wherein the other first serial selection structure includes a first connection element SSL _N+1 And a first interlayer connector 412.

A second serial selection structure is coupled to a respective second string selection line (eg, ASSL0) in the first group, and a second second series selection line (eg, ASSL2) in the second group. another A second serial selection structure is coupled to a respective second serial selection line (eg, ASSL1) in the first group, and a respective second serial selection line (eg, ASSL3) in the second group.

The combination of the first serial column selection structure and the second serial column selection structure may have a reverse sequence of the first serial column selection line SSL0 and the second serial column selection line ASSL0, and the first serial column selection structure is coupled to the first A string of select lines SSL0 and SSL1, and a second string select structure coupled to the second string select lines ASSL0 and ASSL2. A combination of the first serial column selection structure and the second serial column selection structure may be selected by a first serial column selection line SSL1 and a second serial column selection line ASSL1, and the first serial column selection structure is coupled to the first A string of select lines SSL0 and SSL1, and a second string select structure coupled to the second string select lines ASSL1 and ASSL3.

Similarly, a combination of the first serial selection structure and the second serial selection structure may select a reverse sequence of the first serial selection line SSL2 and the second serial selection line ASSL2, and the first serial selection structure The first string selection lines SSL2 and SSL3 are coupled to the second series selection lines ASSL0 and ASSL2. The combination of the first serial column selection structure and the second serial column selection structure may have a reverse sequence of the first serial column selection line SSL3 and the second serial column selection line ASSL3, and the first serial column selection structure is coupled to the first A series of select lines SSL2 and SSL3, the second series select structure is coupled to the second series select lines ASSL1 and ASSL3.

As shown in the embodiment of FIG. 4, each of the second series selection structures is coupled to a plurality of strings in respective groups in the complex array string. For example, a second string selection structure including a second connection element ASSL _N+1 is coupled to a plurality of strings in a series of columns, including a series including stacks 443 and 444, and including a stack 443b And another string of 444b, wherein the two series of columns are coupled to the same first serial column selection line SSL1 and second serial column selection line ASSL1. The second tandem selection structure including the second connection element ASSL _N+1 is also coupled to a plurality of strings in a set of strings, including a string comprising stacks 447 and 448 and another comprising stacks 447b and 448b A string, wherein the two series of columns are coupled to the same first string select line SSL3 and the second string select line ASSL3.

The K first series selection structures may include K first coupling elements in a first patterned conductor layer on a stack of a plurality of conductive strips, wherein each K connecting elements are connected to N series of K groups N first series of select lines in a respective group. The N second series selection structures may include N second connection elements in the first conductor layer, wherein each N second connection elements are connected to a respective one of each of the N series of K groups Two string selection lines.

As shown in the embodiment of FIG. 4, the first link component SSL _{N is} connected to the first string select lines SSL0 and SSL1 in the first set of reverse gate trains, and the first link component SSL _{N+1 is} connected to the second group. The first series of select lines SSL2 and SSL3 in the gate sequence are reversed. The second link element ASSL _N connects the respective second string select line ASSL0 in the first group and the respective second string select line ASSL2 in the second group. The second link component ASSL _N+1 connects the respective second string select line ASSL1 in the first group and the respective second string select line ASSL3 in the second group. The first joining element and the second joining element may be disposed in a first patterned conductor layer (eg, metal layer 1) on the stack of the plurality of conductive strips.

The K first series selection structures may include first inter-layer connectors that respectively connect the K first patterned wires to the K first connection elements. The N second series selection structures may include a second interlayer connector that individually connects the N second patterned wires to the N second connection elements. The K first patterned wires and the N second patterned wires may be disposed in one or a plurality of patterned conductor layers (eg, metal layer 3) higher than the first patterned conductor layer, and N series connected to the K group To a serial decoder (eg, FIG. 4 460) to decode the first tandem select line (SSL) and the second tandem select line (ASSL). A serial decoder (eg, 460) can also be connected to a ground select line (GSL).

As shown in the embodiment of FIG. 4, the first interlayer connectors 411 and 412 respectively connect the first patterned wires 431 and 432 to the first connecting elements SSL _N and SSL _N+1 . The second interlayer connectors 421 and 422 respectively connect the second patterned wires 451 and 452 to the second connecting members ASSL _N and ASSL _N+1 .

A block select transistor is arranged at the upper end of the odd stack in the reverse gate train. For example, a block select switch 405 is arranged at the upper end of the odd stack 441 in the first AND gate sequence. A ground select line GSL is connected to the gate of the block select switch. The word line WLs are connected by electronic communication to a word line decoder (e.g., the eighth figure/odd level decoder 850) to receive the bias during operation as described herein.

The block selection transistor is configured to selectively couple the upper end of the odd stack in the block to a common source line CSL. The common source line CSL receives the bias voltage from a bias circuit (e.g., FIG. 8 820) during operation as described herein. In some of the operations described herein, the CSL is biased to a reference voltage, the absolute value of the reference voltage being higher than a bit line coupled to the other end of the reverse gate train. The reference voltage is not in the more traditional source role.

The bit lines BL0 and BL1 are coupled to additional blocks (not shown) in the array and to the page buffer 480. A state machine 470 is shown for controlling the memory array and supporting circuitry to perform program, block erase, and sub-block erase (sub) -block erase) and read operation.

Figure 5 is a simplified diagram showing the partial bias of the series of selected and deselected memory cells on the first tandem select line and the second tandem select line along the Y direction in Fig. 4. schematic diagram. The same elements in Fig. 5 will be denoted by the same reference numerals in Fig. 4. In this embodiment, four inverted gate trains are illustrated, wherein each of the reverse gate trains includes a memory cell even stack and a memory cell odd stack connected to form a current channel (eg, FIG. 2 145). One of the semiconductor films on the even stack is stacked from the upper end to the lower end, and from one of the lower ends of the semiconductor film on the odd stack to an upper end. The AND gate sequence is connected to a bit line (eg, BL1) at the upper end of the even stack, and to a common source line (eg, CSL) at the upper end of the odd stack.

As shown in the embodiment of FIG. 5, a first reverse gate sequence includes an odd stack 441, and an even stack 442 includes a first upper strip for use as a first string select line SSL0. And a second upper strip used as the second string selection line ASSL0. Similarly, a second reverse gate train includes an odd stack 443 and an even stack 444 including a first upper strip for use as a first string select line SSL1, and as a first The second string selects a second upper strip of the line ASSL1. A third reverse gate train includes an odd stack 445 and an even stack 446 including a first upper strip for use as a first string select line SSL2 and as a second string Select a second upper strip of line ASSL2. A fourth reverse gate train includes an odd stack 447 and an even stack 448 including a first upper strip for use as a first string select line SSL3 and as a second string Select a second upper strip of line ASSL3.

Each even stack (eg, 442, 444, 446, 448) includes an intermediate strip for use as a word line (eg, a word line at gates G15, ..., G8), and a bottom strip (eg, a gate) The bottom strip at the pole AG), wherein the second upper strip is disposed between the upper strip and the middle strip. Each odd stack (e.g., 441, 443, 445, 447) includes an intermediate strip for use as a word line (e.g., a word line at gates G7, ..., G0) for use as a ground select line GSL. a strip, and one The bottom strip (for example, the bottom strip at the gate AG), wherein the middle strip is disposed between the ground selection line GSL and the bottom strip AG.

As shown in the embodiment of FIG. 5, wherein K=2 and N=2, there are four first series selection lines SSL0, SSL1, SSL2, and SSL3, first, second, third, and fourth. The reverse gate series are arranged in two groups, and each group has two reverse gate series. The first group includes first and second inverted gate trains, including even stacks 442 and 444, first string select lines SSL0 and SSL1, and second string select lines ASSL0 and ASSL1. The second group includes third and fourth NAND gate trains each including an even stack 446 and 448, a first tandem select line SSL2 and SSL3, and a second tandem select line ASSL2 and ASSL3.

To select a particular string in the series of complex memory cells, a first turn-on voltage can be applied to a first string of the first series of select lines coupled to the particular string. A column select line, and a second enable voltage can be applied to a second string select line of the plurality of second string select lines coupled to the particular string. The second starting voltage can be lower than the first starting voltage.

As shown in the embodiment of FIG. 5, in order to select the first reverse gate sequence including an even stack 442 and an odd stack 441, a first startup voltage (eg, V _SSL = 3.3 V) can be applied to the coupling. a first series select line (eg, SSL0) of the first reverse gate train, and a second start voltage (eg, V _ASSL = 3.3V) may be applied to the second string coupled to the first reverse gate train Column selection line (for example, ASSL0). A stylized voltage Vpgm can be applied to the memory cell G7 for one of the memory cells (eg, the memory cell at the gate G7) of the first reverse gate sequence selected for stylization.

To deselect a particular string in the series of complex memory cells, a turn-off voltage can be applied to a first string select line coupled to the first string select line of the particular string and coupled One or both of a second string select line of the second string select line of the particular string.

As shown in the embodiment of FIG. 5, in order to deselect the second reverse gate _sequence including an even stack 444 and an odd stack 443, a turn-off voltage (eg, V _ASSL2 = -1 V) may be applied to the coupling. The second serial selection line (for example, ASSL1) of the gate sequence. To deselect a third reverse gate _sequence comprising an even stack 446 and an odd stack 445, a turn-off voltage (eg, V _SSL2 = -1V) can be applied to the second string coupled to the third AND gate sequence. Column selection line (for example, ASSL2). To deselect the fourth reverse gate _sequence including an even stack 448 and an odd stack 447, a turn-off voltage (eg, V _SSL2 = -1 V) can be applied to the first string coupled to the fourth reverse gate train. A column select line (e.g., SSL3), and a turn-off voltage (e.g., V _ASSL2 = -1V) may be applied to a second string select line (e.g., ASSL3) coupled to the fourth AND gate train.

The stylized, read and erase biases represented on the first tandem select line SSL and the second tandem select line ASSL can be understood in accordance with the following table.

For example, a memory cell (eg, a memory cell at the gate G7) selected by one of the first reverse gate series including an even stack 442 and an odd stack 441 is coupled to a memory cell. The bit line (eg, BL1) can be biased to a ground voltage (eg, GND=0V) coupled to a selected first string select line (eg, SSL0) of the first AND gate sequence. A first startup voltage (eg, V _SSL1 =VCC=3.3V) can be applied, and a selected second string selection line (eg, ASSL0) coupled to the first AND gate sequence can be biased A second startup voltage (e.g., V _ASSL1 = VCC = 3.3V), and a stylized voltage (Vpgm = 20V to 25V) can be applied to the selected memory cell G7.

In an embodiment, the second startup voltage may be lower than the first startup voltage, such as a programmed voltage (eg, V _ASSL1 = Vpgm).

A program pass voltage (eg, Vpass = approximately 10 V) may be applied to unselected memory cells on the first AND gate series (eg, memory cells at gates G15...G8, G0) ). The ground selection line GSL coupled to the first AND gate series can be applied with a bias ground voltage (eg, GND=0V), and the common source line CSL coupled to the first AND gate series can be biased. Supply voltage (for example, VCC = 2.5V to 3.3V).

In order to read a selected memory cell on the first back gate (for example, the memory cell at the gate G7), a selected bit line (eg, BL1) coupled to the memory cell can be biased to a channel side. A channel-side read voltage (eg, Vread = 0.6V to 1V), a selected first string select line (eg, SSL0) and a selected second string select line (eg, ASSL0) may be applied A memory cell having a bias voltage of the same voltage is programmed, and a word line read voltage (e.g., Vw1 = 0 V) can be applied to the selected memory cell G7. Read pass voltage (eg Vpass_r=5 to 8V) Unselected memory cells (eg, memory cells at gates G15...G8, G0) that can be applied to the first AND gate sequence. The ground selection line GSL coupled to the first AND gate series can be applied with a bias supply voltage (eg, VCC=2.5V to 3.3V), and the common source line CSL coupled to the first AND gate series can be Apply a bias ground voltage (eg GND=0V).

To erase a plurality of memory cells, the bit line and the common source line coupled to the string can be applied with a channel-side erase voltage (eg, Vbl_ers=14 to 20V), coupled. The first string select line, the second string select line, and the ground select line GSL connected to the series may be applied with a string select erase voltage (eg, Vssl_ers=6 to 12V), and coupled The word line of the series of columns can be applied with a word line erase voltage (eg, Vers = 0V).

6A, 6B, and 6C are diagrams showing the portion of the first string selection line and the second string selection line along the X direction for selecting and deselecting the bias voltage of the string of memory cells in FIG. Simplify the schematic. FIG. 6A is a diagram showing a selection of a complex inverse gate sequence, and FIG. 6B is a diagram showing a deselected page of the complex reverse gate sequence, and FIG. 6C is a diagram showing the complex reverse gate sequence. A deselected page. The same elements in the drawings of Figs. 6A, 6B, and 6C will be denoted by the same reference numerals in Fig. 4.

As shown in the embodiment of FIG. 6A, a reverse gate train 612 includes an odd stack 441, and an even stack 442 including a first upper strip for use as a first string select line SSL0. And a second upper strip used as a second serial selection line ASSL0. The reverse gate sequence 612b includes an odd stack 441b and an even stack 442b that shares the first string select line SSL0 and the second string select line ASSL0 with the inverse gate train 612. The opposite gate series 612 and 612b represent at least the first series of columns and the gate sequence 612 and 612b. The complex line of the line SSL0 and the second string selection line ASSL0 is opposite to one page of the gate string.

The inverse gate train 612 is coupled to a first bit line (e.g., BL0) at the upper end of the even stack 442 in the reverse gate train 612. The inverse gate train 612b is coupled to a second bit line (e.g., BL1) at the upper end of the even stack 442b in the reverse gate train 612b. The AND gate series 612 and 612b are coupled to ground select lines and common source lines (e.g., CSL) at the upper ends of the odd stacks (e.g., 441 and 441b) in the reverse gate trains 612 and 612b.

To select one of the plurality of inverted gate series including the inverted gate trains 612 and 612b, a first start voltage (eg, V _SSL1 = 3.3V) can be applied to the complex reverse gate coupled to the page. The first series of select lines (eg, SSL0) of the string, and a second enable voltage (eg, V _ASSL1 = 3.3V) may be applied to the second series of selects of the complex and gate series coupled to the page. Line (for example, ASSL0). To select the inverse gate sequence 612 in the selected page of the reverse gate sequence, the bit line (eg, BL0) coupled to the gate sequence 612 can be biased to a ground voltage (eg, GND = 0V). For stylized selection of a memory cell on the gate sequence 612 (eg, the memory cell at gate G7), a stylized voltage Vpgm can be applied to the memory cell G7, and a stylized transfer voltage Vpass can be Deselected memory cells (e.g., memory cells at gates G15 through G8) applied to selected reverse gate train 612.

To deselect the inverse gate sequence 612b in the selected page of the reverse gate sequence, the bit line (eg, BL1) coupled to the gate sequence 612b can be biased by a supply voltage (eg, VCC). =2.5V to 3V).

As shown in the embodiment of FIG. 6B, a reverse gate train 656 includes an odd stack 445 and an even stack 446 including a first upper strip for use as a first string select line SSL2. And a second upper strip for use as a second serial selection line ASSL2. One The reverse gate train 656b includes an odd stack 445b and an even stack 446b that shares the first tandem select line SSL2 and the second tandem select line ASSL2 with the inverse gate train 656. The inverse gate trains 656 and 656b represent a page of a plurality of inverse gate trains sharing at least the first tandem select line SSL2 and the second tandem select line ASSL2 with the anti-gate trains 656 and 656b.

The AND gate string 656 is coupled to a first bit line (e.g., BL0) at the upper end of the even stack 446 in the anti-gate string 656. The AND gate string 656b is coupled to a second bit line (e.g., BL1) at the upper end of the even stack 446b in the opposite gate string 656b. The gate series 656 and 656b are coupled to the ground select line GSL and the common source line (e.g., CSL) at the upper ends of the odd stacks (e.g., 445 and 445b) in the gate series 656 and 656b.

In order to deselect a page comprising a plurality of anti-gate sequences of the gate series 656 and 656b, a turn-off voltage (eg, V _SSL2 = -1 V) may be applied to the plurality of anti-gates coupled to the page. The first series of line selects (eg, SSL2), and a voltage above the turn-off voltage (eg, V _ASSL1 = 3.3V) can be applied to the second of the plurality of inverted gates coupled to the page. Serial selection line (for example, ASSL2).

As shown in the embodiment of FIG. 6C, a reverse gate train 678 includes an odd stack 447, and an even stack 448 including a first upper strip for use as a first string select line SSL3. And a second upper strip used as a second serial selection line ASSL3. The reverse gate sequence 678b includes an odd stack 447b and an even stack 448b that shares the first tandem select line SSL3 and the second tandem select line ASSL3 with the inverse gate train 678. The anti-gate sequence 678 and 678b represent a page of the plurality of inverse gate series that share at least the first string selection line SSL3 and the second string selection line ASSL3 with the gate sequence 678 and 678b.

The anti-gate string 678 is connected to the even stack 448 in the anti-gate string 678. A first bit line (eg BL0) at the top. The anti-gate string 678b is coupled to a second bit line (e.g., BL1) at the upper end of the even stack 448b in the anti-gate string 678b. The gate series 678 and 678b are connected to the ground select line GSL and the common source line (e.g., CSL) at the upper ends of the odd stacks (e.g., 447 and 447b) in the gate series 678 and 678b.

In order to deselect a page comprising a plurality of anti-gate columns of the gate series 678 and 678b, a turn-off voltage (eg, V _SSL2 = -1 V) may be applied to the plurality of anti-gates coupled to the page. A series of first string select lines (eg, SSL3), and a turn-off voltage (eg, V _ASSL2 = -1V) may be applied to a second string select line that couples a plurality of inverse gate _trains in the page ( For example, ASSL3).

As shown in the embodiments of FIGS. 6B and 6C, in order to deselect a particular one of the plurality of strings, a turn-off voltage may be applied to a first string select line coupled to the particular string and coupled One or both of a second string selection line of this particular string.

Figure 7 is a simplified schematic diagram of another embodiment of the present technology. The description of the three-dimensional inverse thyristor device shown in Figs. 1 to 6 is generally applicable to another embodiment of Fig. 7. In particular, the first and second series selection lines, the first and second connection elements, the first and second interlayer connectors, and the first in the first described embodiment shown in FIGS. 1 to 6 And the description of the second patterned wire is applicable to another embodiment shown in FIG.

The three-dimensional anti-gate memory device shown in Figures 1 to 6 has an even stack of conductive strips and an odd stack of conductive strips, and the even stack of conductive strips is included as a first serial select line (SSL) The first upper strip and the second upper strip used as the second tandem select line (ASSL), the odd stack of conductive strips including the upper strip used as the ground select line. In comparison, Another embodiment has a stack of conductive strips comprising a first upper strip for use as a first tandem select line (SSL) and as a second tandem select line (ASSL) a second upper strip and a bottom strip for use as a ground select line in the same stack as the first tandem select line and the second tandem select line.

The inverse of the memory cell shown in Fig. 7 represents the inverse of the plurality of memory cells in the memory device. Each stack shows two reversed gate trains (eg, 742 and 742b, 744 and 744b, 746 and 746b, 748, and 748b) representing a plurality of inverse gate trains in a stack. The gate series are connected to respective bit lines (eg, BL0, BL1) at the upper end of the stack.

As shown in the embodiment of FIG. 7, a first reverse gate train 742 includes a first upper strip as a first serial select line SSL0 for use as a second serial select line ASSL0. a second upper strip, an intermediate strip used as a word line (eg, a word line at gates G15, G14, ..., G0), and a bottom portion used as a ground selection line GSL The strip is disposed under the middle strip, wherein the second upper strip is disposed between the first upper strip and the middle strip.

Similarly, a second reverse gate train 744 includes a first upper strip for use as a first string select line SSL1 and a second strip for use as a second string select line ASSL1. band. A third reverse gate train 746 includes a first upper strip for use as a first string select line SSL2 and a second upper strip for a second string select line ASSL2. A fourth reverse gate train 748 includes a first upper strip for use as a first string select line SSL3 and a second upper strip for a second string select line ASSL3.

The data temporary storage structure is disposed on the sidewalls of the stack in the plurality of stacks. The semiconductor film is disposed on the data storage structure on the sidewall of the stack to form an upper end of the semiconductor film on the stack A current path formed to the lower end.

As shown in the embodiment of FIG. 7, where K=2 and N=2, there are four first series selection lines SSL0, SSL1, SSL2, and SSL3, first, second, third, and fourth. The reverse gate series are arranged in two groups, and each group has two reverse gate series. The first group separately includes first and second reverse gate trains, first tandem select lines SSL0 and SSL1, and second tandem select lines ASSL0 and ASSL1. The second group separately includes third and fourth reverse gate trains, first tandem select lines SSL2 and SSL3, and second tandem select lines ASSL2 and ASSL3.

A first serial selection structure is coupled to the two first serial selection lines (eg, SSL0 and SSL1) in the first group, wherein the first serial selection structure includes a first connection element SSL _N and a first layer Interconnector 711. Another first serial selection structure is coupled to two other first serial selection lines (eg, SSL2 and SSL3) in the second group, wherein the other first serial selection structure includes a first connection element SSL _{N+ 1} and a first interlayer connector 712.

A second serial selection structure is coupled to a respective second string selection line (eg, ASSL0) in the first group, and a second second series selection line (eg, ASSL2) in the second group. Another second serial selection structure is coupled to a respective second string selection line (eg, ASSL1) in the first group, and a second second series selection line (eg, ASSL3) in the second group.

A combination of the first serial column selection structure and the second serial column selection structure may have a reverse sequence of the first serial column selection line SSL0 and the second serial column selection line ASSL0, and the first serial column selection structure is coupled to the first A string of select lines SSL0 and SSL1, and a second string select structure coupled to the second string select lines ASSL0 and ASSL2. The combination of the first serial column selection structure and the second serial column selection structure may have a reverse sequence of the first serial column selection line SSL1 and the second serial column selection line ASSL1, and the first serial column selection structure is coupled to the first A series of select lines SSL0 and SSL1, the second string selection The structure is coupled to the second serial selection lines ASSL1 and ASSL3.

Similarly, a combination of the first serial selection structure and the second serial selection structure may select a reverse sequence of the first serial selection line SSL2 and the second serial selection line ASSL2, and the first serial selection structure The first string selection lines SSL2 and SSL3 are coupled to the second series selection lines ASSL0 and ASSL2. A combination of the first serial column selection structure and the second serial column selection structure may have a reverse sequence of the first serial column selection line SSL3 and the second serial column selection line ASSL3, and the first serial column selection structure is coupled to the first A series of select lines SSL2 and SSL3, the second series select structure is coupled to the second series select lines ASSL1 and ASSL3.

As shown in the embodiment of FIG. 7, the first link element SSL _{N is} connected to the first series select lines SSL0 and SSL1 in the reverse and gate trains of the first group, and the first link element SSL _{N+1 is} connected The first series of selection lines SSL2 and SSL3 in the second group of reverse gate series. The second link element ASSL _{N is} connected to the respective second string select line ASSL0 in the first group and the respective second string select line ASSL2 in the second group. The second link element ASSL _{N+1 is} connected to the respective second string select line ASSL1 in the first group and the respective second string select line ASSL3 in the second group. The first joining element and the second joining element may be disposed in a first patterned conductor layer (eg, metal layer 1) on a stack of a plurality of conductive strips.

As shown in the embodiment of FIG. 7, the first interlayer connectors 711 and 712 respectively connect the first patterned wires 731 and 732 to the first connecting elements SSL _N and SSL _N+1 . The second interlayer connectors 721 and 722 respectively connect the second patterned wires 751 and 752 to the second connecting members ASSL _N and ASSL _N+1 . The first patterned conductive line and the second patterned conductive line may be disposed in one or more patterned conductor layers (eg, metal layer 3) higher than the first patterned conductor layer, and connected to the gate string group to a series A decoder (eg, 760) to decode the first tandem select line (SSL) and the second tandem select line (ASSL). A serial decoder (eg, 760) can also be connected to a ground select line (GSL).

The block selection transistor is arranged at the lower end of the opposite gate sequence with respect to the upper end of the first string selection line (e.g., SSL0). For example, the block selection switch 705 is arranged at the lower end of the reverse gate train 742. A ground selection line GSL is connected to the gate of the block selection switch 705. Word line WL is electronically coupled to a word line decoder (e.g., even/odd level decoder 850 of FIG. 8) to receive the bias voltage in the operations described herein.

The block selection transistor is configured to selectively couple the lower end of the reverse gate sequence in the block to a common source line CSL. The common source line CSL receives a bias voltage from a bias circuit (e.g., FIG. 8 820) in the operations described herein. In some of the operations described herein, the CSL is biased to a reference voltage, the absolute value of the reference voltage being higher than the reference voltage of a one-dimensional line coupled to the other end of the gate series. Not in a more traditional source role.

Bit lines BL0 and BL1 are coupled to additional blocks (not shown) in the array and to page buffer 780. A state machine 770 is shown for controlling the memory array and supporting circuitry to perform stylization, block erase, sub-block erase, and read operations.

Figure 8 is a simplified wafer block diagram of an integrated circuit 800 including a three-dimensional vertical thin-channel film NAND array. The integrated circuit 800 includes a memory array 860 that includes one or more memory blocks as described herein that use a first serial select line (SSL) and a second serial select line. (ASSL) to select a string of memory cells in a block of memory cells.

An SSL/ASSL/GSL decoder 840 is coupled to a plurality of SSL/ASSL/GSL lines 845 arranged in the memory array 860. An even/odd level decoder 850 is coupled to a complex number An even number/odd number element line 855. A global bit line column decoder 870 is coupled to a plurality of global bit lines 865 arranged along rows in the memory array 860 for reading data and writing data from the memory array 860. To memory array 860. The address is supplied to the bus 830, from the control circuit 810 to the global bit line line decoder 870, the SSL/ASSL/GSL decoder 840, and the even/odd level decoder 850. In the present embodiment, a sense amplifier and a program buffer circuit 880 are coupled to the global bit line line decoder 870 via a first data line 875. The program buffer in circuit 880 can store multiple-level programming code, or a function value of the code, to indicate the stylized or suppressed state of the selected bit line. The global bit line row decoder 870 can include circuitry that selectively applies stylized and suppressed voltages to bit lines in the memory in response to data values in the program buffer.

The sensed data from the sense amplifier/program buffer circuit is supplied to the multi-level data buffer 890 via a second data line 885, which in turn is coupled to the input/output circuit 891 via a data path 893. Moreover, in the present embodiment, input data is applied to the multi-level data buffer 890 for use as a support for multi-level programmatic operations of each of the independent sides of the individual dual gate memory cells in the array.

The input/output circuit 891 drives data to an external destination of the integrated circuit 801. The input/output data and control signals are passed between the input/output circuit 891, the control circuit 810, and the input/output port on the integrated circuit 801 or the internal or external data source of the other integrated circuit 801 via the data bus 805. Mobile, such as a general purpose processor or special purpose application circuitry, or a system-on-a-chip module that is supported by the memory array 860. The combination.

As shown in the embodiment of FIG. 8, control circuit 810 uses a bias arrangement state machine (e.g., FIG. 4, 470, FIG. 7 770) to control the supply of voltage via block 820. Or use of supplied supply voltages such as read, erase, verify, and programmed bias. The control circuit 810 is coupled to the first serial selection line, the second serial selection line, the multi-level data buffer 890, and the memory array 860. Control circuit 810 includes logic units that control multi-level stylized operations. In an embodiment that supports the vertical thin-channel film NAND structures described herein, the logic unit is configured to perform the method of applying a first startup voltage to a first a serial selection line, and a second startup voltage to a second serial selection line, selecting a particular one of the plurality of serials, the first serial selection line coupled to the particular serial, the second serial selection The line is coupled to the specific series, wherein the second starting voltage is lower than the first starting voltage; and by applying a closing voltage to one or both of the first series selection line and the second series selection line, Deselecting a particular one of the plurality of strings, the first string select line is coupled to the particular string, and the second string select line is coupled to the particular string.

In some embodiments, the logic unit is configured to store a multi-level charge to represent more than one bit of data in a charge trapping site in a selected layer on the selected side. In the method, a selected memory cell in a selected frustum of a vertical channel structure in the array stores more than two bits, including one bit greater than on each side of the memory cell.

Control circuit 810 can be implemented as a special purpose logic circuit as is known in the art. In another embodiment, the control logic includes a general purpose processor that can be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In other embodiments, special use The combination of the way logic and a general purpose processor can be used to implement the control logic.

The memory array 860 can include a charge trapping memory cell for storing a plurality of bits per memory cell by establishing a plurality of stylized levels corresponding to the amount of stored charge, which sequentially builds the memory. Cell critical voltage V _T . Single-bit-per-cell embodiments may include the structures described herein.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

800‧‧‧ integrated circuit

805‧‧‧ data bus

810‧‧‧Control circuit

820‧‧‧bias circuit

830‧‧ ‧ busbar

840‧‧‧SSL/ASSL/GSL decoder

845‧‧‧SSL/ASSL/GSL line

850‧‧‧ even/odd level decoder

855‧‧‧ even/odd digital lines

860‧‧‧ memory array

865‧‧‧Global bit line

870‧‧‧Global Bit Line Line Decoder

875‧‧‧First data line

880‧‧‧Sense Amplifier and Program Buffer Circuit

885‧‧‧Second data line

890‧‧‧Multi-level data buffer

891‧‧‧Input/Output Circuit

893‧‧‧data channel

Claims (18)

A memory device includes a plurality of strings of memory cells, the memory device comprising: a plurality of stacks of a plurality of conductive strips, including a plurality of first a first upper strip, a plurality of second upper strips, and a plurality of intermediate strips, the first strips being the plurality of strips in the series a first string select line, the second upper strips being used as a plurality of second string select lines in the series, the intermediate strips being used as the second string select line a plurality of word lines in the series, wherein the series of the memory cells are vertically disposed between the stacks of the conductive strips; and a control circuit coupled to the The first series of select lines and the second series of select lines, and by applying a first turn-on voltage to the first series of select lines coupled to a particular series One of them, and applying a second turn-on voltage to Connected to one of the plurality of second selection lines of the tandem of tandem particular, to select the particular series. The memory device of claim 1, wherein the second upper strips are disposed between the first upper strips and the intermediate strips. The memory device of claim 1, wherein the plurality of memory cells comprise a plurality of serial arrays, the memory device comprising: a plurality of first string select structures Each of the first serial selection structures is coupled to a respective one of the plurality of serial arrays a first string selection line; and a plurality of second string select structures, each of the second string selection structures being coupled to one of each of the plurality of strings in the complex array string a second string selection line, wherein a first series selection structure of the first series selection structures and one of the second series selection structures of the second series selection structures are combined to select the plurality A list of columns in a string. The memory device of claim 3, wherein each of the second serial selection structures is coupled to a plurality of strings in a plurality of individual string groups in the complex array string. The memory device of claim 1, wherein the series of the memory cells comprises K sets of N strings, the memory device comprising: K first a string selection structure, each of the K first series selection structures being coupled to N first series selection lines in a respective one of the N series of the K groups; and N second series selection a second second string selection structure coupled to a respective second string selection line of the N series of the K groups, wherein the first string of the K first series selection structures A combination of the column selection structure and a second string selection structure of the N second series selection structures selects one of the N columns of the K group. The memory device of claim 5, wherein: the K first series selection structures comprise a first patterned conductor layer (first K first guiding elements in the patterned conductor layer, the first patterned conductor layer is located on the stack of the conductive strips, and each of the K first connecting elements is connected to the N of the K group N first string selection lines in a respective one of the plurality of strings; and the N second series selection structures including N second linking elements in the first patterned conductor layer And each of the N second connecting elements is connected to a respective second string selection line of each of the N series of the K groups. The memory device of claim 6, wherein: the K first series selection structures comprise a plurality of first interlayer connectors, and the first interlayer connectors are different Connecting K first patterned conductor lines to the K first connecting elements; the N second serial selecting structures include a plurality of second interlayer connectors, the second The interlayer connectors are respectively connected with N second patterned conductor lines to the N second connecting elements; and the K first patterned wires and the N second patterned wires are disposed higher than In the one or a plurality of patterned conductor layers of the first patterned conductor layer, the K first patterned conductors and the N second patterned conductors connect the N strings of the K group to a string String decoder. The memory device of claim 1, wherein the control circuit selects by first applying a turn-off voltage to one of the first series of select lines One or both of the second string selection lines of the line and one of the second series of select lines for deselecting a particular one of the series, the first series of select lines The specific string is coupled to the specific string. The second string select lines are coupled to the specific string. The memory device of claim 1, wherein the second starting voltage is lower than the first starting voltage. The memory device of claim 1, wherein the stack comprises a plurality of even stacks and a plurality of odd stacks, the memory device comprising: a plurality of data storage structures (data Storage structure), the data storage structures are located on a plurality of even-numbered stacks and a plurality of odd-numbered stacked sidewalls of the plurality of conductive strips in the stack; and a plurality of semiconductor films disposed on the plurality of semiconductor films In the data storage structure, the data storage structures are on the sidewalls of the corresponding even-numbered stacks and odd-numbered stacks, and the semiconductor films are connected to form a current path, and the current paths are formed by the corresponding even-numbered stacks. The semiconductor film has an upper end to a lower end, and a lower end to an upper end of the semiconductor films stacked on the corresponding odd numbers. The memory device of claim 10, wherein the even stack of the conductive strips comprises the first upper strips and the second upper strips, the first upper strips being used as The first series of select lines are used as the second series of select lines. The memory device of claim 10, wherein the memory device The odd stack of conductive strips includes a plurality of upper strips for use as a plurality of ground select lines. The memory device of claim 10, wherein at least one of the even stack and the odd stack of the conductive strips comprises a plurality of bottom strips, the bottom strips being used as A plurality of auxiliary gates below the intermediate strips. The memory device of claim 1, wherein the memory device comprises: a plurality of data storage structures located on sidewalls of the stack of the plurality of conductive strips in the stack; a plurality of semiconductor films disposed on the data storage structures on the sidewalls of the stacks, the semiconductor films forming a current path from an upper end of the plurality of semiconductor films on the stack To the bottom. The memory device of claim 1, wherein the stacking comprises a plurality of bottom strips, the bottom strips being used as a plurality of ground selection lines below the intermediate strips. A method of operating a memory device, the memory device comprising a plurality of strings of a plurality of memory cells, wherein the plurality of stacks of the plurality of conductive strips comprise a plurality of first upper strips and a plurality of second upper strips And a plurality of intermediate strips, wherein the first upper strips are used as the plurality of first series select lines of the series, and the second upper strips are used as the plurality of the plurality of series Aligning the selection lines, the intermediate strips are used as the plurality of word lines of the series, wherein the memory cells The series is disposed vertically between the stacks of the conductive strips, the method comprising: applying a first startup voltage to a first one of the first series of select lines, and Applying a second startup voltage to a second string selection line of the second series of select lines, selecting a particular one of the series, the first series select lines being coupled to the specific string The second series of select lines are coupled to the particular string. The method of claim 16, wherein the second starting voltage is lower than the first starting voltage. The method of claim 16, wherein the method comprises: applying a turn-off voltage to a first string selection line and the second string selection lines of the first series selection lines One or both of the second series of select lines are deselected, and the first series of select lines are coupled to the particular series, and the second series of select lines are selected The particular string is coupled.