CN104347635A - Semiconductor array arrangement comprising carrier supply - Google Patents

Abstract

The invention discloses a semiconductor array arrangement comprising a carrier supply. The semiconductor array arrangement is applicable to a thin film transistor base material storage device of a memory through a hole carrier supply. The hole carrier supply can comprise a diode with a first end and a second end. An NAND series arrangement is formed by coupling a first switch at a first tail end to a bit line and coupling a second switch at a second tail end to the first end of the diode. A first source line and a second source line which can be individually driven are coupled to the first end and the second end of the diode respectively. A circuit coupled to the first source line and the second source line biases the first source line and the second source line according to an operation mode under different bias conditions including forward bias conditions or reverse bias conditions.

Description

Comprise the semiconductor array arrangement of carrier supply

Technical field

The invention relates to a kind of high density memory Set, and relate to a kind of storage device especially and can comprise multiple thin-film transistor memory cell arrangement and form a three-dimensional (3D) array, comprise the semiconductor array arrangement of carrier supply, be through a hole carrier for the thin-film transistor base material storage device being applied to a memory.

Background technology

The design of high density memory Set comprises multiple arrays of the memory cell of multiple flash memory cell (flash memory cells) or multiple other types.In some instances, the multiple memory cell comprising multiple thin-film transistor can be arranged in three-dimensional structure (3D architectures).

Three-dimensional memory devices has developed into various different structure, comprises multiple film and by the isolated multiple bit lines of insulating material.Known three-dimensional perpendicular grid structure uses multiple thin-film transistor as the three-dimensional memory devices of multiple Storage Unit Type, such as be recorded in U.S. Patent Application No. the 13/078th, No. 311 cases, apply on April 1st, 2011, denomination of invention is " having the 3D storage array body structure (Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures) of the configuration of stored interleaved string and string choice structure " (U.S. Patent Publication No. US 2012/0182806A1, be disclosed on July 19th, 2012), invent the artificial old scholar assignee that to expand with the two pieces United States Patent (USP) of Lv Hanting be subject application to be owned together, can as reference.Three-dimensional perpendicular grid structure comprises multiple film tape lamination and covers the word line structure on lamination, extend with making word line structure sections transverse between multiple lamination, the crosspoint place of the part that word line structure extends and multiple film tape is as many wordline in memory cell.Many film bit lines, in this structure or the storage organization of other types, can be lightly doped and not have body contact, therefore insulate in the source of many film bit lines and electric charge carrier in the operation of device.The operating efficiency of structure can be injured when hole carrier is under-supply.

Therefore, relevant dealer expects to provide a kind of array structure for having higher operating efficiency in three dimensional integrated circuits.

Summary of the invention

The present invention is to provide the structure for meeting hole carrier supply requirement in thin-film transistor base material storage device.

In one embodiment, a memory can comprise a diode, a series arrangement, one first source electrode line, one second source electrode line, many wordline and a circuit.Diode has a first end and one second end.Series arrangement comprises multiple memory cell, and series arrangement is such as be coupled to a bit line by one first switch on one first end in NAND serial, is coupled to the first end of diode by the second switch on one second end.First source electrode line that can drive individually and the second source electrode line are respectively coupled to first end and second end of diode.Many wordline is coupled to corresponding memory cell.Circuit is coupled to first, second source electrode line, and circuit is with different first, second source electrode lines of bias condition bias voltage according to operator scheme.

In another embodiment, circuit is configured in the memory cell of selection or a block of multiple memory cell, use erasing bias voltage arrangement (erase bias arrangement) to produce to bring out hole.Erasing bias voltage for N-shaped passage arranges the one source pole lateral deviation pressure be included on the second source electrode line, and this this diode of source side bias voltage forward bias voltage drop makes one or more bit line be wiped free of to provide the source in hole.The arrangement of erasing bias voltage also can comprise the first source electrode line and keep floating, and many wordline applies erasing voltage and produces to bring out hole.

In another embodiment, during program bias arrangement (program bias arrangement), circuit is that the configuration one source pole side that can be used on the first source electrode line applies bias voltage with in programming operation, and the second source electrode line keeps floating or being subjected to bias voltage with reverse bias diode.

Different embodiment is that the three-dimensional comprising a three-dimensional perpendicular grid structure stores arrangement, and wherein diode described above can be used in the certain operations pattern of device to provide a carrier supply.Generally speaking, the embodiment provided is a hole carrier supply of the multiple bit lines for semi-conducting material, and bit line may insulate with a conductivity substrate and may not have body contact.

In order to have better understanding to other aspects of the present invention and advantage, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:

Accompanying drawing explanation

Fig. 1 illustrates the perspective view of a three-dimensional perpendicular grid NAND memory array structure, and wherein three-dimensional perpendicular grid NAND storage array comprises the film bit line not having body contact without knot.

Fig. 2 illustrates the layout that one embodiment of the invention comprises the three-dimensional perpendicular Gate Memory of diode structure.

Fig. 2 A, Fig. 2 B, Fig. 2 C illustrate the diode structure be applicable to as in the three-dimensional storage in Fig. 2.

Fig. 3 illustrates the layout of the intermediate structure in a technique, and wherein this technique is the memory construction of the similar Fig. 2 for the manufacture of the diode structure had as Fig. 2 A.

Fig. 3 A, Fig. 3 B are the profiles illustrated according to the operation stage of the layout of Fig. 3.

Fig. 4 illustrates the layout of another intermediate structure in a technique, and wherein this technique is the memory construction of the similar Fig. 2 for the manufacture of the diode structure had as Fig. 2 A.

Fig. 4 A, Fig. 4 B are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 4.

Fig. 5 illustrates the layout of another intermediate structure in a technique, and wherein this technique is for the manufacture of the structure in similar Fig. 2.

Fig. 5 A, Fig. 5 B are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 5.

Fig. 6 illustrates the layout of another intermediate structure in a technique, and wherein this technique is for the manufacture of the structure in similar Fig. 2.

Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 6.

Fig. 7 illustrates the layout carrying out an intermediate structure after the technique of Fig. 6 for the manufacture of the structure in similar Fig. 2.

Fig. 7 A, Fig. 7 B are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 7.

Fig. 8 illustrates the layout of another intermediate structure in a technique, and wherein this technique is the memory construction of the similar Fig. 2 for the manufacture of the diode structure had as Fig. 2 B.

Fig. 8 A, Fig. 8 B are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 8.

Fig. 9 illustrates the technique for the manufacture of the structure in similar Fig. 2, the layout of an intermediate structure after the technique of carrying out Fig. 8.

Fig. 9 A, Fig. 9 B are the profiles illustrating the extra stage according to the operation stage of the layout of Fig. 9.

Figure 10 illustrates the layout of another intermediate structure in a technique, and wherein this technique is the memory construction of the similar Fig. 2 for the manufacture of the diode structure had as Fig. 2 C.

Figure 10 A, Figure 10 B are the profiles illustrating the extra stage according to the operation stage of the layout of Figure 10.

Figure 11 illustrates the technique for the manufacture of the structure in similar Fig. 2, carries out the layout of another intermediate structure after the technique of Figure 10.

Figure 11 A, Figure 11 B are the profiles illustrating the extra stage according to the operation stage of the layout of Figure 11.

Figure 12 is the schematic diagram of the three dimensional NAND structure of similar Fig. 2, and the bias voltage illustrated in figure for a programming operation arranges.

Figure 13 is the schematic diagram of the three dimensional NAND structure of similar Fig. 2, and the bias voltage illustrated in figure for an erase operation arranges.

Figure 14 is the schematic diagram of the three dimensional NAND structure of similar Fig. 2, illustrates an erasing bias voltage arrangement substituted in figure.

Figure 15 is the schematic diagram of the three dimensional NAND structure of similar Fig. 2, illustrates a reading bias voltage arrangement in figure.

Figure 16 is the schematic diagram of another three dimensional NAND structure, and its each bit line lamination illustrating a circuit has an embodiment of a diode, and three dimensional NAND structure imposes bias voltage to carry out a programming operation.

Figure 17 is that one of the integrated circuit comprising three-dimensional storage simplifies calcspar, and wherein three-dimensional storage is the carrier supply comprising embodiment.

[symbol description]

10: array

11: column decoder

12: bit line

13: page buffer

14: global bit lines

15,17: bus

16,18,20: square

19: state machine

23: Data In-Line

24: other circuit

25: integrated circuit

102,103,104,105,112,113,114,115,202,202-1,202-2,202-8,203,203-2: bit line

102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A, 202-A ~ 202-D, 203-A ~ 203-D, 220,223,330,331: contact pad

109,119,119-A1,119-A2,119-D1,119-D2: serial selection line grid structure

125-0 ~ 125-N, WL: wordline

126,127, GSL: ground connection selects line

128: source electrode line

205-1 ~ 205-8,210-A ~ 210-D, 211-A ~ 211-D: serial is selected to connect

219-1 ~ 219-8: the first source line contact

221-1 ~ 221-8: the second source line contact

220A ~ 220D, 605,606,607,650-1 ~ 650-8,651-1 ~ 651-8,850-1 ~ 850-8: opening

224,351,557,558,724,824:P+ region

302: substrate

225,350: knot

305: insulating barrier

320,345,346,355,550-1,550-2,550-8,651,660,665: cylinder

321,524-1,524-2,524-3,590,591,725-1,725-2,725-3,825-1,825-2,825-3:N+ region

325,326,327,356,610,611,612,859-1,859-2,859-8,869-1,869-2,869-8: interlayer conductor

332,333,342,343,353,592,593,655,656: PN junction

410,410A, 420,420A, 430: stepped contact

500: upper strata

501,502,503: through hole

509: top insulator material layer

510: the second active material

511: the first active material

512: semi-conducting material

519: charge storing structure layer

524:N+ injects

555,579: mask

556:P+ injects

565: polysilicon layer

598: silicide layer

600,855: insulation fill stratum

601,650: interlayer dielectric packed layer

651:N+ cylinder

652:N+ part

653,654:P+ part

661:P+ cylinder

750-1 ~ 750-8,751-1 ~ 751-8: interlayer articulamentum

800: diode

801: diode N-type end

804-1 ~ 804-4: contact

824-1,824-2,825-1,825-2: serial selector switch

814-1 ~ 814-4: ground connection selector switch

840,842,845,847: memory cell

859-1,859-2,859-8,869-1,869-2,869-8: interlayer conductor

861,866: first end

860,865: the second ends

SSL: serial selection line

BLL1, BLL2: bit line layer

GSL: ground connection selects line

SC: source contact end

PNS, PNS1, PNS2:PN tie source terminal

P1PNS: upper strata diode source is extreme

P2PNS: lower diodes source terminal

X, Y, Z: direction

ML1, ML2, ML3: metal level

A, B, C, D: block

Embodiment

Various embodiment is that the appended diagram of collocation is described in detail.

Fig. 1 illustrates the perspective view of a three-dimensional NAND gate storage array (3D NAND memory array) structure, three dimensional NAND structure is U.S. patent application case that assignee owns together number the 13/078th, No. 311 cases of the above-mentioned in this way subject application of reference example.In order to preferably represent additional structure, insulating material is removed by diagram.For example remove be arranged in lamination multiple bit lines (being such as 112-115) between and multiple insulating barriers between multiple bit line lamination.

Multiple tier array is formed on an insulating barrier, and comprise many wordline (Word Line, WL) 125-0 to 125-N, many wordline and multiple lamination system conformal.Multiple lamination comprises multiple bit lines 112,113,114,115, multiple bit lines comprise multiple there is a relative lower concentration impurity doping or the semiconductor material thin film bar of other extrinsic semiconductor (intrinsic semiconductor), semiconductor material thin film bar can be made as passage in NAND serial.Multiple storage device is configurable for N-shaped passage or p-type channel operation.In some illustrative structures, the source/drain that multiple bit lines does not comprise between many wordline connects, and is therefore called as " without knot " bit line.And multiple bit lines is not connected to semi-conductive substrate or other semiconductor bodies yet, therefore, when not selecting (string select) or ground connection to select (ground select) switch to apply a voltage to multiple bit lines via string, multiple bit lines can be regarded as " floating (floating) ".

Multiple bit lines in same level is by a contact pad (pad) electric property coupling together, and contact pad has the touch-down zone (landing area) contacted with an interlayer conductor (interlayer conductor).Multiple contact pads of multiple layers can be arranged in stepped construction as shown in Figure 1, and each contact pad be sequentially configured on the single order of structure has touch-down zone.In order to expect or special manufactures that need set, for multiple touch-down zones of the connection of multiple contact pad, and multiple interlayer conductors in multiple touch-down zones in multiple contact pad can be arranged in simply stepped beyond pattern.

Increase progressively to N by 0 for the word line numbers of even number memory page (even memory pages) from the rear end of total to front end shown in figure.Successively decreased to 0 by N for the word line numbers of odd number memory page (odd memory pages) from the rear end of total to front end.

Contact pad 112A, 113A, 114A and 115A stop (terminate) staggered multiple bit lines, and contact pad 112A, 113A, 114A and 115A stop the bit line 112,113,114 and 115 in each layer in this example.As shown in FIG., in order to be connected to decoding circuit (decoding circuitry) to select plane in an array, these contact pad 112A, 113A, 114A and 115A are electrically connected at different wordline.These contact pad 112A, 113A, 114A and 115A can be patterned while the multiple lamination of definition.

Contact pad 102B, 103B, 104B and 105B stop staggered multiple bit lines, are such as stop the bit line 102,103,104 and 105 in each layer in this example.As shown in FIG., in order to be connected to decoding circuit to select plane in an array, these contact pad 102B, 103B, 104B and 105B are electrically connected at different wordline.Multiple through holes in these contact pad 102B, 103B, 104B and 105B and touch-down zone can be patterned while defining multiple lamination.

In other examples, all bit lines in a block can terminate on the bit line contact pad on same end.

In the example illustrated, all bit line laminations are coupled to contact pad 112A, 113A, 114A and 115A or contact pad 102B, 103B, 104B and 105B, but can not be coupled to both simultaneously.The position of a lamination of multiple bit lines to for from bit line end to source electrode line end (bit line end-to-source line end) or from source electrode line end to two opposite positions of bit line end (source line end-to-bit line end) to one of them.For example, the lamination of multiple bit lines 112,113,114 and 115 have from bit line end to the position of source electrode line end to the lamination of, multiple bit lines 102,103,104 and 105 have from source electrode line end to the position of bit line end to.

An end of the lamination of multiple bit lines 112,113,114 and 115 passes through serial selection line (String Select Line, SSL) grid structure 119, ground connection select line (Ground Select Line, 126 GSL), wordline 125-0 to 125-N and ground connection selects line 127 and ends at contact pad 112A, 113A, 114A and 115A, and another end ends at source electrode line 128.The lamination of multiple bit lines 112,113,114 and 115 can not extend to contact pad 102B, 103B, 104B and 105B.

An end of the lamination of multiple bit lines 102,103,104 and 105 passes through serial selection line grid structure 109, ground connection selection line 127, wordline 125-N to 125-0 and ground connection select line 126 and end at contact pad 102B, 103B, 104B and 105B, and another end ends at source electrode line (being covered by the another part in figure).The lamination of bit line 102,103,104 and 105 can not extend to contact pad 112A, 113A, 114A and 115A.

Wordline 125-0 to 125-N and bit line 112-115 and 102-105 separate by one deck of storage medium.Ground connection selects line 126 and 127, similar in appearance to serial selection line grid structure, is conformal with bit line.

An end of each lamination of multiple bit lines ends at multiple contact pad, and another end ends at one source pole line.For example, an end of multiple bit lines 112,113,114 and 115 ends at contact pad 112A, 113A, 114A and 115A, and another end ends at source electrode line 128.At graphic near-end, the lamination of multiple bit lines at interval ends at contact pad 102B, 103B, 104B and 105B, and the lamination of multiple bit lines at interval ends at a different source electrode line.Graphic long-range, the lamination of multiple bit lines at interval ends at contact pad 112A, 113A, 114A and 115A, and the lamination of multiple bit lines at interval ends at a different source electrode line.

Multiple bit lines and many serial selection lines are formed at multiple patterning conductor layer place, such as, be metal level (Metal Layer, ML) ML 1, ML 2 and ML 3.Multiple transistor is formed at the crosspoint between multiple bit lines (being such as 112-115) and wordline 125-0 to 125-N.In multiple transistor, bit line (being such as 113) is as the channel region in device.

Serial choice structure (being such as 119,109) can be patterned in the process of definition wordline 125-0 to 125-N (as shown in Figure 2) simultaneously.Multiple transistor is formed at the crosspoint between multiple bit lines (being such as 112-115) and serial choice structure (being such as 119,109).In order to select specific multiple lamination in array, as multiple transistor couples of serial selector switch in decoding circuit.

One charge storing structure (charge storage structure) layer is the crosspoint place being at least arranged at memory cell formation.Charge storing structure can comprise multilayer dielectric charge storing structure, such as, be eka-silicon O-N-Si oxygen (SONOS) structure.Known dielectric charge storage structure is energy gap engineering silica nitrogen silica (bandgap engineered SONOS) or " BE-SONOS ".BE-SONOS charge storing structure can comprise a multilayer tunnel layer, such as, be the silicon oxide layer that a thickness is about the silicon oxide layer of 2 nanometers, a thickness is about 2-3 nanometer silicon nitride layer and a thickness are about 2-3 nanometer.BE-SONOS charge storing structure can comprise the dielectric layer being positioned at and being used for above multilayer tunnel layer storing electric charge, the silicon nitride layer of 5-7 nanometer that to be such as a thickness be.Charge storing structure also can comprise the dielectric layer being positioned at and electric charge storage layer being used for stop electric leakage (leakage), the silicon oxide layer of 5-8 nanometer that to be such as a thickness be.The material of other types also can be used in BE-SONOS lamination.

In the device comprising BE-SONOS electric charge storage layer, an erase operation (erasing operation) can comprise F-N tunnelling (Fowler Nordheim tunneling) hole from passage to electric charge storage layer with and the electronics that catches in electric charge storage layer.

But, for the structure shown in picture Fig. 1, in whole serial, do not have P+ district.(Gate Induced Drain Leakage, GIDL) mechanism of may leaking electricity via Gate Induced Drain is brought out one and can be brought to and can be with hot hole electric current (band-to-band hot hole current).But, an extra or other source, hole may be needed.As described in content of the present invention, a carrier supply comprising diode can produce source, hole to address this problem.

Fig. 2 illustrates the layout of the first arrayed of three-dimensional finger vertical gate NAND storage device (finger VG (vertical gate) 3D NAND memory device).In order to reference, " X " axle is arranged in the direction being parallel to structure wordline (being such as 125-0,125-5,125-15), " Y " axle is positioned at the direction being parallel to structure neutrality line (being such as 202-1,202-8), and " Z " axle is arranged in be orthogonal to the bit line of structure and the direction of bit line.

In the layout of Fig. 2, arrayed comprises multiple bit lines.Memory cell is the crosspoint being arranged at bit line (being such as 202-1,202-2,202-8) and wordline (being such as 125-0,125-5,125-15).In the embodiment illustrated, have four blocks being denoted as A, B, C, D, in order to simplify, each block of embodiment has two bit line laminations of two layer depths.In other embodiments, may have more multi-layered, such as, be 4,8,16 or more, and may have multiple bit line lamination in each block, such as, be 4,8,16 or more.In this embodiment, four blocks A, B, C, D illustrating share a carrier supply, below will do more detailed describing.

Multiple bit lines in upper water plane extend to the top of source electrode line and carrier Supply Structure from the contact pad (upper water plane contact pad 202-A, 202-D) of a correspondence.Carrier Supply Structure comprises the first source line contact 219-1 to 219-8 of the N+ region 524-3 being arranged in multiple bit line, and contact pad 220 comprises the second source line contact 221-1 to 221-8 in the P+ region of a P+ region and contact pad.N+ region 524-3 establishes the source terminal of bit line.A knot 225 on N+ region 524-3 and source line contact pad 220 between P+ region 224 provides the PN junction of a diode.In a p-type channel embodiment, the doping type of region 224 and 524-3 is conversely.

Bit line in lower layer of water plane extends from the contact pad (lower layer of water plane contact pad 203-A, 203-D) of a correspondence, and as shown in FIG., the bit line in lower layer of water plane can be obtained by the stepped opening of contact pad in upper water plane.Be such as in the metal level ML3 shown in Fig. 1 at the conductor layer of a patterning, serial is selected to connect 210-A to 210-D and 211-A to 211-D and is coupled contact pad and superincumbent bit line.

The wordline (being such as 202-1,202-2,202-8) of level and the ground connection of level select line 127 to cover on bit line (being such as 125-0,125-5,125-15).Serial selection line grid structure also covers and is positioned at line, comprise serial selection line grid structure 119-A1, the 119-A2 for coupling bit line and contact pad 202-A, 203-A, be used for coupling serial selection line grid structure 119-D1,119-D2 of bit line and contact pad 202-D, 203-D, multiple serial selection line grid structures similar in block B, C do not indicate reference symbol.Serial selection line grid structure controls the electric connection between any one bit line and contact pad (being such as 202-A, 203-A) corresponding to this bit line.Be such as in the metal level ML2 shown in Fig. 1 at the conductor layer of a patterning, serial is selected to connect 205-1 to 205-8 and is coupled multiple serial selection line grid structure and superincumbent serial selection line.

Three dimensional NAND storage device comprises multiple memory cell plane.In multiple memory cell plane, multiple bit line selects a specific plane via multiple contact pad (being such as 202-A and 202-B).This specific plane selects line and multiple bit line to carry out decoding by multiple serial choice structure, multiple horizontal grounding.Apply a positive serial selection line voltage (VSSL) to serial choice structure (119-A1) to select a specific lamination (being such as comprise upper horizontal plane bit line 202-1).For example apply one be 0 volt (V) voltage to multiple serial choice structure with cancels selection other laminations multiple.

Fig. 2 A-Fig. 2 C illustrates the structure of the alternative carrier supply in the layout that can be used for similar Fig. 2.

Fig. 2 A is the end view at Z-Y in-plane, illustrates and is positioned at the carrier Supply Structure that is similar to bit line 202, the 203 lamination end of Fig. 2 structure.The lamination of bit line 202,203 is arranged on the insulating barrier 305 that is positioned on a substrate 302.Ground connection selects line 127 to be that configuration is adjacent on the side of bit line 125-N, 125-N-1 etc.In this example, bit line 202,203 selects line 127 to extend to a N+ end regions 321 in bit line by ground connection.N+ end regions 321 is contacted with the N+ cylinder (column) 320 of semi-conducting material or a part for the N+ cylinder 320 of semi-conducting material, and the N+ cylinder 320 of semi-conducting material provides the N+ of bit line to hold.One interlayer conductor 325 be coupled to N+ cylinder 320 top and in order to connect one first source electrode line (not shown).Bit line 202,203 extends to the P+ region of source line contact pad 330,331 from vertical cylinder 320.P+ region in source line contact pad 330,331 and the PN junction 332,333 between the N+ region on N+ cylinder 320 establish diode.Interlayer conductor 326,327, for example tungsten plug (tungsten plugs) can be comprised, extend from the P+ region source line contact pad 330,331 in a stair-stepping structure, and provide for being connected to one second source electrode line (not shown) or separating multiple second source electrode line in each horizontal plane.P1PNS shown in Fig. 2 A is that upper strata diode source is extreme, P2PNS is lower diodes source terminal, SC is source contact end (function is the source electrode of traditional NAND serial).

Fig. 2 B illustrates the end view of the carrier Supply Structure that substitutes, and similar element is with reference to identical component symbol.In this structure, bit line 202,203 extends semiconductor interface touch pad, comprises the vertical N+ semi-conducting material cylinder 345 being connected to one first source electrode line (not shown).Semiconductor interface touch pad also comprises the vertical P+ semi-conducting material cylinder 346 be connected with contact pad, and produces PN junction 342,343.Vertical cylinder 346 is used for connection one second source electrode line (not shown).

Fig. 2 C illustrates the end view of the carrier Supply Structure that another substitutes.In this example, bit line (being such as the bit line 202 ending at knot 350) ends at the vertical N+ semi-conducting material cylinder 355 be connected with one first source electrode line (not shown).Cylinder vertical in Semiconductor substrate 302 is coupled to a P+ region 351, sets up a PN junction 353 at interface.One interlayer conductor 356, for example can comprise a tungsten plug, provides for connecting P+ region 351 and one second source electrode line (not shown).Multiple diode carrier Supply Structures that Fig. 2 A-Fig. 2 C illustrates can use together with three-dimensional storage.Also other structures of the practising way of applicable memory and other elements can be used.

Fig. 3, Fig. 3 A, Fig. 3 B, Fig. 4, Fig. 4 A, Fig. 4 B, Fig. 5, Fig. 5 A, Fig. 5 B, Fig. 6, Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D, Fig. 7, Fig. 7 A and Fig. 7 B illustrates the different phase for the manufacture of the such as technique of the storage organization of Fig. 2, and storage organization has the carrier Supply Structure as Fig. 2 A.Fig. 3 illustrates the plane graph on material upper strata 500 that is used for manufacturing bit line, above the lamination that can cover a staggered active material and insulating material as aforementioned upper strata 500.Be used for manufacturing the material of multiple bit lines the polysilicon layer of can be semiconductor material be such as siliceous deposits.Alternatively, material can be the semi-conducting material of a single-crystal semiconductor material or other types.Material can be adapted at the relatively light dope as passage in thin-film transistor, or the constitutionally of applicable specific demand (intrinsically) doping.For N-shaped channel thin film transistors, material has a p type light dope or essence doping.

As shown in Figure 3, after forming staggered active material and insulating material, form the multiple through holes (vias) (being such as 501,502,503) through lamination, multiple through hole at least extends to the bottom of active material.There is the structure of multiple bit line lamination, form multiple through hole, the corresponding bit lines in each hole.The lamination of the active material that multiple through hole (such as 501,502,503) is interlocked by patterning and insulating material is to aim at the position of multiple bit lines.

Fig. 3 A illustrates an end view of the lamination of staggered active material and insulating material.At this visual angle, one can be that the substrate 302 of the material of semiconductor or other types is above covered with an insulation material layer 305.One first active material 511 and one second active material 510 are separated by an insulating barrier.One top insulator material layer 509 covers on lamination.One through hole 501 is formed through top insulator material layer 509 and at least extends to the first active material 511.

Fig. 3 B illustrates the end view with the lamination after semi-conducting material 512 filling vias 501 of N+ doping.The surface that a planarisation step makes the top alignment top insulator material layer 509 of semi-conducting material can be carried out.

Fig. 4 structure illustrated in Fig. 3 carries out the plane graph after pattern etched technique.Pattern etched defines multiple bit line contact pad (being such as 202-A, 202-B, 202-C and 202-D) with being used in each three-dimensional block A, B, C, D as shown in Figure 2.Pattern etched also defines one source pole linear contact lay pad (being such as 220), and source line contact pad (being such as 220) is shared by four blocks in this example.Multiple semi-conducting material bit line (being such as 202-1,202-2,202-8) extends to the bit line contact pad (being such as 202-A, 202-B, 202-C and 202-D) of a correspondence from source line contact pad (being such as 220).

As shown in Figure 4, pattern etched is also etched through the semi-conducting material 512 of filling vias (being such as 501,502,503), and through hole is illustrated in Fig. 3.Therefore, N+ type semi-conducting material cylinder (being such as 550-1,550-2,550-8) connects bit line in ground floor and compared with the bit line in upper strata, and the width of N+ type semi-conducting material cylinder meets the width of bit line in this example.In other embodiments, various different width can be had according to the pattern in the region of the multiple cylinders expected.

Fig. 4 also illustrates the region 224 of carrying out P+ doping in source line contact pad (being such as 220).

Fig. 4 A illustrates the lamination end view along a wherein bit lines (being such as 202-2).Therefore, the first semiconductor material layer and the second semiconductor material layer have been patterned the lamination defining bit line, comprise lower floor bit line 203-2 and upper level bitline 202-2 at the lamination of this two-layer example neutrality line.Fig. 4 A illustrate a charge storing structure layer 519 be deposited on patterning bit line on.One mask is such as that photolithographic mask 555 also covers structurally, and photolithographic mask 555 has an opening exposed region 224 to inject 556 to carry out P+.Carrying out P+ injection with enough energy makes P+ be doped into lower floor, the upper strata source line contact pad of first, second active material.

Fig. 4 B illustrates and carries out injecting and the structure removed after mask 555.The structure of Fig. 4 B comprise in the second source contact pads with the P+ district 557 of upper level bitline 202-2 same layer and the second source contact pads in the P+ district 558 of lower floor bit line 203-2 same layer.

Fig. 5 illustrates the plane graph after the technique forming wordline, ground connection selection line and serial selection line.Technique can comprise the mode of filling the multiple raceway grooves between multiple bit lines with, deposit a P+ or N+ doped polycrystalline silicon on charge storing structure (Fig. 5 does not illustrate), thus between multiple bit lines (being such as 202-1,202-2,202-8), form vertical gate structure.

This technique makes horizontal wordline (being such as 125-0,125-5,125-15) and horizontal grounding select line 127 to cover on bit line (being such as 202-1,202-2,202-8).Serial selection line grid structure also covers bit line, comprise serial selection line grid structure 119-A1, the 119-A2 for coupling bit line and contact pad 202-A, be used for coupling serial selection line grid structure 119-D1,119-D2 of bit line and contact pad 202-D, serial selection line grid structure similar in block B, C does not indicate reference symbol.Flash memory cell is formed in the crosspoint between multiple bit lines and the vertical gate structure on many wordline 125-0 to 125-15, and flash memory cell is made up of film, bigrid and charge-stroage transistor.Double gate transistor is formed at multiple bit lines and selects the crosspoint between the vertical gate structure on line 127 and serial choice structure ground connection, and double gate transistor couples along the memory cell serial of bit line in bit line contact pad or carrier Supply Structure as selecting property of switch selectable.The end view that Fig. 5 A, Fig. 5 B figure illustrate wordline, ground connection selects Wiring technology, deposit a P+ or N+ doped polysilicon layer 565 as shown in Figure 5 A on charge storing structure layer 519, then after patterned polysilicon layer 565, form wordline (being such as 125-N, 125-N-1,125-N-2) as shown in Figure 5 B select line (being such as 127) with ground connection, serial selection line (figure does not illustrate) is also formed in this step.

Fig. 6 illustrates and in source line contact pad 220, forms opening 220A, 220B, 220C and 220D and the plane graph formed in bit line contact pad (being such as 202-A, 202-B, 202-C and 202-D) after the technique of corresponding opening.These openings expose below source line contact pad (being such as 223) and below bit line contact pad (being such as 203-A, 203-B, 203-C and 203-D) thus interlayer contact (interlayer contacts) can be formed.Also illustrate one in figure for the pattern of N+ doped region, comprise the N+ district 524-3 on multiple N+ cylinders (being such as 550-2) of being arranged in multiple bit line contact pad Shang N+ district 524-1, being positioned at the N+ district 542-2 between multiple serial choice structure (being such as 119-A1) and the first wordline 125-0 and being positioned at multiple bit line.N+ district 524-3 also the covering on source line contact pad 220 and extend upwardly to along multiple bit line or select line 127 close to ground connection of part.

Fig. 6 A illustrates the structure in similar Fig. 5 B, and the mask (photolithographic mask) 579 that this structure has to cover, mask 579 has the opening corresponding to region 524-3.Opening allows the injection 524 of N-type dopant, and injection enters lower floor bit line 203-2 as shown in FIG..

Fig. 6 B illustrates and form stair-stepping opening 220A (see Fig. 6) after removing mask 579.As depicted in figure 6b, a PN junction 592 is formed between Zhong N+ district, upper strata 590 and Zhong P+ district, upper strata 557.Similarly, a PN junction 593 is formed between Zhong N+ district of lower floor 591 and Zhong P+ district of lower floor 558.

Fig. 6 C illustrates the formation being positioned at superstructure insulation fill stratum 600, can carry out planarization insulation fill stratum 600 and expose the upper surface that many wordline (being such as 125-N) and ground connection select line 127.Then, silicide layer 598 is such as cobalt silicide is be formed at ground connection to select on line and many wordline.In the preferred embodiment, silicide layer 598 is also formed on serial choice structure (not showing in Fig. 6 C).

Fig. 6 D illustrates another interlayer dielectric packed layer 601 be formed on silicide layer.Insulate wordline, ground connection of interlayer dielectric packed layer 601 selects grid and serial to select grid structure and the patterning conductor layer above covered.

Fig. 7 illustrates the plane graph after the technique forming interlayer contact in the structure.Structure comprises stepped contact in stepped contact in source line contact pad 220,223 (be such as 410,410A) and bit line contact pad (being such as 202-A, 203-A) (be such as 420,420A).Structure also comprises the stepped contact (being such as 430) being positioned at serial choice structure (being such as 119-D1) top.Fig. 7 incorporates the many features be set forth in Fig. 4, Fig. 5, Fig. 6.

Fig. 7 A illustrates the end view of opening 605,606,607, the opening of formation 605,606,607 through packed layer (being such as 601,600) and charge storing structure layer 519 with is formed and N+ cylinder 550-2 contact, formed and upper strata source line contact pad P+ region 557 contact and formed and the contact in P+ region 558 of lower floor's source line contact pad.

After Fig. 7 B illustrates the conductor filled opening of interlayer, forming interlayer conductor 610,611,612, such as, is tungsten plug or other conductive structures, and the structure that planarization obtains makes applicable the formation on one or more of body structure surface cover patterned conductive layer.

As shown in fig.7b, carrier Supply Structure comprise by N+ district 550-2, each be positioned at N+ district corresponding to line with form PN junction 592,593 along source contact pads Zhong P+ district 557,558.Carrier Supply Structure also comprises interlayer conductor 610,611,612.These interlayer conductors provide for first, second source line contact above covered, below will be further described.

Fig. 8, Fig. 8 A, Fig. 8 B, Fig. 9, Fig. 9 A and Fig. 9 B illustrates the multiple operation stages manufactured as the carrier Supply Structure in Fig. 2 B.By Fig. 8, in figure, illustrate the pattern of the after etching of the cross laminates formation of active material and insulating material.In this etching, one first end of bit line 202-1,202-2,202-8 of formation is connected to bit line contact pad (being such as 202-A, 202-B, 202-C, 202-D).One second end of bit line is connected to source line contact pad (being such as 220).In this example, opening 650-1 to 650-8,651-1 to 651-8 are formed in source line contact pad (being such as 220).In this example, two openings (being such as 650-2,651-2) aim at a wherein bit lines (being such as 202-2).

Fig. 8 A illustrates along opening 650-2,651-2 that bit line 202-2 is formed in bit line contact pad, and opening 650-2,651-2 extend into lower floor bit line 203-2.

Illustrate in Fig. 8 B and fill opening 650-2,651-2 with semi-conducting material, form the cylinder 665,666 with the bit line contact in active material (being such as 510,511).Surface can carry out planarization then a charge storing structure layer 519 be formed on the lamination of multiple bit line.

Fig. 9 illustrates the plane graph of the structure that the above-mentioned multiple step relevant with the first manufacturing process is made.Therefore, illustrate stepped contact in bit line contact pad in plane graph, the contact be positioned on serial choice structure contacts (750-1 to 750-8 and 751-1 to 751-8) with two groups.Interlayer connects 750-1 to 750-8 and is connected to the cylinder formed in source line contact pad, such as, be the cylinder with reference to being formed in Fig. 8 A, Fig. 8 B.The plane graph of Fig. 9 also illustrates the N+ injection region 725-1 of part, the N+ injection region 725-2 between the first wordline and serial choice structure that cover source line contact pad contiguous ground connection selection line 127 and the N+ injection region 725-3 covering bit line contact pad district.Fig. 9 also illustrates the P+ injection region 724 covering in source line contact pad (being such as 220) line of offing normal region far away.

The result in the region injected near source line contact pad is illustrated in Fig. 9 A, carry out injecting the N+ cylinder 651 of the source line contact bed course forming upper strata and lower floor and N+ part (being such as 652) in the 725-1 of region, in region 724, carry out P+ cylinder 661 and the P+ part 653,654 of injecting the source line contact bed course forming upper strata and lower floor.Therefore PN junction 656,655 is formed in the structure.

Fig. 9 B illustrates the structure structurally forming silicide layer 598, interlayer dielectric filling 650 and interlayer and connect the technique of 751-2,750-2.It can be seen that carrier Supply Structure is as shown in Figure 2 B formed by this flow process.

Figure 10, Figure 10 A, Figure 10 B, Figure 11, Figure 11 A and Figure 11 B illustrates multiple operation stages of manufacture carrier structure as shown in FIG. 2 C.By Figure 10, in figure, illustrate the pattern of the after etching of the cross laminates formation of active material and insulating material.In this etching, one first end of bit line 202-1,202-2,202-8 of formation is connected to bit line contact pad (being such as 202-A, 202-B, 202-C, 202-D).One second end of bit line is connected to source line contact pad (being such as 220).In this example, upper strata source line contact pad (being such as 220) is etched with a part for exposing semiconductor substrate.Also formed through upper strata source line contact pad until the opening 850-1 to 850-8 of the horizontal plane of lower floor's source line contact pad.This plane graph also illustrates in substrate 302 for the formation of the region 824 that the P+ in P+ region 351 injects.

Figure 10 A is the end view of the lamination along bit line 202-2,203-2, illustrates the opening 850-2 extending through the P+ region 351 be stacked in substrate 302.

Figure 10 B illustrates the end view after the formation of semiconductor material N+ cylinder (cylinder 355), and semi-conducting material N+ cylinder extends through source line contact pad 220 and is coupled to multiple bit lines.PN junction is formed at the interface be positioned between N+ cylinder (cylinder body 355) and P+ district 351, sets up the diode of carrier Supply Structure.Also the formation of charge storing structure layer 519 above the bit line of patterning is illustrated in 10B figure.

Figure 11 illustrates the plane graph of the structure that the above-mentioned multiple step relevant with the first manufacturing process is made.Therefore, illustrate stepped contact in bit line contact pad in plane graph, the contact be arranged on serial choice structure, be positioned at source line contact pad 220 one group, region with the interlayer conductor (859-1,859-2,859-8) formed with reference to the mode of above-mentioned Figure 10 A, Figure 10 B and one group for being connected to the interlayer conductor (869-1,869-2,869-8) in substrate Zhong P+ district 351.Figure 11 also illustrates region 824 that P+ injects, the N+ injection region 825-1 on source line contact pad 220, the N+ injection region 825-2 between the first wordline and serial choice structure and the N+ injection region 825-3 on bit line contact pad.

Figure 11 A is the end view being similar to Fig. 6 C, illustrates and forms the result that the charge storing structure 519, horizontal wordline (being such as 125-N, 125-N-1,125-N-2) and the horizontal grounding that cover bit line select line 127.

Figure 11 B illustrates the result of the formation of silicide layer 598, insulation filling 855, the interlayer conductor 859-2 of connection N+ cylinder (cylinder 355) and the interlayer conductor 869-2 in connection substrate 302 Zhong P+ district 351.It can be seen, PN junction 353 is formed and sets up the diode of carrier Supply Structure.

Figure 12 to Figure 15 is the wherein block in a two-layer cubical array, and be such as the structural representation of the block A illustrated in fig. 2, block can have any one in the carrier Supply Structure of Fig. 2 A-Fig. 2 C.Although use regular transistor symbol at this, but the embodiment of the present invention comprises without knot NAND serial (junction-free NAND strings).

In order to clearly represent, the term " programming " that the present invention uses relates to an operation of the threshold voltage (threshold voltage) increasing memory cell.The data being stored in memory cells can be expressed as logical zero or logical one.The term " erasing " that the present invention uses relates to an operation of the threshold voltage reducing memory cell.The data utilogic " 1 " or the logical zero that are stored in eraseable memory unit represent.Multi-bit cell (multibit cells) also can have multiple different critical level (threshold levels) according to the expectation programming of designer or wipe and have the single minimum or the highest critical level.In addition, the term " write " that the present invention uses describes an operation of the threshold voltage changing memory cell, and expects the combination comprising both programming and erasing or programming and erase operation.

The programming operation that the present invention describes comprises the memory cell that is biased in selection will be electronically injected to the charge storing structure in a memory cell selected, and therefore increases threshold voltage.One programming operation can carry out to programme be such as in one page (page), a character or a hyte one or more select memory cell.In programming operation, be biased in unselected memory cell to avoid or to reduce the upset (disturbance) of electric charge of storage.

The present invention describes the block erase operation being used for N-shaped channel memory, comprise be biased in multiple unit a block hole is injected in the charge storing structure unit in the block of selection, therefore threshold voltage is reduced, the threshold voltage that at least multiple unit of block are not low at the beginning.Other programming and erasing biased operation may be used.

For two-layer 3-D stacks structure, as shown in Figure 12, according to double-layer structure block as Fig. 2 will comprise up and down totally four NAND serials, upper strata dual serial is coupled to bit line layer BLL1, and lower floor's dual serial is coupled to bit line layer BLL2.The serial choice structure of one first lamination in the lamination of multiple bit line comprises serial selector switch 824-1,824-2 of being connected to a serial selection line SSL1.Similarly, the serial choice structure of one second lamination in the lamination of multiple bit line comprises serial selector switch 825-1,825-2 of being connected to a serial selection line SSL2.Ground connection selection line GSL is covered in many and is positioned at line, forms four grounded selector switch 814-1,814-2,814-3 and 814-4.Bit line is also coupled to the N-type end 801 of PN diode 800, and order is first be coupled to one first source electrode line 803 by contact 804-1,804-2,804-3 and 804-4.The P type end of PN diode 800 is coupled to one second source electrode line 802.Identical circuit structure is illustrated in 12-15 figure.

Figure 12 illustrates a bias voltage arrangement of the unit for a selection of programming.Figure 13 illustrates the bias voltage arrangement for wiping the block in multiple memory cell.Figure 14 illustrates the another kind of bias voltage arrangement for wiping the block in multiple memory cell.Figure 15 illustrates the bias voltage arrangement for reading the unit that one in block is selected.

Therefore, memory circuit comprises a series arrangement (series arrangement) of multiple memory cell, such as, be the serial comprising memory cell 840,842,845 and 847.A second switch (being such as 814-1) on one second end of series arrangement is coupled to a first end of diode.Memory circuit also comprises many wordline WL.Circuit is coupled to many wordline, the first and second source electrode lines, ground connection selection line GSL, sequence selection line SSL and the bit line for control store circuit operation.In this structure, Circnit Layout is used for driving or first, second source electrode line of bias voltage with different bias condition.Controller can comprise configuration be used for applying one bring out hole produce erasing bias voltage arrangement, one program bias arrangement and one read bias voltage arrangement.Controller system with reference to Figure 17 describe as after.

Figure 12 illustrates program bias arrangement.In the arrangement of this bias voltage, apply one source pole lateral deviation and be pressed on the first source electrode line 803 (such as the first source contact end SC=0), when the second source electrode line 802 receives a bias voltage of reverse bias diode or the second source electrode line 802 is in the state of floating (floating), diode is closed and cannot delivered current to the second source electrode line 802, now the diode of source terminal can not affect the programming of element.

Program bias arrangement as illustrated in Figure 12 in one embodiment is be described as follows:

The wordline BL:0V selected

Unselected wordline BL:3.3V

The serial selection line SSL:3.3V selected

Unselected serial selection line SSL:0V

The wordline WL:Vpgm selected

Unselected wordline WL:Vpass

Ground connection selects line GSL:0V

Source contact end SC:0V

PN junction source terminal PNS:0V (closedown of PN diode)

The arrangement of this program bias can represent the programming pulse in a programming operation, such as increase rank type pulse program (Incremental Step Pulsed Programming, ISPP) method, for more traditional flash memory, do not need extra carrier supply, and diode system closes.

Figure 13 illustrates the erasing bias voltage arrangement that brings out tunneled holes.In one embodiment, erasing bias voltage arrangement is as illustrated in Figure 13 be described as follows:

All bit line BL: float

All serial selection line SSL:0V

All wordline WL:-8V

Ground connection selects line GSL:-2V

Source contact end SC: float

PN junction source terminal PNS:V > Vbi (unlatching of PN diode)

In this erase operation, PN diode opens, and one of hole source can be provided to carry out tunneled holes erasing.Select Gate Induced Drain electric leakage in wiretap that hole also can be provided to bit line ground connection.

Figure 14 illustrates and utilizes another kind that the Gate Induced Drain of serial choice structure and ground connection choice structure leaks electricity to wipe bias voltage to arrange.Erasing bias voltage arrangement as illustrated in Figure 14 in one embodiment is be described as follows:

All bit line BL:-8V

All serial selection line SSL:-2V

All wordline WL:-8V

Ground connection selects line GSL:-2V

Source contact end SC: float

PN junction source terminal PNS:V > Vbi (unlatching of PN diode)

In this erasing bias voltage arrangement, diode opens, and keep source contact at a reference voltage, when the first source electrode line is in quick condition, the first source electrode line does not participate in bias voltage.In order to bring out the formation in hole, serial selector switch receives a suitable negative-gate voltage, and Gate Induced Drain is leaked electricity.The memory cell being biased in selection produces FN tunneled holes.

Figure 15 illustrates a reading bias voltage arrangement.Read in bias voltage arrangement at this, diode is what close, and signal can be spread out of by the first source terminal, allows the operation according to more typical read method.In one embodiment, read bias voltage arrangement system as illustrated in Figure 15 and be described as follows:

The wordline BL:1V selected

Unselected wordline BL:0V

The serial selection line SSL:3.3V selected

Unselected serial selection line SSL:0V

The wordline WL:Vref selected

Unselected wordline WL:Vpass

Ground connection selects line GSL:3.3V

Source contact end SC:0V

PN junction source terminal PNS:0V (closedown of PN diode)

In reading process, be biased in diode makes diode two ends not have pressure drop, and in order to high speed and efficient reading, the bias voltage of diode keeps load.

The schematic diagram of the substituting circuit of Figure 16 mark one, represents enforceable another different structure.In this structure, every one deck has respective carrier supply diode.Therefore the layer being coupled to bit line layer BLL1 has a diode and comprises first end 866 and one second end 865.The layer being coupled to bit line layer BLL2 has a diode and comprises first end 861 and one second end 860.The second independent source electrode line 862 and 867 is second ends being connected to diode.Different bias voltage arrangements can be applied to the circuit shown in Figure 16 as above-mentioned discussion and with reference to the mode of 12-15 figure.

Figure 17 is the simplification calcspar of an integrated circuit 25, the nand flash memory array 10 that integrated circuit 25 comprises a p-type passage, can be operated by the embodiment of the present invention.In certain embodiments, array 10 is the three-dimensional storage comprising multilayered memory unit.One column decoder 11 is coupled to multiple bit lines 12 along the row arrangement in storage array 10.Multiple row decoders in square 16 are coupled to one group of page buffer (page buffers) 13, are in this embodiment to couple via data/address bus (data bus) 17.Global bit lines (global bit lines) 14 is coupled to local bitline (local bit lines) (not shown) along the row arrangement in memory.Position (addresses) is sent to row decoder (square 16) and column decoder (square 11) via bus 15.In addition, can be derived from circuit by square 20 and comprise driver for the first and second source electrode lines, make the first and second source electrode lines can dividually or biased independently.

Data provide from other circuit 24 (comprise is such as input/output end port) integrated circuit via Data In-Line 23, and integrated circuit is such as a general processor (general purpose processor), special-purpose applications circuit (special purpose application circuitry) or provide by the combination of the system single chip of the functional support of array 10 (system-on-a-chip) module.Data are sent to input/output end port, the data destination of other inside or the integrated circuit 25 to outside via Data In-Line 23.

One controller, be such as state machine (state machine) 19 in one embodiment, provide signal to comprise reading in array and write operation with the application controlling the bias voltage arrangement supply voltage providing via one or more voltage controller in square 18 or produce to implement operations different in the present invention.These operations comprise erasing, programming or read.Controller can be carried out by the special purpose logic circuitry of known technology (special-purpose logic circuitry).In another embodiment, controller comprises the general processor that may be implemented on same integrated circuit, and general processor performs computer program with the operation of control device.In another embodiment, the enforcement of controller can use the combination of special purpose logic circuitry and general processor.

Controller can comprise the circuit of execution one program, program comprises and is biased in diode to provide minority carrier to series arrangement with forward bias voltage drop condition in operation, change a threshold voltage of one or more memory cell in memory, in reading process, be biased in diode with reverse bias condition.For example, the program performed by the circuit in controller can be included in erase operation process and be biased in diode with a forward bias voltage drop condition.The program performed by the circuit in controller also can be included in programming operation process and be biased in diode with a reverse bias condition.

The source side of described structure NAND serial in an array comprises the performance that can improve erasing in the three-dimensional storage in an additional PN diode source.

In one embodiment, carrier Supply Structure is arranged in vertical gate nand flash memory.During operation, because thin-film transistor (TFT) structure and the electronic tunnelling erase and traditional NAND lacking body contact three-dimensional perpendicular Gate Memory may be very different.In that case, source, hole can improving device erasing.

In sum, although the present invention discloses as above with preferred embodiment and detailed example, so itself and be not used to limit the present invention.Will be appreciated that, persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.

Claims (24)

1. one kind comprises the semiconductor array arrangement of carrier supply, comprising:

One diode, has a first end and one second end;

One series arrangement (series arrangement), comprises multiple memory cell, and this series arrangement is coupled to a bit line by one first switch on one first end, is coupled to this first end of this diode by the second switch on one second end;

One first source electrode line and one second source electrode line, be connected to this first end and this second end of this diode;

Many wordline, these wordline are coupled to these memory cell corresponding in multiple memory cell; And

One circuit, is coupled to these wordline, this first source electrode line and this second source electrode line, and this circuit is configured to this first source electrode line of bias voltage and this second source electrode line under different bias condition.

2. semiconductor array arrangement according to claim 1, wherein this circuit is configured to utilization one to wipe bias voltage arrangement (erase bias arrangement) to bring out tunneled holes, this erasing bias voltage arranges the one source pole lateral deviation pressure be included on this second source electrode line, this source side bias voltage is this diode of forward bias voltage drop, when this first source electrode line keeps floating, the erasing voltage in these wordline brings out tunneled holes.

3. semiconductor array arrangement according to claim 1, wherein this circuit is configured to utilization one program bias arrangement (program bias arrangement) this program bias to arrange the one source pole lateral deviation pressure comprised on this first source electrode line, and this second source electrode line keeps floating or being subjected to bias voltage with this diode of reverse bias.

4. semiconductor array arrangement according to claim 1, wherein these memory cell comprise multiple film crystal pipe unit.

5. semiconductor array according to claim 1 arrangement, wherein these memory cell comprise the multiple film crystal pipe units be arranged on a single semiconductor bar, and in the semiconductor bar that this is single, this first end of this diode comprises a doped region.

6. semiconductor array arrangement according to claim 1, wherein these memory cell comprise the multiple film crystal pipe units be arranged on a single semiconductor bar, and in the semiconductor bar that this is single, this first end of this diode and this second end comprise a doped region separately.

7. semiconductor array arrangement according to claim 1, wherein these memory cell comprise the multiple film crystal pipe units on the single semiconductor bar that is arranged in and is covered in above semi-conductive substrate, this first end of this diode comprises the doped semiconductor materials being coupled to this single semiconductor bar and this Semiconductor substrate, and this second end of this diode comprises a doped region in the semiconductor substrate.

8. semiconductor array arrangement according to claim 1, wherein this series arrangement is a NAND gate (NAND) serial, and this memory comprises at least one extra NAND gate serial of this first end being coupled to this diode.

9. semiconductor array arrangement according to claim 1, wherein these memory cell are be configured for a N-shaped channel operation in a read mode, and this first end of this diode has N-shaped doping, and this second end of this diode has p-type doping.

10. semiconductor array arrangement according to claim 1, wherein these memory cell are be configured for a p-type channel operation in a read mode, and this first end of this diode has p-type doping, and this second end of this diode has N-shaped doping.

11. semiconductor array arrangements according to claim 1, wherein these memory cell comprise a film, multiple vertical gate unit.

12. 1 kinds of semiconductor arrays comprising carrier supply arrange, and comprising:

One cubical array, comprises multiple horizontal plane, each the multiple bar of semiconductor material comprising a contact pad and extend from this contact pad in these horizontal planes;

Multiple first diode end, one of them of these the first diode ends be long-range on a contact point of one or more these bar of semiconductor material;

One second diode end, one in these the first diode ends of this second diode end in contact;

One first source electrode line, is connected to these the first diode ends;

One second source electrode line, is connected to this second diode end;

Many wordline, are coupled to these bar of semiconductor material in these horizontal planes;

One charge-trapping element and a data storage elements, between these wordline and these bar of semiconductor material, wherein multiple memory cell is arranged on these crosspoints of these bar of semiconductor material and these wordline; And

One circuit, is coupled to this first source electrode line and this second source electrode line, and this circuit is for this first source electrode line of bias voltage under different bias condition and this second source electrode line.

13. semiconductor array arrangements according to claim 12, wherein this circuit is configured to utilization one to wipe bias voltage arrangement to bring out tunneled holes, this erasing bias voltage arranges the one source pole lateral deviation pressure be included on this second source electrode line, this source side bias voltage is forward bias voltage drop one diode, when this first source electrode line keeps floating, the erasing voltage in these wordline brings out tunneled holes.

14. semiconductor array arrangements according to claim 12, wherein this circuit is configured to the arrangement of utilization one program bias to close diode end, this program bias arranges the one source pole lateral deviation pressure comprised on this first source electrode line, when this second source electrode line keep float or pressurized with this diode of reverse bias time, now diode end does not affect element programs.

15. semiconductor array arrangements according to claim 12, more comprising many first selects line and one second to select line, these the first selection lines are coupled to the lamination of these corresponding bar of semiconductor material in these bar of semiconductor material of a near-end of these contact pads, and this second selection line covers on these bar of semiconductor material between these the first diode end and these wordline.

16. semiconductor array arrangements according to claim 12, wherein these the first diode ends comprise the multiple doped regions being arranged in these bar of semiconductor material.

17. semiconductor array arrangements according to claim 12, wherein these the first diode ends and this second diode end comprise the multiple doped regions being arranged in these bar of semiconductor material.

18. semiconductor array arrangements according to claim 12, wherein these horizontal planes cover on semi-conductive substrate, these the first diode ends and this second diode end, these the first diode ends comprise the doped semiconductor materials being coupled to these bar of semiconductor material, and this second diode end comprises the doped region being arranged in this Semiconductor substrate.

19. semiconductor array arrangements according to claim 12, wherein these memory cell are be configured for a N-shaped channel operation in a read mode, and these the first diode ends comprise n-type semiconductor, and this second diode end comprises p-type semiconductor material.

20. semiconductor array arrangements according to claim 12, wherein these memory cell are be configured for a p-type channel operation in a read mode, and these the first diode ends comprise p-type semiconductor material, and this second diode end comprises n-type semiconductor.

21. semiconductor array arrangements according to claim 12, wherein these memory cell comprise a film, multiple vertical gate unit.

22. 1 kinds of operations comprise the method for a three-dimensional flash memory (3D flash memory) of carrier supply, this three-dimensional flash memory comprises a series arrangement of multiple memory cell, one first end function of this series arrangement is the one source pole end of traditional NAND memory element, and one second end of this series arrangement is an operating side of a diode PN junction, this first end of this series arrangement is coupled to this diode, this second end of this series arrangement is coupled to a bit line, and the method comprises:

In operating process under a forward bias voltage drop condition this diode of bias voltage to provide this series arrangement minority carrier to change a threshold voltage of one or more memory cell, in reading process under a reverse bias condition this diode of bias voltage.

23. methods according to claim 22, comprising: in erase operation process, this diode of bias voltage under a forward bias voltage drop condition.

24. methods according to claim 22, comprising: in procedure operation process, this diode of bias voltage under a reverse bias condition.