KR102626137B1 - Three-dimensional vertical nor flash thin-film transistor strings - Google Patents

Abstract

A memory structure comprising active columns of polysilicon formed on a semiconductor substrate, each active column comprising one or more vertical NOR strings, each NOR string comprising thin film storage transistors sharing a local source line and a local bit line. and the local bit line is connected to a sense amplifier provided on the semiconductor substrate by one segment of the segmented global bit line.

Description

THREE-DIMENSIONAL VERTICAL NOR FLASH THIN-FILM TRANSISTOR STRINGS}

The present invention relates to high-density memory structures. In particular, the present invention relates to high-density memory structures formed with interconnected thin film storage elements, such as thin film storage transistors formed in vertical strips with horizontal word lines.

In this post, memory circuit structures are explained. The structures can be fabricated on planar semiconductor substrates (eg, silicon wafers) using conventional manufacturing processes. For clarity, the term “vertical” refers to a direction perpendicular to the surface of the semiconductor substrate, and the term “horizontal” refers to any direction parallel to the surface of the semiconductor substrate.

Numerous high-density non-volatile memory structures such as “3-dimensional vertical NAND strings” are known in the art. Many of the above high-density memory structures are formed using thin film storage transistors formed from stacked thin films (eg, polysilicon thin films) and organized into arrays of “memory strings.” One type of memory string is referred to as NAND memory strings, or simply “NAND strings.” A NAND string consists of numerous series-connected thin film storage transistors (“TFTs”). Reading or programming the content of any of the series-connected TFTs requires activation of all series-connected TFTs in the string. Thin film NAND transistors have lower conductivity than NAND transistors formed in single crystal silicon, resulting in relatively slow read access (i.e., long latency) due to the low read power required to conduct across long strings of NAND TFTs.

Another type of high-density memory structures are referred to as NOR memory strings or “NOR strings.” The NOR string includes numerous storage transistors, each connected to a shared source region and a shared drain region. Accordingly, the transistors in the NOR string are connected in parallel, so that the read current in the NOR string conducts through a much lower resistance than the read current across the NAND string. To read or program a storage transistor in a NOR string, only that storage transistor needs to be active (i.e., "on" or conducting), and all other storage transistors in the NOR string are dormant. (i.e., may remain “off” or non-conducting). Therefore, the NOR string allows much faster detection of active storage transistors to read. Conventional NOR transistors are programmed by the channel hot-electron injection technique, in which electrons are accelerated in the channel region due to the voltage difference between the source and drain regions, and an appropriate voltage is applied to the control gate. When supplied, it is injected into the charge-trapping layer between the control gate and the channel region. Channel thermal-electron injection programming requires relatively large electron currents to flow through the channel region, limiting the number of transistors that can be programmed in parallel. Unlike transistors programmed by hot-electron injection, in transistors programmed by Fowler-Nordheim tunneling or direct tunneling, electrons are supplied between the control gate and the source and drain regions. They are injected from the channel region into the electron-confinement layer by an electric field. Fowler-Nordheim tunneling, or direct tunneling, is much more efficient than channel thermo-electron injection in terms of size, allowing for massively parallel programming; However, such tunneling is more susceptible to program-disturb conditions.

3-D NOR memory arrays are disclosed in the United States by H.T Lue, entitled "Memory Architecture of 3D NOR Array", filed on March 11, 2011, registered on January 14, 2014. It is published in Patent No. 8,630,114.

Haibing Peng's published U.S. patent application entitled "Three-Dimensional Non-Volatile NOR-type Flash Memory," filed on September 21, 2015, published on March 24, 2016 No. US2016/0086970 A1 discloses non-volatile NOR flash memory devices, said non-volatile NOR flash memory devices comprising all field effect transistors located on one side or two opposite sides of a conducting channel. Individual memory cells with shared source and drain electrodes are comprised of arrays of basic NOR memory groups stacked along a horizontal direction parallel to the semiconductor substrate.

Three-dimensional vertical memory structures are described, for example, in Alsmeier et al., filed January 30, 2013, registered November 4, 2014, titled “Compact Three-Dimensional.” Published in U.S. Patent No. 8,878,278 (“Alsmeyer”), “Vertical NAND and Methods of Making Thereof.” “Alsmeyer” refers to “terabit cell array transistor” (TCAT) NAND arrays (Figure 1A), “pipe shaped bit-cost scalable” (P -BiCS) flash memory (Figure 1B), and various types of high-density NAND memory structures, such as “vertical NAND” memory string structures. Similarly, Walker et al., filed on December 31, 2002, registered on February 28, 2006, entitled "Method for Fabricating Programmable Memory Array Structures Incorporating Series - Connected Transistor Strings" U.S. Patent No. 7,005,350 (“Walker I”) also discloses a number of three-dimensional high-density NAND memory structures.

Walker's U.S. Patent No. 7,612,411 ("Walker II"), entitled "Dual-Gate Device and Method," filed on August 3, 2005, and granted on November 3, 2009, Publishes a "dual gate" memory structure in which a common active area serves independently controlled storage elements in two NAND strings formed on opposite sides of the common active area.

3-D NOR memory arrays are disclosed in U.S. Patent No. 8,630,114, entitled “Memory Architecture of 3D NOR Array,” by H. T. Louis, filed March 11, 2011, issued January 14, 2014. It is posted in the issue.

A three-dimensional memory structure comprising horizontal NAND strings controlled by vertical polysilicon gates is described in W. W. Kim et al., 2009 Symposium on VLSI Tech. Dig. of Technical Papers, pp. It is published in the paper "Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" ("Kim") published at 188-189. Another three-dimensional memory structure that also includes horizontal NAND strings along with vertical polysilicon gates is presented by H. T. Lui et al., 2010 Symposium on VLSI: Tech. Dig. It is published in the paper "A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device" published in Of Technical Papers, pp.131-132.

1A shows prior art three-dimensional vertical NAND strings 111 and 112. Figure 1B shows a basic circuit representation 140 of a prior art three-dimensional vertical NAND string. Specifically, the vertical NAND strings 111 and 112 of FIG. 1A and their circuit representation 150 - each of which has 32 or more transistors connected in series along the surface of the substrate - each have 90 volts essentially perpendicular to the substrate. is a conventional horizontal NAND string also rotated. Vertical NAND strings 111 and 112 are series-connected thin film transistors (TFTs) in a string structure that rises from the substrate like a skyscraper, with each TFT connected to one of the word line conductors within an adjacent stack of word line conductors. It has a control gate and storage element provided by . As shown in FIG. 1B , in the simplest implementation of a vertical NAND string, TFTs 15 and 16 are each connected to the first line of NAND string 150 controlled by individual word lines WL ₀ and WL ₃₁ . 1 memory transistor and the last memory transistor. The bit line select transistor 11, activated by signal BLS, and the ground select transistor 12, activated by signal SS, are positioned within the vertical NAND string 150 during read, programming, program-inhibit, and erase operations. It serves to connect the addressed TFT to the corresponding global bit line (GBL) at terminal 14 and to the global source line (ground) (GSL) at terminal 13. Reading or programming the contents of any one TFT (e.g., TFT 17) requires activation of all 32 TFTs in vertical NAND string 150, which allows each TFT to be read- Exposure to disturb and programmable-disturb conditions. These conditions limit the number of TFTs that can be provided in a vertical NAND string to no more than 64 or no more than 128 TFTs. Moreover, polysilicon thin films on which vertical NAND strings are formed have much lower channel mobility - and thus higher resistivity - than conventional NAND strings formed on single-crystal silicon substrates, resulting in lower read currents for conventional NAND strings. This results in a lower read current compared to

U.S. Patent Application Publication No. 2011/0298013 (“Hwang”), entitled “Vertical Structure Semiconductor Memory Devices And Methods OF Manufacturing The Same,” discloses three-dimensional vertical NAND strings. “Yellow” shows in Figure 4D a block of three-dimensional vertical NAND strings addressed by wrap-around stacked word lines 150 (as shown in Figure 1C of the present invention). .

Eitan's U.S. Patent No. 5,768,192, filed on July 23, 1996, and granted on June 16, 1998, entitled "Memory Cell utilizing asymmetrical charge trapping," is a disclosure of the present invention. Describes the operation of an NROM-type memory transistor of the type used in one embodiment.

U.S. Patent No. 8,026,521, entitled “Semiconductor Device and Structure,” filed October 11, 2010, issued September 27, 2011, to Zvi Or-Bach et al. discloses a first layer and a second layer of layer-transferred single-crystal silicon, where the first layer and the second layer include horizontally oriented transistors. In that structure, a second layer of horizontally oriented transistors overlaps the first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has side gates.

Transistors that have a conventional non-volatile memory transistor structure but have a short retention time may be referred to as “quasi-volatile.” In this context, conventional non-volatile memories have a data retention time of over 10 years. A planar quasi-volatile memory transistor on a single crystal silicon substrate is described by H.C. Wann and C.Hu, IEEE Electron Device letters, Vol. 16, no. 11, November 1995, pp. It is published in the paper “High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application,” published at 491-493. A semi-volatile 3-D NOR array with quasi-volatile memory is disclosed in US Pat. No. 8,630,114 to H. T. Louis, discussed above.

T. Tanaka et al., Digest of Technical Papers , 2016 IEEE International Solid-State Circuits Conference, pp. The paper “A 768 Gb 3b/cell 3D-Floating-Gate NAND Flash Memory,” published in 142-144, describes placing CMOS logic circuits beneath a three-dimensional NAND memory array.

According to one embodiment of the invention, the high-density memory structure is a three-dimensional vertical NOR flash memory string (referred to as a “multi-gate vertical NOR string” or simply “vertical NOR string”). do. The vertical NOR string includes numerous thin film transistors (“TFTs”) connected in parallel, each having a shared source region and a shared drain region extending generally in a vertical direction. Additionally, the vertical NOR string includes a number of horizontal control gates, each controlling a respective one of the TFTs in the vertical NOR string. Since the TFTs in a vertical NOR string are connected in parallel, the read current in a vertical NOR string is conducted through a much lower resistance than the read current across a NAND string of a similar number of TFTs. To read or program any one of the TFTs in the vertical NOR string, only that TFT needs to be activated, and all other TFTs in the vertical NOR string can remain non-conducting. As a result, a vertical NOR string can contain more (eg, hundreds or more) TFTs, allowing faster detection and minimizing program-disturb or read-disturb conditions.

In one embodiment, the shared drain region of the vertical NOR string is connected to a global bit line (“voltage V _bl “) and the shared source region of the vertical NOR string is connected to the global source line. line) ("voltage V _ss "). Alternatively, in a second embodiment, only the shared drain region is connected to the global bit line biased to the supply voltage, and the shared source region is connected to the global bit line biased to the supply voltage and the shared source region is connected to the global bit line biased to the supply voltage. Pre-charged. To perform pre-charging, one or more dedicated TFTs may be provided to pre-charge the parasitic capacitance (C) of the shared source region.

According to one embodiment of the present invention, multi-gate NOR flash thin film transistor string arrays (“multi-gate NOR string arrays”) are comprised of vertical NOR strings each running perpendicular to the surface of a silicon substrate. Organized as arrays. Each multi-gate NOR string array includes a number of vertical active columns arranged in rows, each row extending along a first horizontal direction, and each active column having a first horizontal direction. 1 having two perpendicular heavily-doped polysilicon regions of conductivity, wherein the two perpendicular heavily-doped polysilicon regions are undoped or lightly doped with a second conductivity. -doped) separated by one or more vertical polysilicon regions. Each of the over-doped regions forms a shared source or drain region, and each of the lightly-doped regions forms a plurality of channel regions in relation to one or more stacks of horizontal conductors, each extending perpendicular to the first horizontal direction. form them. The charge-confinement material forms multiple storage elements, covering at least the channel regions of the TFTs in the active column. Horizontal conductive lines within each stack are electrically isolated from each other and form control gates over the channel regions and storage elements of the active column. In this way, the multi-gate NOR string array forms a three-dimensional array of storage TFTs.

In one embodiment, support circuitry is formed within the semiconductor substrate to support support circuitry and a plurality of multi-gate NOR string arrays formed on the semiconductor substrate. Support circuitry includes address encoders, address decoders, sense amplifiers, input/output drivers, shift registers, latches, reference cells, power, among others. Supply lines, bias and reference voltage generators, inverters, NAND, NOR, Exclusive-Or and other logic gates, other memory elements, sequencers, and state. May include machines. Multi-gate NOR string arrays can be organized into multiple circuit blocks, each block having multiple multi-gate NOR string arrays.

According to embodiments of the invention, variations in the threshold voltages of the TFTs within a vertical NOR string can be compensated for by providing one or more electrically programmable reference vertical NOR strings within the same or another multi-gate vertical NOR string array. there is. The background leakage currents inherent in the vertical NOR string can be significantly neutralized during the read operation by comparing the results of the TFT being read with the results of the TFT being read simultaneously on the programmable reference vertical NOR string. In some embodiments, each TFT in a vertical NOR string is shaped to amplify the capacitive coupling between each control gate and their corresponding channel region, thereby removing charge from the channel regions during programming. Increases tunneling into the confinement material (i.e., storage element) and reduces charge injection from the control gate into the charge-constraint material during erasure. This advantageous capacitive coupling is particularly useful for storing two or more bits in each TFT of a vertical NOR string. In another embodiment, the charge-confinement material of each TFT may have a modified structure to provide high write/erase cycle durability despite shorter retention times requiring refresh of stored data. However, since the refreshes required for vertical NOR string arrays are expected to be much less frequent than in conventional dynamic random-access memory (DRAM), the multi-gate NOR string arrays of the present invention are suitable for several DRAM applications. It can operate in . This use of vertical NOR strings allows the advantage of significantly lower cost-per-bit characteristics compared to conventional DRAMs and allows significantly lower read-latency compared to conventional NAND string arrays.

In another embodiment, vertical NOR strings can be programmed/erased and read as NROM/Mirror-bit TFT strings.

Organizing the TFTs into vertical NOR strings -- rather than the vertical NAND strings of the prior art -- results in a performance that, compared to NAND flash strings, can (i) approach the read-latency period of a dynamic random access memory (DRAM) array; (ii) reduced sensitivity to read-disturb and program-disturb conditions associated with long NAND flash strings, and (iii) reduced cost per bit.

According to an alternative embodiment of the invention, each active column in the memory structure includes one or more vertical NOR strings, each NOR string having thin film storage transistors sharing a local source line and a local bit line, and the local The bit line is connected to a sense amplifier provided in the semiconductor substrate by one segment of a segmented global bit line. To significantly reduce read detection latency, multiple shorter global bit line segments are provided, rather than a global bit line spanning a significant distance (eg, half to the full length of the chip). Each such global segment connects one or more neighboring local bit lines via a segment connector to a segment sense amplifier provided within the semiconductor substrate. In embodiments where the local source lines are pre-charged with a virtual ground voltage (e.g., V _ss ), the parasitic capacitance of the virtual ground connects a group of neighboring local source lines to one local source line segment. This is significantly increased by providing short global source line segment connectors. The number of local source lines included within the segment determines the combined parasitic capacitance (C).

The invention will be better understood upon consideration of the detailed description below, taken in conjunction with the accompanying drawings.

1A shows prior art three-dimensional vertical NAND strings 111 and 112.
Figure 1B shows a basic circuit representation 140 of a prior art three-dimensional vertical NAND string.
Figure 1C shows a three-dimensional representation of a block of three-dimensional vertical NAND strings addressed by wrap-around stacked word lines 150.
Figure 2 shows a conceptualized memory structure 100 representing a three-dimensional organization of memory cells; According to one embodiment of the invention, memory cells are provided in vertical NOR strings, each vertical NOR string having memory cells each controlled by one of a number of horizontal word lines.
Figure 3a shows a basic circuit representation of the ZY plane of a vertical NOR string 300 formed within an active column; The vertical NOR string 300 represents a three-dimensional structure of non-volatile storage TFTs, each TFT having a global bit line (GBL) 314 and a global source line (314), respectively, according to one embodiment of the present invention. They share a local source line (LSL) 355 and a local bit line (LBL) 354, which are accessed by GSL) 313.
Figure 3b shows a basic circuit representation of the ZY plane of a vertical NOR string 305 formed within an active column; The vertical NOR string 305 represents a three-dimensional structure of non-volatile storage TFTs and, according to one embodiment of the invention, stores a voltage ( and a dedicated pre-charge TFT 370 for setting "V _ss ").
Figure 3C shows a basic circuit representation of a dynamic non-volatile storage transistor 317 connected to a parasitic capacitor 360 with one or more programmed threshold voltages; Capacitor 360 is pre-charged to temporarily maintain a virtual voltage (V _ss ) on source terminal 355 so that when control gate 323p rises to a voltage exceeding the threshold voltage, transistor 317 Allows the threshold voltage to be dynamically detected by discharge of voltage (V _ss ).
Figure 3D shows a variation of the vertical NOR memory array circuit architecture of the embodiment of Figure 3A, where global bit line (GBL) 314 is divided into bit line segments (MSBL ₁ , MSBL ₂ ,...). is replaced with, each of the bit line segments connects a plurality of neighboring vertical local bit lines 374-1, 374-2, ...; The segments are then connected to regional bit line segments (SGBL ₁ , SGBL ₂ , ...) via segment-select thin film transistors 586-1, ..., 586-n. The bit line segments are each associated with a number of bit line segments and are isolated from the sense amplifiers and other circuitry in the silicon substrate 310 beneath them by a dielectric 393.
FIG. 3E shows a variation of the circuit architecture of the embodiment of FIG. 3D , where the global source-select line 313 is connected to the neighboring vertical line segment associated with the source line segment MSSL ₁ , via the source-select transistor SLS ₁ . Access a group of local source lines (375-1, 375-2, ...).
Figure 3F shows a variation of the circuit architecture of the embodiment of Figure 3E, where global source line 313 is deleted and local source lines connected to vertical local source lines 375-1, 375-2,... Replaced by a line segment (MSSL ₁ ), the vertical local source lines are charged via pre-charge transistors (e.g., pre-charge transistor 370 ) and maintained at the virtual ground voltage (V _ss ).
Figure 3g shows a variation of the circuit architecture of the embodiment of Figure 3f, where local bit line segments (SGBL ₁ , SGBL ₂ ,...) are connected to bit line segments (MSBL ₁ , MSBL ₂ ,...). Segment-select transistors 315-1, 315-2, ... are merged and located within the substrate via vias 322 (and thus segment-select thin film transistors 586-1 in FIG. 3D, 586-2, ...) is connected to.
Figure 3h shows the circuit architecture of the embodiment of Figure 3g, where two neighboring bit line segments (MSBL ₁ , MSBL ₂ ) are dedicated to a single circuit formed within the space labeled BLO between the two bit line segments. It has their local source line segments MSSL ₁ and MSSL ₂ connected from the substrate 310 via an active vertical column 381.
Figures 3i and 3ia(3i-1) (key to Figures 3i and 3ia(3i-1)) show an XY plane view of the embodiment of Figure 3h, where each vertical local source within source segment MSSL ₁ The line is maintained at a voltage (V _ss or V _bl ) supplied through column 381.
FIG. 4A is a cross-sectional view in the ZY plane showing side-by-side active columns 431 and 432, each of which, according to one embodiment of the invention, is a vertical NOR circuit having the basic circuit representation shown in FIG. 3A or FIG. 3B. A string can be formed.
FIG. 4AA (FIG. 4A-1) is a top view of the vertical NOR string of FIG. 4A, where the conductivity of the vertical local source or drain line is reduced by a metallic material (FIG. 4A-1) at the center of the pillars of the local source or drain line. It is increased by including 420)(M).
4B shows active columns 430R, 430L, 431R, and 431L, charge-confinement layers 432 and 434, and word lines 423 p -L and 423 p -R, according to one embodiment of the present invention. ) is a cross-sectional view of the ZX plane showing ).
Figure 4C shows a basic circuit representation of the ZX plane of vertical NOR string pairs 491 and 492, according to one embodiment of the invention.
FIG. 5A shows the global bit line 514-1 (GBL ₁ ), the global source line 507 (GSL ₁ ), and the common body bias source 506 (V _bb ), according to one embodiment of the present invention. is a cross-sectional view in the ZY plane showing the connections of the vertical NOR string of the active column 531 to .
5B illustrates an example connection of body region 556 (providing P ^- channel material) by conductive pillars 591 (formed in dielectric layer 592 with P ⁺ polysilicon), according to one embodiment of the present invention. For example, here is a cross-sectional view in the ZY plane showing the connection to the conductor 590 provided above the active column 581 and running parallel to the word lines; Conductor 590 receives body bias voltage (V _bb ) from voltage source 594 in substrate 505 through via 593 in the opening of dielectric isolation 509 .
FIG. 6A illustrates a TFT 685 (T _L ) of a vertical NOR string 451a within a vertical NOR string pair 491, as described with respect to FIG. 4C, according to an embodiment of the present invention. is a cross-sectional view in the XY plane showing the TFT 684 (T _R ) of the NOR string 451b; 6A, global bit line 614-1 accesses alternating local bit lines LBL-1, and a predetermined bend 675 of transistor channel 656L is each controlled during programming. Amplifies the capacitive coupling between the gate and the corresponding channel.
FIG. 6B illustrates a TFT 685 (T _L ) of a vertical NOR string 451a within a vertical NOR string pair 491, as described with respect to FIG. 4C, according to one embodiment of the present invention. is a _cross -sectional view in the 6B, global bit line 614-1 accesses alternating (odd) local bit lines 654 (LBL-1), and global bit line 614-2 accesses local bit lines 614-2. Addressing alternating (even) local bit lines of field 657-2 (LBL-2), and local source lines (LSL-l and LSL-2) are pre-configured to provide a virtual supply voltage (V _ss ). It is charged.
FIG. 6C shows dedicated word line stacks 623 p , each having word lines that surround (“wrap around”) a TFT of a vertical NOR string, a global horizontal bit line 614 and a global horizontal source line ( is a cross-sectional view in the ; In Figure 6C, adjacent word line stacks 623p are isolated from each other by an air gap 610 or another dielectric isolation.
FIG. 6D shares word-line stacks 623 p , similar to those shown in FIG. 6C , and pre-charge parasitic capacitors 660 each providing a pre-charge virtual supply voltage (V _ss ). is a cross-sectional view in the XY plane showing the staggered close-packing of vertical NOR strings.
Figure 6E shows the body bias voltage (V _bb ) shared between body regions 656 (L+R) in adjacent rows of active columns (e.g., using the layout of the embodiment shown in Figure 6B). For example, this is a diagram showing what is provided (via conductors 690-1 and 690-2) in the XY plane.
FIG. 6F is a diagram illustrating an example of implementation of global word lines for connecting local word lines on one plane (i.e., in one cascade step) in relation to the bit line segmentation method of the present invention.
6G shows a vertical NOR string memory array that avoids doubling the silicon area taken up by word line cascades when the number of layers of storage transistors is doubled in the vertical direction, according to one embodiment of the present invention. This is a drawing showing an example of implementation.
7A, 7B, 7C, and 7D are cross-sectional views of intermediate structures formed in a manufacturing process for a multi-gate NOR string array, according to an embodiment of the present invention.
FIG. 7D (FIG. 7D-1) shows in the XY plane the inclusion of conductive material 720 (M) in the core of the vertical pillars of the local source line or local bit line.
Figure 8A is a schematic diagram of a read operation for embodiments in which the local source line (LSL) of the vertical NOR string is hard-wired; In Figure 8A, “WL _S ” represents the voltage on the selected word line, and all unselected word lines (“WL _NS ”) in the vertical NOR string are set to 0V during a read operation.
FIG. 8B is a schematic diagram of a read operation for embodiments where the local source line is floating at the pre-charge virtual voltage (V _ss ); In Figure 8B, "WL _CHG " represents the gate voltage on a pre-charge transistor (e.g., pre-charge transistor 317 or 370 in Figure 3C).

Figure 2 shows a conceptualized memory structure 100 showing a three-dimensional organization of memory cells (or storage elements) provided within vertical NOR strings. According to one embodiment of the invention, in the conceptualized memory structure 100, each vertical NOR string includes memory cells each controlled by a corresponding horizontal word line. In the conceptualized memory structure 100 , each memory cell is formed “vertically”, i.e., in stacked thin films provided along a direction perpendicular to the surface of the substrate layer 101 . Substrate layer 101 may be, for example, a conventional silicon wafer used to fabricate integrated circuits, familiar to those skilled in the art. In this detailed description, a Cartesian coordinate system (such as that shown in Figure 2) has been adopted solely for the purpose of facilitating explanation. Under the above coordinate system, the surface of the substrate layer 101 is considered a plane parallel to the X-Y plane. Accordingly, as used in this description, the term “horizontal” refers to any direction parallel to the X-Y plane and the term “vertical” refers to the Z-direction.

In Figure 2, each vertical column in the Z-direction represents storage elements or TFTs within a vertical NOR string (eg, vertical NOR string 121). The vertical NOR strings are arranged in a regular manner within columns each extending along the X-direction. (Of course, alternatively, the same arrangement can be viewed as an array of columns, each extending along the Y-direction.) The storage elements of the vertical NOR string are connected to the vertical local source line and the vertical local bit line (as shown). does not work) is shared. A stack of horizontal word lines (e.g., WL 123) runs along the Y-direction, with each word line connected to corresponding TFTs of vertical NOR strings located adjacent to the word line along the Y-direction. It serves as control gates for Global source lines (e.g., GSL 122) and global bit lines (e.g., GBL 124) generally extend below or on the top of the conceptualized memory structure 100, Directions are provided along the lines. Alternatively, signal lines GSL 122 and GBL 124 may both be routed below the conceptualized memory structure 100 (or may both be routed on top of the conceptualized memory structure), Each of the signal lines can be selectively connected to the local source lines and local bit lines of the respective vertical NOR strings by access transistors (not shown). Unlike the vertical NAND strings of the prior art, in the vertical NOR string of the present invention, writing to or reading any one of its storage elements does not result in activation of any other storage element in the vertical NOR string. does not entail As shown in FIG. 2 , for illustrative purposes only, the conceptualized memory block 100 is a multi-gate vertical NOR string array consisting of a 4×5 array of vertical NOR strings, with each NOR string generally It has more than 32 storage elements and access selection transistors. As a conceptualized structure, memory block 100 is merely an abstraction of certain key features of the memory structure of the present invention. Although shown in Figure 2 as a 4x5 array of vertical NOR strings, each vertical NOR string has numerous storage elements, and the memory structure of the present invention provides a random array of storage elements in each row along the X-direction or Y-direction. can have any number of vertical NOR strings, and any number of storage elements within each vertical NOR string. For example, thousands of vertical NOR strings may be arranged in rows along both the , 128, or more storage elements.

The number of storage elements within each vertical NOR string (e.g., vertical NOR string 121) in FIG. 2 depends on the word lines (e.g., WL 123) that provide control gates to the vertical NOR string. corresponds to the number of The word lines are formed from long narrow metal strips, each extending along the Y-direction. The word lines are stacked on top of each other and electrically isolated from each other by dielectric insulating layers between them. The number of word lines in each stack can be any number, but is preferably an integer power of 2 (i.e., 2 ⁿ , where n is an integer). The choice of a power of 2 for the number of word lines follows conventional memory design practice. It is customary to access each addressable unit of memory by decoding its binary address. The above practices are a matter of preference and do not have to be followed. For example, within the scope of the present invention, the conceptualized memory structure 100 may have M vertical NOR strings along each row in the X-direction and Y-direction, where M must be (a random integer (for n) 2 is a number that does not have to be ⁿ . In some embodiments described below, two vertical NOR strings may share a vertical local source line and a vertical local bit line, but their respective storage elements are controlled by two separate word line stacks. . This effectively doubles the storage density of a vertical NOR string.

The conceptualized memory structure 100 of FIG. 2 is provided merely to illustrate the organization of memory cells and is therefore not drawn to a specific scale in any of the X-direction, Y-direction, and Z-direction.

Figure 3A shows the basic circuit surface in the ZY plane of a vertical NOR string 300 formed in an active column; The vertical NOR string 300 represents a three-dimensional array of non-volatile storage TFTs, each TFT having a local source line (LSL) 355 and a local bit line 354, according to one embodiment of the invention. ) share. In this detailed description, the terms “active region,” “active column,” or “active strip” refer to a region, column, or strip of one or more semiconductor materials from which an active device (e.g., transistor or diode) can be formed. refers to As shown in Figure 3A, vertical NOR string 300 runs along the Z-direction, and TFTs 316 and 317 are connected to a vertical local source line 355 and a vertical local drain or bit line 354. are connected in parallel. Bit line 354 and source line 355 are separated from each other, with the area between them (i.e., body area 356) providing channel areas for the TFTs in the vertical NOR string. Storage elements are formed at intersection points between the channel region 356 and each horizontal word line 323 p , where p is the index of the word line in the word line stack; In the above example, p can take any value between 0 and 31. Word lines extend along the Y-direction. The local bit line 354 is connected to a horizontal global bit line (GBL) 314 via a bit line access select transistor 311, which runs along the ) is connected to the access bit line supply voltage (V _bl ). Local source line 355 is connected to the source supply voltage (V _ss ) via a horizontal global source line (GSL) 313 . An optional source-select transistor (not shown in Figure 3A) may be provided to connect between local source line 355 and GSL 313. As known to those skilled in the art, the optional source-select transistor may be implemented within a substrate (e.g., semiconductor substrate 101 of FIG. 2) or above the substrate and below the memory structure 100. It can be controlled by circuitry. The body region 356 of the active column may be connected to a substrate bias voltage (V _bb ) at terminal 331 . A substrate bias voltage (V _bb ) may be used, for example, during an erase operation. The V _bb supply voltage may be supplied to the entire multi-gate vertical NOR string array, or may be selectively supplied to one or more rows of vertical NOR strings through a decoding mechanism. The lines connecting the V _bb supply voltage to body region 356 preferably run along the direction of the word lines.

Figure 3b shows a basic circuit representation of the ZY plane of a vertical NOR string 305 formed within an active column; The vertical NOR string 305 represents a three-dimensional structure of non-volatile storage TFTs and, according to one embodiment of the invention, has a shared parasitic capacitance C (represented by capacitor 360). Includes (optionally) a dedicated pre-charge TFT 370 for instantaneously setting the voltage (“V _ss “) on the local source line 355. Unlike vertical NOR string 300 in FIG. 3A, vertical NOR string 305 does not implement GSL 313, but rather connects GSL to pre-charge transistor 370, which pre-charges parasitic capacitor 360. Instead, the parasitic capacitor temporarily maintains a voltage of V _ss volts. Under the pre-charge method, global source lines (e.g., global source lines 313 in FIG. 3A) and their decoding circuitry become unnecessary, so both the circuit layout as well as the manufacturing process are simplified, and each vertical This provides a very tight footprint for the NOR string of . Figure 3C highlights the structure of non-volatile storage TFTs 317, which, in addition to their normal storage functions, can also be used to perform the pre-charge function of the dedicated pre-charge transistor 370. Dynamic read operations for TFT 317 are described below in relation to detecting which of several threshold voltages are programmed into the storage element 334 of TFT 317 is correct.

FIG. 4A is a cross-sectional view in the ZY plane showing active columns 431 and 432 side by side, each of which is a vertical NOR circuit having the basic circuit representation shown in FIG. 3A or FIG. 3B, according to one embodiment of the invention. A string can be formed. As shown in Figure 4A, active columns 431 and 432 each have a vertical N+ doped local source region 455 and a vertical N+ doped local source region 455, separated by a P- lightly-doped or undoped channel region 456. and an N+ doped local drain or bit line region 454. P- doped channel region 456, N+ doped local source region 455, and N+ doped local drain or bit line region 454 have body bias voltage (V _bb ), source supply voltage (V _ss ), and bit voltage, respectively. It can be biased with line voltage (V _bl ). In some embodiments of the invention, the use of a body bias voltage (V _bb ) becomes optional, such as when the active strip is sufficiently thin (eg, 10 nanometers or less). For sufficiently thin active strips, the active area can easily be completely depleted below the appropriate voltage on the control gate, so that the voltage V _bb does not provide a solid supply voltage to the channel regions of the TFTs along the vertical NOR string. It may not be possible. Isolation region 436 electrically insulating active columns 431 and 432 may be a dielectric insulator or an air-gap. A vertical stack of word lines 423 p , respectively labeled WL ₀ - WL ₃₁ (and optionally WL _CHG ), provides control gates to TFTs in vertical NOR strings formed in active columns 431 and 432. to provide. Word line stack 423 p is typically formed of long, narrow metal conductors (e.g., tungsten, silicide or salicide) extending along the Y-direction, each typically silicon oxide. They are electrically isolated from each other by the dielectric layers 426 formed by (eg, SiO ₂ ) or an air gap. The non-volatile storage element provides a charge-confining material (not shown) between the word line 423 p and the P-doped channel region 456, thereby providing a charge-confining material (not shown) between each word line 423 p and each P-doped channel region 456. It may be formed at an intersection point of the channel area 456. For example, Figure 4A shows dotted boxes 416, indicating locations where non-volatile storage elements (or storage transistors) T ₀ to T ₃₁ may be formed. The dotted box 470 shows that when all transistors T ₀ to T ₃₁ are in the off state, when momentarily switched on, charge flows from the common local bit line region 454 to the common local source line region 455. ) indicates where a dedicated pre-charge transistor can be formed, allowing the transfer to be made.

4B shows active columns 430R, 430L, 431R, and 431L, charge-confinement layers 432 and 434, and word line stacks 423 p -L and 423 p -, according to one embodiment of the present invention. It is a cross-sectional view of the ZX plane showing R). Similar to FIG. 4A , each of the vertical word line stacks 423 p -L and 423 p -R in FIG. 4B represents a stack of long, thin conductors, where p is an index labeling the word lines within the stack (e.g. For example, word lines (WL ₀ to WL ₃₁ ). As shown in Figure 4B, each word line is connected to non-volatile TFTs in vertical NOR strings formed on adjacent active columns 430L and 431R on opposite sides of the word line (in region 490). It serves as control gates for For example, in FIG. 4B, word line WL ₃₁ in word line stack 423p -R controls both transistor 416L on active column 430L and transistor 416R on active column 431R. They function as gates. Adjacent word line stacks (e.g., word line stacks 423 p -L and 423 p -R) have a trench formed by etching successive word line layers, as described below. They are separated by a distance (495), which is the width of . Active columns 430R and 430L and their respective charge-confinement layers 432 and 434 are formed substantially within the trench that etched the word line layers. A charge-confinement layer 434 is provided sandwiched between the word line stack 423 p -R and the vertical active columns 431R and 430L. As described in detail below, during programming of transistor 416R, the charge injected into charge-confined layer 434 is confined to the portion of charge-constrained layer 434 within the dashed box 480. The bound charge changes the threshold voltage of TFT 416R, which can be detected by measuring the read current flowing between local drain region 454 and local source region 455 on active column 431R (this region are shown, for example, in an orthogonal cross-section of the active column in Figure 4a). In some embodiments, pre-charge word line 478 (i.e., WL _CHG ) is used to charge the parasitic capacitance (C) of local source line 455 to ground or source supply voltage (V _ss ). It serves as the control gate of the charging TFT 470 (see capacitor 360 in Figure 3B and local source line 455 in Figure 4A). Conveniently, charge-confined layer 434 also provides a storage element within pre-charge transistor 470, but it is not used alone as a memory transistor. Pre-charging may alternatively be performed using any of the memory transistors T ₀ to T ₃₁ formed on active column 431R. One or more of the memory transistors may, in addition to their storage function, perform the function of a pre-charge transistor. To perform pre-charge, the voltage on the word line or control gate is temporarily raised a few volts above its highest programmable threshold voltage, such that the voltage supplied to the local bit line 454 (V _ss ) is equal to or greater than the local source line. (455) (Figure 4a). When the memory transistors T ₀ to T ₃₁ perform the pre-charge function, a separate dedicated pre-charge TFT 470 is not needed. However, when this memory TFT performs its pre-charge function, care must be taken to avoid excessively disturbing the threshold voltage of this memory TFT.

Although active columns 430R and 430L are shown in FIG. 4B as two separate active columns separated by an air-gap or dielectric isolation 433, adjacent vertical N+ local source lines are connected to a single, shared vertical Can be implemented by local source line. Likewise, N+ vertical local drains or bit lines can be implemented by a single shared vertical local bit line. This configuration provides a "vertical NOR string pair". In that configuration, active columns 430L and 430R can be viewed as two branches (hence, a “pair”) within one active column. The vertical NOR string pair flows through charge-confinement layers 432 and 434 sandwiched between active columns 430R and 430L and word line stacks 423 p -L and 423 p -R on opposite sides. Provides double-density storage. In fact, active columns 430L and 430R can be merged into one active string by eliminating the air gap or dielectric insulation 433, but a pair of NOR TFT strings implemented on two opposite sides of a single active column Still achieved. Because the TFTs formed on opposite sides of the active columns are controlled by individual word line stacks and formed with individual charge-confinement layers 434 and 432, this configuration achieves the same double-density storage. It is advantageous to maintain separate thin active columns 430R and 430L (i.e., instead of merging them into one active column), since the TFTs on each active column are thinner than the merged column, and therefore an appropriate control gate voltage. Under conditions that can be more easily fully depleted, significantly reducing the source-drain subthreshold leakage current between the vertical drain regions 454 and vertical source regions 455 of the active columns. This is because there is (Figure 4a). Having very-thin (and therefore high-resistivity) active columns is possible for very long vertical NOR strings (e.g. 128 TFTs or longer), as the TFTs in the string are connected in series. In contrast to the high-resistance of a NAND TFT string, which requires all of the TFTs in the string to be switched on in order to sense any one of them, the TFTs in a vertical NOR string are connected in parallel so that only one of the many TFTs is switched on at any time. Because it becomes. For example, in a 32-TFT vertical NOR string, to be able to read transistor T ₃₀ (FIG. 4A), the channel length of channel region 456 may be 32 times longer, or 640 nanometers. , compared to the corresponding channel length of a NAND string, may be only 20 nanometers.

Figure 4C shows a basic circuit representation of the ZX plane of vertical NOR string pairs 491 and 492, according to one embodiment of the invention. As shown in Figure 4C, vertical NOR strings 451b and 452a are connected to a common word line stack 423 in the manner shown for the vertical NOR strings of active strips 430L and 431R in Figure 4B. p -R) is shared. For their respective common-connected local bit lines, vertical NOR string pairs 491 and 492 are accessed by global bit line 414-1 (GBL ₁ ) and via access select transistor 411, respectively. It is served by global bit line 414-2 (GBL ₂ ) via select transistor 414. For their respective common-connected local source lines, vertical NOR string pairs 491 and 492 are connected to global source line 413-1 (GSL ₁ ) and global source line 413-2 (GSL ₂ ), respectively. ) (source line select access transistors can be provided similarly and are therefore not shown in Figure 4c). As shown in Figure 4C, the vertical NOR string pair 491 is composed of vertical NOR strings 451a and 451a that share a local source line 455, a local bit line 454, and an optional body connection 456. 451b). Accordingly, vertical NOR string pair 491 represents the vertical NOR strings formed on active columns 430R and 430L in FIG. 4B. Word line stacks 423 p -L and 423 p -R (in this example, 31≧ p ≧0) provide control gates for vertical NOR string 451a and vertical NOR string 451b, respectively. . The word lines to the control gates in the stack are such that appropriate voltages are supplied to the addressed TFT (i.e., the activated word line) and to the unaddressed TFTs (i.e., all other non-activated word lines in the string). To ensure this, it is decoded by a decoding circuit formed on the substrate. Figure 4C shows how storage transistors 416L and 416R on active columns 430L and 431R of Figure 4B are served by the same word line stack 423p -R. Accordingly, the vertical NOR string 451b of the vertical NOR string pair 491 and the vertical NOR string 452a of the vertical string pair 492 are adjacent to each other formed on the active columns 430L and 431R in FIG. 4B. Corresponds to vertical NOR strings. The storage transistors (e.g., storage transistor 415R) of vertical NOR string 451a are served by word line stack 423p -L.

In another embodiment, the hard-wired global source lines 413-1, 413-2 of Figure 4C are removed - common to both vertical NOR strings 451a and 451b - and the shared N+ local Parasitic capacitance between source line 455 and its numerous associated word lines 423 p -L and 423 p -R (e.g., by capacitor 460 in Figure 4C or capacitor 360 in Figure 3C). It is replaced by the parasitic capacitance expressed. In a vertical stack of 32 TFTs, each of the 32 word lines contributes their parasitic capacitance to provide the total parasitic capacitance (C), so that during the relatively short duration of read or programming operations, the virtual source voltage (V _ss ) is large enough to temporarily maintain the voltage provided by the pre-charge TFT 470 to provide . In this embodiment, the virtual source voltage temporarily maintained on parasitic capacitor C is transferred from global bit line GBL ₁ to local source line 455 via access transistor 411 and pre-charge transistor 470. provided. Alternatively, one or more of the memory TFTs in the vertical NOR string, in addition to their storage function, may load the local source line 455 by momentarily raising its word line voltage above its highest programmed voltage. If used for pre-charging, the dedicated pre-charge transistor 470 can be eliminated. However, using a storage TFT for this purpose must be done with care to avoid over-programming the storage TFT. Using a virtual V _ss voltage offers the significant advantage of eliminating hard-wired global source lines (e.g., GLS ₁ , GLS ₂ ) and their associated decoding circuitry and access transistors, thereby substantially improving the process flow and This simplifies design challenges and results in vertical NOR strings being significantly more compact.

FIG. 5A illustrates the common to global bit line 514-1 (GBL ₁ ) of the vertical NOR string of active column 531, to global source line 507 (GSL ₁ ), according to one embodiment of the present invention. is a cross-sectional view in the ZY plane showing connections to body bias source 506 (V _bb ). As shown in Figure 5A, bit-line access select transistor 511 connects GBL ₁ with local bit line 554, and buried contact 556 connects the P-body region on the active strip to the substrate. It is selectively connected to the body bias source 506 (V _bb ) within. A bit-line access select transistor 511 is formed above the active column 531 in FIG. 5A. However, alternatively, the bit-line access select transistor 511 may be formed at the bottom of the active column 531 or within the substrate 505 (not shown in Figure 5A). In Figure 5A, bit-line access select transistor 511 may be formed, for example, in an isolation island of an N+/P-/N+ doped polysilicon stack along with access select word line 585. When a sufficiently large voltage is supplied to select word line 585, the P-channel is inverted, connecting local bit line 554 to GBL ₁ . Word line 585 runs along the same direction (i.e., Y-direction) as word lines 523 p , which serve as control gates for the vertical NOR string of TFTs. The word line 585 may be formed separately from the word lines 523 p . In one embodiment _{, GBL 1 runs} horizontally along the Provides access to only one local bit line, local bit line 554. To increase the efficiency of read and programming operations, in a multi-gate NOR string array, thousands of global bit lines may be used to parallel access the local bit lines of thousands of vertical NOR strings accessed by word line 585. You can. 5A , local source line 555 is connected to global source line 513-1 (GSL ₁ ) via contact 557, which may be connected to, for example, decoding circuitry in substrate 505. It can be decoded by .

Alternatively, as already described, provide a virtual source voltage (V _ss ) on local bit line 555 and through TFT 570 to a parasitic capacitor 560 of local source line 555 (i.e., By temporarily pre-charging the capacity (C), the global source line can be eliminated.

Support circuitry formed within substrate 505 may include, among other things, address encoders, address decoders, sense amplifiers, input/output drivers, shift registers, latches, reference cells, power supply lines, bias and reference voltages. It may include generators, inverters, NAND, NOR, Exclusive-Or and other logic gates, other memory elements, sequencers, and state machines. Multi-gate NOR string arrays can be organized into multiple circuit blocks, each block having multiple multi-gate NOR string arrays.

FIG. 6A shows a TFT 685 (T _L ) of vertical NOR string 451a and TFT 684 of vertical NOR string 451b in a pair of vertical NOR strings 491, as described with respect to FIG. 4C. ) is a cross-sectional view of the XY plane showing (T _R ). As shown in Figure 6, TFTs 684 and 685 share an N+ local source region 655 and an N+ local drain or bit line region 654, both of which are long along the Z-direction and Extended with thin pillars. (N+ local source region 655 corresponds to local source line 455 in Figure 4A, and N+ local drain region 654 corresponds to local bit line 454 in Figure 4A). In the above example, P-doped channel regions 656L and 656R form a pair of active strings between local source pillar 655 and local drain pillar 654, extending along the Z-direction, and forming an isolation region ( 640) are isolated from each other. Charge-confinement layer 634 is between word line 623 p -L (WL _31-0 ) and word line 623 p -R (WL _31-1 ), and in channel regions 656L and 656R, respectively. formed externally. Charge-confinement layer 634 is a tunnel, followed by a thin layer of charge-confinement material, such as isolated floating gates, or conductive nanodots embedded in, for example, silicon nitride or a non-conducting dielectric material. The transistor gate dielectric material may be comprised of a thin film of a dielectric (e.g., silicon dioxide), a high dielectric constant film such as aluminum oxide or hafnium oxide, or a combination of several of these dielectrics, or an ONO (oxygen-nitrogen-oxide) material. covered with a blocking dielectric layer, such as an oxygen tri-layer. Source-drain conductivity is controlled by word lines 623 p -L and 623 p -R, respectively forming control gates on the exterior of charge-confinement layer 634. When programming or reading TFT 684 (T _R ), TFT 685 (T _L ) is turned off by maintaining an appropriate inhibit voltage on word line 623 p -L. Likewise, when programming or reading TFT 685 (T _L ), TFT 684 (T _R ) is turned off by maintaining an appropriate inhibit voltage on word line 623 p -R.

In the embodiment shown in Figure 6A, word lines 623p -L and 623p -R are TFT-translated to reduce reverse-tunneling efficiency during erasing, while increasing tunneling efficiency during programming. They are outlined with fields 684 and 685. In particular, as will be known to those skilled in the art, curvature 675 in channel region 656R reduces the electric field at the interface between the word line and the blocking dielectric during erasing, but reduces the electric field at the interface between the active channel polysilicon and the tunneling dielectric during programming. Amplifies the electric field. This feature is particularly beneficial when storing more than two bits per TFT transistor in a multi-level cell (MLC) configuration. Using this technique, 2, 3, or 4 or more bits can be stored in each TFT. In fact, TFTs 684 and 685 can be used as analog storage TFTs with successive storage states. Following a programming sequence (described below), electrons are confined within the charge-confinement layer 634, as schematically represented by dashed lines 680. In Figure 6A, global bit lines 614-1 and 614-2 run perpendicular to word lines 623p -R and 623p -L, and bit lines 414-1 and 414- in Figure 4C. Corresponding to 2), respectively, vertical NOR strings are provided above or below. As described above with respect to FIG. 2 , word lines may span the entire length of memory block 100 along the X-direction, while global bit lines span memory block 100 along the Y-direction. ) can span the width of 6A, the important thing is that word line 623p -R is shared by TFTs 684 and 683 of two perpendicular NOR strings on opposite sides of word line 623p -R. Accordingly, to allow TFTs 684 and 683 to be read or programmed independently, global bit line 614-1 (GBL ₁ ) is connected to local drain or bit line region 657-1 (“odd address and global bit line 614-2 (GBL ₂ ) contacts local drain or bit line region 657-2 (“even addresses”). To achieve this effect, the contacts along global bit lines 614-1 and 614-2 are staggered, with each global bit line receiving every other pair of vertical NOR strings along the X-direction row. Contact.

In a similar manner, the global source lines (not shown in Figure 6A), which can be positioned below or above the multi-gate NOR string array, can run parallel to the global bit lines and perpendicular to the odd or even addresses. The local source lines of the NOR string pairs of can be contacted. Alternatively, if temporarily pre-charging the parasitic capacitor (i.e., capacitor 660) with the virtual source voltage (V _ss ) is used, global source lines do not need to be provided, thereby improving the process as well as the decoding method. Complexity becomes simple.

Figure 6A shows just one of several possible embodiments in which vertical NOR string pairs may be provided with stacked word lines. For example, curvatures 675 within channel region 656R may be further emphasized. Conversely, this curvature can be completely eliminated (i.e. straightened) as shown in the embodiment of FIG. 6B. 6B, the isolation gap 640 of FIG. 6A can be reduced or completely eliminated by merging channel regions 656L and 656R into a single region 656(L+R), resulting in a dual-channel Area efficiency can be further increased without sacrificing configuration: for example, TFT 685 (T _L ) and TFT 684 (T _R ) are located on opposite sides of the same active strip. 6A and 6B, vertical NOR strings that share a word line can be laid out in a pattern that is staggered relative to each other (not shown), so that the vertical NOR strings are close to each other. There is, and thus the effective footprint of each vertical NOR string can be reduced. 6A and 6B show a direct connection through a contact between the global bit line 614-1 and the N+ doped local drain bit line pillar 654 (LBL-1), such connection can also be made through a bit-line access select transistor. This can be achieved using (e.g., bit line access select transistor 511 in Figure 5A, not shown in Figures 6A and 6B, which is already complex).

In the embodiments of FIGS. 6A and 6B , N+ doped local drain region 654 and its adjacent local N+ doped region (corresponding to isolation region 436 in FIG. 4A) such that the charge-confinement layers are merged together during stacking. The dielectric isolation between source regions 658 may, for example, separate isolation 676 between word lines 623 p -R and 623 p -L to form two back-to-back charges. -Can be built by defining less than the thickness of the constraining layers. Merging the stacked charge-confinement layers results in a desirable dielectric isolation. Alternatively, the isolation between adjacent active strings creates a gap 676 (air gap or filled dielectric) that isolates the N+ pillars 658 of one string from the N+ pillars 654 of an adjacent string (i.e. , can be achieved by using a high aspect ratio etch of N+ polysilicon to create a gap 436, as shown in FIG. 4A.

In contrast between the vertical NAND strings of the prior art and the vertical NOR strings of the present invention, both types of devices use thin film transistors with similar word line stacks as control gates, but their transistor orientations are different: Prior Art In a NAND string, each vertical active strip can have 32, 48, or more TFTs connected in series. Conversely, each active column (vertical column) forming the vertical NOR strings of the present invention may have one or two sets of 32, 48, or more TFTs connected in parallel. In prior art NAND strings, the word lines in some embodiments typically wrap around the active strip. In some embodiments of the vertical NOR string of the present invention, separate designed left and right word lines are used for each active strip, as shown in Figures 4C, 6A, and 6B, so that each global bit line The storage density for is doubled (i.e., pairs). The vertical NOR strings of the present invention do not suffer from program-disturb or read-disturb degradation, nor do they suffer from the slow latency of prior art NAND strings. Therefore, a much larger number of TFTs can be provided in a vertical NOR string than in vertical NAND strings. However, vertical NOR strings are more susceptible to subthreshold or other leakage between long vertical source and drain diffusions (e.g., local source region 455 and local drain region 454, respectively, shown in Figure 4A). can do.

Two additional embodiments of the vertical NOR string of the present invention are shown in FIGS. 6C and 6D. In the above embodiments, all word lines within each word-line stack wrap around a vertical active strip.

In Figure 6C, vertical NOR strings are formed within voids formed by etching metal word lines and a stack of dielectric isolation layers between word lines. The manufacturing process flow is similar to that of prior art vertical NAND strings, except that the transistors in a vertical NOR string are provided in parallel with each other, as opposed to in series in a vertical NAND string. Forming the transistors within the vertical NOR string provides a shared local source line 655 (LSL) and a shared local bit line (drain) 654 (LBL) to all of the TFTs along the vertical NOR string. This is facilitated by N+ doped vertical pillars extending the entire depth of the void, with undoped or lightly-doped channel regions 656 adjacent to them. The charge storage element 634 is located between the channel 656 and the word line stack 623 p to store 2, 4, 8, ... 32, 64, or more TFTs (e.g. For example, device 685 (T ₁₀ ) is formed. 6C , the word line stacks run in the Y-direction, with individual horizontal strips 623 p (WL _31-0 ), 623 p (WL _31-1 ) forming an air gap or dielectric isolation. 610). Global bit lines 614 (GBL) and global source lines 615 (GSL) run horizontally in columns along the X-direction, perpendicular to the word lines. Each global bit line 614 accesses local bit line pillars 654 (LBL) along the row of vertical strips via access select transistors (511 in Figure 5A, not shown in Figure 6C), The access select transistor may be located below or above the memory array. Similarly, each global source line 615 accesses local source line pillars along the row. Although the structures shown in Figures 6A and 6B can fit a pair of vertical NOR strings into approximately the same area taken by a single vertical NOR string of the embodiment of Figure 6C, each vertical NOR string shown in Figure 6C Each TFT within has two parallel conducting channels (i.e., channel regions 656a and 656b), allowing it to store more charge and increase or double the read current, allowing each TFT More bits can be stored.

Figure 6d shows a more compact vertical NOR string with wrap-around word lines, according to one embodiment of the invention. As shown in FIG. 6D, the vertical NOR strings are staggered to be closer to each other, so that the word line stack 623 p (WL _31-0 ) can be shared by more vertical NOR strings. A staggered configuration may be possible using a parasitic capacitor (i.e., parasitic capacitors 660) of the local source line pillar 655 (LSL). As described below, the hard-wired global source lines (e.g., in FIG _. 6C GSL(615)) becomes unnecessary. Compared to prior art vertical NAND strings (e.g., the NAND strings of Figure 1C), the vertical NOR strings of Figures 6C and 6D cannot provide significant area efficiency on their own, but these vertical NOR strings The string length is much longer than vertical NAND strings. For example, the vertical NOR strings of the present invention may well support strings of TFTs of length 128 to 512 or more in each stack, but given the severe limitations that come with series-connected TFT strings, such String lengths are simply not feasible for a vertical NAND string.

Alternative embodiments having long global bit lines split into short, segmented bit lines to facilitate quick access to sense amplifiers.

The inventors have used global interconnection conductors provided above or below the memory array, along with sense amplifiers and other support circuits provided on the semiconductor substrate to connect global bit lines to vertical local bit lines (e.g. Note that routing the global bit line (GBL ₁ ) in Figure 5A (connected to the vertical local bit line 554) results in large RC delays resulting from the significant length of wiring. Moreover, it uses up the area of the silicon substrate beneath the memory arrays (as opposed to taking up precious silicon real estate next to the arrays), such as sense amplifiers, decoders, voltage sources, and other circuitry needed for memory operations. It is highly desirable to form numerous support circuits.

According to one embodiment of the invention, the conductor to be used as a global bit line may alternatively be segmented into a number of relatively short line segments (e.g., each line segment being less than 1/100th of the global bit line). can have any length). Each line segment provides a horizontal line connector for connecting a group of neighboring vertical local bit lines. It may be desirable for the bit line segments to be located between and genetically isolated from the substrate and the memory arrays. The bit line segment facilitates connections between neighboring vertical local bit lines within a group and dedicated sense amplifiers and other support circuitry formed in the semiconductor substrate beneath the array of vertical NOR strings. In this detailed description, the term “bit line segment” may refer to a collection of local bit lines connected by a line connector.

Similarly, conductors to be alternatively used as global source lines may also be segmented into a number of relatively short line segments, each of which is a horizontal line connector for connecting a group of neighboring vertical local source lines. provides. The line connector and its associated vertical local source lines form a common source line whose parasitic capacitance is many times greater than the parasitic capacitance of just one vertical local source line. The common source line connector may be connected to the global source line by a segment-select transistor, preferably at the top of the array. In this detailed description, the term “source line segment” may refer to a collection of local source lines connected by a line connector. If a source line segment can be further divided into smaller groups of connected local source lines, each such smaller group may be referred to as a “source line sub-segment.”

In another alternative embodiment of the invention, global source lines running on top of or below the memory stacks are not provided, but the neighboring vertical local source lines of each source line segment and its associated group are localized. It operates as a common source area. In that configuration, one or more pre-charge transistors are provided in each active column connected to a source line segment to transfer a virtual ground voltage (V _ss ) from the substrate. In a 64-layer vertical NOR memory array, each local source line may have a parasitic capacitance of approximately 1 femtofarad (i.e., 1.0×10 ^-15 farad), which in some cases may be , provides too little charge to maintain the virtual ground voltage (V _ss ) during charge-sharing readout operations. By combining the capacities of a group of 64 local source lines, their combined pre-charge capacity (C) increases to approximately 64 femtofarads, which is more than sufficient for charge-sharing readout operation.

3D, 3E, 3F, and 3G illustrate the present invention utilizing the silicon substrate beneath the array to achieve fast read access and to form support circuitry such as sense amplifiers, decoders, resistors, and voltage sources. shows examples. As shown in Figure 3D, vertical NOR string 380 represents a three-dimensional structure of non-volatile storage TFTs, each TFT having a local source line 375 and a local bit, according to one embodiment of the invention. Share line 374. Local bit line 374 and local source line 375 are separated from each other by body region 356, which provides channel regions for the TFTs in vertical NOR string 380. Storage elements are formed at intersection points between the channel region 356 and each horizontal word line 323 p , where p is the index of the word line in the word line stack; In the above example, p can take any value between 0 and 31. Word lines extend along the Y-direction. In this embodiment, the source line supply voltage (V _ss ) is connected to the source select transistor (SLS) 371 from the substrate 310 via the global source line (GSL ₁ ) 313, which is shown running on the top of a vertical column. It is provided to the vertical local source line 375 through . Note that the body region 356 providing the transistor channels of the active column may be connected to a substrate bias voltage (V _bb ) at terminal 331 . However, electrically connecting the P-doped channel 556 can also be accomplished from the top of the vertical NOR string (see discussion of Figure 5B below).

In Figure 3D, neighboring active columns (e.g., active columns of vertical NOR string 380) are grouped, and the local bit lines of the active columns of each group are associated with associated bit line segments (e.g., provided below the memory array). For example, it is connected to bit line segments (MSBL ₁ and MSBL ₂ ). The bit line segment MSBL ₁ provides a low-resistivity connector 373 , which may be implemented by, for example, a narrow strip of N+ doped polysilicon, silicide or a refractory metal. A group of neighboring vertical local bit lines (374-1, 374-2, ... 374-n) connected by a horizontal bit line segment (MSBL ₁ ) is provided long along the X-direction, It is provided perpendicular to the word lines (WL ₀ to WL ₃₁ ). Bit line segments (MSBL ₁ , MSBL ₂ , ...) are formed on the dielectric insulator 392 and have between 1 (i.e., unsegmented) and 16, 64, 256, 512, or more vertical local segments. It may be relatively short, such as containing bit lines. Each bit line segment is connected to a plurality of MSBL ₁ -type via segment-select transistors (e.g., segment-select transistors 586-1, ..., 586-n, which may be implemented with thin film transistors). It may be connected to longer horizontal conductors forming local bit line segments SGBL ₁ and SGBL ₂ containing bit line segments. A horizontal bit line segment (SGBL ₁ ) may be formed on the insulating layer 393 over the substrate 310, allowing logic elements, such as sense amplifiers, to be formed within the substrate directly underneath the localized bit line segment. do. Preferably, the area segment is long enough to allow sense amplifiers, decoders, resistors, voltage sources, and other circuitry formed within the substrate to physically fit underneath the local bit line segment.

In a double-density configuration, as shown in Figure 6A, each word line serves both active columns on both sides of the word line. In that configuration, two adjacent local bit lines on opposite sides of the word line are each associated with bit line segments (MSBL ₁ (L) and MSBL ₁ (R)) and their respective segment sense amplifiers and decoders. , they are close together and move parallel to each other. The spacing is also the spacing along the Y-direction between adjacent vertical active columns in the memory array. It may not be possible to provide a dedicated sense amplifier and other support circuits for each of the bit line segments laid out along the Y-direction. In this architecture, each sense amplifier can serve 1, 2, 4, 8, or more adjacent bit line segments through a segment-select decoder in the substrate. In the

Figure 3e shows a variation of the circuit architecture of the embodiment of Figure 3d, where groups of neighboring vertical local source lines 375-1, 375-2,..., like bit-line segments, have They are connected by source line segments (MSSL _1, MSSL ₂ , ...) running along the direction. This grouping of local source lines connected by source line segments includes source line select transistors (SLS ₁ , SLS ₂ ) required to provide a source voltage (V _ss ) to each of the vertical NOR strings associated with the source line segment. , ...) decreases the number. Moreover, as noted earlier, the connection of a group of vertical local source lines by a source line segment directly contributes to an increase in the cumulative parasitic capacitance (C). Vertical local source lines connected by horizontal source line segments are also closely related to vertical local bit lines connected by corresponding horizontal bit line segments. However, the number of vertical local bit-lines associated with a bit line segment need not be the same as the number of vertical local source lines associated with a source line segment. As a result, one bit line segment may be associated with multiple source line segments, for example. For example, bit line segment MSBL ₁ may be associated with 256 vertical local bit lines 374-1, 374-2, ..., which may be associated with 8 source line segments. and each of the source line segments may be associated with only 32 local source lines 375-1, 375-2, .... Each source line segment may have a voltage (V _ss ) individually delivered to it through a dedicated source-line select transistor (eg, source-line select transistor SLS ₁ ).

3F shows a variation of the circuit architecture of the embodiment of FIG. 3E, where the global source line (e.g., global source line 313) also has a source line-select transistor (e.g., source-select transistor SLS ₁ ). )) is also not provided. 3F, the vertical local source lines associated with each source line segment are pre-charged with a source voltage (V _ss ) via a pre-charge transistor (e.g., pre-charge transistor 370), and pre-charge The word line (WL _CHG ) of the charge transistor is turned on with a voltage pulse sufficient to transfer the voltage (V _bl ) supplied from circuitry within substrate 310 through the associated vertical local bit lines associated with the source line segment. . The number of vertical local bit lines associated with a source line segment is an optimization between maximizing the parasitic capacitance (C) of the source line segment to maintain the virtual ground voltage (V _ss ) during readout of the cell, and This is balanced by the need to keep the background leakage current associated with all of the "off" transistors in the vertical NOR strings associated with low enough so as not to interfere with reading the associated storage transistor in the source line segment. Within a bit line segment, any unselected source line sub-segment may be pre-charged to have its V _ss voltage equal to its associated bit line segment voltage (V _bl ) to eliminate its background leakage current. You can.

Figure 3G is a variation of the circuit architecture of the embodiment of Figure 3F. In Figure 3g, the connection between the memory array and the substrate connects the local bit line segments (SGBL ₁ , SGBL ₂ , ...) with their respective local bit line segments (MSBL ₁ , MSBL ₂ , ...). Merge each bit line segment via respective vias or conductors (e.g., buried contacts) to segment-select transistors 315-1, 315 in the substrate underneath the bit line segments. It is further simplified by connecting to -2, ...). In this configuration, rather than providing thin film segment-select transistors (e.g., segment-select transistors 586-1, ..., 586-n in Figure 3F) on a silicon substrate, segment-select transistors are This is provided by high-efficiency transistors within the single-crystal substrate 310. The configuration provides powerful access to sense amplifiers, decoders, resistors, voltage sources, and other circuitry associated with the bit line segment. By eliminating the global source line select transistors (SLS ₁ , SLS ₂ , ...) (made possible by the pre-charge path), and the segment-select thin film transistors (586-1, ..., 586-n) (or select transistors expensively fabricated from selective epitaxial silicon, as is commonly done in conventional 3D NAND arrays) positioning), the process integration flow is substantially simplified.

Figures 3h and 3i show another embodiment similar to that of Figure 3g. 3H and 3I, the voltage on the source line segment connectors MSSL ₁ and MSSL ₂ , and thus also on the vertical local source lines 375 (LSL) within each source line segment, is connected to the active column 381. (“filled column”), wherein the active column 381 is not used for memory storage and is supplied from any of the storage active columns of the memory array (e.g., active column 380 )) is structurally imitated. That is, charge column 381 is dedicated to charging local source lines within source line segments MSSL ₁ and MSSL ₂ . (In other embodiments, each packed column may supply only a single source line segment.) As shown in Figure 3H, packed column 381 is connected to neighboring bit line segments (SEG ₁₎ , for example. and SEG ₂ ) may be formed within the opening (BLO). Throughout a read operation (and optionally any program, program-disable _, or erase operation), charge column ₃₈₁ stores the required Transmits and maintains voltage. (Source line segments MSSL ₁ and MSSL ₂ are both served by packed column 381.) In this regard, packed column 381 is, for example, global source line (GSL ₁ ) in Figure 3E. 313 and eliminates the need for the associated source line segment-select transistor (SLS ₁ ). There is also a need for pre-charge transistors 370 in the memory stack - which requires extra word line plane (WL _CHG ) - for example, as shown for the embodiment of Figure 3G. Also remove.

3H and 3I, in the read operation of any storage transistor on any of the memory planes, the source voltage on each local source line of the source line segments MSSL ₁ and MSSL ₂ is connected to the charge column ( 381) is imposed to Vss (e.g., 0 volts) via connection (VSL) from vertical source line 375 (LSL). Voltage (Vss) is applied to the decoded select transistor (shown as 315 pass transistor 371, and a vertical local source line 375 (LSL). (Pass transistor 371 is activated by word line WL ₃₁ and remains conducting, or “on,” throughout the read operation.) During any program, program-inhibit, or erase operation, source line segments ( The source voltages imposed on MSSL ₁ and MSSL ₂ ) may also be provided similarly. The selection transistor 315X in the silicon substrate 310 may be a high voltage transistor capable of withstanding the high voltage imposed on the local bit line 374 (LBL) during an erase operation.

FIG _{. 3I shows} in great detail a top is maintained. In Figure 3I, the memory array has a layout similar to that shown in the embodiment of Figure 6B. As shown in Figure 3I, an array of filling columns is provided between the bit line segments SEG ₁ and SEG ₂ , with each row extending along the X-direction having two filling columns, and a predetermined number (e.g., 2048) of these rows are laid out along the Y-direction. The array of charge columns is provided between two discontinuities or openings (labeled “BLO” in Figure 3I) within the bit lines. In _one row of the active columns, between _the two dashed lines, a source line connector extending along the Connect to the local source lines in every other active column (along the dotted line). The same right charging column is connected to the local source lines of the active columns of the source line segment (MSSL ₂ ) in the bit line segment (SEG ₂ ). The source voltage is provided to the bit line connector from the silicon substrate to the local bit line of the right active column. The word lines labeled "WL ₃₁ " activate the pass transistor in the charge column, delivering the source voltage to the local source line labeled VSL, which is connected to the source line segments MSSL ₁ and MSSL ₂ . Provides source voltage to local source lines. (This circuit configuration is shown in the circuit of Figure 3H.) The left charge column in the row of charge columns between the dotted lines is connected in a similar manner to another pair of source line segments along the bottom dotted line.

In a three-dimensional vertical NOR string memory array with multiple word-line planes, the local word lines for all planes in the stack may be arranged in stepped steps (WL _STC ) at the edge of the array (e.g. see Figures 3i and 6g). One or more dedicated global word lines (e.g., labeled “GWL _chg ” in Figure 3I) are, for each memory plane, connected to neighboring bit line segments (e.g., bit line segments (SEG) in Figure 3H). ₁ and SEG ₂ )) may be required to activate a packed column (e.g., packed column 381) for each pair. As shown in the example of FIG. 3I (see inset), the global word lines labeled GWL _chg are all connected to the local word line (WL ₃₁ ) corresponding to the active column 381, and the bit line segments ( All other word lines within SEG ₁ and SEG ₂ are skipped. Conversely, each global word line (e.g., GWL) for the storage transistors of the memory array is hard-wired to the numerous local word lines associated with the bit line segments (SEG ₁ and SEG ₂ ), and the charge column Word lines at (381) are skipped. The global word lines (all labeled "GWL _chg " in the inset of FIG. 3I) of charge column 381 on different memory planes can be shorted together in peripheral circuitry (not shown), resulting in the word lines Activate any (or all) of the pass transistors of charge column 381 associated with WL ₀ -WL ₃₁ . In one embodiment, the pass transistors of all charge columns within a block of connected source line segments may be activated together when the chip is powered; Any source line segment or pair of source line segments within that block switches off its associated segment-select transistor (e.g., segment-select transistor 315X) thereby isolating its corresponding packed column from the silicon substrate. Can be deselected.

The embodiment of FIGS. 3H and 3I eliminates the need for a pre-charge sequence of the floating source, as performed in the embodiment of FIG. 3G. Eliminating the pre-charge sequence speeds up the read operation because the source voltage can be set to voltage V _ss and kept constant before the start of the read operation, eliminating the overhead required for floating source pre-charge pulses. Because it eliminates time. Moreover, since charge column 381 maintains the local source lines of source line segment MSSL ₁ at voltage V _ss throughout the read operation (i.e., not just the momentary pre-charge pulse), connection VSL The constant current provided through compensates for any source-drain leakage that, if excessive, could impair read detection of the addressed storage transistor.

In summary, charge column 381 serves as a vertical local connector to transfer voltages (V _ss or V _bl ) from the silicon substrate to local source lines in vertical NOR memory strings. The local bit line may also be charged directly from the bit line connector (MSBL ₁ ), which may be connected to voltage sources in the silicon substrate via segment-select decoders 315-1, but may also be charged directly from the vertical local charge column. Any voltages (V _ss or V _bl ) on the source line may be transferred to its associated local bit line through a pass transistor (e.g., pass transistor 371).

In a three-dimensional vertical NOR memory stack with 64 or 128 memory planes, the height of the stack, which is also the length of the packed column 381, can exceed 5 microns, which is the vertical local source line of the packed column 381. This is quite a long distance for either 375 (LSL) or local bit line 374 (LBL) (Figure 3h). Corresponding N+ doped polysilicon pillars 455 and 454 (see Figure 4A; or also shown as 655(N+) LSL-1 and 654(N+) LBL-1 in Figure 6E and sometimes referred to as pylons. The electrical resistance (R in ohms) can be exceeded, introducing RC delays that have a primarily detrimental effect on the read path. The resistance (R) of the pillar can be further reduced in size by providing a low-resistance metallic material within the core of the pillar. For example, in the detailed description below, Figure 4AA (Figure 4A-1) shows metal core 420 (M) and Figure 7D (Figure 7D-1) shows metal core 720 (M). do.

5B shows an example connection of body region 556 (providing P ^- channel material) by conductive pillars 591 (formed in dielectric layer 592 with P ⁺ polysilicon), according to one embodiment of the present invention. For example, a cross-sectional view in the ZY plane showing the connection to the conductor 590 provided above the active column 581 and running parallel to the word lines in one configuration. Conductor 590 may also be formed of over-doped polysilicon, or a silicide or metal conductor. In this structure, to facilitate block erase operations, a body bias voltage (V _bb ) 594 is provided from the substrate 505 to the conductor 590 through a via 593 in an opening in the dielectric isolation 509. It can be.

Figure 6E shows providing a body bias voltage via conductors 690-1 and 690-2 (“body bias conductors”). The body bias voltage is shared between body regions within adjacent rows of active columns, using the layout of the embodiment shown in Figure 6B. In this configuration, word line 592 (i.e., word line 623 p -L) runs in line with body bias conductor 690-1. The block size of the erase operation is limited to the active columns on the left and active columns on the right of each body bias conductor (e.g., conductor 690-1). Larger erase blocks can be constructed, for example, by tying together a group of body bias conductors to match the number of word lines addressing the bit line segment. A decoder within the substrate provides an appropriate body bias voltage (eg, erase voltage) to one or more selected erase blocks.

Returning to Figure 5B, after the active columns (e.g., active column 581) are formed, a dielectric layer 592 is formed over the active columns. Via holes are then anisotropically etched from the top of the dielectric layer 592 to the top of the body region 556. A P ⁺ doped polysilicon layer is then deposited over dielectric layer 592, filling the via holes, forming conductive pillars (e.g., conductive pillars 591). The layer of P ⁺ doped polysilicon is then patterned and etched to form conductors (e.g., conductor 590) that, through vias 593, provide a body bias voltage (V _bb ). Connect to voltage source 594. The body bias voltage (V _bb ) can be a positive high voltage supplied during erase or a low negative substrate bias voltage supplied during readout to increase the TFT threshold voltage or reduce its sub-threshold leakage. Figure 6E is a top view showing formed P+ doped polysilicon features 690-1 and 690-2.

In the embodiment shown in FIG. 5B , conductor 590 is provided over body region 556 . However, in other embodiments, conductor 590 may be provided underneath body region 556 to contact body region 556 from below. In fact, it may be advantageous to provide the body bias voltage from both above and below the body region 556. When providing the body bias voltage from below, a conductor similar to conductor 590 may be provided directly from the substrate through a via in the interlayer dielectric, similar to that shown in Figure 5A.

Operating modes of segmented local bit line and segmented local source line arrays

As described above in connection with embodiments of the invention, in a memory stack of word lines in 64 planes with bit line segments, storage on any plane (e.g., the 25th plane) associated with the selected bit line segment. When reading a transistor, all word lines on all planes associated with the selected bit line segment are maintained at their “off” threshold voltages, except the word line on the selected plane that is addressing the selected storage transistor. When the word line voltage comes on, the storage transistor in the cleared state (i.e., conducting or “on” state) is connected to its local source line (and, if applicable, pre-charged to the virtual ground potential (V _ss )). will discharge its bit line voltage (V _bl ) into its associated source line segment. The discharge rate of the bit line voltage (V _bl ) is sensed by a sense amplifier for the bit line segment. Other storage transistors on the selected plane (i.e., plane 25 in the example above) associated with other bit line segments along the Y-direction that share the same word line, or other storage transistors along the X-direction addressed by different word lines. Different storage transistors associated with bit line segments can be read simultaneously because each bit line segment has its own dedicated sense amplifier. For a read operation, the virtual source voltage is first pre-charged by setting the local bit line to 0V during the pre-charge operation. (Alternatively, the virtual source voltage can be as high as ~1V.) After pre-charging, the local bit line is charged to the sense amplifier voltage (e.g., ~0.1V to 0.5V above the source voltage), and the substrate is set to the voltage V _bb (e.g., ~0V to ~-2V), and the word line (WL) is increased to ~1V-3V beyond the erase threshold voltage.

For embodiments in which storage transistors are on both sides of each word line (e.g., the embodiments of Figures 6A and 6E), ensure that only one of the two storage transistors is conductive at any time during a read operation. Care must be taken to do so. As described above, this is accomplished by providing individual bit line segments that run parallel to each other, although each is served by its own sense amplifiers, decoders, voltage sources, and other support circuitry. As shown in Figure 6E, the bit line segments are MSBL ₁ (L) for the left-side storage transistors and MSBL ₁ (R) for the right-side storage transistors.

To program a storage transistor, all word lines on all planes except the selected plane (i.e., the 25th plane in the above example) are set to ground potential, and a word addressing the selected storage transistor (i.e., on the 25th plane) is set to ground potential. The line supplies voltage pulses, e.g., starting at ~8 volts and increasing in magnitude in increasing steps, until verified by a read operation that the desired programmed voltage has been reached. ) to increase to the appropriate programming voltage. During programming operations, the voltage on the bit line segment, like the associated source line segment, is maintained at ground potential.

To inhibit further programming while continuing to program storage transistors on the selected plane associated with other bit line segments sharing the same word line, the bit line segment and the source line segment are configured with a read verify cycle between successive programming pulses, By the end of the programming sequence, the programming-inhibit voltage is increased to approximately 1/3 to 1/2 the programming voltage. All programming and inhibiting voltages on local bit lines and local source lines within a bit line or source line segment are provided only through the bit line segment (via a pre-charge operation on the source line). Similar to a read operation, storage transistors associated with different bit line segments along the Y-direction (i.e., sharing the same word line as the selected storage transistors), and along the X-direction (i.e., with different word lines). Storage transistors associated with different bit line segments may be programmed or program-disabled simultaneously.

The erase operation raises the body bias voltage (V _bb ) to ~12 V for virgin storage transistors (i.e., storage transistors that have never been programmed or erased) and 20 V for high cycle-count storage transistors. This is achieved by holding all word lines to 0V for the storage transistors associated with the bit line segments, source line segments, or blocks to be erased while raising the above. Since the floating N+ vertical local source lines and N+ vertical local bit lines within a block follow positive voltages supplied to their p-body regions, all sense amplifiers associated with a bit line segment are connected to their bit lines or bit lines. Can be isolated from line segments.

Read, programming, program-inhibit, and erase are possible through different conditions familiar to those skilled in the art.

Low-latency split local and global word lines

The bit line segmentation of embodiments of the present invention serves to significantly reduce RC delays in conventional global bit lines of conventional 3D NAND and 3D NOR memory arrays. Another major cause for long read latencies are the long, highly capacitive local word line conductors perpendicular to the global bit lines, which typically run nearly all or half the width of the chip. Accordingly, 3D virtual NOR flash memory arrays of US 2017/0092371 Al, like conventional 3D NAND flash memory arrays, require at least one layer of local word line conductors for each memory plane. In a 64-plane NAND or NOR memory array, these word line conductors are structured in high cascading steps. Because local word lines supply high voltages during programming, their decoders require circuitry of high voltage transistors that can occupy significant silicon area for each of these cascade steps.

To reduce their associated overhead cost, word lines are typically made very long, which means high RC delays and poor read dash times (eg, in the range of a few microseconds). In conventional 3D NAND memory arrays, global bit lines also have long, slow rise or fall times, which inherently masks long word line latency. With the bit line segments of the present invention, bit-line response times can be very short (e.g., in the range of 100 nanoseconds), so long word line RC delays become a limiting factor for fast read access. According to one embodiment of the invention, one partial solution is to make 3D NOR memory chips long and short (i.e., short along the direction of the word lines and long along the direction of the bit line segments). Although this design does not reduce the silicon area for forming the word line decoders, the lengths and RC delays of the word lines are significantly reduced without significantly increasing the RC delays along the bit line segments.

According to another embodiment of the invention, word line delays can be further reduced by partitioning the memory array into more blocks with shorter word lines, each of which is formed by its repetitive cascade steps. do. Splitting the memory arrays by doubling the number of cascade stages and their word line decoders reduces RC delays by a factor of 4.

Another major cause for long read latency is the long RC delays of the global word lines (GWL) running in the X-direction over the length of the memory array over cascades along the sides of the memory array. FIG. 6F shows an example implementation of global word lines for connecting local word lines on one plane (i.e., in one cascade step) with respect to the bit line segmentation method of the present invention. In Figure 6F, only the local word lines in one For clarity, all other details (eg, P ^- channel material layers and charge confinement layers) have been omitted. As shown in FIG. 6F, the word lines (WL ₀ , WL ₁ , ...) of the memory array (e.g., the memory array corresponding to the embodiment shown in FIG. 6E) are along the Y-direction. Goes. Global word lines (GWL ₀ , GWL ₁ , ...) advance along the X-direction in cascading steps. Global word lines connect the word lines in each plane of the memory array to their respective decoders, voltage sources, and other support circuitry in substrate 605. For example, applying bit line segmentation to the architecture of Figures 3D, 3E, 3F, and 3G, each cascade in the cascade accommodates up to n global word lines matching the number n of local word lines within the bit line segment. do. In the embodiment of Figure 6F, for example, each bit line segment may include 128 bit lines, and each storage transistor in each stage is selected by the corresponding word line. Accordingly, there are 128 word lines in each stage of the bit line segment. Accordingly, each global word line is connected every 128th word line. For example, on each plane, to its substrate decoders and voltage sources in substrate 605, the global word line (GWL ₀ ) is connected to the word line via vias (VIA ₀ , VIA ₁₂₈ , ...). GWL ₁ is connected to word lines (WL-1, WL-129) through vias (VIA ₁ , VIA ₁₂₉ , ...). The structure allows 128 sets of storage transistors on each plane to be read simultaneously by activating a common global word line and their dedicated sense amplifier decoders. For example, the storage transistors associated with the word lines (WL _i , WL _i+128 , ...) (generally, WL _i+128k , k=0, 1, ... ) are connected to the global word line (GWL _i) . ), but all other global word lines in the same phase and other phases can be either at ground potential (i.e., all other storage transistors are off) or floated at ground potential. .

The embodiment shown in Figure 6f can be considered expensive in terms of silicon area: with 128 word lines within each bit line segment and 64 cascade steps, there are 128 global word lines per 64-cascade step. will be needed (or a total of 8192 global word lines). According to one embodiment of the invention, by having each global word line contact two or more local word lines within each bit-line segment, the number of global word lines required is doubled, quadrupled, or eight times. , can be reduced by 16 times or more. For example, the global word line (GSL ₁ ) includes word lines (WL ₁ , WL ₁₂₉ , ...) as well as word lines (WL ₃₃ , WL ₆₅ ...) (generally, WL _1+32k , k =0, 1, ... ), which reduces the number of global word lines required per step by a factor of 4 and reduces the total width of the staircase by a factor of 4. Of course, additional decoding circuitry or four times the number of dedicated sense amplifiers for each bit line segment are required on the silicon substrate. (Alternatively, a single sense amplifier in a bit line segment can be time-shared over four consecutive read or programming sequences.)

Because the global word lines are implemented on top of the memory array over cascading steps, the global word lines can be implemented using low-resistance copper interconnections. As known to those skilled in the art, the capacitance between adjacent global word lines within a stage can be reduced by replacing dielectric air gaps between them. Global word line RC delays are below cascading steps to access global word lines every 1/2, 1/4, or 1/8 of their length with breaks depending on the length of the global word lines. It can be further reduced by connecting global word line decoders and voltage sources within the silicon substrate.

When going from a 32-layer stack to a 64-layer stack, the number of word line cascades doubles from 32 to 64. Figure 6g shows one implementation of a vertical NOR string memory array that avoids this step doubling, according to one embodiment of the invention. 6G , the total number of planes within the memory array are presented as two or more sequentially formed stacks (e.g., STK ₁ and STK ₂ ), one on top of the other. A cross section is shown. Each stack is provided with its own set of cascading steps that are completed before the next stack is formed. In prior art three-dimensional NAND memory arrays, two stacks of memory cells are formed, each with 32 planes. The 64-plane cascade steps are then formed individually, followed by their associated global word lines. In contrast, Figure 6f shows the formation of stacks (STK ₁ and STK ₂ ) each having only 32 cascade size steps (steps A, steps B), each step (in the X-direction) It is a word line (running along the Y-direction) connected to one of the global word lines (GWL ₁ , GWL ₂ , ..., GWL ₃₂ ). The stacks (STK ₁ and STK ₂ ) are isolated from each other by an isolation layer 617, so that the total width providing 64 cascading steps is reduced by half. Under this scheme, the local bit line (e.g., BL 654) and local source line (e.g., SL 655) within the stack (STK ₂ ) are isolated to expose the top of the N+ doped vertical columns. By etching openings across layer 617 to connect their corresponding local bit lines and local source lines in stack STK ₁ , vertical active columns in the upper 32 planes are connected to the lower 32 planes on substrate 605 . to their corresponding vertical active columns within the columns. Likewise, the P- doped channel regions of both stacks (STK ₁ and STK ₂ ) (e.g., channel region 656 corresponding to channel region 556 in FIG. 5B) have P+ doped plugs 691. ), and the P+ doped plugs are formed in the isolation layer 617 before forming STK ₂ .

The silicon substrate area associated with the global word lines can be reduced by locating the global word line decoders and voltage sources below the cascade steps or on top of the memory arrays rather than locating them outside the arrays in the substrate. This positioning may be provided in relation to the memory arrays of FIGS. 3F and 3G. In such embodiments, the top surface of the memory array is free of any source line or bit line interconnections. Of course, these word line decoders and voltage sources are implemented using thin film transistors, which must be able to support the relatively high voltages (e.g., in the range of 12V - 20V) needed on the global word lines during programming. These thin film transistors are produced through shallow (Excimer) laser annealing to partially recrystallize the stacked polysilicon or through other seeding methods developed for solar panels or LED displays or other applications. ) can be achieved through technologies. The top surface of the memory array can also be used to advance global word line interconnections that are more widely spaced, wider or taller, reducing their RC delays without unduly increasing memory chip area.

3D vertical NOR arrays with segmented bit lines for semi-volatile NOR strings

Provisional Patent Application III, previously incorporated by reference and now published as US 2017/0092371A1 ("'237 Publication"), describes a method suitable as a replacement for DRAM within certain storage applications that do not require very high cycle endurance. Publish semi-volatile NOR strings (see paragraphs [0128] - [0131] in '237 Publication). To this end, the read access time of semi-volatile NOR strings approaches that of DRAM, which is less than 100 nanoseconds, approximately 500 times faster than conventional 3D NAND flash memory. In the three-dimensional vertical NOR strings published in this detailed description, the segmented bit-lines at the bottom of the array have their dedicated sense amplifiers, decoders, in the substrate below the bit line segment (e.g., Figure 3D , 3e, 3f, and 3g) closely mimics the horizontal strings of regular patent application III and can have nearly similar DRAM read latency. The process steps for fabricating the semi-volatile vertical NOR strings are similar to those described in paragraph [0129] of the '237 publication. Due to the relatively short retention time (e.g., in the range of 1 hour to several days) of semi-volatile storage transistors, semi-volatile storage transistors need to be read-refreshed frequently; In that context, having the ability to read or reprogram a large number of storage transistors simultaneously (i.e., read and reprogram storage transistors associated with many bit line segments in parallel) means that the chip density can be reduced to 1- This is important to minimize disruption to normal reads when approaching terabytes.

Regular Patent Application III also discloses the pairing of two storage transistors for fast-read cache memory in horizontal NOR strings (see paragraphs [0194] - [0196] in the '237 publication). Segmented bit lines with dedicated segment sense amplifiers in vertical NOR strings, such as those posted in this detailed description, are well suited for these fast read cache memories, where a dual transistor pair programs data on one transistor and It can be used to program reverse data (i.e. erased state) on adjacent transistors that share the same word line. For example, in Figure 6E, two transistors in two adjacent bit-line segments (MSBL ₁ (L), MSBL ₁ (R)) sharing two sides of the same word line (WL _31-1 ). Readout output signals from (T _L (683), T _R (682)) are provided to a differential sense amplifier within the silicon substrate. A differential sense amplifier is shared between two adjacent bit line segments along the Y-direction. This dual-segment structure provides very fast sensing, higher cycle endurance, and eliminates the need for programmable reference strings, although it reduces array bit efficiency by 50%, due to process variations, string leakage, and parameter changes. Alternatively, device sensitivities across the chip can be well tolerated. Other blocks use normal sensing of single transistors at double density, but due to the isolation between bit line segments along the X-direction (i.e. along the same direction as the global bit lines), paired transistors It is possible to have differential sensing for cache storage on the same chip blocks of bit line segments consisting of . This flexibility allows the same chip to act partly as cache memory and partly as storage memory. It also supports storing files that require many storage pages (for example, a single photo image that requires 4 MB of storage occupies 2,000 pages per 2 KB), so that their first one or more pages can be stored in fast cache memory. and allowing the remaining pages to be written to non-cache segments on the same chip, reading its first page very quickly and retrieving the image using pipelined reads for the other pages. The read waiting time for the entire 4MB becomes shorter.

The present invention (described with respect to FIGS. 6F and 6H), segmentation of a global bit line into local bit line segments with corresponding segment sense amplifiers and global word line segmentation for three-dimensional vertical NOR strings Although described, it can be similarly applied to conventional 3D vertical NAND memory strings.

Manufacture process

7A, 7B, 7C, and 7D are cross-sectional views of intermediate structures formed in a manufacturing process for a multi-gate NOR string array, according to an embodiment of the present invention.

FIG. 7A shows a cross-sectional view of the ZY plane of the semiconductor structure 700 after low resistivity layers 723 p are formed over the substrate 701, according to one embodiment of the invention. In the above example, p is an integer between 0 and 31, each representing 32 word lines. As shown in Figure 7A, semiconductor structure 700 includes low resistivity layers 723-0 through 723-31. For example, semiconductor substrate 701 represents a P-doped bulk silicon wafer, on and within which support circuits for memory structure 700 may be formed prior to forming the vertical NOR strings. . These support circuits may include both analog and digital logic circuits. Some examples of these support circuits include shift registers, latches, sense amplifiers, reference cells, power supply lines, bias and reference voltage generators, inverters, NAND, NOR, Exclusive-Or and other It may include logic gates, input/output drivers, address decoders including bit-line and word line decoders, other memory elements, sequencers, and state machines. As known to those skilled in the art, to provide these support circuits, conventional N-wells, P-wells, triple wells (not shown), N ⁺ diffusion regions (e.g., regions ( 707-0)) and P ⁺ diffusion regions (e.g., region 706), isolation regions, low and high voltage transistors, capacitors, resistors, diodes, and interconnections are provided.

After the support circuits have been formed in and on the semiconductor substrate 701, insulating layers 708 are provided, which may be, for example, laminated or grown thick silicon dioxide. In some embodiments, one or more metal interconnect layers may be formed including global source line 713-0, which may be provided as horizontal long narrow strips running along a predetermined direction. Global source line 713-0 is connected to circuit portion 707 in substrate 701 through etched openings 714. To facilitate explanation of this detailed description, the global source lines are assumed to run along the X-direction. Metal interconnect lines can be formed by applying photo-lithographical patterning and etching steps to one or more stacked metal layers. (Alternatively, these metal interconnect lines can be formed using a conventional damascene process, such as a conventional copper or tungsten damascene process.) A thick dielectric layer 709 is then deposited, followed by a conventional damascene process. This is followed by planarization using chemical mechanical polishing (CMP).

After that, conductor layers 723-0 to 723-31 are formed in succession, and each conductor layer is insulated from the layer below it and the layer above it by intervening insulating layers 726. It is insulated. In Figure 7a, 32 conductor layers are shown, but any number of such layers could be provided. In practice, the number of conductor layers that can be provided may depend on the processing technique, such as the possibility of a well-controlled anisotropic etching process allowing cutting across multiple conductor layers and the dielectric isolation layers 726 between them. there is. For example, the conductor layers 723 p may be formed by first depositing a 1-2 nm thick layer of titanium nitride (TiN), followed by a 10-50 nm thick layer of tungsten (W) or similar refractory metal, or nickel, cobalt, among others. , or may be formed by depositing a layer of silicide, such as those of tungsten, or salicide, followed by depositing a thin layer of etch-stop material, such as aluminum oxide (Al ₂ 0 ₃ ). Each conductor layer is etched within the block 700 after lamination, or is laminated as a block through a conventional damascene process. In the embodiment shown in FIG. 7A , each successive conductor layer 723 p extends in the Y-direction shorter than the edge of the immediately preceding metal layer by a distance 727 (i.e., recessed from the edge), At a later stage in the process all conductive layers may be contacted from the top of structure 700. However, to reduce the number of masking and etching steps required to form the staged conductor stack of FIG. 7A, each individual conductor plane is individually masked and etched to create exposed recessed surfaces 727. It is possible to create recessed surfaces 727 for multiple conductor layers simultaneously by using other processing techniques known to those skilled in the art that do not require After the conductive layer is deposited and etched, a corresponding dielectric isolation layer 726 is deposited. For example, dielectric isolation layers 726 may be silicon dioxide with a thickness of 15 to 50 nanometers. Conventional CMP prepares the surface of each dielectric layer for depositing the next conductive layer. The number of conductor layers in the stack of block 700 can be at least the number of memory TFTs in the vertical NOR string and non-memory TFTs, such as pre-charge TFTs (e.g., pre-charge TFT 575 in FIG. 5A). corresponds to the sum of any additional conductor layers that can be used as control gates of or as control gates of bit-line access selection TFTs (e.g., bit-line access selection TFT 511 in Figure 5A). The conductor layer deposition and etching steps and the dielectric layer deposition and CMP process are repeated until all conductor layers are provided.

Afterwards, the dielectric isolation layer 710 and the hard mask layer 715 are stacked. Hard mask 715 is patterned to allow etching conductor layers 723 p to form long strips in which word lines have not yet been formed. Word lines extend long along the Y-direction. An example of a masking pattern for word lines 623p -R, 623p -L is shown in FIG. 6, which includes extensions of adjacent word lines facing each other at separation 676 and the desired curvature. Includes features such as recessed portions of each word line to create fields 675. A deep trench is created by anisotropically etching the successive conductor layers 723 p and the dielectric insulating layers 726 between each of them until the dielectric layer 709 at the bottom of the conductor layers 723 p is reached. are created. Because a large number of conductive layers are etched, the photoresist mask itself may not be strong enough to maintain the desired word line pattern through numerous successive etches. To provide a strong mask, a hard mask layer 715 (e.g., carbon) is preferred, as known to those skilled in the art. The etch may be terminated at the dielectric material 709, or at landing pads 713 on the global source lines, or at the substrate 701. To protect the landing pads 713 from etching, it may be beneficial to provide an etch-stop barrier film (eg, aluminum oxide).

FIG. 7B is a cross-sectional view in the Z Etching through successive conductive layers 723 p and corresponding dielectric layers 726 is shown. In FIG. 7B , conductor layers 723 p are anisotropically etched to form conductor stacks 723 p -R and 723 p -L separated from each other by a deep trench 795 . The anisotropic etching is a high aspect-ratio etching. To achieve best results, as known to those skilled in the art, the etch chemistry should alternate between etching the conductive material and etching the dielectric since different layers of materials are etched. The anisotropy of the multi-step etch is important so that the resulting word lines at the bottom of the stack have conductor widths and trench spacings that are approximately the same as the corresponding conductor widths and trench spacings of the word lines at or near the top of the stack. This is because undercutting of any layer must be avoided. Naturally, the greater the number of conductor layers in a stack, the more difficult it is to maintain tight pattern tolerance over numerous successive etches. For example, to alleviate difficulties associated with etching 64 or 128 or more conductor layers, etching may be performed in sections of each of the 32 layers. The individually etched sections can then be stitched together, for example, as taught in the above-mentioned reference “Kim.”

Etching multiple conductive layers 723 p of conductive material (eg, tungsten or other refractory materials) is more difficult and time-consuming than etching the intervening insulating layers 726 . For that reason, an alternative process may be adopted that eliminates the need to etch the conductor layers 723 p multiple times. The process, well known to those skilled in the art, consists in first replacing sacrificial layers of easily etchable material in place of the conductor layers 723 p in Figure 7b. For example, the insulating layers 726 may be silicon dioxide, and the sacrificial layers (occupying the spaces shown at 723 p in FIG. 7B) may be silicon nitride or another fast etch dielectric material. Deep trenches then anisotropically etch alternating Oxide-Nitride-Oxide-Nitride (ONON) dielectric layers, creating tall stacks of these dielectrics. At a later stage of the manufacturing process flow (described below), the stacks are supported by active vertical strips of polysilicon, allowing the sacrificial layers to be etched, preferably via selective chemical or isotropic etching. The cavities thus created are then filled through conformal stacking of the conductive material, resulting in the conductor layers 723 p being separated by the intervening insulating layers 726.

After the structure of FIG. 7B is formed, charge-confinement layers 734 and polysilicon layers 730 are conformally deposited sequentially on the vertical sidewalls of the etched conductor word line stacks. A cross-sectional view in the Z-X plane of the resulting structure is shown in Figure 7c. As shown in FIG. 7C, charge-confinement layers 734 may be, for example, 5 to 15 nanometers thick and have a high dielectric constant (e.g., aluminum oxide, hafnium oxide, or silicon dioxide). It is formed by first stacking a blocking dielectric 732a made of a dielectric film (some combination of silicon nitride and silicon nitride). Charge-confinement material 732b is then deposited to a thickness of 4 to 10 nanometers. Charge-confinement material 732b can be, for example, silicon nitride, silicon-rich oxynitride, conductive nanodots contained in a dielectric film, or a thin conductive floating gate isolated from adjacent TFTs that share the same vertical active strip. You can take it in. Charge-confinement 732b may then be covered with a stacked conformal thin tunnel dielectric film ranging in thickness from 2 to 10 nanometers (e.g., a silicon dioxide layer, or a silicon oxide-silicon nitride-silicon oxide layer). -silicon nitride-silicon oxide; "ONO") triple layer). The storage device formed from charge-constrained layers 734 may be any one of SONOS, TANOS, nanodot storage, isolated floating gates, or any suitable charge-constrained sandwich structures known to those skilled in the art. The combined thickness of charge-confinement layers 734 is typically 15 to 25 nanometers.

After deposition of the charge-confined layer 734, a masking step was used and the charge-confined layers 734 and the dielectric layer 709 were anisotropically etched from the bottom of the trench 795 and then anisotropically etched for the source supply voltage (V _ss ). P+ region 706 for contact at the lower global source line landing pad 713, at the global bit line voltage (V _bl ) (not shown), or to the back bias supply voltage (V _bb ) (see FIG. 7C ). By stopping at , contact openings are created in the bottom of trench 795. In some embodiments, prior to the etching step, a very-thin ( This is preceded by laminating a polysilicon film (e.g., 2 to 5 nanometers thick). In one embodiment, each global source line is connected only to alternating ones within a row of vertical NOR string pairs. For example, in Figure 5A, for odd address word lines only, N+ doped local source lines (e.g., local source line 555 in Figure 5A) to connect to global source line 513-1. Electrical contacts (eg, contact opening 557) are etched. Likewise, for even address word lines only, electrical contacts are etched to connect the N+ doped local source lines in a row of vertical NOR string pairs to the global source line 513-2 (not shown in Figure 5A). . In embodiments that use virtual V _ss through parasitic capacitor C (i.e., capacitors 560 in FIG. 5A), the step of etching charge-confinement layer 734 from the bottom of trench 795 is skipped. You can.

Afterwards, a polysilicon thin film 730 is deposited to a thickness ranging from 5 to 10 nanometers. In Figure 7C, polysilicon thin film 730 is shown on opposite sidewalls of trench 795, labeled 730R and 730L, respectively. The polysilicon thin film 730 is either undoped or p-doped, preferably with boron, at a doping concentration typically ranging from 1×10 ¹⁶ per ^{cm 3 to} 1×10 ¹⁷ per cm 3 , which allows the TFT to operate at an increased basic threshold. Allows a voltage to form within it. Trench 795 is wide enough to accommodate charge-confinement layers 734 and polysilicon thin film 730 on its opposite sidewalls. After deposition of polysilicon 730, the sacrificial layers in the above-described stack are etched away, so that the formed cavities are filled with conformally stacked conductor layers 723 p (FIG. 7C).

As shown in Figure 7B, trench 795 extends along the Y-direction. After forming isolated word line stacks 723 p -L and 723 p -R, in one example, semiconductor structure 700 can have more than 16,000 side-by-side word line stacks, each word line stack having a respective It serves as control gates for more than 8,000 active columns or 16,000 TFTs (8,000 TFTs on each side of the stack) formed along the length of the stack. With 64 word lines in each stack, eventually 16 billion TFTs can be formed in each of these multi-gate vertical NOR string arrays. If each TFT stores two data bits, this multi-gate vertical NOR string array would store 32 gigabytes of data. Approximately 32 of these multi-gate vertical NOR string arrays (and spare arrays) can be formed on a single semiconductor substrate, providing a 1-terabit integrated circuit chip.

FIG. 7D is a cross-sectional view in the XY plane of the top surface of the FIG. 7C structure in one embodiment. Between word lines 723 p -L and 723 p -R are two sidewalls 730L and 730R of vertically stacked P-doped polysilicon structure (i.e., active column). The deep void 740 between sidewalls 730L and 730R may be filled with a fast-etch insulating dielectric material (eg, silicon dioxide or liquid glass or carbon doped silicon oxide). The top surface can then be planarized using conventional CMP. A photolithography step then exposes the openings 776 and 777, followed by a high aspect ratio selective etch to etch the fast-etch dielectric material in the exposed areas 776 and 777 to the bottom of the trench 795. The etching step may require a hard mask to avoid excessive pattern degradation during etching. The excavated voids are then filled with N+ doped polysilicon in-situ. N+ dopants diffuse into the very thin lightly-doped active polysilicon pillars 730L and 730R within the exposed voids, thereby making the active polysilicon pillars N+ doped. Alternatively, prior to filling the voids with in-situ N+ doped polysilicon, the lightly-doped polysilicon within the voids can be etched through a simple isotropic plasma etch or selective wet etch. CMP or top surface etch then removes the N+ polysilicon from the top surface, leaving tall N+ polysilicon pylons in areas 754(N+) and 755(N+). The N+ pilons form a shared vertical local source line and a shared vertical local bit line for the TFTs in the resulting vertical NOR strings.

FIG. 7D (FIG. 7D-1) only partially fills the exposed voids 776 of vertical pilons 754 and 755, e.g., with N+ doped polysilicon 754(N+) and 755(N+). ) of (each having a thickness of 5 to 15 nanometers (insufficient to fill the voids)) first, then filling the remaining voids 720 (M) in the core of the source/drain pilons. By depositing (e.g., using Atomic Layer Deposition (ALD)) a metallic conductive material (e.g., titanium nitride, tungsten nitride, or tungsten) to form a tall vertical source. /shows a substantial increase in the electrical conductivity of the drain pilons. See also FIG. 4AA (FIG. 4A-1), which shows in the YZ plane the metal conductor 420 (M) occupying the core of the pilons in intimate contact with the very-thin N+ poly 454 (N+). Due to the relatively fairly high conductivity of the metallic material in the core, the N-type doping concentration of very-thin N+ doped polysilicon can be reduced by one or two orders of magnitude, thereby reducing the transfer of the N-type dopant to the P-type dopant in the channel. Unwanted heat diffusion is reduced. An N+/metal conductor structure may be applied to one or both of the source and drain pilons. In another embodiment, a thin P-doped polysilicon within region 757 -- outside of channel region 756 -- is first added to the P-doped polysilicon within channel region 756, which may be greater than 2×10 ¹⁸ per cm ³ . Compared to , it may be more P+ over-doped (eg, more than 10 ¹⁹ per cm ³ ). When the local source line is raised to a high positive voltage during a erase operation, the erase efficiency can be increased by adding a P+ poly in the source pilon contacting the P- poly in the channel.

Next, a dielectric isolation layer is deposited and patterned using photolithographic masking and etching steps. The etching step includes contacts to connect the vertical local bit lines to the horizontal global bit lines (e.g., contacts 657-1 for strings of odd addresses and even contacts 657-1, as shown in FIG. 6). Open the contacts 657-2) for the strings of addresses. A low-resistivity metal layer (eg, tungsten) is deposited. The deposited metal is then patterned using photolithography and etching steps to form global bit-lines (e.g., the global word line 614-1 for strings of odd addresses, as shown in Figure 6). or GBL ₁ ) and a global bit line 614-2 or GBL ₂ ) for strings of even addresses. Alternatively, global bit lines can be formed using a conventional copper damascene process. As known to those skilled in the art, all metal layers 723 p of all global bit lines and word line stacks (FIG. 7A) are connected to the word line and bit-line decoding and sensing circuits in the substrate by etched vias. . Switch and sense circuits, decoders, and reference voltage sources can be provided to the global bit lines and global word lines individually or shared by several bit lines and word lines.

In some embodiments, as known to those skilled in the art, the bit line access select transistors (511 in Figure 5A) and their associated control gate word lines (e.g., word lines 585 in Figure 5A) are isolated Formed as vertical N+P-N+ transistors, vertical rows of odd and even addresses alternate across odd and even global bit lines (e.g., bit lines 614-1 and 614-2 in FIG. 6A). It is selectively connected to NOR strings (e.g., local bit lines 657-1 and 657-2, respectively, in FIG. 6A).

reading operation

In all embodiments of the invention, the vertical NOR string of TFTs is connected in parallel, so that a shared local source line and a shared local bit line (e.g., local bit line 455 and local source line shown in Figure 4C) are connected in parallel. To suppress leakage current during read operations between lines 454, it is desirable for all TFTs in the active column (including the active column formed in a vertical NOR string pair) to be in augmented mode - i.e. Each TFT must have a positive gate-to-source threshold voltage --. Enhancement mode TFTs are achieved by doping the channel regions (e.g., P-channel region 756 in FIG. 7C) with boron, typically at a concentration of 1×10 ¹⁶ to 1×10 ¹⁷ per cm ³ , resulting in a voltage of about 1 V. Aim for the default TFT threshold voltage of Using these TFTs, all deselected word lines within the vertical NOR string pair of the active column can be maintained at 0V. Alternatively, a read operation raises the voltage on the shared local N+ source line (e.g., local source line 455 in FIG. 4C) to about 1.5V and the shared local N+ drain line (e.g., local source line 455 in FIG. The voltage on the bit line 454 is raised to approximately 2V and all deselected local word lines are held at 0V. This configuration is equivalent to setting the word line to -1.5V relative to the source, so that leakage current by the TFTs at a slightly reduced threshold voltage, which would occur if the TFTs were slightly over-cleared, for example, is suppressed.

After clearing the TFTs in the vertical NOR string, a soft programming operation is required to transition any TFTs in the vertical NOR string that were over-cleared (i.e., now have a derating mode threshold voltage) back to the increasing mode threshold voltage. It can be. In Figure 5A, operative connection 556 is shown with the P-channel connected to a back bias voltage 506 (V _bb ) (also shown as body connection 456 in Figure 4C). A negative voltage can be used for V _bb to adjust the threshold voltage of the TFTs in each active column to reduce subthreshold leakage current between the shared N+ source and the shared N+ drain/local bit line. In some embodiments, a positive V _bb voltage may be used during an erase operation to tunnel-erase the TFTs whose control gates are held at 0V.

To read data stored in the TFTs of a vertical NOR string pair, all TFTs on the two vertical NOR strings of the vertical NOR string pair are initially powered by maintaining all word lines in the multi-gate NOR string array at 0V. It is in the “off” state. An addressed vertical NOR string can share sensing circuitry among several vertical NOR strings along a common word line through the use of decoding circuitry. Alternatively, each vertical NOR string can be connected directly to a dedicated sensing circuit via a global bit-line (e.g., GBL ₁ in Figure 4C). In the latter case, one or more vertical NOR strings sharing the same word line plane can be sensed in parallel. Each addressed vertical NOR string is set to V _ss ~ 0V via its hard-wired global source line (e.g., GSL ₁ in Figure 4C) as schematically shown in Figure 8A, or It has its local source line set to a virtual V _ss ~ 0V via a pre-charge transistor (e.g., pre-charge transistor 470 in Figure 4C or transistor 317 in Figure 3C), wherein the pre-charge The transistor has a parasitic capacitance (C) of the local source line 455 or 355 (e.g., capacitor 460 or capacitor 360) floating V _bl ~0V during pre-charge, as schematically shown in FIG. 8B. ) is transmitted instantaneously.

Immediately after turning off pre-charge transistor 470, the local bit line (e.g., local bit line 454 in Figure 4C) is connected to the bit line access select transistor (e.g., bit line access select transistor in Figure 4C). V _bl is set to 2V through (411) or access selection transistor 511 in FIG. 5A. V _bl ~ 2V is also the voltage to the sense amplifiers for the addressed vertical NOR strings. At this time, the addressed word line rises from 0 V in small incremental voltage steps, typically to about 6 V, with all deselected word lines to both the odd and even address TFTs of a vertical NOR string pair reaching 0 V. remains in In the hard-wired V _ss embodiment of Figure 8A, the addressed TFT was programmed, in one example, with a threshold voltage of 2.5 V, so the voltage (V _bl ) on the local bit line (LBL) is such that its WLs are 2.5 V. As soon as V is exceeded, it begins to discharge towards 0V of the local source line (V _ss ) through the selected TFT, resulting in a voltage drop (shown by the dashed arrow in Figure 8a) that is detected at the sense amplifier serving the selected global bit line. provided. In the virtual V _ss embodiment of FIG. 8B , the pre-charge transistor word line (WL _CHG ) is turned on to pre-charge the floating local source line (LSL) to 0V when the read sequence begins. The selected word lines (WL) then go through its increasing voltage steps, and as soon as it exceeds the programmed 2.5V, the selected TFT momentarily drops the voltage on its local bit line from its V _bl ~ 2V. I order it. The voltage drop (shown as a dashed arrow in Figure 8B) is detected by a sense amplifier on the global bit line connected to the selected local bit line. As known to those skilled in the art, other alternative ways to properly read the programmed threshold voltage of a selected TFT exist. Embodiments that rely on parasitic capacitance (C) to temporarily maintain the virtual voltage (V _ss ) are presented in the selected sense amplifier as the higher the vertical stack, the larger the capacitance (C) and, therefore, the longer the retention time. The read signal becomes larger. To further increase C, in one embodiment, it is possible to add one or more dummy conductors to the vertical string, the main purpose of which is to increase the capacitance C.

For MLC implementations (i.e., “multi-level cell” implementations in which each TFT stores two or more bits), the addressed TFT may be supplied at several voltages (e.g., 1 V (cleared state), 2.5 V). , 4V, or 5.5V). Addressed word lines (WL) are raised in increasing voltage steps until conduction within the TFT is detected at the sense amplifier. Alternatively, a single word line voltage can be supplied (e.g., ~6 volts) and the discharge rate of the local bit line (LBL) (V _bl ) can be programmed to represent the stored multi-bit voltage states. The rate of discharge can be compared from possible reference voltages. This approach can be extended to sequences of states and provides analog storage efficiently. Programmable reference voltages can be stored in dedicated reference vertical NOR strings located within a multi-gate vertical NOR string array so that characteristics during readout, programming, and background leakage are closely tracked. In a vertical NOR string pair, only the TFTs on one of the two vertical NOT strings can be read in each read cycle; The TFTs on the other vertical NOR strings are in the "off" state (i.e., all word lines are at 0V). During a read cycle, only one of the TFTs in the vertical NOR string is exposed to read voltages, so read disturb conditions are essentially eliminated.

In one example of an embodiment of the invention, 64 TFTs and one or more pre-charged TFTs may be provided on each vertical NOR string of the vertical NOR string pair. Each word line at its intersection with the local vertical N+ source line pillar forms a capacitor (e.g., see capacitor 660 in FIG. 6A). A typical value for this capacitor may be, for example, 1×10 ¹⁸ Farad. Including all capacitors in both vertical NOR strings of a pair of vertical NOR strings, the total distributed capacitance (C) amounts to approximately a total of ¹ -sufficient to preserve the charging source voltage (V _ss ) and is typically completed within 1 microsecond immediately after the pre-charge operation. Charging time through bit-line access select transistors 411 and pre-charge TFT 470 is on the order of nanoseconds, so charging time does not add appreciably to read latency. A read from a TFT in a vertical NOR string is fast, because unlike a read operation on a NAND string where many TFTs in series need to be conductive, a read operation takes place on only one of the TFTs in a vertical NOR string. This is because it involves evangelism.

There are two main factors that contribute to the read latency of the vertical NOR strings of the present invention: (a) the resistance (R _bl ) of the global bit line (e.g., GBL 614-1 in Figure 6A) and RC time delay associated with the capacitance (C _bl ), and (b) the response of the sense amplifier to the voltage drop (V _bl ) on the local bit line (e.g., LBL-1) when the addressed TFT begins to conduct. hour. For example, the RC time delay associated with a global bit line serving 16,000 vertical NOR strings is on the order of tens of nanoseconds. The read latency for reading a TFT of a prior art vertical NAND string (e.g., the NAND string in Figure 1B) depends on the current across 32 or more series-connected TFTs and the select transistor discharge capacity of the global bit line ( C _bl ) is determined by. In contrast, in the vertical NOR string of the present invention, the read current discharge (C _bl ) flows through only one addressed transistor in series with the bit line access select transistor 411 (e.g., transistor 416L in Figure 4A). ), resulting in much faster discharge of the local bit line voltage (V _bl ). As a result, waiting times are much shorter.

In FIG. 4C , once one TFT (e.g., TFT 416L in vertical NOT string 451b) is read, once in vertical NOR string 451a or 451b of vertical NOR string pair 491. All other TFTs remain in their “off” states and their word lines remain at 0V. Although TFT 416R in vertical NOR string 452a of vertical NOR string pair 492 shares word line WL ₃₁ with TFT 416L, TFT 416R can be read simultaneously with TFT 416L. This is because the vertical NOR string 452a is served by the global bit line 414-2, and the vertical NOR string 451b is served by the global bit line 414-1. (FIGS. 6A and 6B illustrate how global bit lines 614-1 and 614-2 serve adjacent vertical NOR string pairs.)

In one embodiment, the word line stack includes 32 or more word lines presented in 32 planes. In one multi-gate vertical NOR string array, each plane may include 8000 word lines controlling 16,000 TFTs, with each bit line connected to a dedicated sense amplifier. Each can be read in parallel via 16,000 global bit lines. Alternatively, if several global bit lines share a sense amplifier with a decode circuit, 16,000 TFTs are read over several consecutive read cycles. Reading large numbers of discharging TFTs in parallel can cause voltage bounce within the chip's ground supply (V _ss ), resulting in read errors. However, embodiments that use a pre-charge parasitic capacitor C in the local source line (i.e., providing a virtual source voltage V _ss to the vertical NOR string) have the particular advantage that this ground voltage bounce is eliminated. This is because the virtual source voltages in the vertical NOR strings are independent and not connected to the chip's ground supply.

Programming (recording) and programming-inhibit operations

Programming of an addressed TFT occurs when a high programming voltage is supplied between a selected word line (e.g., word line 423p -R) and an active channel region (e.g., active channel region 456 in FIG. 4A). Tunneling of electrons from the channel region of the TFT (e.g., channel region 430L shown in FIG. 4B) to the charge-confined layer (e.g., charge-confined layer 434) - direct tunneling. Or it can be achieved by Fowler-Nordheim tunneling. Because tunneling is so efficient, very little current is needed to program a TFT, and parallel programming of tens of thousands of TFTs can be achieved with low power consumption. Programming by tunneling may require, for example, 20V, 100-microsecond pulses. Preferably, programming is implemented through a series of shorter duration cascading voltage pulses starting at approximately 14V and rising to approximately 20V. Cascade voltage pulsing reduces electrical stress across the TFT and avoids overshooting the intended programmed threshold voltage.

After programming each high-voltage pulse, the addressed transistor is read to determine whether it has reached its target threshold voltage. If the target threshold voltage has not been reached, the next programming pulse supplied to the selected word line is typically increased by a few hundred millivolts. This program-verify sequence produces one addressed word with 0V supplied to the local bit line (e.g., local bit line 454 in FIG. 4A) of the active column (e.g., column 430L in FIG. 4B). It is applied repeatedly to the line (i.e. control gate). At these programming high word line voltages, the channel region of TFT 416L is inverted and held at 0V, allowing electrons to tunnel into the charge storage layer of TFT 416L. If read detection indicates that the addressed TFT has reached its target threshold voltage, the addressed TFT should be inhibited from further programming, and other TFTs sharing the same word line should continue to be programmed up to their higher target threshold voltages. can do. For example, when programming TFT 416L in vertical NOR string 451b, programming all other TFTs in vertical NOR strings 451b and 451a should be inhibited by holding all their word lines at 0V. do.

A half-select voltage (i.e., approximately 10V) is applied to local bit line 454 to inhibit further programming of TFT 416L once TFT 416L reaches its target threshold voltage. With 10 V in the channel region and 20 V at the control gate, only a net 10 V is supplied across the charge-confinement layer, so the Fowler-Nordheim tunneling current is insignificant and the TFT ( No further programming of significance is performed on 416L). By raising the local bit line 454 to 10V while continuing to increase the programming voltage pulses on the word line (WL ₃₁ ), all TFTs in the vertical NOR strings sharing the same selected word line are correctly aligned with their higher target threshold voltages. It is programmed. The “program-read-don’t-program” sequence allows tens of thousands of TFTs to be placed in parallel, at various target threshold voltage states, within multi-level cell storage.

It is essential for programming correctly. Without this programming prohibition against over-programming of individual TFTs could result in overstepping or merging of the threshold voltage of the next higher target threshold voltage state. Although TFT 416R and TFT 416L share the same word line, they belong to different vertical NOR string pairs 452 and 451. It is possible to program both TFT 416R and TFT 416L from the same programming pulsed voltage sequence because their respective bit line voltages are supplied through GBL ₁ and GBL ₂ and are individually controlled. For example, at one time TFT 416R may be inhibited from being further programmed, while TFT 416L may continue to be programmed. Vertical NOR strings 451a and 451b of vertical NOR string pair 491 can each be controlled by individual word lines 423 p -L and 423 p -R, and the voltage on each local bit line Since it can be set independently from all other vertical NOR string pairs, these programming and non-programming voltage conditions can be satisfied. During programming, any deselected word line within the addressed or unaddressed word line stacks can be brought to 0V, half-selected 10 Volts, or floated. In embodiments where the global source line (e.g., GSL ₁ in Figure 4C) is accessed through a source access select transistor (not shown in Figure 4C), the access select transistor is turned off during programming, resulting in programming and inhibiting programming. While the voltage on local source line 455 follows the voltage on local bit line 454. The same holds true for the embodiment in which the voltage on the local source line is provided by its parasitic capacitance (C), represented by capacitor 460 in Figure 4C. In the embodiment of Figure 4C, with a global source line but no source access select transistor, the voltage supplied to the global source line 413-1 of the addressed string during programming and program-inhibit is greater than or equal to the global bit line 414 of the addressed string. It is desirable to track the voltage of -1).

A read cycle follows each incrementally higher voltage programming pulse to determine whether TFTs 416L and 416R have reached their respective target threshold voltages. Once the target threshold voltage has been reached, the drain, source, and body voltages are raised to 10V (alternatively, they float close to 10V), inhibiting further programming, but the word lines (WL ₃₁ ) are raised to their target. Continue programming other addressed TFTs on the same plane that have not yet reached their threshold voltages. The sequence ends when it has been read-verified that all addressed TFTs have been correctly programmed. For MLC, programming one of multiple threshold voltage states means programming each addressed global bit line to several predetermined voltages (e.g., representing four distinct states in which 2-bit data is stored). It can be set to one of 0V, 1.5V, 3.0V, or 4.5V and then accelerated by supplying stepped programming pulses (up to about 20V) to the word line (WL ₃₁ ). In this way, the addressed TFT accepts a predetermined one of the effective tunneling voltages (i.e., 20, 18.5, 17, and 15.5 volts, respectively), and consequently one of the predetermined threshold voltages is programmed to the TFT within a single programming sequence. do. Fine programming pulses can then be provided to individual TFT levels.

Accelerated full-plane parallel programming

Due to the parasitic capacitance (C) inherent in all local source lines in a multi-gate vertical NOR string array, all local source lines in a multi-gate vertical NOR string array are For example, the global bit line (GBL ₁ ) and bit line access string select transistor 411 and pre-charge transistor 470 are placed at 0V momentarily (for programming) on all vertical NOR strings, or Can be set to 10V (against prohibition). This procedure can be performed by addressing the word line planes plane-by-plane. For each addressed word line plane, a programming pulsing sequence is applied to many or all word lines on the addressed word line plane, and all word lines on the other word line planes are held at 0V, thereby reducing the number of word lines on the addressed plane. TFTs are programmed in parallel, followed by individual read-verify and, if necessary, the local source lines of the correctly programmed TFTs are reset to the program-inhibit voltage. This approach is quite beneficial because, although the programming time is relatively long (i.e., about 100 microseconds), pre-charging all local source line capacitors and read-verifying all TFTs that share the addressed word line plane takes about 1,000 microseconds. This is because it is more than twice as fast. Therefore, it is advantageous to parallel program as many TFTs as possible within each word line plane. This accelerated programming feature provides a significant advantage even in MLC programming, which is significantly slower than single-bit programming.

delete action

For some charge-constrained materials, the erasure operation is performed by reverse-tunneling of the confined charge, which can be rather slow, sometimes requiring tens of milliseconds of pulsing above 20 V. Therefore, delete operations can be implemented at the level of a vertical NOR string array (“block delete”) and are often performed in the background. A typical vertical NOR string array may have 64 word line planes, each word line plane controlling 16,384 x 16,384 TFTs, for a total of approximately 17 billion TFTs. Therefore, with 2 bits of data stored in each TFT, a 1-terabit chip can contain approximately 30 such vertical NOR string arrays. In some embodiments, block erase applies approximately 20V to the P-channel (e.g., body contact 456 in FIG. 4C and contact 556 in FIG. 5A) shared by all TFTs in the vertical NOR string. This can be done by supplying and maintaining all word lines in the block at 0V. The duration of the erase pulse should be such that most of the TFTs in the block are erased with a slightly increasing mode threshold voltage (i.e. between 0 and 1 volt). Some TFTs will overshoot and fall into derating mode (i.e., slightly negative threshold voltage). As part of the erase command, after the end of the erase pulses, soft programming may be required to return the over-erase TFTs to a slightly increased mode threshold voltage. Vertical NOR strings, which may contain one or more decrement mode TFTs that cannot be programmed in augmentation mode, may have to be retired to be replaced with spare strings.

Alternatively, rather than providing erase pulses to the body (i.e., P-layer), for the duration of the erase pulse, local source lines and local bit lines on all vertical NOR string pairs in the vertical NOR string array. (e.g., local source line 455 and local bit line 454 in Figure 4C) rises to approximately 20V, maintaining all word lines on all word line planes at 0V. This method requires that the global source line and global bit line select decoders use high voltage transistors that can withstand 20V at their junctions. Alternatively, all TFTs that share the addressed word line plane could be cleared together, supplying -20V pulses to all word lines on the addressed plane, while keeping word lines on all other planes at 0V. All other voltages within the vertical NOR string pairs are maintained at 0V. This will delete only the X-Y slice of all TFTs touched by one addressed plane of word lines.

Semi-non-volatile NOR TFT strings

Some charge-confinement materials suitable for use in vertical NOR strings (e.g., oxygen-nitrogen-oxygen, or "ONO") have long data retention times, typically on the order of several years, but are relatively low durability. (i.e. performance degrades after a few write-erase cycles, typically less than 10,000 cycles). However, in some embodiments, charges store degradation for much reduced retention times but with much higher durability (e.g., retention times on the order of minutes or hours, endurance on the order of tens of millions of write-erase cycles). -Confining materials may be selected. For example, in the embodiment of Figure 7C, tunnel dielectric layer 732c, typically a 6-8 nanometer layer of SiO2, may be thinned to a thickness of about 2 nanometers or may be layered with another dielectric material of similar thickness (e.g. SiN) can be replaced. Much thinner dielectric layers can enable the use of suitable voltages to introduce electrons into the charge-confinement layer by direct tunneling (as distinct from Fowler-Nordheim tunneling, which requires higher voltages), where the charges are You will be detained for anywhere from minutes to hours or even days. Charge-confinement layer 732b may be silicon nitride, conductive nanodots dispersed in a thin dielectric film, or a combination of other charge-confinement films including isolated thin floating gates. The blocking layer 732a may be silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, a high-k dielectric, or any combination thereof. The blocking layer 732a blocks electrons in the charge-confined layer 732b from escaping to the control gate word line. The trapped electrons will eventually leak back into the active region 730R, either as a result of destruction of the very-thin tunnel dielectric layer or by reverse direct tunneling. However, the loss of these bound electrons is relatively slow. Other combinations of charge storage materials can also be used, resulting in highly durable but low retention “semi-volatile” storage TFTs that record periodically to replenish lost charge. or require read refresh operations. Because the vertical NOR strings of the present invention have relatively fast read access (i.e., low latency), they can be used in several applications that currently require the use of dynamic random access memories (DRAMs). The vertical NOR strings of the present invention have significant advantages over DRAMs: since DRAMs cannot be built in three-dimensional stacks, the vertical NOR strings of the present invention have a much lower cost-per-bit, and the DRAMs Compared to needing to refresh every few milliseconds, the vertical NOR strings of the present invention have much lower power losses since refresh cycles need to be performed on the order of minutes or hours. The three-dimensional semi-volatile storage TFTs of the present invention select an appropriate material as described above for the charge-confinement material, appropriately adjust the programming/reading/program-disable/erase conditions, and include periodic data refreshes. It is achieved by doing.

NROM/Mirror Bit NOR TFT Strings

In another embodiment of the invention, vertical NOT strings can be programmed using a channel hot-electron injection approach, similar to that used in two-dimensional NROM/mirror bit transistors known to those skilled in the art. Using the embodiment of FIG. 4A as an example, programming conditions for channel hot-electron injection may be as follows: 8 V on control gate 423 p , 0 V on local source line 455, local drain line 454 ) 5V on. The charge representing one bit is stored in a charge storage layer at one end of the channel region 456 next to the junction with the local bit line 454. By reversing the polarity of local source line 455 and local bit line 454, the charge representing the second bit is programmed such that the charge at the opposite end of the channel region 456 next to its junction with local source line 455 It is stored in the storage layer. As known to those skilled in the art, reading both bits requires reading them in reverse order of programming. Channel thermo-electronic programming is much less efficient than programming by direct tunneling or Fowler-Nordheim tunneling, and therefore does not participate in the massively parallel programming made possible by tunneling. However, each TFT has twice the bit density, making it attractive for applications such as active memory. Erase for the NROM TFT embodiment can be accomplished using the conventional NROM erase mechanism of band-to-band tunneling-introducing heat-hole injection to neutralize the charge of the bound electrons: supplying -5V on the word line; 0V is supplied to the local source line 455, and 5V is supplied to the local bit line 454. Alternatively, the NROM TFT can be erased by supplying a high positive substrate voltage (V _bb ) to the body region 456 with the word line at 0V. Due to the high programming currents involved in channel thermal electron injection programming, all embodiments of vertical NROM TFT strings, as in the embodiments of Figures 3A and 6C, must use hard-wired local source lines and local bit lines.

The above detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Numerous variations and modifications are possible within the scope of the invention. The invention is specified in the appended patent claims.

101: substrate layer
454: Local bit line
455: Local source line
456: Body area
423 p : control gate

Claims (33)

A thin film NOR memory string formed on a planar surface of a semiconductor substrate, wherein the semiconductor substrate includes circuitry formed therein or on the semiconductor substrate to support memory circuitry, the thin film NOR memory string having:
a common source region and a common drain region each extending lengthwise along a first direction substantially perpendicular to the planar surface;
a plurality of channel regions, each provided between the common drain region and the common source region and in contact with both the common drain region and the common source region;
a plurality of regions of data storage material, each associated with and provided in contact with a respective one of the channel regions; and
a plurality of gate electrodes spaced apart from each other and insulated from each other by a dielectric material, each gate electrode positioned adjacent one of the channel regions, each gate electrode being separated from the channel region by an associated region of data storage material, and the gate electrode extends elongatedly along a second direction substantially parallel to the planar surface. According to paragraph 1,
The thin film NOR memory string is formed of a semiconductor structure, the semiconductor structure having:
a source line select transistor electrically connected to the common source region, the source line select transistor configured to receive a control signal to switch the source line select transistor between a conductive state and a non-conductive state; and
an interconnection conductor extending along a third direction substantially orthogonal to both the first and second directions, the interconnection conductor electrically connecting the circuitry for supporting memory operation to the source line select transistor, and wherein the common source region is electrically connected to the circuitry for memory operation through the interconnection conductor when the line select transistor is in a conducting state. According to paragraph 2,
A thin film NOR memory string, wherein the interconnection conductor is provided over the thin film NOR memory string. According to paragraph 3,
The source line select transistor includes a thin film transistor having a source region, a channel region, and a drain region stacked along the first direction. According to paragraph 1,
A thin-film NOR memory string, where each channel region is substantially semi-annular. According to paragraph 1,
A thin film NOR memory string, wherein circuitry within said circuitry for supporting memory operations includes one or more voltage sources. According to paragraph 1,
A thin film NOR memory string, wherein the thin film NOR memory string is one thin film NOR memory string of an array of thin film NOR memory strings. A memory structure formed on a planar surface of a semiconductor substrate, wherein the semiconductor substrate includes circuitry formed therein or on the semiconductor substrate to support memory circuit operation, the memory structure comprising:
An array of thin film NOR memory strings comprising first, second, and third thin film NOR memory strings, wherein each of the first, second, and third thin film NOR memory strings is substantially a thin film NOR memory according to claim 1. Consists of strings -;
First, second, and third conductor segments - (a) the first conductor segment is electrically connected to both a common drain region of the first thin-film NOR memory string and a common drain terminal of the second thin-film NOR memory string; and (b) the second conductor segment is electrically connected to the common drain region of the third thin film NOR memory string, and (c) the third conductor segment is electrically connected to the circuitry to support memory operations. Connected -; and
First and second bit-line select transistors, each configured to receive a control signal to cause the bit-line select transistor to switch between a conducting state and a non-conducting state, (i) When the first bit-line select transistor is biased into a conducting state, the first bit-line select transistor connects the first conductor segment to the third conductor segment, and (ii) the second conductor segment. When the bit-line select transistor is biased into a conducting state, the second bit-line select transistor connects the second conductor segment to the third conductor segment. According to clause 8,
wherein the first and second conductor segments are provided between any one of the first, second and third thin film NOR memory strings and a planar surface of the semiconductor substrate. According to clause 8,
The first bit-line select transistor and the second bit-line select transistor each include a thin film transistor having a source region, a channel region, and a drain region stacked along the first direction. According to clause 8,
The array of thin film NOR memory strings is organized into rows and columns of thin film NOR memory strings, each row of thin film NOR memory strings extending in a third direction substantially orthogonal to the first direction. Extended memory structure. According to clause 11,
A memory structure wherein the thin film NOR memory strings in the array of thin film NOR memory strings are isolated from each other by an isolating dielectric material or an air gap. According to clause 8,
In an array of thin-film NOR memory strings, the gate electrode of each thin-film NOR memory string terminates in a stepped structure, and each gate electrode is supported by conductor-filled vias in the stepped structure to support memory operations. A memory structure electrically connected to the circuit unit for. According to paragraph 1,
A thin film NOR memory string, further comprising a pre-charge transistor that electrically connects the common source region and the common drain region when biased into a conductive state. According to paragraph 1,
A thin film NOR memory string, wherein the circuitry for supporting memory operation includes a body bias voltage source, and the channel regions of the thin film NOR memory string are connected to the body bias voltage source. A composite memory structure comprising first and second modular memory structures, one provided on top of the other,
A composite memory structure, wherein each modular memory structure comprises a memory structure such as the memory structure according to claim 8. According to clause 16,
wherein the first and second modular memory structures are isolated from each other by a dielectric layer. According to clause 17,
The thin film NOR memory strings in the first and second modular memory structures are aligned along the first direction, and the common source regions of corresponding thin film NOR memory strings in the first and second modular memory structures are: A composite memory structure connected by vias filled with conductors through the dielectric layer. According to paragraph 1,
The thin film NOR memory string further comprising metal pylons embedded in both the common source region and the common drain region. According to clause 19,
A thin film NOR memory string, wherein each of the metal pilons includes one or more of titanium nitride, tungsten nitride, or tungsten. According to clause 19,
Thin-film NOR memory strings, where each metal pilon is formed using atomic layer deposition technology. delete delete delete delete delete delete delete delete delete delete delete delete