JP2021512494A - 3D vertical NOR flash thin film transistor string - Google Patents

Abstract

The memory structure of the present disclosure includes an active row of polysilicon formed above a semiconductor substrate. Each active column contains one or more vertical NOR strings, each NOR string having a thin film storage transistor that shares a local source line and a local bit line. The local bit line is connected to a sense amplifier provided on the semiconductor substrate by one segment of the segmented global bit line. [Selection diagram] Fig. 3D

Description

The present invention relates to a high density memory structure. In particular, the present invention relates to high density memory structures formed by interconnected thin film storage elements, such as thin film storage transistors formed on vertical strips having horizontal word lines.

In the present disclosure, a memory circuit structure will be described. These memory circuit structures can be manufactured on a flat semiconductor substrate (eg, a silicon wafer) using conventional manufacturing processes. For clarity, the term "vertical" refers to the direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate. And.

Various high-density non-volatile memory structures, such as "three-dimensional vertical NAND strings," are known in the art. Many of these high-density memory structures are made using thin film storage transistors formed from deposited thin films (eg, polysilicon thin films) and are configured as arrays of "memory strings." One type of memory string is called a NAND memory string, or simply a "NAND string". The NAND string is composed of a large number of thin film memory transistors (“TFTs”) connected in series. In order to read or program the contents of one of the series connected TFTs, activation of all series connected TFTs in the NAND string is required. Thin film NAND transistors have lower conductivity than NAND transistors formed in single crystal silicon, so read access is relatively slow (ie, read) at low read currents that need to be conducted through long NAND strings. Latency is relatively long).

Another type of high density memory structure is called a NOR memory string, or "NOR string". The NOR string includes a large number of storage transistors connected to the shared source region and the shared drain region, respectively. In this way, since the transistors in the NOR string are connected in parallel with each other, the read current in the NOR string is conducted with a resistance much smaller than the read current through the NAND string. In order to read or program a memory transistor in the NOR string, only that memory transistor needs to be activated (ie, "on" or conductive) and all other in the NOR string. The memory transistor is maintained in a dormant state (ie, off or non-conducting state). As a result, the NOR string allows for faster detection of the activated storage transistor to be read. In a conventional NOR transistor, when an appropriate voltage is applied to the control gate, electrons are accelerated in the channel region by the voltage difference between the source region and the drain region, and between the control gate and the channel region. Programmed by channel hot electron injection technology injected into the charge trap layer. The channel hot electron injection program requires a relatively large electron flow to flow through the channel region, which limits the number of transistors programmable in parallel. Unlike transistors programmed by hot electron injection, in transistors programmed by Fowler-Nordheim tunneling or direct tunneling, electrons are channeled by the high electric field applied between the control gate and the source and drain regions. It is injected from the region into the charge trap layer. Fowler Nordheim tunneling and direct tunneling are orders of magnitude more efficient than channel hot electron infusion, allowing large-scale parallel programming, but being more susceptible to program ban conditions.

The 3D NOR memory array was filed on March 11, 2011 and published on January 14, 2014. It is disclosed in US Pat. Nos. 8,630,114 (Patent Document 1) entitled "Memory Architecture of 3D NOR Arrays" by T Tyronn Lue.

US Patent Application Publication No. 2016/0086970A1 (Patent), filed September 21, 2015 and published March 24, 2016, entitled "Three-Dimensional Non-Volatile NOR Flash Memory" by Haiving Peng. In Document 2), source electrodes and drains in which individual memory cells are stacked along the horizontal direction parallel to the semiconductor substrate and shared by all field effect transistors arranged on one or both sides of the conduction channel. A non-volatile NOR flash memory device consisting of an array of basic NOR memory groups with electrodes is disclosed.

The 3D NAND memory structure is, for example, the United States entitled "Compact 3D Vertical NAND and Its Manufacturing Methods" by Alsmeier et al., Filed on January 30, 2013 and published on November 4, 2014. It is disclosed in Japanese Patent No. 8,878,278 (Patent Document 3) (Alsmeier). In Patent Document 3, for example, "terabit cell array transistor" (TCAT) NAND array (FIG. 1A), "pipe-shaped bit cost scalable (P-BiCS) flash memory" (FIG. 1B), and "vertical NAND". Various types of high density NAND memory structures, such as memory string structures, are disclosed. Similarly, a US patent filed December 31, 2002 and published February 28, 2006, entitled "Methods for Manufacturing Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings" by Walker et al. No. 7,005,350 (Patent Document 4) (Walker I) also discloses various three-dimensional high-density NAND memory structures.

US Pat. No. 7,612,411, entitled "Dual Gate Devices and Methods" by Walker, filed August 3, 2005 and published November 3, 2009 (Patent Document 5) (Patent Document 5). Walker II) discloses a "dual gate" memory structure that provides a storage element in which a shared active region is independently controlled in two NAND strings formed on either side of the shared active region.

The 3D NOR memory array was filed on March 11, 2011 and published on January 14, 2014. It is disclosed in US Pat. Nos. 8,630,114 (Patent Document 1) entitled "Memory Architecture of 3D NOR Arrays" by T Tyronn Lue.

A three-dimensional memory structure containing a horizontal NAND string controlled by a vertical polysilicon gate is described by W. In the paper "Multilayer Vertical Gate NAND Flash Overcoming Stack Limits for Terabit Density Storage" by Kim et al. (2009 VLSI Symposium: Technical Digest of Technical Papers, pp.188-189) (Non-Patent Document 1) (Kim) It is disclosed. Another 3D memory structure, including a horizontal NAND string with a vertical polysilicon gate, is described in H.I. T. Liu et al., "Highly scalable 8-layer 3D vertical gate (VG) TFT NAND flash using junction-free embedded channel BE-SONOS device" (2010 VLSI Symposium: Technical Digest of Technical Papers, pp.131-132) ( It is disclosed in Non-Patent Document 2).

FIG. 1A shows three-dimensional vertical NAND strings 111 and 112 according to the prior art. FIG. 1B shows a basic circuit diagram 140 of a three-dimensional vertical NAND string according to the prior art. Specifically, the vertical NAND strings 111 and 112 of FIG. 1A, and their schematics, respectively, are essentially conventional horizontal NAND strings, with 32 or more transistors in series along the surface of the substrate. Rather than connecting, they are oriented by rotating 90 degrees so that they are orthogonal to the substrate. Vertical NAND strings 111 and 112 are thin film transistors (TFTs) connected in series in the form of strings that rise from the substrate like a skyscraper, and each TFT is a storage element and a word wire conductor in an adjacent stack of word wire conductors. It has a control gate provided by one. As shown in FIG. 1B, in the simplest embodiment of the vertical NAND string, the TFTs 15 and 16 are the first and last memory transistors of the NAND string 150 controlled by separate word lines WL0 and WL31, respectively. The bit line selection transistor 11 activated by the signal BLS and the ground selection transistor 12 activated by the signal SS address in the vertical NAND string 150 during read, program, program prohibition, and erase operations. The designated TFT is connected to the corresponding global bit line GBL at the terminal 14 and is grounded to the global source line (GSL) at the terminal 13. For reading or programming the contents of any one TFT (eg, TFT 17), activate all 32 TFTs in the vertical NAND string 150 to put each TFT in read-disabled and program-disabled state. There is a need. Under such conditions, the number of TFTs that can be provided in the vertical NAND string is limited to 64 or less or 128 or less. In addition, the polysilicon thin films on which the vertical NAND strings are formed have much lower channel mobility than conventional NAND strings formed on single crystal silicon substrates, and thus have higher resistivity, resulting in conventional conventional NAND strings. The read current is lower than the read current of the NAND string.

A three-dimensional vertical NAND string is disclosed in US Patent Application Publication No. 2011/0298013 (Patent Document 6) (Hwang) entitled "Vertical Structure Semiconductor Memory Device and Method for Manufacturing". FIG. 4D of Patent Document 6 illustrates a block of three-dimensional vertical NAND strings addressed by a wraparound stack word line (reposted herein as 150 in FIG. 1C). Reprinted as Figure 1C in the book).

US Pat. Nos. 5,768,192, filed July 23, 1996 and published June 16, 1998, entitled "Memory Cell Utilizing Asymmetric Charge Traps" by Eitan. 7) discloses the type of NROM type memory transistor operation used in one embodiment of the present invention.

US Pat. No. 8,026,521, entitled "Memory Cell Utilizing Asymmetric Charge Traps" by Zvi Or-Bach et al., Filed October 11, 2010 and published September 27, 2011. The document (Patent Document 8) discloses a first layer and a second layer of layer-transferred single crystal silicon, which comprises a transistor in which the first layer and the second layer are horizontally oriented. .. In this structure, a second layer of horizontally oriented transistors covers a first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has a side gate. In this structure, a second layer of horizontally oriented transistors covers a first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has a side gate.

A transistor having a conventional non-volatile memory transistor structure but having a short data retention time can be called "quasi-volatile". In this regard, the data retention time of conventional non-volatile memory exceeds several decades. A flat semi-volatile memory transistor on a single crystal silicon substrate can be found in H. et al. C. Wann and C.I. Hu's paper "Highly durable ultra-thin tunnel oxide in monodevice structure for dynamic memory applications" (IEEE Electron Device letters, Vol. 16, No. 11, November 1995, pp 491-493) (Non-Patent Document 3) ). Further, a quasi-volatile 3-D NOR array having a quasi-volatile memory is disclosed in the above-mentioned US Pat. No. 8,630,114 (Patent Document 1).

T. The paper "768Gb 3b / cell 3D floating gate NAND flash memory" by Tanaka et al. (The Digest of Technical Papers, the 2016 IEEE International Solid-State Circuits Conference, pp. 142-144) (Non-Patent Document 4) has three dimensions. It is disclosed that a CMOS logic circuit is arranged directly under the NAND memory array.

U.S. Pat. Nos. 8,630,114 U.S. Patent Application Publication No. 2016/0086970 U.S. Pat. No. 8,878,278 U.S. Pat. No. 7,005,350 U.S. Pat. Nos. 7,612,411 U.S. Patent Application Publication No. 2011/0298013 U.S. Pat. No. 5,768,192 U.S. Pat. No. 8,026,521

W. Kim et al., "Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage", 2009 Symposium on VLSI Tech. Dig. Of Technical Papers, pp 188-189 HT Lue et al., "A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device", 2010 Symposium on VLSI: Tech. Dig. Of Technical Papers, pp. 131-13 H.C. Wann and C.Hu, "High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application", IEEE Electron Device letters, Vol. 16, No. 11, November 1995, pp 491-493 T. Tanaka et al., "A 768 Gb 3b / cell 3D-Floating-Gate NAND Flash Memory", Digest of Technical Papers, the 2016 IEEE International Solid-State Circuits Conference, pp. 142-144

According to one embodiment of the present invention, a high density memory structure called a three-dimensional vertical NOR flash memory string (“multi-gate vertical NOR string”, or simply “vertical NOR string”) is provided. The vertical NOR string includes a plurality of thin film transistors (“TFTs”) connected in parallel, each of which has a common source region and a common drain region extending in a substantially vertical direction. In addition, the vertical NOR string includes a plurality of horizontal control gates, each controlling each TFT of the vertical NOR string. Since the TFTs of the vertical NOR string are connected in parallel, the read current in the vertical NOR string is conducted with a resistance much smaller than the read current in the same number of NAND strings. To read or program any one of the TFTs in the vertical NOR string, only that TFT needs to be activated and all other TFTs in the vertical NOR string may remain non-conducting. As a result, the vertical NOR string can contain much more (eg, hundreds or more) TFTs, allowing faster sensing and minimizing program or read disturb states. ..

In one embodiment, the shared drain region of _{the vertical NOR string is connected to the global bit line (“voltage V bl} ”) and the shared source region of the vertical NOR string is connected to the global source line (“voltage V _ss ”). Alternatively, in the second embodiment, only the shared drain region is connected to the global bit line biased to the supply voltage, and the shared source region is precharged to a voltage determined by the amount of charge in the shared source region. In order to perform precharging, one or more dedicated TFTs that precharge the parasitic capacitance C in the shared source region may be provided.

According to one embodiment of the present invention, a multi-gate NOR flash thin film transistor array (“multi-gate NOR string array”) is configured as an array of vertical NOR strings extending perpendicular to the surface of a silicon substrate. Each multi-gate NOR string array contains a number of vertically active columns arranged to form each row extending along the first horizontal direction. Each active row has two vertical polysilicon regions heavily doped in the first conductive type, the two vertical polysilicon regions being undoped or low-concentrated doped in the second conductive type. Insulated from each other by one or more vertical polysilicon regions. The highly doped regions form a shared source region or a shared drain region, respectively. Also, each of the low concentration doped regions cooperates with a stack of one or more horizontal conductors extending orthogonally to the first horizontal direction to form a plurality of channel regions. The charge trap material forms a storage element that covers at least the channel region of the TFT in the active row. The horizontal conductors in each stack are electrically isolated from each other, forming a control gate on the storage element and channel region of the active row. In this way, the multi-gate NOR string array forms a three-dimensional array of storage TFTs.

In one embodiment, the support circuit is formed on the semiconductor substrate to support the support circuit and a plurality of multi-gate NOR string arrays formed above the semiconductor substrate. Support circuits include address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, reference cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, exclusive OR and other. Examples include logic gates, other memory elements, sequencers, and state machines. The multi-gate NOR string array can be configured as a multi-block circuit in which each block has a plurality of multi-gate NOR string arrays.

According to embodiments of the present invention, fluctuations in the threshold voltage of a TFT within a vertical NOR string provide one or more electrically programmable reference vertical NOR strings in the same or different multi-gate vertical NOR string arrays. It can be compensated by. The background leak current inherent in the vertical NOR string effectively nullifies the result of the TFT being read during the read operation by comparing the result of the TFT being read simultaneously with the programmable reference vertical NOR string. be able to. In some embodiments, each TFT in the vertical NOR string increases the capacitive coupling between each control gate and its corresponding channel region, thereby increasing the charge trap material (ie, storage) from the channel region in the program. It is formed to enhance tunneling to the element) and reduce charge injection from the erasing control gate into the charge trap material. This preferred capacitive coupling is particularly useful for storing one or more bits in each TFT of the vertical NOR string. In another embodiment, the charge trap material of each TFT has a modified structure to provide high write / erase cycle durability, although the data retention time is short and the stored data needs to be refreshed. May be good. However, the refreshes required for vertical NOR string arrays are expected to be much less frequent than refreshes in conventional dynamic random access memory (DRAM), so some multi-gate NOR string arrays of the invention are available. It can also work in the DRAM application of. By using such a vertical NOR string, it is possible to achieve a figure of merit with a significantly lower cost per bit compared to a conventional DRAM, and a significantly smaller read latency than a conventional NAND string array. ..

In another embodiment, the vertical NOR string can be programmed, erased, and read as an NROM / mirror bit TFT string.

By configuring the TFT as a vertical NOR string instead of a prior art vertical NAND string, (i) a reduction in read latency that can approach the latency of a dynamic random access memory (DRAM) array, (ii) a long NAND flash. The effect of reducing the influence of the read and program disturb states associated with the string and reducing the cost per bit as compared to the (iii) NAND flash string can be obtained.

According to another embodiment of the invention, each active row in the memory structure comprises one or more vertical NOR strings, each NOR string having a thin film storage transistor that shares a local source line and a local bit line. , The local bit line is connected to the sense amplifier provided on the semiconductor substrate by one segment of the segmented global bit line. To significantly reduce read sense latency, multiple shorter global bit line segments are used instead of a single global bit line extending over a fairly long distance (eg, from the full length of the chip to half its length). Provided. Each such global segment connects one or more adjacent local bit lines to a segment sense amplifier provided on a semiconductor substrate via a gment connector. Local source line virtual ground voltage (e.g., V _ss) In the embodiment precharged to, by providing a short global source line segments connector for connecting a group of local source lines adjacent to one local source line segments, The parasitic capacitance of virtual ground is greatly increased. The synthetic parasitic capacitance (C) is determined by the number of local source lines contained in the segment.

The present invention may be better understood by reference to the following detailed description in conjunction with the accompanying drawings.

FIG. 1A is a diagram showing three-dimensional vertical NAND strings 111 and 112 according to the prior art. FIG. 1B is a diagram showing a basic circuit diagram 140 of a three-dimensional vertical NAND string according to the prior art. FIG. 1C is a diagram showing a three-dimensional structure of a block of three-dimensional vertical NAND strings addressed by the wraparound stack word line 150. FIG. 2 is a diagram showing a conceptualized memory structure 100, and shows a three-dimensional structure of a memory cell provided in the form of a vertical NOR string according to an embodiment of the present invention. Each vertical NOR string has a memory cell controlled by one of a number of horizontal word lines. FIG. 3A is a basic circuit diagram of a ZZ plane of a vertical NOR string 300 formed in an active row according to an embodiment of the present invention. The vertical NOR string 300 represents a three-dimensional array of non-volatile storage TFTs, each TFT sharing a local source line (LSL) 355 and a local bit line (LBL) 354 and a global bit line (GBL) 314. And accessed by global source line (GSL) 313, respectively. FIG. 3B is a basic circuit diagram of a ZZ plane of a vertical NOR string 305 formed in an active row according to an embodiment of the present invention. Vertical NOR string 305 represents a three-dimensional array of non-volatile storage TFT (SEQ), a dedicated pre-charge TFT370 for setting the shared local source line 355 to a predetermined voltage ( _{"V ss")} having a parasitic capacitor C Including. FIG. 3C is a basic circuit diagram of a dynamic non-volatile storage transistor 317 having one or more programmed threshold voltages and connected to a parasitic capacitor 360. The capacitor 360 is precharged so that the source terminal (source line) 355 _{temporarily holds the virtual voltage V ss} , whereby the voltage when the voltage of the control gate 323p rises to a voltage exceeding the threshold voltage. it is possible to dynamically detect the threshold voltage of the transistor 317 by the discharge of the V _ss. FIG. 3D shows a modified example of the vertical NOR memory array circuit architecture in the embodiment of FIG. 3A. In this variant, the global bit line (GBL) 314 is _{replaced by bit line segments MSBL 1} , MSBL ₂ , ..., Each of which is a plurality of adjacent local vertical bit lines 374-1, 374-2, ...・ ・ Connect. The segment is then connected to _{the region bit line segments SGBL 1} , SGBL ₂ , ... Via the segment selection thin film transistors 586-1, ..., 586N. Each region bit line segment is associated with a plurality of bit line segments and is insulated by a dielectric (insulating layer) 393 from the sense amplifier and other circuits provided on the silicon substrate 310 below them. FIG. 3E shows a modified example of the circuit architecture of the embodiment of FIG. 3D. In this variant, the global source selection line 313 accesses a group of adjacent vertical local source lines 375-1, 375-2, etc. associated with the _{source line segment MSSL 1 via the source selection transistor SLS1.} .. FIG. 3F shows a modified example of the circuit architecture of the embodiment of FIG. 3E. In this variant, the global source line 313 is removed and replaced _{with the local source line segment MSSL 1 connecting the vertical local source lines 375-1, 375-2, ....} Vertical local source lines 375-1,375-2, ... are the precharge transistors (e.g., pre-charge transistor 370) through a, are charged to the virtual ground voltage _{V SS} is maintained. FIG. 3G shows a modified example of the circuit architecture of the embodiment of FIG. 3F. In this modification, the local bit line segments SGBL ₁ , SGBL ₂ , ... Are coupled to the bit line segments MSBL ₁ , MSBL ₂ , ..., And a segment selection transistor provided on the substrate via the via 322. It is connected to 315-1, 315-2 ... (This replaces the segment-selected thin film transistors 586-1, 586-2, ... In FIG. 3D). FIG. 3H shows a modified example of the circuit architecture of the embodiment of FIG. 3G. In this modification, the two bit line segments MSBL ₁ and MSBL ₂ adjacent to each other are connected to the substrate 310 via a dedicated vertical active column 381 formed in the space labeled BL0 between the two bit line segments. It has their local source line segments MSSL ₁ and MSSL _{2 connected} to. 3I and 3I-1 (keys to 3I and 3I-1) show the upper XY plan view of the embodiment of FIG. 3H, where each vertical local source line in the _{source segment MSSL 1 has an active column 381.} It is held at the _{voltage V SS} or V _bl supplied through it. 3I and 3I-1 (keys to 3I and 3I-1) show the upper XY plan view of the embodiment of FIG. 3H, where each vertical local source line in the _{source segment MSSL 1 has an active column 381.} It is held at the _{voltage V SS} or V _bl supplied through it. FIG. 4A is a cross-sectional view of a ZZ plane according to an embodiment of the present invention, each capable of forming a vertical NOR string having the basic schematic shown in either FIG. 3A or FIG. 3B. The active columns 431 and the active columns 432 arranged in parallel with each other are shown. FIG. 4A-1 is a top view of the vertical NOR string of FIG. 4A, in which the core of the pillar of the local source line or drain line is made of metal material 420 (M) in order to enhance the conductivity of the vertical local source line or drain line. Contains. FIG. 4B is a cross-sectional view of the ZX plane according to an embodiment of the present invention, with active columns 430R, 430L, 431R and 431L, charge trap layers 432 and 434, and word line stacks 423p-L and 423p-. Indicates R. FIG. 4C is a basic circuit diagram of vertical NOR strings pairs 491 and 492 in the ZX plane according to an embodiment of the present invention. FIG. 5A is a cross-sectional view of a ZZ plane according to an embodiment of the present invention, in which the vertical NOR string of the active column 531, the global bit line 514-1 (GBL ₁ ), and the global source line 507 (GSL ₁ ). , And the connection with the common body bias source 506 (V _bb). FIG. 5B is a cross-sectional view of a ZZ plane according to an embodiment of the present invention, for example, a main body region 556 (P-) via a conductive pillar 591 formed from P + polysilicon in a dielectric layer 592. It provides a channel material) and shows the connection between the conductor 590, which is provided above the active row 581 and extends parallel to the word line. The conductor 590 receives the _{body bias voltage V bb} from the voltage source 594 in the substrate 505 via the via 593 provided in the opening formed through the dielectric insulator 509. FIG. 6A is a cross-sectional view of the XY plane according to an embodiment of the present invention, the TFT 685 ( _TL ) of the vertical NOR string 451a and the vertical NOR string pair 491, as described in connection with FIG. 4C. show TFT684 the _{(T R)} of the vertical NOR string 451b of. In FIG. 6A, the global bit line 614-1 accesses every other local bit line LBL-1 and has a channel corresponding to each control gate in the program by a predetermined curved portion 675 of the transistor channel region 656L. Capacitive coupling between and is amplified. Figure 6B, according to one embodiment of the present invention, a cross-sectional view of the X-Y plane, as described in relation to FIG. 4C, the vertical NOR string 451b of vertical NOR string pairs 491 TFT684 _(T R), _{And the TFT 685 (TL} ) of the vertical NOR string 451a that shares the active region. In FIG. 6B, the global bit line 614-1 accesses every other (odd number) with respect to the local bit line 654 (LBL-1), and the global bit line 614-2 is the local bit line 657-2 (the odd number). Every other (even number) address is specified for LBL-2), and the local source lines LSL-1 and LSL-2 are precharged to supply the _{virtual power supply voltage V ss.} FIG. 6C is a cross-sectional view of an XY plane according to an embodiment of the present invention, each containing a dedicated word line stack 623p and a local vertical pillar bit line (pillar or columnar portion) 654. (Extended along the Z direction) and local vertical pillar source line 655 (extended along the Z direction). Each word line of the word line group of the dedicated word line stack 623p extends so as to wrap (“wrap around”) the TFT of the vertical NOR string, and the local vertical pillar bit line 654 and the local vertical pillar source line 655 are respectively. , Accessed by the global horizontal bit line 614 and the global horizontal source line 615. In FIG. 6C, adjacent wordline stacks 623p are insulated from each other by an air gap 610 or another dielectric insulator. FIG. 6D is a cross-sectional view of an XY plane according to an embodiment of the present invention, showing a form in which vertical NOR strings are densely packed in a staggered pattern. The vertical NOR strings share the word line stack 623p, as in the case shown in FIG. 6C, and each of the precharged parasitic capacitors 660 supplies a precharged virtual supply voltage V _ss . FIG. 6E uses the layout of the embodiment shown in FIG. 6B to share body bias voltages V _bb (eg, conductors 690-1 and 690) between body regions 656 (L + R) in adjacent rows of active columns. It is an XY plan view which shows that (via -2) is provided. FIG. 6F shows an embodiment of a global word line for connecting local word lines on a plane (ie, a step step), which is related to the bit line segmentation scheme of the present invention. FIG. 6G shows an embodiment of a vertical NOR string memory array according to an embodiment of the present invention. In this embodiment, when the number of layers of storage transistors is doubled in the vertical direction, a word line stepped shape is shown. It is possible to avoid doubling the silicon area occupied by the steps. FIG. 7A is a cross-sectional view of an intermediate structure produced in the process of manufacturing a multi-gate NOR string array according to an embodiment of the present invention. FIG. 7B is a cross-sectional view of an intermediate structure produced in the process of manufacturing a multi-gate NOR string array according to an embodiment of the present invention. FIG. 7C is a cross-sectional view of an intermediate structure produced in the process of manufacturing a multi-gate NOR string array according to an embodiment of the present invention. FIG. 7D is a cross-sectional view of an intermediate structure produced in the process of manufacturing a multi-gate NOR string array according to an embodiment of the present invention. FIG. 7D-1 is a cross-sectional view of the XY plane, showing that the core of the vertical pillar of the local source line or the local bit line contains the conductive material 720 (M). FIG. 8A is a schematic diagram of a readout operation in an embodiment in which the local source line (LSL) of the vertical NOR string is hard-wired. In FIG. 8A, “WL _s ” represents the voltage on the selected word line and all unselected word lines in the vertical NOR string (“WL _NS ”) are set to 0V during the read operation. FIG. 8B is a schematic diagram of a read operation in the embodiment in which the local source line is _{in a float state at the precharge virtual voltage V ss.} In FIG. 8B, “WL _CHG ” represents the gate voltage on the precharged transistor (eg, the precharged transistor 317 or 370 of FIG. 3C).

FIG. 2 is a diagram showing a conceptualized memory structure 100, showing a three-dimensional structure of a memory cell (or storage element) provided in the form of a vertical NOR string. According to one embodiment of the invention, in this conceptualized memory structure 100, each vertical NOR string comprises a memory cell controlled by a corresponding horizontal word line. In the conceptualized memory structure 100, each memory cell is formed "vertically", i.e., in a deposited thin film provided along a direction orthogonal to the surface of the substrate layer 101. The substrate layer 101 can be, for example, a conventional silicon wafer used for manufacturing integrated circuits, which is well known to those skilled in the art. In this detailed description, a Cartesian coordinate system (as shown in FIG. 2) is employed solely for the purpose of facilitating the description. Under this coordinate system, the surface of the substrate layer 101 is considered to be a plane parallel to the XY plane. Thus, as used herein, the term "horizontal" refers to any direction parallel to the XY plane, while the term "vertical" refers to the Z direction.

In FIG. 2, each vertical active row in the Z direction represents a storage element or TFT of a vertical NOR string (eg, vertical NOR string 121). The vertical NOR strings are regularly arranged to form multiple rows, each extending along the X direction (of course, this arrangement can also be viewed as an array of rows, each extending along the Y direction. ). The storage element of the vertical NOR string shares a vertical local source line and a vertical local bit line (not shown). A stack of horizontal word lines (eg, WL123) extends along the Y direction, and each word line serves as a control gate for the corresponding TFT of a vertical NOR string located adjacent to the word line along the Y direction. Function. Global source lines (eg, GSL122) and global bit lines (eg, GBL124) are generally provided along the X direction through either below the bottom or above the top of the conceptualized memory structure 100. Alternatively, both signal lines GSL122 and GBL124 may be routed below the conceptualized memory structure 100, or above the top thereof, in which case each of these signal lines is an access transistor (not shown). ) May selectively connect to the local source line and local bit line of each vertical NOR string. In the vertical NOR strings of the present invention, unlike the vertical NAND strings of the prior art, writing or reading to any one of the storage elements does not involve activation of the other storage elements in the vertical NOR strings. As shown in FIG. 2, as an example for the purpose of explanation only, the conceptualized memory block (memory structure) 100 is a multi-gate vertical NOR string array composed of a 4 × 5 array of vertical NOR strings, and each NOR is A string typically has 32 or more storage elements and access selection transistors. As a conceptualized structure, the memory block (memory structure) 100 is merely an abstraction of certain salient features of the memory structure of the present invention. Although each vertical NOR string is shown in FIG. 2 as a 4 × 5 array of vertical NOR strings having a plurality of storage elements, the memory structure of the present invention is along either the X direction or the Y direction. Each row may have any number of vertical NOR strings, and each vertical NOR string may have any number of storage elements. As an example, each NOR string has thousands of vertical NOR strings with, for example, 2, 4, 8, 16, 32, 64, 128 or more storage elements along both the X and Y directions. They may be arranged in rows.

The number of storage elements in each vertical NOR string (eg, vertical NOR string 121) in FIG. 2 corresponds to the number of word lines (eg, WL123) that provide the vertical NOR string control gate. The word lines are formed as elongated metal strips, each extending along the Y direction. The word wires are stacked on top of each other and electrically insulated from each other by a dielectric insulating layer between them. The number of word lines in each stack may be any number, but is preferably 2 to the power of an integer (ie, 2 to the power of n (n is an integer)). The choice of powers of 2 to the number of word lines follows conventional memory design conventions. It is customary to access each addressable memory unit by decoding the binary address. This convention is a matter of taste and does not need to be followed. For example, within the scope of the present invention, the conceptualized memory structure 100 has a number of M vertical NORs along each row in the X and Y directions, which is not necessarily 2 to the nth power (n is an arbitrary integer). Can have strings. In some embodiments described below, two vertical NOR strings can share a vertical local source line and a vertical local bit line, but each storage element of the two vertical NOR strings is two separate. Controlled by the wordline stack. This effectively doubles the storage density of the vertical NOR string.

The conceptualized memory structure 100 of FIG. 2 is provided solely to illustrate the configuration of memory cells and should not be drawn on a particular scale in any of the X, Y, and Z directions. Not in.

FIG. 3A is a basic circuit diagram of the vertical NOR string 300 formed in the active row in the ZZ plane. The vertical NOR string 300 represents a three-dimensional array of non-volatile storage TFTs, and according to one embodiment of the invention, each TFT shares a local source line 355 and a local bit line 354. In this detailed description, the term "active region,""activerow," or "active strip" refers to a region, row of one or more semiconductor materials on which an active device (eg, a transistor or diode) can be formed. , Or refers to a strip. As shown in FIG. 3A, the vertical NOR string 300 extends in the Z direction and has a TFT 316 and a TFT 317 connected in parallel between the vertical local source line 355 and the vertical local drain or bit line 354. Have. The bit line 354 and the source line 355 are separated from each other, and the region between them (ie, the body region 356) provides a channel region for the TFT in the vertical NOR string. The storage element is formed at the intersection of the channel region 356 and each horizontal word line 323p. Where p is the index of the wordline in the wordline stack. In this example, p can take any value in the range 0-31. The word line extends along the Y direction. The local bit line 354 is connected to the horizontal global bit line (GBL) 314 via the bit line access selection transistor 311. The horizontal global bit line (GBL) 314 extends along the X direction and connects the _{local bit line 354 to the access bit line supply voltage V b1.} The local source line 355 is connected to the _{source power supply voltage V ss} via the horizontal global source line (GSL) 313. In order to connect the local source line 355 and the GSL 313, a source selection transistor (not shown in FIG. 3A) may be optionally provided. The optional source selection transistor can be mounted on a substrate (eg, semiconductor substrate 101 in FIG. 2) or above the substrate and below the memory structure 100, as known to those of skill in the art, by means of a source decoding circuit. It may be controlled. The body region 356 of the active row may be connected to the _{substrate bias voltage V bb at the terminal 331.} The substrate bias voltage V _bb can be used, for example, during the erasing operation. The V _bb supply voltage may be applied to the entire multi-gate vertical NOR string array or may be selectively applied to one or more rows of the vertical NOR string via a decoding mechanism. The line connecting the power supply voltage V _bb to the body region 356 preferably extends along the direction of the word line.

FIG. 3B is a basic circuit diagram of the vertical NOR string 305 formed in the active row in the ZZ plane. The vertical NOR string 305 represents a three-dimensional array of non-volatile storage TFTs, according to one embodiment of the invention, on a shared local source line 355 having a parasitic capacitor C (represented by capacitor 360). Includes (optionally) a dedicated precharge TFT 370 for instantaneously setting the voltage (“V _ss”). Unlike vertical NOR string 300 of FIG. 3A, the vertical NOR string 305 of FIG. 3B does not implement GSL313, _instead, the pre-precharging the parasitic capacitor 360 for temporarily holding the voltage _{V ss} bolts It has a charge transistor 370. Under this precharge scheme, the global source line (eg, global source line 313 in FIG. 3A) and its decoding circuit are no longer needed, which simplifies both the manufacturing process and the circuit layout and for each vertical NOR string. It can provide a very narrow footprint. FIG. 3C highlights the structure of the non-volatile storage TFT 317, which can be used to perform the precharge function of the dedicated precharge transistor 370 in addition to its normal storage function. The dynamic read operation with respect to the TFT 317 will be described later in relation to sensing the correct one of several threshold voltages programmed in the storage element 334 of the TFT 317.

FIG. 4A shows the active columns 431 arranged in parallel with each other, each of which can form a vertical NOR string having the basic schematic shown in either FIG. 3A or FIG. 3B, according to an embodiment of the invention. It is sectional drawing of the ZZ plane which shows the active row 432. As shown in FIG. 4A, the active columns 431 and 432 are vertically N + doped local source regions 455 and vertical N + doped, respectively, isolated from each other by low concentration P-doped or non-doped channel regions 456. Includes local drain or bit line area 454. The P-doped channel region 456, the N + doped local source region 455, and the N + doped local drain or bit line region 454 are the body bias voltage V _bb , the source power supply voltage V _ss , and the bit line voltage V _bl. Is biased to each. According to some embodiments of the present invention, the use of the _{body bias voltage V bb} is optional, for example when the active strip is sufficiently thin (eg, 10 nm or less). For sufficiently thin active strip, so that the voltage V _bb not supply solid feed voltage to the channel region of the TFT along the vertical NOR string active area readily fully depleted under appropriate voltages on the control gates Will be done. The insulating region 436 that electrically insulates the active row 431 and the active row 432 can be either a dielectric insulator or an air gap. A vertical stack of word lines 423p, respectively labeled WL _{0- WL 31} (and optionally WL _CHG ), provides a control gate for the TFTs in the vertical NOR strings formed in active column 431 and active column 432, respectively. To do. The wordline stack 423p is generally an elongated metal conductor extending along the Y direction (eg, tungsten) that is electrically isolated from each other by a dielectric layer 426 formed of _{silicon oxide (eg, SiO 2) or an air gap.} , ►, or ►). The non-volatile memory device provides a charge trap material (not shown) between the word line 423p and the P-doped channel region 456, thereby intersecting each word line 423p with each P-doped channel region 456. Can be formed in the part. For example, in FIG. 4A, the dashed box 416 indicates where the non-volatile storage elements (or storage transistors) T _0- T ₃₁ can be formed. The dashed box 470 indicates where a dedicated precharge transistor can be formed. This dedicated precharge transistor transfers charge from the common local bit line region 454 to the common local source line region 455 when _{all transistors T 0 to} T ₃₁ are in the off state when switched on instantly. Make it possible.

FIG. 4B is a cross-sectional view of a ZX plane showing active columns 430R, 430L, 431R and 431L, charge trap layers 432 and 434, and word line stacks 423p-L and 423p-R according to an embodiment of the present invention. Is. Similar to FIG. 4A, each of the vertical wordline stacks 423p-L and 423p-R of FIG. 4B shows a stack of thin conductors. Here, p is an index that labels the word lines in the stack (eg, word lines WL _{0 to WL 31).} As shown in FIG. 4B, each word line serves as a control gate for a non-volatile TFT of vertical NOR strings formed on adjacent active rows 430L and 431R on either side of the word line (in region 490). For example, in FIG. 4B, the word line WL ₃₁ in the word line stack 423p-R functions as a control gate for both the transistor 416L on the active row 430L and the transistor 416R on the active row 431R. Adjacent word line stacks (eg, word line stacks 423p-L and 423p-R) are separated by a distance of 495, which is the width of a trench formed by etching continuous word line layers, as described below. .. The active rows 430R and 430L, and their respective charge trap layers 432 and 434, are then formed inside the trench etched through the word line layer. The charge trap layer 434 is provided between the word line stack 423p-R and the vertical active columns 431R and 430L. As described in detail below, during the programming of the transistor 416R, the charge injected into the charge trap layer 434 is trapped in the portion of the charge trap layer 434 in the dashed box 480. The trapped charge changes the threshold voltage of the TFT 416R. This can be detected by measuring the read current flowing between the local source region 455 and the local drain region 454 on the active row 431R (these regions are, for example, orthogonal to the active row in FIG. 4A). Shown in cross section). In some embodiments, the precharge word line 478 (ie, WL _CHG ) grounds or sources the parasitic capacitor C of the local source line 455 (see capacitor 360 in FIG. 3B and local source line 455 in FIG. 4A). It is provided as a control gate for the precharge TFT 470 used to charge the power supply voltage V _ss. For convenience, the charge trap layer 434 also provides a storage element for the precharge transistor 470, but is not itself used as a memory transistor. Alternatively, precharging may be performed using any of _{the memory transistors T 0-} T ₃₁ formed in the active column 431R. One or more of these memory transistors can perform the function of a precharge transistor in addition to their memory function. To perform the precharge, the voltage on the ward line or control gate temporarily rises to a voltage several volts higher than the programmable maximum threshold voltage, which causes the voltage V applied to the local bit line 454. _{It becomes possible to transfer the ss} to the local source line 455 (Fig. 4A). By causing the memory transistors T _{0 to} T ₃₁ to execute the precharge function, it is not necessary to individually provide the dedicated precharge TFT 470. However, care must be taken not to excessively interfere with the threshold voltage of the memory TFT when it is performing its precharge function.

The active columns 430R and 430L are shown in FIG. 4B as two separate active columns isolated from each other by an air gap or dielectric insulation 433, while the adjacent vertical N + local source lines are a single shared vertical. It may be realized by a local source line. Similarly, a vertical N + local drain or bit line may also be implemented by a single shared vertical local bit line. Such a configuration provides a "vertical NOR string pair". In this configuration, the active columns 430L and 430R can be considered as two branches (hence, "pairs") within one active column. The vertical NOR string pair provides double density memory via charge trap layers 432 and 434 interposed between the active columns 430R and 430L and the wordline stacks 423p-L and 423p-R on both sides. In fact, the active rows 430R and 430L can be integrated into one active string by removing the air gap or dielectric insulator 433, but are nevertheless formed on opposite surfaces of a single active row. A pair of NOR TFT strings is provided. With such a configuration, the TFTs formed on the opposite surfaces of the active row are controlled by separate wordline stacks and are formed from separate charge trap layers 434 and 432, thus resulting in similar double density storage. Is achieved. It is advantageous to maintain separate thin active columns 430R and 430L (ie, instead of consolidating them into one active column). The reason is that the TFTs in each active row are thinner than the integrated rows, so they can be more easily and completely depleted under proper control gate voltage conditions, thereby making the active rows (FIG. 4A) vertical. This is because the source-drain subthreshold leakage current between the source region 455 and the vertical drain region 454 is significantly reduced. Even very long vertical NOR strings (eg, 128 TFTs and above) can have ultra-thin (and therefore high resistance) active rows. The reason is that the TFTs in the string are connected in series, which is in contrast to the high resistance of NAND TFT strings, where all TFTs need to be switched on to sense any TFT in the string. This is because the vertical NOR string TFTs are connected in parallel, and only one of the many TFTs can be switched on at any given time. For example, in a 32-TFT vertical NOR string, the channel length of the channel region 456 may be only 20 nm in order to read _{the transistor T 30 (FIG. 4A).} The corresponding channel length of the NAND string is 32 times this, or 640 nm.

FIG. 4C is a basic circuit diagram of vertical NOR strings pairs 491 and 492 in the ZX plane according to an embodiment of the present invention. As shown in FIG. 4C, the vertical NOR strings 451b and 452a share a common wordline stack 423p-R in the manner shown for the vertical NOR strings of the active strips 430L and 431R of FIG. 4B. The locally connected local bit lines in the vertical NOR string pairs 491 and 492 are the global bit line 414-1 (GBL ₁ ) via the access selection transistor 411 and the global bit via the access selection transistor 414. Served by line 414-2 (GBL ₂ ) respectively. The respective commonly connected local source lines in the vertical NOR string pairs 491 and 492 are served by global source lines 413-1 (GSL ₁ ) and global source lines 413-2 (GSL ₂ ), respectively (FIG. 4C). Although not shown in the above, an access selection transistor for selecting a source line can be provided in the same manner). As shown in FIG. 4C, the vertical NOR string pair 491 includes vertical NOR strings 451a and 451b that share a local source line 455, a local bit line 454, and an optional body connection 456. Therefore, the vertical NOR string pair 491 represents a vertical NOR string formed on the active columns 430R and 430L of FIG. 4B. The word line stacks 423p-L and 423p-R (31 ≧ p ≧ 0 in this example) provide control gates for the vertical NOR string 451a and the vertical NOR string 451b, respectively. Word lines that control gates in the stack are suitable for addressed TFTs (ie, activated word lines) and unaddressed TFTs (ie, all other deactivated word lines in the string). It is decoded by a decoding circuit formed on the substrate to ensure that a high voltage is applied. FIG. 4C shows how the same wordline stack 423p-R is served to the storage transistors 416L and 416R on the active columns 430L and 431R of FIG. 4B. Therefore, the vertical NOR string 451b of the vertical NOR string vs. 491 and the vertical NOR string 452a of the vertical string pair 492 correspond to the adjacent vertical NOR strings formed on the active columns 430L and 431R of FIG. 4B. The storage transistor of the vertical NOR string 451a (eg, storage transistor 415R) is served by the word line stack 423p-L.

In another embodiment, the hard-wired global source lines 413-1 and 413-2 of FIG. 4C are removed, and the shared N + local source lines 455 common to both the vertical NOR strings 451a and 451b and a number of related words. It is replaced by a parasitic capacitor between the lines 423p-L and 423p-R (eg, the parasitic capacitor represented by the capacitor 460 in FIG. 4C or the capacitor 360 in FIG. 3C). In a vertical stack of 32 TFTs, each of the 32 word lines provides a total parasitic capacitor C due to their parasitic capacitors, thereby temporarily holding the voltage supplied by the precharged TFT 470. It should be large enough to provide a _{virtual source voltage V ss} during a relatively short read or program operating period. In this embodiment, the virtual power supply voltage temporarily held in the parasitic capacitor C _{is supplied from the global bit line GBL 1} to the local source line 455 via the access selection transistor 411 and the precharge transistor 470. Alternatively, one or more of the memory TFTs in the vertical NOR string, in addition to their memory function, momentarily raise their wordline voltage above their programmed maximum voltage to cause the local source line 455. When used to precharge, the dedicated precharge transistor 470 can be omitted. However, when using the storage TFT for this purpose, care must be taken to avoid overprogramming the storage TFT. The use of virtual V _ss voltage provides the important advantage of eliminating hardwired global source lines (eg, GLS ₁ , GLS ₂ ) and their associated decoding circuits and access transistors. This greatly simplifies the process flow and design challenges, resulting in a significantly more compact vertical NOR string.

FIG. 5A shows a vertical NOR string of active column 531 according to an embodiment of the present invention, a global NOR bit line 514-1 (GBL ₁ ), a global source line 507 (GSL ₁ ), and a common body bias source 506 ( It is sectional drawing of the ZZ plane which shows the connection with V _bb). As shown in FIG. 5A, the bit line access selection transistor 511 connects the GBL ₁ to the local bit line 554, and the embedded contact 556 connects the P-body region on the active strip to the body bias source 506 (V) in the substrate. _{Connect to bb} ) arbitrarily. The bit line access selection transistor 511 is formed on the active row 531 of FIG. 5A. However, as an alternative, the bit line access selection transistor 511 may be formed at the bottom of the active row 531 or on the substrate 505 (not shown in FIG. 5A). In FIG. 5A, the bit line access selection transistor 511 can be formed, for example, with the access selection word line 585 on independent islands of the N + / P− / N + doped polysilicon stack. When a voltage large enough to select the word line 585 is applied, the P-channel is inverted, thereby connecting the _{local bit line 554 to GBL 1.} The word line 585 extends along the same direction (ie, the Y direction) as the word line 523p, which functions as a control gate for the TFT of the vertical NOR string. The word line 585 may be formed separately from the word line 523p. In one embodiment, the GBL ₁ extends horizontally along the X direction (ie, perpendicular to the direction of the word line) and the bit line access selection transistor 511 has a number of verticals _{served by the GBL 1.} It provides access to the local bit line 554, which is the only local bit line of the NOR string. Thousands of global bit lines are used in a multi-gate NOR string array to improve read and program operation efficiency, in parallel with the local bit lines of thousands of vertical NOR strings accessed by word line 585. You may access it. In FIG. 5A, the local source line 555 is connected via contact 557 to the _{global source line 513-1 (GSL 1} ), which can be decoded, for example, by decoding the circuit of substrate 505. Alternatively, as described above, the virtual power supply voltage V _ss is supplied to the local source line 555, and the parasitic capacitor 560 (that is, the parasitic capacitor C) of the local source line 555 is temporarily precharged via the TFT 570. By doing so, the global source line may be removed.

The support circuits formed on the substrate 505 include, among others, address encoders, address decoders, sense amplifiers, input / output drivers, shift registers, latches, reference cells, power lines, bias and reference voltage generators, inverters, NAND, NORs, etc. Exclusive OR and other logic gates, other memory elements, sequencers, and state machines may be included. The multi-gate NOR string array can be configured as multiple blocks of the circuit, each block having a plurality of multi-gate NOR string arrays.

Figure 6A, as described above in connection with FIG. 4C, TFT685 _(T L) of the vertical NOR string 451a of the vertical NOR string pairs 491, and the vertical NOR string 451b TFT684 _{(T R)} of the X-Y plane showing the It is a cross-sectional view. As shown in FIG. 6, TFTs 684 and 685 share an N + local source region 655 and an N + local drain or bit line region 654, both of which extend in the Z direction to form elongated pillars. (The N + local source area 655 corresponds to the local source line 455 of FIG. 4A, and the N + local drain area 654 corresponds to the local bit line 454 of FIG. 4A). In this embodiment, the P-doped channel regions 656L and 656R form a pair of active strings between the local source pillar 655 and the local drain pillar 654, isolated from each other by an insulating region 640 and extending along the Z direction. Form. A charge trap layer 634 is formed between the word lines 623p-L (WL _31-0 ) and 623p-R (WL _31-1 ) and outside the channel regions 656L, 656R. The charge trap layer 634 is, for example, a thin layer of a tunnel dielectric (eg, silicon dioxide) followed by a thin layer or insulation of a charge trap material such as silicon nitride or conductive nanodots embedded in a non-conductive dielectric material. Can be a gate dielectric material for a transistor consisting of a floating gate, a layer of blocking dielectric such as ONO (oxide-nitride-oxide triple layer), a high dielectric constant film such as aluminum oxide or hafnium oxide, Or capped by any combination of such dielectrics. The source-drain conductive section is controlled by word lines 623p-L and 623p-R, which form a control gate on the outside of the charge trap layer 634, respectively. TFT 684 _{(T R)} when the program or read, by maintaining the word line 623p-L in a suitable inhibit voltage, turning off the TFT685 _{(T L).} Similarly, TFT685 _{(T L)} when the program or read, turn off TFT684 the _{(T R)} by maintaining the word line 623p-R the appropriate inhibit voltage.

In the embodiment shown in FIG. 6A, the word lines 623p-L and 623p-R are formed into contour shapes that increase the tunnel efficiency to TFTs 684 and 685 during programming and decrease the reverse tunneling efficiency during erasing. ing. Specifically, as is known to those skilled in the art, the curved portion 675 of the channel region 656R amplifies the electric field at the interface between the polysilicon of the active channel and the tunnel dielectric in the program, and in addition, Reduces the electric field at the interface between the word line and the blocking dielectric during erasing. This feature is particularly useful when storing 2 bits or more per TFT transistor in a multi-level cell (MLC) configuration. By using this technique, each TFT can store 2 bits, 3 bits, 4 bits, or more. In fact, TFTs 684 and 685 can be used as analog storage TFTs with a continuum of storage states. Following the program sequence (discussed below), the electrons are trapped in the charge trap layer 634, as schematically indicated by the dashed line 680. In FIG. 6A, the global bit lines 614-1 and 614-2 extend perpendicular to the word lines 623p-R and 623p-L and correspond to the bit lines 414-1 and 414-4 in FIG. 4C, respectively. It is provided either above or below the vertical NOR string. As described above in connection with FIG. 2, the word line extends along the X direction over the entire length of the memory block (memory structure) 100, and the global bit line extends along the Y direction of the memory block (memory structure). Body) extends over a width of 100. Importantly, in FIG. 6A, the word line 623p-R is shared by the two vertical NOR strings TFT684 and 683 on either side of the word line 623p-R. Therefore, to allow the TFTs 684 and 683 to be read or programmed independently of each other, the global bit line 614-1 (GBL ₁ ) is placed in the local drain or bit line region 657-1 (“odd address”). Connect and connect the global bit line 614-2 (GBL ₂ ) to the local drain or bit line area 657-2 (“even address”). To achieve this effect, the connections along the global bit lines 614-1 and 614-2 are staggered, with each global bit line connecting every other pair of vertical NOR strings along the X direction. ..

Similarly, a global source line (not shown in FIG. 6A) located at the bottom or top of a multi-gate NOR string array extends parallel to the global bit line and is perpendicular to even or odd addresses. Connect to the local source line of the NOR string pair. Alternatively, the parasitic capacitor C (i.e., capacitor 660) To temporarily precharged to the virtual power supply voltage V _ss, it is not necessary to provide a global source line, thereby simplifying the complexity of decoding schemes and processes Will be done.

FIG. 6A shows only one of several embodiments in which vertical NOR string pairs can be provided as stacked word lines. For example, the curved portion 675 of the channel region 656R can be further increased. Conversely, as shown in the embodiment of FIG. 6B, the curved portion 675 may be completely removed (ie, straightened). In the embodiment of FIG. 6B, the spacing of the insulation areas 640 of FIG. 6A can be reduced or completely eliminated by integrating the channel areas 656L and 656R into a single area 656 (L + R), thereby it is possible to achieve greater area efficiency without sacrificing the dual-channel configuration (e.g., present on the facing surfaces of the same active strip TFT685 (T _L) and 684 (T _R)). In the embodiments of FIGS. 6A, 6B, the vertical NOR strings sharing the word line may be staggered relative to each other in order to bring them closer to each other in order to reduce the effective footprint of each vertical NOR string (FIG. 6A). Not shown). 6A and 6B show a direct connection via a contact between the global bit line 614-1 and the N + doped local drain bit line pillar 654 (LBL-1), where such a connection is a bit. It can also be achieved using a line access selection transistor (eg, not shown in the bit line access selection transistors 511, 6A and 6B of FIG. 5A).

In the embodiments of FIGS. 6A and 6B, the dielectric insulation between the N + dope local drain region 654 and the adjacent local N + dope source region 658 (corresponding to the insulation region 436 of FIG. 4A) is, for example, a word line. It can also be established by defining 623p-R and 623p-L to be less than the thickness of the two back-to-back charge trap layers so that the charge trap layers integrate with each other during the deposition process. By integrating the deposited charge trap layers in this way, the desired dielectric insulation is formed. Alternatively, the insulation between adjacent active strings uses a high aspect ratio etching of N + polysilicon to insulate the N + pillar 658 of one string from the N + pillar 654 of the adjacent string gap 676 (air gap). Or by forming a dielectric filling) (ie, by forming the gap 436 shown in FIG. 4A).

Comparing the vertical NAND strings of the prior art with the vertical NOR strings of the present invention, they both use thin film transistors with similar wordline stacks as control gates, but with different orientations of their transistors. In the conventional NAND strings, each of the vertical active strips may have 32, 48, or more TFTs connected in series. In contrast, each active row forming the vertical NOR string of the present invention may have one or two sets of TFTs (32, 48 or more) connected in parallel. .. In the conventional NAND strings, the word lines in some embodiments are generally arranged so as to surround the active strip. In some embodiments of the vertical NOR string of the present invention, left and right word lines individually designated for each active strip are used, thereby, as shown in FIGS. 4C, 6A, and 6B. Twice (ie, a pair) of storage density is achieved for each global bit line. The vertical NOR string of the present invention does not have the problem of program interference or read interference, and does not have the problem of delay of the conventional NAND string. Therefore, the vertical NOR string can be provided with a larger number of TFTs than the vertical NAND string. However, the vertical NOR string is more susceptible to subthreshold or other leaks between the long vertical source and drain diffuser (eg, local source region 455 and local drain region 454 shown in FIG. 4A).

Two additional embodiments of the vertical NOR string of the present invention are shown in FIGS. 6C and 6D. In these embodiments, all wordlines in each wordline stack are arranged so as to surround the vertical active strip.

In FIG. 6C, a vertical NOR string is formed in a space formed by etching through a stack of metal word wires and a dielectric insulating layer between the word wires. The manufacturing process flow is similar to the prior art vertical NAND strings, except that the transistors in the vertical NOR strings are provided in parallel with each other rather than in series within the vertical NAND strings. The formation of transistors in the vertical NOR string is facilitated by N + doped vertical pillars extending throughout the depth of space, with shared local source line 655 (LSL) and shared local bits for all TFTs along the vertical NOR string. Line 654 (drain) (LBL) is provided with a non-doped or low-concentration doped channel region 656 adjacent to both. The charge trap region 634, which is the charge storage element, is arranged between the channel 656 and the word line stack 623p, whereby 2, 4, 8, ..., 32, along the vertical active strip, A stack of 64 or more TFTs (eg, device 685 (T ₁₀ )) is formed. In the embodiment of FIG. 6C, the wordline stack 623p extends in the Y direction and the individual horizontal strips (WL _31-0 ), (WL _31-1 ) are isolated from each other by an air gap or dielectric insulation 610. There is. The global bit line 614 (GBL) and the global source line 615 (GSL) extend horizontally in a row along the X direction perpendicular to the word line. Each of the global bit lines 614 is a local bit line along a row of vertical strips via an access selection transistor (511 in FIG. 5A, not shown here) that can be located either below or above the memory array. Access pillar 654 (LBL). Similarly, each global source line 615 accesses the local source line pillar along that line. The structures shown in FIGS. 6A and 6B allow a pair of vertical NOR strings to fit into substantially the same region occupied by a single vertical NOR string in the embodiment of FIG. 6C, but each shown in FIG. 6C. Since each TFT in the vertical NOR string has two parallel conductive channels (ie, channel regions 656a and 656b), more charge can be accumulated and the read current can be increased or doubled. This makes it possible to accumulate more bits in each TFT.

FIG. 6D shows a more compact vertical NOR string with wraparound word lines according to an embodiment of the invention. As shown in FIG. 6D, the vertical NOR strings are staggered so that they are close to each other so that the word line stack 623p (WL _31-0 ) can be shared by more vertical NOR strings. This staggered arrangement is made possible by the use of parasitic capacitors C (ie, capacitors 660) on the local source line pillar 655 (LSL). As described below, by precharging the capacitor 660 for temporarily holding the virtual voltage V _ss during read and program operations, hardwired global source line (e.g., GSL615 in FIG. 6C) is not required. The vertical NOR strings of FIGS. 6C and 6D themselves do not provide greater area efficiency compared to prior art vertical NAND strings (eg, NAND strings of FIG. 1C), but such vertical NOR strings do. Achieve a string length that is significantly longer than the string. For example, the vertical NOR strings of the present invention can sufficiently support 128 to 512 or more TFT length strings in each stack, but the length of such strings is. Given the significant limitations associated with series-connected TFT strings, it is completely impractical for vertical NAND strings.

An alternative embodiment having long global bit lines divided into short segmented bit lines to facilitate high speed access to the sense amplifier.

In the sense amplifier and other support circuits provided on the semiconductor substrate, the present inventor uses a global interconnect conductor provided above or below the memory array to wire the global bit line to the vertical local bit line. It was noted that when connected to (for example, the global bit line GBL ₁ connected to the vertical local bit line 554 in FIG. 5A), the length of the wiring becomes long, so that a large RC delay occurs. In addition, the area of the silicon substrate beneath the memory array (rather than using the precious silicon area near the memory array) is used for sense amplifiers, decoders, voltage sources, and other memory operations. It is highly desirable to form a large number of support circuits, such as circuits.

According to one embodiment of the invention, a conductor that would otherwise be used as a global bit line is segmented into a number of relatively short line segments (eg, each line segment is one of the global bit lines. Has a length of / 100 or less). Each line segment provides a horizontal line connector for connecting groups of adjacent vertical local bit lines to each other. It is preferred that the bit line segment resides between the substrate and the memory array and is isolated from the substrate and the memory array. The bit line segment facilitates the connection between adjacent vertical local bit lines in the group and dedicated sense amplifiers and other support circuitry formed within the semiconductor substrate beneath the array of vertical NOR strings. In this detailed description, the term "bit line segment" refers to a set of local bit lines connected by a line connector.

Similarly, a conductor that would otherwise be used as a global source line may be segmented into a number of relatively short line segments, in which case each segment groups adjacent local vertical source lines together. Provides a horizontal line connector for connection. The line connector and its associated local vertical source line form a common source line with a parasitic capacitance that is multiple times the parasitic capacitance of a single local vertical source line. The common source line connector can be connected to the global source line by means of a segment selection transistor, preferably at the top of the array. In this detailed description, the term "source line segment" refers to a set of local source lines connected to each other by a line connector. When a source line segment is further subdivided into smaller groups of connected local source lines, each of these smaller groups is referred to as a "source line subsegment".

In another alternative embodiment of the invention, there is no global source line routed above or below the memory stack, but each source line segment of an adjacent local vertical source line and its associated group is a local common source. Acts as an area. In this configuration, in order to transfer the virtual ground voltage (V _ss) from the substrate, at least one pre-charge transistor is provided in each active column connected to the source line segment. In a 64-layer vertical NOR memory array, each local source line has ^{a parasitic capacitance of about 1 femtofarad (ie, 1.0 × 10-15} farad), which in some cases is a charge-sharing read operation. The charge may be too small to maintain a virtual ground voltage (V _{ss) inside.} By combining the capacitances of a group of 64 local source lines, for example, their total precharged capacitance C increases to about 64 femtofarads, which is more than sufficient for charge sharing read operation.

3D, 3E, 3F, and 3G achieve high-speed read access and utilize the silicon substrate beneath the array to form support circuits such as sense amplifiers, decoders, registers, and voltage sources. An embodiment of the present invention is shown. As shown in FIG. 3D, the vertical NOR string 380 represents a three-dimensional array of non-volatile storage TFTs, in which each TFT shares a local source line 375 and a local bit line 374, according to an embodiment of the invention. The local bit line 374 and the local source line 375 are separated from each other by a body area 356 that provides a channel area for the TFT in the vertical NOR string 380. A storage element is formed at the intersection between the channel region 356 and each horizontal word line 323p. p is the wordline index in the wordline stack. In this example, p can take any value in the range 0-31. The word line extends along the Y direction. In this embodiment, the source line supply voltage _{V ss} through the source select transistor (SLS) 371, a substrate 310, a global source line extending top of the vertical active column _(GSL 1) 313 via a local vertical source It is supplied to line 375. Note that the body region 356, which provides the transistor channels in the active row, is connected to the _{substrate bias voltage V bb at terminal 331.} However, electrical connection of the P-doped channel 556 can also be achieved from the top of the vertical NOR string (see description below for FIG. 5B).

In FIG. 3D, adjacent active columns (eg, active columns of vertical NOR string 380) are grouped, and the local bit lines of each group of active columns are associated bit line segments (eg, directly below the memory array). , Bit line segments MSBL ₁ and MSBL ₂ ). The bit wire segment MSBL ₁ provides a low resistance connector 373, which can be accomplished, for example, with a narrow strip of N + doped polysilicon, Silicide, or refractory metal. Groups of adjacent local vertical bit lines, 374-1, 374-2, ..., 374-n, connected by the horizontal bit line segment MSBL _1, are in the X direction orthogonal to the _{word lines WL 0 to WL 31.} It is provided in the longitudinal direction along the above. The bit line segments MSBL ₁ , MSBL ₂ , ... Are formed on a dielectric insulator 392 and include vertical local bit lines from 1 (ie, without segmentation) to 16, 64, 256, 512 or more. As such, it may be relatively short. Each bit line segment is a region bit line segment including _{a plurality of MSBL type 1} bit line segments via a segment selection transistor (for example, a segment selection transistor 586-1, ..., 586-n implemented as a thin film transistor). It can be connected to a longer horizontal conductor forming SGBL ₁ , SGBL _2. By forming the horizontal region bit line segment SGBL ₁ on the insulating layer 393 above the substrate 310, a logic element such as a sense amplifier can be formed in the substrate directly below the region bit line segment. The region segment is preferably long enough so that the sense amplifiers, decoders, registers, voltage sources, and other circuits formed within the substrate can be physically fitted beneath the region bit line segment.

In a dual density configuration as shown in FIG. 6E, each word line serves both active columns on either side of it. In this configuration, two adjacent local bit lines on either side of the word line are associated with the bit line segments MSBL ₁ (L), MSBL ₁ (R), and the sense amplifier and decoder of each segment, respectively. They are close to each other and separated in parallel. This spacing is also the spacing along the Y direction between adjacent vertically active columns in the memory array. It is not possible to provide a dedicated sense amplifier and other support circuits for each of the bit line segments laid out along the Y direction. In such a configuration, each sense amplifier can serve 1, 2, 4, 8, or more adjacent bit line segments via a segment selection decoder within the substrate. In the X direction, a 1 terabit 3D vertical NOR flash memory chip can have hundreds of region bit line segments instead of long global bit lines, which can significantly reduce bit line RC delays. it can.

FIG. 3E shows a modified example of the circuit architecture of the embodiment of FIG. 3D. In the example of FIG. 3E, the groups of adjacent vertical local source lines 375-1, 375-2, ... Are source line segments MSSL ₁ , MSSL ₂ , which extend along the same X direction as the bit line segment.・ ・ Connected by. This grouping of local source lines connected by a source line segments, the source line necessary to provide a source voltage V _ss to each of the vertical NOR string select transistor SLS 1, _SLS 2 associated with the source line _segment, -・ ・ Reduce the number of. Also, as described above, connecting groups of vertical local source lines with source line segments directly contributes to the increase in cumulative parasitic capacitance (C). The vertical local source line connected by the horizontal source line segment is also closely associated with the vertical local bit line connected by the corresponding horizontal bit line segment. However, the number of vertical local bit lines associated with the bit line segment does not have to be the same as the number of vertical local source lines associated with the source line segment. As a result, the bit line segment is associated with, for example, a plurality of source line segments. For example, the bit line segment MSBL1 can be associated with 256 local vertical bit lines 374-1, 374-2, etc., each of which has 32 local source lines 375-1, 375-5. It can be associated with eight source line segments that can only be associated with 2, ... Each source line segment can be individually applied with its voltage V _ss via its dedicated source line selection transistor (eg, source line selection transistor SLS _1).

FIG. 3F shows a modified example of the circuit architecture of the embodiment of FIG. 3E. In the example of FIG. 3F, neither the global source line (for example, the global source line 313) nor the source line selection transistor (for example, the source selection transistor SLS ₁ ) is provided. In FIG. 3F, the local vertical source line associated with each source line segment is precharged to the source voltage V _ss via a precharge transistor (eg, precharge transistor 370), and the word line WL _CHG is the source line segment. It is turned on by a voltage pulse sufficient to transfer the _{voltage Vbl} supplied from the circuitry within the substrate 310 via the local vertical bit line associated with. The number of vertical local bit lines associated with the source line segment is an optimized number during the parasitic capacitance of the source line segment (C) to maximize, to hold the virtual ground voltage V _ss during the readout of the cell Keeps the background leakage current associated with all "off" transistors in the vertical NOR string associated with the source line segment low enough so that it does not interfere with the reading of the accessed storage transistors in the source line segment. Balanced for need. Within the bit line segment, any unselected source line _{subsegment is precharged to equalize its V ss} voltage to its associated bit line segment voltage V bl to eliminate its background leak current. be able to.

FIG. 3G is a modification of the circuit architecture according to the embodiment of FIG. 3E. In the example of FIG. 3G, the connectivity between the memory array and the substrate combines the region bit line segments SGBL ₁ , SGBL ₂ , ... With the respective local bit line segments MSBL ₁ , MSBL ₂ , .... Each bit wire segment connected to the segment selection transistors 315-1, 315-2, ..., Via each via or conductor (eg, an embedded contact) is in the substrate directly below the bit wire segment. Is further simplified by. In this configuration, instead of providing the thin film transistor on the silicon substrate (for example, the segment selection transistor 586-1, ..., 586-n in FIG. 3F), the segment selection transistor is a high efficiency transistor in the single crystal substrate 310. Provided by. This configuration provides robust access to sense amplifiers, decoders, registers, voltage sources, and other circuits associated with the bit line segment. The segment selection thin film transistor made possible by abolishing the global source line selection transistors SLS ₁ , SLS ₂ , ... made possible by the precharge path and arranging each bit line segment near the segment circuit in the substrate. The abolition of 586-1, ..., 586n (or selective transistors constructed of expensive selective epitaxy silicon, as is commonly done in conventional 3D NAND arrays) significantly increases the process integration flow. It can be simplified.

3H and 3I show another embodiment similar to the embodiment of FIG. 3G. In the examples of FIGS. 3H and 3I, _{the voltage on the connectors MSSL 1} and MSSL _{2 of the} source line segment, and thus the voltage on the local vertical source line 375 (LSL) in each source line segment, is also the storage active column of the memory array. It is supplied from the substrate 310 via an active row 381 (“charge row”) that mimics any configuration of (eg, active row 381) but is not used for memory storage. In other words, the charge column 381 is _{dedicated to charging the local source lines in the source line segments MSSL 1} and MSSL ₂ (in other embodiments, each charge column is only a single source line segment. Serve against). As shown in FIG. 3H, the charge sequence 381 is formed, for example, in the opening BLO between the _{adjacent bit line segments SEG 1} and SEG _2. Through a read operation (optionally, any program, program prohibition, or erase operation), the charge sequence 381 delivers and holds the required voltage on the vertical local source lines in the _{source line segments MSSL 1} and MSSL _{2 (source).} The line segments MSSL ₁ and MSSL ₂ are both served by charge row 381). In this regard, the charge column 381, for example, eliminating the need for global source line GSL1313 in FIG. 3E, eliminating the need for the associated source line segment select transistors SLS _1. It also eliminates the need for a precharge transistor 370 in the memory stack, which requires an extra wordline plane WL _{chg, as shown, for example, in the embodiment of FIG. 3G.}

In the segmented structure of FIGS. 3H and 3I, in the read operation of the storage transistor on an arbitrary memory surface, _{the source voltage on each local source line of the source line segments MSSL 1} and MSSL ₂ is the vertical source line 375 of the charge column 381 ( _{V ss} (e.g. from LSL) via connection VSL, it is applied at 0 volts). The voltage V _ss is a decoded select transistor (shown as 315X in FIG. 3H), a bit line mini-segment SSV _ss , a vertical local bit line 374 (LBL), a pass transistor 371, and a vertical local source in a silicon substrate 310. Supplied from the substrate 310 via wire 375 (LSL) (path transistor 371 is _{activated by word wire WL 31} during the read operation and is held in a conductive or "on" state). _{Source voltages applied to the source line segments MSSL 1} and MSSL ₂ during any program, program prohibition, or erase operation can be provided as well. The selection transistor 315X in the silicon substrate 310 can be a high voltage transistor capable of withstanding the high voltage applied to the local bit line 374 (LBL) during the erasing operation.

FIG. 3I shows the upper XY plan view of the embodiment of FIG. 3H in more detail, where each vertical local source line in the _{source segment MSSL 1 has a voltage V ss} or V _{bl supplied through the active column 381.} Is held in. In FIG. 3I, the memory array has a layout similar to that shown in the embodiment of FIG. 6B. As shown in FIG. 3I, _{between the bit line segments SEG 1} and SEG ₂ , each row extending along the X direction has two charge columns and a predetermined number (for example, 2048) laid out along the Y direction. An array of charge columns with such rows of is provided. The array of charge trains is provided between two discontinuities or openings in the bit line (labeled "BLO" in FIG. 3I). In one row of the active column between the two dashed lines, the source line connector extending along the X direction traverses the charge column on the right side along the source line segment MSSL1 of the bit line segment SEG1 (ie, along the upper dashed line). Connect to the local source line (every other active column). The same right-charged column is connected to the local source line of the active column of the source line segment MSSL _{2 in the bit line segment SEG 2.} The source voltage is supplied from the silicon substrate to the bit line connector and to the local bit line in the active column on the right. The word line labeled "WL ₃₁ " activates the pass transistor in the charge train and transfers the source voltage to the local source line labeled VSL, which transfers the source voltage to the source line. It is supplied to the local source lines of segments MSSL ₁ and MSSL ₂ (this circuit configuration is shown in the circuit of FIG. 3H). The charge column to the left of this charge column row between the dashed lines is similarly connected to another source line segment pair along the lower dashed line.

In a 3D vertical NOR string memory array with multiple wordline planes, the local wordlines of all planes in the stack are placed in a stepped step WLSTC at the end of the array (see, eg, FIGS. 3I and 6G). ). One or more dedicated for each memory surface to activate the charge sequence (eg, charge sequence 381) for each pair of adjacent bit line segments (eg, bit line segments SEG1 and SEG2 in FIG. 3H). A global word line (eg, in FIG. 3I, labeled "GWL _CHG ") may be required. As shown in the example of FIG. 3I (see insert), _{all global word lines labeled GWL CHG are connected to the local word line WL 31} corresponding to the active column 381 and are connected to the bit line segments SEG ₁ and SEG. Skip all other word lines in _2. In contrast, each global word line for a storage transistor in a memory array (eg, GWL) has a large number of local word lines associated with the _{bit line segments SEG 1} and SEG _{2, skipping the word line in charge sequence 381.} Hard wire is connected to. The global word lines of charge rows 381 on different memory planes ( _{all labeled "GWL CHG} " in the insert of FIG. 3I) are shorted together in a peripheral circuit (not shown) thereby. , Activate any (or all) of the pass transistors in the charge sequence 381 associated with the word lines WL _{0- WL 31.} In one embodiment, all charge row pass transistors in the block of connected source line segments are activated together when the chip is powered on. However, any source line segment or source line segment pair in the block switches off its associated segment selection transistor (eg, segment selection transistor 315X) to its corresponding charge sequence isolated from the silicon substrate. By having it, it can be deselected.

The embodiments of FIGS. 3H and 3I eliminate the need for a floating power supply precharge sequence as implemented in the embodiment of FIG. 3G. By eliminating the need for a precharge sequence, the source voltage can be set before the start of the read operation and then _{kept stable at the voltage V ss} , which is required for the floating source precharge pulse. Since no overhead time is required, the read operation can be speeded up. In addition, the charge sequence 381 holds the local source line of the source line segment MSSL1 at the voltage V _ss throughout the read operation (ie, not just the momentary precharge pulse), so that the steady state provided via the connection VSL The current compensates for any source-drain leak that could impair read detection of the addressed storage transistor if in excess.

In summary, the charge sequence 381 acts as a local vertical connector for transferring the _{voltage V ss} or V _{bl from the silicon substrate to the local source line within the vertical NOR memory string. Any voltage V ss} or V _bl on the vertical local source line of the charge train can be transferred via a pass transistor (eg, pass transistor 371) to its associated local bit line, which is a local bit line. It may be charged directly from the _{bit line connector MSBL 1} which may be connected to a voltage source in the silicon substrate via the segment selection decoder 315-1.

In a three-dimensional vertical NOR memory stack with 64 or 128 memory planes, the height of the stack is also the length of the charge row 381, which can exceed 5 micrometers (microns), which is the charge row 381 ( It is a fairly long distance for the vertical local source line 375 (LSL) or local bit line 374 (LBL) of FIG. 3H). Corresponding N + dope polysilicon pillars 455 and 454 (see FIG. 4A; also shown in FIG. 6E as 655 (N +) LSL-1 and 654 (N +) LBL-1 and are sometimes referred to as pylon. ) Excessive electrical resistance (R: ohm) may result in RC delays that primarily adversely affect the read path. The resistance R of the pillar can be reduced by an order of magnitude or more by providing a low resistance metal material in the core of the pillar. For example, in the following detailed description, FIG. 4A-1 shows the metal core 420 (M) and FIG. 7D-1 shows the metal core 720 (M).

FIG. 5B shows a body region 556 (providing a P-channel material) and an active row, for example, via a conductive pillar 591 formed in a dielectric layer 592 from P + polysilicon, according to an embodiment of the invention. FIG. 5 is a cross-sectional view of a ZZ plane showing a connection between a conductor 590 provided above 581 and extending parallel to the word line. The conductor 590 may also be formed from a highly concentrated polysilicon, silicide, or metal conductor. _{In this configuration, the body bias voltage (V bb} ) 594 is conducted through the via 593 provided in the opening formed through the dielectric insulator 509 from the substrate 505 in order to facilitate the block erasing operation. It can be provided to 590.

FIG. 6E shows that the body bias voltage is provided via conductors 690-1 and 690-2 (“body bias conductor”). The body bias voltage is shared between body regions in adjacent rows of the active column using the layout of the embodiment shown in FIG. 6B. In this configuration, the word line 592 (ie, the word line 623p-L) extends consistently with the body bias conductor 690-1. The block size of the erasing operation is limited to the left active row and the right active row of each body bias conductor (eg, conductor 690-1). A larger erase block can be configured, for example, by having a cluster of body bias conductors coupled to match the number of word lines addressing the bit line segment. The on-board decoder supplies an appropriate body bias voltage (eg, erasure voltage) to one or more selected erasure blocks.

With reference to FIG. 5B again, the active row (eg, active row 581) is formed, and then the dielectric layer 592 is formed on the active row. Subsequently, the via hole is anisotropically etched from the top of the dielectric layer 592 to the top of the body region 556. Next, a layer of P + doped polysilicon is deposited on the dielectric layer 592 to fill the via holes to form conductive pillars (for example, conductive pillars 591). The layer of P + doped polysilicon is then patterned and etched to form a conductor (eg, conductor 590), which is connected via a via 593 to a voltage source 594 that supplies the _{body bias voltage V bb.} The body bias voltage V _bb is a positive high voltage applied during erasing or a low negative substrate bias voltage applied during readout to increase the TFT threshold voltage or reduce its subthreshold leakage. Can be. FIG. 6E is a top view showing the formed P + doped polysilicon features 690-1 and 690-2.

In the embodiment shown in FIG. 5B, the conductor 590 is provided above the body region 556. However, in other embodiments, the conductor 590 may be provided directly below the body region 556 so that it contacts the body region 556 from below. In fact, it may be advantageous to provide the body bias voltage from both above and below the body region 556. When providing the body bias voltage from below the body region 556, a conductor similar to conductor 590 may be provided directly from the substrate via the interlayer of the interlayer dielectric, similar to that shown in FIG. 5A.

Operating modes of segmented local bit lines and segmented local source line arrays

In a memory stack of, for example, 64 planes of word lines having bitline segments, as described above for embodiments of the present invention, storage on any plane (eg, the 25th plane) associated with the selected bitline segment. When reading a transistor, all wordlines in all planes associated with the selected bitline segment have their "off" threshold, except for wordlines on the selected plane that address the selected storage transistor. It is held in voltage. As the ward line voltage rises, the erased (ie, conducting or "on") storage transistor _{precharges its bit line voltage (V bl} ) to its virtual ground potential (V _ss ). Discharge to the local source line (and its associated source line segment; if applicable). The discharge rate of the bit line voltage V _bl is sensed by the sense amplifier of the bit line segment. Addressed by other storage transistors on the selected plane (ie, the 25th plane in this example) associated with other bitline segments along the Y direction that share the same wordline, or by different wordlines. Other storage transistors associated with other bitline segments along the specified X direction can be read out simultaneously because each bitline segment has its own sense amplifier. In the read operation, first, the virtual source voltage is precharged (or the virtual power supply voltage may be raised to about 1 V) by setting the local bit line to 0 V during the precharge operation. After precharging the local bit line sense amplifier voltage (e.g., about 0.1V~0.5V voltage higher than the power supply voltage) is charged, the substrate voltage _{V bb} (e.g., about 0V~ about -2 V) The word line WL is set to be about 1V to 3V higher than the erasing threshold voltage.

In embodiments of storage transistors on either side of each word line (eg, embodiments of FIGS. 6A and 6E), care is taken that only one of the two storage transistors conducts at any time during the read operation. Must. This is achieved by providing separate bitline segments that extend parallel to each other, as described above, but each is served by its own sense amplifier, decoder, voltage source, and other support circuitry. .. As shown in FIG. 6E, the bit line segments are MSBL ₁ (L) of the left storage transistor and MSBL ₁ (R) of the right storage transistor.

To program the storage transistor, all word lines on all planes except the selected plane (ie, the 25th plane in this example) are set to ground potential, while selected (ie, 25). The word line addressing the storage transistor (on the third plane) starts at, for example, an incremental voltage step (eg, about 8 volts) and steps the voltage until the desired program voltage is confirmed to have been reached by the read operation. To increase the voltage and apply a voltage pulse) to raise the voltage to an appropriate program voltage. During program operation, the voltage on the bit line segment is held at ground potential as well as the associated source line segment.

To forbid further programming while continuing to program the storage transistors on the selected plane associated with other bit line segments that share the same word line, the bit line segment and the source line segment are of continuous program pulses. In the read verification cycle between, the program prohibition voltage (for example, about 1/3 to 1/2 of the program voltage) is raised until the end of the program sequence. All program and program prohibition voltages to the local bit line and the local source line within the bit line or source line segment are provided only through the bit line segment (due to the source line precharge operation). Similar to the read operation, the storage transistor associated with the other bit line segment along the Y direction (ie, sharing the same word line with the selected storage transistor), and the other bit line segment along the X direction. Storage transistors associated with (ie, associated with different wordlines) can be programmed or program-banned at the same time.

The erase operation holds all the word lines of the storage transistor associated with the bit line segment, source line segment, or block to be erased at 0V and the virgin storage transistor (ie, never programmed or erased). _{This is achieved by increasing the body bias voltage (V bb} ) of the storage transistor) to about 12 V and increasing the body bias voltage (V _bb ) of the high cycle number storage transistor to 20 V or more. The floating N + vertical local source lines and N + vertical local bit lines in the erase block follow the positive voltage applied to their p-body region, so that all sense amplifiers associated with the bit line segment have their bit lines. Alternatively, it may be isolated from the bit line segment.

It is possible to read, program, program ban, and erase using other conditions well known to those of skill in the art.

Low latency split local line and global word line

Bit line segmentation in the embodiments of the present invention helps to significantly reduce RC delays in conventional global bit lines of conventional 3D-NAND and 3D-NOR memory arrays. Another major source of long read latency is usually a long, high capacity local word line conductor that extends orthogonally to the global bit line over almost half or the entire width of the chip. For this reason, the 3D vertical NOR flash memory array of US Pat. No. 2017/0092371A1 requires at least one layer of local word line conductors for each memory surface, similar to conventional 3D-NAND flash memory arrays. To do. In 64-sided NAND or NOR memory arrays, these word line conductors consist of high stepped steps. Since local word lines provide high voltage during the program, their decoders require high voltage transistor circuits that can occupy a significant silicon area of each such stepped step.

To reduce the overhead costs associated with them, word lines are generally formed very long, which results in high RC delays and poor read latency (eg, in the range of a few microseconds). Inside). In a conventional 3D-NAND memory array, the latency of a long word line is substantially hidden because the global bit line is also long and the rising or falling is slow. In the bit line segment of the present invention, the bit line response time can be very short (eg, within the range of 100 nanoseconds), so the RC delay of a long word line is a limiting factor for high speed read access. According to one embodiment of the invention, as a partial solution, the 3D-NOR memory chip is lengthened and narrowed (ie, shortened along the direction of the word line and lengthened along the direction of the bit line segment. ). Such a design does not significantly reduce the silicon region for forming the wordline decoder, but significantly reduces the wordline length and RC delay without significantly increasing the RC delay along the bitline segment.

According to another embodiment of the invention, the wordline delay is further reduced by dividing the memory array into more blocks with shorter wordlines and forming each block into repeated stepped steps. be able to. Dividing the memory array by doubling the number of stepped steps, their wordline decoders reduce the RC delay by a factor of four.

Another major cause of long read latency is the large RC delay of the global word line (GWL) extending in the X direction over the length of the memory array above the stepped steps along the sides of the memory array. FIG. 6F shows an embodiment of a global word line for connecting local word lines on a plane (ie, a stepped step), which is related to the bit line segmentation scheme of the present invention. In FIG. 6F, only local word lines in an XY plane through stepped steps along the sides of the memory array, global word lines on stepped steps, and their interconnects are shown. All other details (eg, P-channel material layer and charge trap layer) are omitted for clarity. _{As shown in FIG. 6F, the word lines WL 0} , WL ₁ , ... Of the memory array (for example, the memory array corresponding to the embodiment shown in FIG. 6E) extend along the Y direction. The global word lines GWL ₀ , GWL ₁ , ... Extend along the X direction above the stepped steps. The global word line connects the word lines on each side of the memory array to their respective decoders, voltage sources, and other support circuits within the board 605. For example, when applying bit line segmentation to the architectures of FIGS. 3D, 3E, 3F and 3G, each stepped step has a maximum of n matching the number n of local word lines in the bit line segment. Accommodates the global ward line of. In the embodiment of FIG. 6F, for example, each bit line segment contains 128 bit lines, and each storage transistor in each step is selected by the corresponding word line. Therefore, there are 128 word lines in each step of the bit line segment. Therefore, each global word line is connected at every 128th word line. For example, on each plane, the global word line GWL ₀ is connected to the word lines WL-0, WL-127, ... Via via VIA ₀ , VIA ₁₂₇ , ..., And the GWL ₁ is a word. The lines WL-1, WL-129, ... Are connected to the substrate decoder and the voltage source in the substrate 605 _{via via VIA 1} , VIA _{128, ....} With this configuration, by activating the common global word line and its dedicated sense amplifier decoder, 128 sets of storage transistors on each plane can be read out at the same time. For example, the storage transistors associated with the word lines WL _i , WL _{i + 128} , ... (Usually WL _{i + 128k} ; k = 0, 1, ...) Can be simultaneously read or read by activating the global word line GWLi. It can be programmed, while all other global word lines in the same step and other steps may be at ground potential (ie, turn off all other storage transistors) or at ground potential. It may be floated.

The embodiment shown in FIG. 6F is considered to be costly in the silicon region. If there are 128 word lines in each bit line segment and there are 64 steps in the stepped structure, then each step in the 64 step stepped structure (or a total of 8192 global word lines) , 128 global word lines are required. According to one embodiment of the invention, the number of global word lines required is 2, 4, 8 by contacting each global word line with two or more local word lines within each bit line segment. , 16, or more. For example, the global word line GSL ₁ includes not only word lines WL ₁ , WL ₁₂₉ , ..., but also word lines WL ₃₃ , WL ₆₅ , ... (Usually WL _{1 + 32k} ; k = 0, 1, ... ) Can also be contacted, which can reduce the number of global word lines required per step by a factor of four and the overall width of the stepped structure by a factor of four. Of course, the silicon substrate requires four times as many dedicated sense amplifiers for each additional decoding circuit or bit line segment (or a single sense amplifier for the bit line segment is four consecutive Time may be shared via read or program sequence).

Since the global ward wire is mounted on the top of the memory array above the stepped steps, the global ward wire can be implemented using low resistance copper wiring. As is known to those of skill in the art, the capacitance between adjacent global word lines within a step can be reduced by a substitution air gap as a dielectric between them. The global word line RC delay connects the voltage source in the global word line decoder and silicon substrate directly under the stepped step, and through a break along the length of the global word line, of the length of the global word line. It can be further reduced by accessing every half, one quarter, or one eighth.

For example, when transitioning from a 32-layer stack to a 64-layer stack, the number of wordline stepped steps is doubled from 32 to 64. FIG. 6G shows an embodiment of a vertical NOR string memory array that avoids such step doubling according to one embodiment of the present invention. FIG. 6G shows a ZZ cross section of the memory array, where the total number of planes in the memory array is two or more consecutively formed stacks (eg, STK ₁ and STK ₂ ) stacked on top of each other. Provided as. Each stack is provided with a set of stepped steps that was completed before the next stack was formed. In a prior art three-dimensional NAND memory array, two stacks of memory cells are formed on each of the 32 planes. The steps of the 64-planar stepped structure are then formed separately, after which their associated global word lines are formed. In contrast, FIG. 6F shows a word line (Y direction) in which _{each step is connected by one of the global word lines GWL 1} , GWL ₂ , ..., GWL _{32 (extending along the X direction).} Shows the formation of _{stack STK 1} and stack STK ₂ each having a width step (step A, step B) of 32 stepped structures (extending along). Stacks STK ₁ and STK ₂ are insulated from each other by an insulating layer 617 and are therefore reduced to half the total width that provides 64 stepped steps. Under this scheme _{, local bit wires (eg, BL654) and local source wires (eg, SL655) in stack STK 2} etch openings through an insulating layer 617 to expose the top of the N + dope vertical active row. By letting it _{connect to the corresponding local bit lines and local source lines in stack STK 1} , the vertical active rows of the upper 32 planes correspond in the lower 32 planes above the substrate 605. Connected to what you do. Similarly, _{both P-doped channel regions of stacks STK 1} and STK ₂ (eg, channel regions 656 corresponding to channel regions 556 of FIG. 5B) are formed in the insulating layer 617 prior to forming _{stack STK 2.} They are connected to each other by a P + dope plug 691.

The silicon substrate area associated with the global word line is reduced by placing the global word line decoder and voltage source either below the stepped steps or above the memory array rather than outside the array within the board. be able to. Such an arrangement may be provided in connection with the memory arrays of FIGS. 3F and 3G. In these embodiments, the top surface of the memory array is not interconnected with the source or bit lines. Of course, such wordline decoders and voltage sources are implemented using thin film transistors that need to be able to support the relatively high voltages required on the global wordline during the program (eg, in the range of 12V to 20V). Will be done. Such thin film transistors are shallow (excimer) laser annealing for partial recrystallization of the deposited polysilicon, or other seedings developed for solar panels, LED displays, or other applications. It can be achieved using technology. Also, the top surface of the memory array is to perform wider or higher global word line interconnects at greater intervals to reduce their RC delays without excessively increasing the memory chip area. It can be used.

3D vertical NOR array with segmented bit lines for semi-volatile NOR strings

Non-provisional patent application III (US Patent Application Publication No. 2017/0092371A1) discloses a semi-volatile NOR string suitable to replace DRAM in certain storage applications that do not require extremely high cycle durability. (See paragraphs [0128]-[0131]). Therefore, the read access time of the quasi-volatile NOR string approaches the read access time of the DRAM, which is 100 nanoseconds or less, which is about 500 times faster than that of the conventional 3D-NAND flash memory. In the 3D vertical NOR string disclosed in this detailed description, the segmented bit lines at the bottom of the array have a dedicated sense amplifier and a decoder in the substrate directly below the bit line segments (eg, figure). 3D, FIG. 3E, FIG. 3F, and FIG. 3G) can closely mimic the horizontal strings of non-provisional patent application III and achieve equal read latencies close to DRAM. The process steps for constructing these quasi-volatile vertical NOR strings are similar to those described in paragraph [0129] of Non-Provisional Patent Application III. Semi-volatile storage transistors have a relatively short retention time (eg, in the range of one hour to several days) and therefore need to be read and refreshed frequently. Therefore, having the ability to read or reprogram a large number of storage transistors simultaneously (ie, read or reprogram the storage transistors associated with a large number of bit line segments in parallel) has brought the chip density closer to 1 terabit. In some cases, it is important to minimize interruptions in normal reads.

Non-provisional patent application III also discloses pairing of two storage transistors for fast read cache memory in a horizontal NOR string (see paragraphs [0194] to [0196]). As disclosed in this detailed description, segmented bit lines with a dedicated segment sense amplifier in the vertical NOR string are well suited for such high speed read cache memory and use dual transistor pairs. Data on a transistor that shares the same wordline can then be programmed with inverse data (ie, erased) on a transistor adjacent to it. For example, in FIG. 6E, two transistors TL (683), TR (in FIG. 6E) in two adjacent bit line segments MSBL ₁ (L), MSBL _{1 (R) sharing both sides of the same word line WL 31-1.} The read output signal from 682) is supplied to the differential sense amplifier in the silicon substrate. The differential sense amplifier is shared between two adjacent bit line segments along the Y direction. This dual segment configuration reduces array bit efficiency by 50%, but provides excellent resistance to process variation and string leaks, parameter drift across the chip, or device sensitivity. Moreover, it can provide very fast sensing, higher cycle durability, and eliminate the need for programmable reference strings. The same chip block of the bit line segment configured with anti-transistor differential sensing for cache storage for isolation between the bit line segments along the X direction (ie, along the same direction as the global bit line). On the other hand, other blocks use the usual sensing of a single transistor at a time for double density. This flexibility allows the same chip to partially function as cache memory and storage memory. In addition, it is possible to store a file that requires storage of many pages (for example, one photographic image that requires a storage capacity of 4 MB occupies 2000 pages per 2 KB), and a high-speed cache memory can be used. Use to write the first one or more pages to a segment, write the rest to a non-cached segment on the same chip, and get the image by reading that first page very fast, while the other pages Use pipeline reads to enjoy low read latency for the entire 4MB.

Although the segmentation of global bit lines into regional bit line segments and global word line segmentation by the corresponding segment sense amplifiers of the present invention (discussed in relation to FIGS. 6F and 6H) have described 3D vertical NOR strings. , Can be similarly applied to conventional 3D vertical NAND memory strings.

Manufacturing process

7A, 7B, 7C, and 7D are cross-sectional views of an intermediate structure formed in the process of manufacturing a multi-gate NOR string array according to an embodiment of the present invention.

FIG. 7A shows a cross-sectional view of the ZZ plane of the semiconductor structure 700 after the low resistance layer 723p is formed above the substrate 701 according to the embodiment of the present invention. In this example, p is an integer in the range 0-31 and represents each of the 32 word lines. As shown in FIG. 7A, the semiconductor structure 700 includes a low resistivity layer 723-0 to 723-31. The semiconductor substrate 701 represents, for example, a P-doped bulk silicon wafer on which a support circuit for the memory structure 700 is formed before forming the vertical NOR string. Such support circuits may include both analog and digital logic circuits. Some examples of such support circuits include shift registers, latches, sense amplifiers, reference cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, exclusive logic sums and other logic gates. Input / output drivers, address decoders including bit line and word line decoders, other memory elements, sequencers, and state machines may be included. To provide these support circuits, as known to those skilled in the art, conventional N-wells, P-wells, triple wells (not shown), N + diffusion regions (eg, regions 707-0) and A P + diffusion region (eg, region 706), low-voltage and high-voltage transistors, capacitors, resistors, diodes, and interconnects are provided.

After the support circuit is formed in and on the semiconductor substrate 701, the insulating layer 708 is provided, for example, by depositing or growing thick silicon dioxide. In some embodiments, one or more metal interconnect layers are formed that include a global source line 713-0. The metal interconnect layer is provided as a horizontal elongated strip extending along a predetermined direction. The global source line 713-0 is connected to the circuit 707 in the substrate 701 via the etched opening 714. For ease of explanation in this detailed description, it is assumed that the global source line extends along the X direction. Metal interconnects can be formed by applying photolithography patterning and etching on one or more deposited metal layers (alternatively, these metal interconnects are of conventional copper or tungsten. It may be formed using a conventional damascene wiring process, such as a damascene wiring process). A thick dielectric layer 709 is then deposited and then flattened using conventional chemical mechanical polishing (CMP).

Next, the conductor layers 723 to 723-31 are sequentially formed. Each conductor layer is insulated from the lower layer and the upper layer by an insulating layer 726 interposed between the lower layer and the upper layer thereof. Although 32 conductor layers are shown in FIG. 7A, any number of conductor layers can be provided. In practice, the number of conductor layers that can be provided is, for example, the use of a well-controlled anisotropic etching process that allows cutting of a large number of conductor layers and the dielectric insulating layer 726 between them. Depends on process technology, such as possibility. For example, the conductor layer 723p first deposits a titanium nitride layer (TiN) with a thickness of 1 to 2 nm, followed by tungsten (W) with a thickness of 10 to 50 nm or a similar refractory metal, or silicide (particularly, among others). It can be formed by depositing a layer such as nickel, cobalt, or tungsten silicide), or salicide, and then a thin layer of etch stop material such as _{aluminum oxide (Al 2} O _3). Each conductor layer is either etched within the block 700 after deposition or deposited as a block by a conventional damascene wiring process. In the embodiment shown in FIG. 7A, each of the continuous conductor layers 723p extends in the Y direction by a distance 727 shorter (ie, recessed from the edge) than the edge of the immediately preceding metal layer, thereby all. The conductor layer of is accessible from the top of the structure 700 at a later stage in the manufacturing process. However, in order to reduce the number of masking and etching steps required to form the stepped conductor stack of FIG. 7A, individual conductor surfaces may be individually masked and etched to form the exposed concave surface 727. Recessed surfaces 727 can also be formed simultaneously for multiple conductor layers using other process techniques known to those skilled in the art that do not require it. After the conductor layer is deposited and etched, the corresponding dielectric insulating layer 726 is deposited. The dielectric insulating layer 726 can be, for example, silicon dioxide having a thickness of 15 nm to 50 nm. Conventional CMPs prepare the surface of each dielectric layer for depositing the next conductor layer. The number of conductor layers in the stack of block 700 is the number of memory TFTs in the vertical NOR string and the control gates of non-memory TFTs such as precharged TFTs (eg, precharged TFTs 575 in FIG. 5A), or bit line access selection. It corresponds at least to the number with any additional conductor layer that can be used as a control gate for the TFT (eg, 585-bit line access selection TFT 511 in FIG. 5A). The conductor layer deposition and etching steps, as well as the dielectric layer deposition and CMP process, are repeated until all conductor layers are provided.

Next, the dielectric insulating layer 710 and the hard mask layer 715 are deposited. The hard mask 715 is patterned to allow the conductor layer 723p to be etched to form long strips of word lines that have not yet been formed. The length of the word line extends along the Y direction. An example of a masking pattern for the word lines 623p-R and 623p-L is shown in FIG. 6, in which the masking pattern is an extension of adjacent word lines facing each other in an insulating portion (gap) 676 and a desired curved portion. Includes features such as recesses in each word line to generate 675. A deep trench is formed by performing anisotropic etching through the continuous conductor layer 723p and the dielectric insulating layer 726 intervening between them until the dielectric layer 709 at the bottom of the conductor layer 723p is reached. Due to the large number of conductor layers being etched, the photoresist mask itself may not be robust enough to retain the desired wordline pattern through multiple continuous etchings. In order to provide a robust mask, it is preferable to provide a hard mask layer 715 (eg, carbon), as is known to those skilled in the art. Etching is terminated on the dielectric material 709, the landing pad 713 on the global source line, or the substrate 701. It may be beneficial to provide an etch stop barrier film (eg, aluminum oxide) to protect the landing pad 713 from etching.

FIG. 7B is a cross-sectional view of the ZX plane of the semiconductor structure 700 according to the embodiment of the present invention. As shown, by etching the continuous conductor layer 723p and the corresponding dielectric layer 726, a trench reaching the dielectric layer 709 (eg, a deep trench 795) is formed. In FIG. 7B, the conductor layers 723p are anisotropically etched to form conductor stacks 723p-R and 723p-L that are insulated from each other by deep trenches 795. This anisotropic etching is an etching having a high aspect ratio. Since various layers of material are etched, it is necessary to change the etching chemicals between conductor material etching and dielectric etching, as is known to those skilled in the art, in order to achieve the best results. Avoid undercuts in any layer so that the conductor width and trench spacing of the word lines formed at the bottom of the stack are approximately the same as the corresponding conductor width and trench spacing of the word lines at or near the top of the stack. The anisotropy of multi-step etching is important because it should be done. Of course, the greater the number of conductor layers in the stack, the more difficult it is to maintain tight pattern tolerances through multiple successive etchings. Etching may be performed, for example, in sections of 32 layers, in order to reduce the difficulties associated with etching through, for example, 64 or 128 or more conductor layers. The separately etched sections can then be stitched together, for example as taught in Non-Patent Document 1 above.

Etching through multiple conductor layers 723p of a conductor material (eg, tungsten, or other hard-to-etch material) is much more difficult and time consuming than etching the intervening insulating layer 726. Therefore, an alternative process is used that eliminates the need for multiple etchings of the conductor layer 723p. This alternative process is well known to those of skill in the art and first replaces the conductor layer 723p of FIG. 7B with a sacrificial layer of easily etchable material. For example, the insulating layer 726 may be silicon dioxide and the sacrificial layer (occupying the space shown as 723p in FIG. 7B) may be silicon nitride or another fast etching dielectric material. Next, the deep trench is anisotropically etched through the ONON (oxide-nitride-oxide-nitride) alternating dielectric layer to form a high stack of dual dielectrics. .. At a later stage of the manufacturing process (discussed below), these stacks are supported by active vertical strips of polysilicon, which can preferably etch and remove the sacrificial layer by selective chemical or isotropic etching. It will be possible. The cavity thus formed is then filled by a conformal deposit of conductor material, resulting in a conductor layer 723p insulated by an intervening insulating layer 726.

After the structure of FIG. 7B is formed, the charge trap layer 734 and the polysilicon layer 730 are formally and continuously deposited on the vertical sidewalls of the etched conductor wordline stack. A cross section of the ZX plane of the structure formed thereby is shown in FIG. 7C. As shown in FIG. 7C, the charge trap layer 734 has, for example, a thickness of 5 made of a high dielectric constant dielectric film (eg, aluminum oxide, hafnium oxide, or some combination of silicon dioxide and silicon nitride). It is formed by first depositing a blocking dielectric 732a of ~ 15 nm. The charge trap material 732b is then deposited to a thickness of 4-10 nm. The charge trap material 732b is, for example, silicon nitride, silicon-rich oxynitride, conductive nanodots embedded in a dielectric film, or a thin conductive floating gate insulated from adjacent TFTs that share the same vertical active strip. Can be. The charge trap 732b was then deposited with a thickness in the range of 2-10 nm to form a thin, conformal tunnel dielectric film (eg, a silicon dioxide layer, or a silicon oxide-silicon nitride-silicon oxide (“ONO”) triple layer. ) To cap. The storage element formed from the charge trap layer 734 can be either SONOS, TANOS, nanodot storage, an insulated floating gate, or any suitable charge trapping sandwich structure known to those of skill in the art. The total thickness of the charge trap layer 734 is generally 15-25 nm.

After depositing the charge trap layer 734, an anisotropic etching is performed through the charge trap layer 734 and the dielectric layer 709 at the bottom of the trench 795 using a masking step to perform a bottom global source line landing pad for the _{source supply voltage V ss.} Trench 795 by stopping at 713 (see FIG. 7B), _{region of global bit line voltage V bl} (not shown), or P + region 706 (see FIG. 7C) for contacting the _{back bias supply voltage V bb.} A contact opening is formed at the bottom. In some embodiments, polysilicon super is used prior to this etching step to protect the vertical surface of the tunnel dielectric layer 732c during etching of the contact openings of the charge trap material 734 at the bottom of the trench 795. A thin film (eg, 2-5 nm thick) is deposited. In one embodiment, each global source line is connected only at alternating positions in the rows of vertical NOR string pairs. For example, in FIG. 5A, an electrical contact (eg, contact opening 557) is etched into an odd-numbered address word line, and an N + doped local source line (eg, local source line 555 in FIG. 5A) is used as a global source line. Connect to 513-1. Similarly, an electrical contact is etched into the even address word line to connect the N + -doped local source line in the row of the vertical NOR string pair to the global source line 513-2 (not shown in FIG. 5A). _{In embodiments where the virtual V ss} is used through the parasitic capacitor C (ie, capacitor 560 in FIG. 5A), the step of etching the charge trap layer 734 at the bottom of the trench 795 can be skipped.

Then, the polysilicon thin film 730 is deposited to a thickness of 5 to 10 nm. In FIG. 7C, the polysilicon thin film 730 is labeled 730R and 730L on the opposite side walls of the trench 795, respectively. The polysilicon thin film 730 is undoped or preferably doped with boron at a doping concentration in the range of ^{1 × 10 16} / cm ³ to 1 × 10 ¹⁷ / cm ^{3, and a TFT formed therein.} However, it can have a larger inherent threshold voltage. The trench 795 has a width sufficient to provide the charge trap layer 734 and the polysilicon thin film 730 on the side walls facing each other. After the polysilicon 730 is deposited, the sacrificial layer in the stack described above is etched and removed, and the cavity formed thereby is filled with the conformally deposited conductor layer 723p (FIG. 7C).

As shown in FIG. 7B, the trench 795 extends along the Y direction. After the formation of the insulated wordline stacks 723p-L and 723p-R, the semiconductor structures 700 of one embodiment each have 8000 or more actives formed along the length of each stack. It can have a row, i.e. 16000 or more parallel wordline stacks that act as control gates for 16000 TFTs (8000 TFTs are provided on each side of the stack). The 64 word lines in each stack will eventually form 16 billion TFTs in each of these multi-gate vertical NOR string arrays. Such a multi-gate vertical NOR string array stores 32 gigabits of data if each TFT stores two data bits. Approximately 32 such multi-gate vertical NOR string arrays (plus spare arrays) can be formed on a single semiconductor substrate, thereby providing a 1 terabit integrated circuit chip.

FIG. 7D is a cross-sectional view of the top surface of the structure of FIG. 7C according to an embodiment in the XY plane. Between the word lines 723p-L and 723p-R are two side walls 730L and 730R of a vertically deposited P-doped polysilicon structure (ie, the active row). The deep space 740 between the side walls 730L and 730R can be filled with a fast etching insulating dielectric material (eg, silicon dioxide, liquid glass, or carbon-doped silicon oxide). The top surface can then be flattened using conventional CMP. Subsequently, the openings 776 and 777 are exposed by a photolithography step. High aspect ratio selective etching is then performed to excavate the fast etched dielectric material in the exposed areas 776 and 777 to the bottom of the trench 795. A hard mask may be required in this etching step to avoid excessive pattern degradation during etching. The excavated space is then filled with N + doped polysilicon on the fly. The N + dopant diffuses into the very thin low concentration doped active polysilicon pillars 730L and 730R in the exposed space to N + dope them. Alternatively, the low-concentration doped polysilicon in the space may be removed by simple isotropic plasma etching or selective wet etching before the excavated space is filled with N + doped polysilicon on the fly. Good. The N + polysilicon is then removed from the apex by CMP or top etching to leave a high concentration of N + polysilicon pylon in the regions 754 (N +) and 755 (N +). These N + pylon form a shared vertical local source line and a shared vertical local bit line for the TFT in the resulting vertical NOR string.

FIG. 7D-1 shows that filling only a portion of the exposed voids 776 of the vertical pylon 754 and 755 substantially enhances the conductivity of the tall vertical source / drain pylon. This means, for example, that an ultrathin layer of N + doped polysilicon 754 (N +) and 755 (N +) is first deposited to a thickness between 5 and 15 nanometers, respectively (this is to fill the gap. (Insufficient), then a metal conductive material (eg, titanium nitride, tungsten nitride, or tungsten) is deposited (eg, using atomic layer deposition (ALD)) to form a source / drain pylon core. It is done by filling the remaining voids 720 (M) of. See also FIG. 4A-1. FIG. 4A-1 shows a state in which the metal conductor 420 (M) filled in the core of the pylon in the YZ plane is in close contact with the ultrathin N + poly 454 (N +). Due to the relatively high conductivity of the metal material packed in the core, the N-type doping concentration of ultrathin N + doped polysilicon can be reduced by one or two orders of magnitude, thereby N-type to the P-type dopant of the channel. Undesirable thermal diffusion of the dopant can be reduced. The N + / metal conductor structure can be applied to one or both of the source pylon and the drain pylon. In another embodiment, the thin P-doped polysilicon present in the outer region 757 of the channel region 756 first has a higher concentration of P + (eg, 1019 cm) as compared to the P-doping in the channel region 756. ³ or more) can be doped, which can be 2 × 1018 / cm ³ or less. By adding P + poly in contact with P-poly in the channel into the source pylon, the erasing efficiency can be increased when the local source line rises to a high positive voltage during the erasing operation.

The dielectric insulating layer is then deposited and patterned using photolithography masking and etching steps. The etching step creates a contact that connects the vertical local bit line to the horizontal global bit line (eg, as shown in FIG. 6, 657-1 is connected to the strings at odd-numbered addresses and 657- at even-numbered addresses. Connect 2 to the string). A low resistance metal layer (eg tungsten) is deposited. The deposited metal is then patterned using photolithography and etching steps to create a global bit line (eg, global word line 614-1 (GBL ₁ ) for strings at odd-numbered addresses, as shown in FIG. 6). , The even-numbered address forms a stringing global bit line 614-2 (GBL ₂ )). Alternatively, the global bit wire may be formed using a conventional copper damascene wiring process. All global bit lines, and all metal layers of the word line stack, 723p (FIG. 7A), are decoded and sensed in the substrate by the etched vias, as is known to those skilled in the art. Connected to the circuit. The switch and sensing circuit, decoder, and reference voltage source can be provided on the global bit and global word lines individually or shared by some of the bit and word lines.

In some embodiments, the bit line access selection transistor (511 in FIG. 5A) and its associated control gate word line (eg, word line 585 in FIG. 5A) are isolated, as known to those skilled in the art. Formed as vertical N + PN + transistors, odd and even global bit lines (eg, bit lines 614-1 and 614-2 in FIG. 6A) are alternated with odd and even addresses (eg, local in FIG. 6A). Selectively connect to the vertical NOR string at bit lines 657-1 and 657-2).

Read operation

Since the TFTs of the vertical NOR string are connected in parallel, in all embodiments of the present invention, all TFTs in the active row (including the active row in which the vertical NOR string pair is formed) are preferably read out. In order to suppress the leakage current between the shared local source line and the shared local bit line (for example, the local bit line 454 and the local source line 455 shown in FIG. 4C) during operation, it should be in the enhancement mode, that is, each The TFT should have a positive gate-source threshold voltage. The enhancement mode TFT targets a native TFT threshold voltage of about 1 V, generally with ^{a concentration of boron in the range of 1 × 10 16} to 1 × 10 ¹⁷ / cm ³ in the channel region (eg, P- in FIG. 7C). This is achieved by doping the channel region 756). In such a TFT, all non-selected word lines in the vertical NOR string pair of active columns can be kept at 0V. Alternatively, the read operation raises the voltage on the shared local N + drain line (eg, local source line 455 in FIG. 4C) to about 1.5 V and the shared local N + drain line (eg, local bit line 454). Is raised to about 2V and all unselected local word lines are kept at 0V. Such a configuration is equivalent to setting the word line to -1.5V with respect to the source, which results in a slightly depleted threshold voltage, for example if the TFT is slightly over-erased. The leakage current due to the TFT is suppressed.

After erasing the TFT of the vertical NOR string, a soft program operation to return any TFT of the over-erased (ie, having a depletion mode threshold voltage) to the enhancement mode threshold voltage. May be needed. FIG. 5A shows an optional contact 556 in which the P-channel is connected to the back bias voltage (V _bb ) of the body bias source 506 (also shown as body connection 456 in FIG. 4C). .. To reduce the subthreshold leakage current between the shared N + source and the shared N + drain / local bit lines, a _{negative voltage on the V bb} can be used to adjust the threshold voltage of the TFTs in each active row. _{In some embodiments, a positive V bb} voltage can be used during the erasing operation of the tunnel erasing TFT where the control gate is held at 0V.

To read the data stored in the TFTs of the vertical NOR string pair, all TFTs on both vertical NOR strings of the vertical NOR string pair first set all word lines in the multi-gate NOR string array to 0V. By holding it, it is put in the "off" state. Addressed vertical NOR strings can use decoding circuits to share sensing circuits among several vertical NOR strings along a common word line. Alternatively, each vertical NOR string may be directly connected to a dedicated sensing circuit via a global bit line (eg, GBL1 in FIG. 4C). In the latter case, one or more vertical NOR strings sharing the same word line plane can be sensed in parallel. Each addressed vertical NOR string, and sets the local source line _V ss _~0V. This setting is made via its hard-wired global source line (eg, GSL1 in FIG. 4C), as schematically shown in FIG. 8A, or is being precharged as schematically shown in FIG. 8B. A precharge transistor (eg, the precharge transistor 470 of FIG. 4C or the transistor of FIG. 3C) that instantaneously transfers _{V bl to 0 V to the parasitic capacitor C (eg, capacitor 460 or capacitor 360 of the floating local source line 455 or 355).} It is set as _{virtual V ss} ~ 0V via 317).

Immediately after turning off the precharge transistor 470, the local bit line (eg, local bit line 454 in FIG. 4C) is replaced by a bit line access selection transistor (eg, bit line access selection transistor 411 in FIG. 4C, or access in FIG. 5A. It is set to _{V bl to} 2V via the selection transistor 511). V _{bl to} 2V is also the voltage in the sense amplifier of the addressed vertical NOR string. At this time, the addressed wordline rises in small increment voltage steps from 0V to generally about 6V, while all non-addressed TFTs in both the odd-numbered and even-numbered address TFTs of the vertical NOR string pair. The selected word line is maintained at 0V. In the hard-wired V _ss embodiment of FIG. 8A, the addressed TFT is programmed to a threshold voltage of 2.5 V, in one example. Therefore, the voltage _{V bl} of the local bit lines LBL, the WL _S as soon as more than 2.5V, starts to discharge towards 0V the local source line _{(V ss)} via the selected TFT, which Causes the voltage drop (indicated by the dashed arrow in FIG. 8A) detected by the sense amplifier serving the selected global bit line. _{In the virtual V ss} embodiment of FIG. 8B, the precharge transistor word line WL _CHG is momentarily turned on at the start of the read sequence to precharge the floating local source line LSL to 0V. Next, the word line WL _S chosen performs the voltage increment step, as soon as it exceeds the programmed 2.5V, momentarily is selected TFT voltages of the local bit lines from V _{bl 2V} Let it descend. This voltage dip (indicated by the dashed arrow in FIG. 8B) is detected by a global bit line sense amplifier connected to the selected local bit line. As known to those of skill in the art, there are other alternative schemes for accurately reading the programmed threshold voltage of the selected TFT. In the embodiment for temporarily holding the virtual voltage V _ss depends on the parasitic capacitor C, read the vertical stack as parasitic capacitor C also increases high, therefore the retention time is long, is provided to the sense amplifier selected The signal gets louder. In order to further increase the parasitic capacitor C, in one embodiment it is possible to add one or more dummy conductors whose main purpose is to increase the capacitor C to the vertical string.

In the case of MLC implementation (ie, "multi-level cell" implementation where each TFT stores 2 bits or more), the addressed TFT has several voltages (eg, 1V (erased state), 2.5V, 4V, etc.). Alternatively, it may be programmed into one of 5.5V). It addressed word line WL _S, at a voltage increment step, incrementing the voltage until conduction TFT is detected by the sense amplifier. Alternatively, a single word line voltage may be applied (eg, about 6 volts) and _{the discharge rate of the local bit line LBL (V bl} ), some representing the stored multi-bit voltage state. It can be compared to the discharge rate from a programmable reference voltage. This approach can be extended to continuous states and effectively provides analog storage. The programmable reference voltage can be stored in a dedicated reference vertical NOR string located within the multi-gate vertical NOR string array, which closely tracks the characteristics between reads, programs, and background leaks. can do. With a vertical NOR string pair, only one TFT of the two vertical NOR strings can be read in each read cycle, and the TFT on the other vertical NOR string is in the "off" state (ie, all word lines are 0V). ) Is placed. Since the read voltage is applied to only one of the TFTs in the vertical NOR string during the read cycle, there is essentially no read disturb condition.

In one example of an embodiment of the invention, 64 TFTs and one or more precharged TFTs are provided on each vertical NOR string pair of vertical NOR strings. Each word line forms a capacitor at the intersection with the local vertical N + source line pillar (see, eg, capacitor 660 in FIG. 6A). A typical capacitance of such a capacitor is, for example, 1 × 10 ¹⁸ F (farad). Including all the capacitors in both vertical NOR strings in the vertical NOR string, the overall distributed capacitance C is about 1 × 10 ¹⁶ farads. This is generally in the completed read cycle in less than 1 microsecond immediately after the precharge operation, a sufficient capacity to the local source line to save the precharged supply voltage (V _ss). The charging time by the bit line access selection transistor 411 and the precharge TFT 470 is about several nanoseconds, and therefore the charging time does not significantly add to the read latency. Reading from the TFT in the vertical NOR string is fast. The reason is that unlike the NAND string read operation, which requires conducting a large number of series-connected TFTs, the read operation involves only one of the TFTs in the vertical NOR string. ..

The following two factors contribute to the read latency of the vertical NOR string of the present invention. _{(A) RC time delay associated with the resistor R bl} and capacitance C _bl of the global bit line (eg, GBL614-1 in FIG. 6A), and (b) the local bit when the addressed TFT begins to conduct. Response time of the sense amplifier to _{the voltage drop Vbl} on the line (eg LBL-1). The RC time delay associated with the global bit line is, for example, about tens of nanoseconds when serving 16,000 vertical NOR strings. The read latency for reading the TFT of the conventional vertical NAND string (for example, the NAND string of FIG. 1B) is that 32 or more series-connected TFTs and a selection transistor for discharging _{the capacitance Cbl of the global bit line are used.} Determined by the passing current. In contrast, in the vertical NOR string of the present invention, the read current discharge C _bl is the bit line access selection transistor 411 in series with one of the addressed transistor (e.g., transistor 416L of FIG. 4A) is supplied only through the This makes the local bit line voltage (V _bl ) discharge much faster. As a result, much shorter latency is achieved.

In FIG. 4C, when one TFT (eg, TFT 416L in the vertical NOR string 451b) is read at a time, all other TFTs in the vertical NOR strings 451a and 451b of the vertical NOR string vs. 491 are in the "off" state. It is held and those word lines are held at 0V. The TFT 416R in the vertical NOR string 452a of the vertical NOR string vs. 492 shares the word line W31 with the TFT 416L, while the vertical NOR string 452a is served by the global bit line 414-2 and the vertical NOR string 451b is the global bit line. Since served by 414-1, the TFT 416R is read out at the same time as the TFT 416L (FIGS. 6A and 6B show how the global bit lines 614-1 and 614-2 serve adjacent vertical NOR string pairs. Show).

In one embodiment, the wordline stack comprises 32 or more wordlines provided on 32 faces. In one multi-gate vertical NOR string array, each surface contains 8,000 word lines that control 16,000 TFTs, each of which has its own bit line connected to a dedicated sense amplifier. Under the condition, it can be read out in parallel through 16,000 global bit lines. Alternatively, if several global bit lines share a sense amplifier via a decoding circuit, 16,000 TFTs are read over several consecutive read cycles. Reading a large amount of discharge TFT in parallel, the voltage bounce on the chip of the ground power supply (V _ss) is generated, a read error may occur. However, using the parasitic capacitor C is precharged to the local source line (i.e., to provide a virtual supply voltage (V _ss) to the vertical NOR string) In the embodiment, special that such a ground voltage bounce is eliminated It has a great advantage. This is because the virtual power supply voltage in the vertical NOR string is independent and is not connected to the ground power supply of the chip.

Program (write) operation and program prohibition operation

The addressed TFT program has a high programming voltage between the selected word line (eg, word line 423p-R) and the active channel region (eg, the active channel region of body region 456 in FIG. 4A). When applied, by electron tunneling (direct tunneling, or Fowler-Nordheim tunneling) from the TFT channel region (eg, channel region 430L shown in FIG. 4B) to the charge trap layer (eg, charge trap layer 434). Can be achieved. Since tunneling is very efficient and requires very little current to program the TFTs, it is possible to achieve parallel programming of tens of thousands of TFTs with low power consumption. A tunneling program may require, for example, a pulse of 20 V, 100 microseconds. Preferably, the program is carried out by a stepwise voltage pulse with a shorter duration on the side, starting at about 14V and increasing to about 20V. By using stepwise voltage pulses, the electrical stress of the TFT can be reduced and overshoot of the intended program threshold voltage can be avoided.

After programming each high voltage pulse, the addressed transistor is read to see if it has reached its target threshold voltage. If the target threshold voltage is not reached, the next program pulse applied to the selected wordline is generally incremented by a few hundred millivolts. In this program verification sequence, one addressed word line (for example, the local bit line 454 of FIG. 4A) is applied with 0V applied to the local bit line (for example, the local bit line 454 of FIG. 4A) of the active column (for example, the active column 430L of FIG. 4B). That is, it is repeatedly applied to the control gate). In these high word line voltage programs, the channel region of the TFT 416L is inverted and held at 0V, which causes electrons to tunnel to the charge storage layer of the TFT 416L. When read sensing indicates that the addressed TFT has reached its target threshold voltage, the addressed TFT must prohibit further programming, but other TFTs that share the same wordline. Can continue programming to those higher target threshold voltages. For example, when programming the TFT 416L in the vertical NOR string 451b, programming of all other TFTs in the vertical NOR strings 451b and 451a must be prohibited by keeping all their word lines at 0V.

A semi-selective voltage (ie, about 10V) is applied to the local bit line 454 to prohibit further programming for the TFT 416L after the TFT 416L has reached its target threshold voltage. With 10V applied to the channel region and 20V applied to the control gate, only the net 10V is applied to the charge trap layer, so the Fowler-Nordheim tunneling current is not important and the step pulse voltage up to 20V. No further meaningful programming for TFT 416L is performed during the rest of the sequence. By increasing the voltage of the local bit line 454 to 10V while incrementing the program voltage pulse on the word line WL31, all TFTs on the vertical NOR string sharing the same selected word line have a higher target. Correctly programmed to the threshold voltage. In order to accurately program tens of thousands of TFTs in parallel to their various target threshold voltage states in multi-level cell storage, a "program-read-program prohibited" sequence is essential. In the absence of such programming prohibition of individual TFT overprogramming, it can cause oversteering or merging due to the threshold voltage of the next higher target threshold voltage state. The TFT 416R and TFT 416L share the same word line, but they belong to separate vertical NOR string pairs 452 and 451. Since the respective bit line voltages of the TFT 416L and the TFT 416R are _{supplied via the GBL 1} and the GBL ₂ and are controlled independently, both the TFT 416L and the TFT 416R can be programmed with the same program pulse voltage sequence. For example, the TFT 416L can continue the program, while the TFT 416R can prohibit further programming at any time. The vertical NOR strings 491a and 451b of the vertical NOR string pairs 491 are controlled by separate word lines 423p-L and 423p-R, respectively, and the voltage of each local bit line is independent of all other vertical NOR string pairs. Since it can be set, these programs and the program prohibition voltage condition can be satisfied. During the program, the unselected wordlines in the addressed or unaddressed wordline stack can be in the 0V, semi-selective voltage 10V, or float state. In an embodiment in which the global source line (eg, GSL ₁ in FIG. 4C) is accessed via a source access selection transistor (not shown in FIG. 4C), the access selection transistor is turned off during the program. As a result, the voltage of the local source line 455 follows the voltage of the local bit line 454 during the program and program prohibition. The same is true for embodiments in which the voltage on the local source line is supplied by its parasitic capacitor C, represented by capacitor 460 in FIG. 4C. In the embodiment of FIG. 4C, where the global source line is present but the source access selection transistor is not present, the voltage applied to the global source line 413-1 of the addressed string is addressed during program and program prohibition. It is preferable to track the voltage of the global bit line 414-1.

After each increment of the voltage of the program pulse, a read cycle is performed to determine if the TFTs 416L and 416R have reached their respective target threshold voltages. If the target threshold voltage is reached, the drain, source, and body voltages are raised to 10V (or floated closer to 10V) to prohibit further programming, while ward. Line WL31 continues the program of other addressed TFTs on the same plane that have not yet reached the target threshold voltage. This sequence ends when all addressed TFTs have been read / verified to be correctly programmed. In the case of MLC, each addressed global bit line has several predetermined voltages (eg, 0V, 1.5V, 3.0V, or 4.5V representing four different states of stored 2-bit data). ), And then a stepped program pulse (up to about 20V) is applied to the word line WL31 to speed up one of the multiple threshold voltage states. .. In this way, the addressed TFT receives a predetermined one of the effective tunneling voltages (ie, 20V, 18.5V, 17V, 15.5V, respectively), resulting in a predetermined threshold voltage. One of them is programmed into the TFT in a single program sequence. Subtle program pulses can then be provided at individual TFT levels.

High-speed full-parallel program

Due to the unique parasitic capacitor C of each local source line in the multi-gate vertical NOR string array, all local source lines in the multi-gate vertical NOR string array are all vertical NOR before applying the high voltage pulse sequence. A voltage of 0V (for programming) or 10V (for prohibition) _{can be instantaneously applied on the string (eg, via global bit line GBL 1} , bit line access selection transistor 411, precharge transistor 470). This procedure can be performed on a plane-by-plane basis by addressing the wordline planes. For each addressed wordline plane, apply the program pulse sequence to many or all wordlines on the addressed wordline plane while keeping all wordlines on the other wordline planes at 0V. This allows a large number of TFTs on an addressed plane to be programmed in parallel and then individual read verifications can be performed. Also, if necessary, the local source line of the properly programmed TFT can be reset to the program prohibition voltage. This approach has a relatively long programming time (ie, about 100 microseconds), while the speed of precharging or reading verification of all local source line capacitors on all TFTs that share an addressed word line plane is It is more than 1000 times faster, which offers a great advantage. Therefore, it is beneficial to program as many TFTs as possible in parallel on each word line plane. This accelerated programming capability offers even greater advantages in MLC programs that are significantly slower than single-bit programs.

Erase operation

For some charge trap materials, the erasing operation is performed by reverse tunneling of the trapped charge. This erasing operation can be quite slow, sometimes requiring a pulse of 20 V or more for tens of milliseconds. Therefore, the erase operation can be performed at the vertical NOR string array level (“block erase”) and is often performed in the background. A typical vertical NOR string array has 64 word line planes, and each word line plane controls, for example, 16,384 × 16,384 TFTs, for a total of about 1.7 billion TFTs. Therefore, if each TFT stores 2 bits of data, a 1 terabit chip can contain about 30 vertical NOR array arrays. In some embodiments, block erasure keeps all word lines in the block at 0V while all TFTs in the vertical NOR string (eg, body connection 456 in FIG. 4C and contact 556 in FIG. 5A). It can be performed by applying about 20V to the P channel shared by. The duration of the erasure pulse must be such that most of the TFTs in the block are erased at the slight threshold voltage in enhancement mode, i.e. in the range 0V to 1V. Some TFTs overshoot and are eliminated in depletion mode (ie, slightly negative threshold voltage). As part of the erasure command, a soft program may be required to return the over-erased TFT to the slight threshold voltage in enhancement mode after the end of the erasure pulse. Vertical NOR strings that can contain one or more depletion mode TFTs that cannot be programmed into enhancement mode need to be removed to replace the spare string.

Alternatively, instead of supplying the erase pulse to the body (ie, the P-layer), the vertical NOR is held at 0 V for all word lines on all word line planes for the duration of the erase pulse. The voltage of the local source line and local bit line (eg, local source line 455 and local bit line 454 in FIG. 4C) on all vertical NOR string pairs in the string array may be increased to about 20 V. In this scheme, the global source line and global bit line selection decoders need to use high voltage transistors capable of withstanding 20V at their junctions. Alternatively, all TFTs that share an addressed wordline plane hold a -20V pulse on all wordlines on the addressed plane, while holding the wordlines on all other planes at 0V. Can be erased at the same time by applying. All other voltages in the vertical NOR string pair are held at 0V. In this way, only the XY slices of all TFTs connected to one addressed word line plane are erased.

Semi-volatile NOR TFT string

Although some charge trapping materials suitable for use in vertical NOR strings (eg, oxide-nitride-oxide, or "ONO") generally have years of data retention time. , Durability is relatively low (ie, generally performance deteriorates after write / erase cycles of about 10,000 cycles or less). However, in some embodiments, the charge retention time is very short but has very improved durability (eg, the retention time is on the order of minutes or hours, but tens of millions of writes. A charge trapping material (with durability that allows for erasure cycles) may be selected. For example, in the embodiment of FIG. 7C _{, the tunnel dielectric layer 732c, which is typically a SiO 2} layer of 6-8 nm, is thinned to about 2 nm or another dielectric material of similar thickness (eg, for example. It can be replaced with SiN). This very thin dielectric layer allows the use of smaller voltages (unlike Fowler Nordheim tunneling, which requires higher voltage) to introduce electrons into the charge trap layer by direct tunneling. , In this case, the electrons can be trapped for minutes to hours or days. The charge trap layer 732b can be a combination of silicon nitride, conductive nanodots dispersed in a thin dielectric film, or other charge trap film containing an insulated thin floating gate. The blocking layer 732a can be silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, a high dielectric constant dielectric, or any combination thereof. The blocking layer 732a prevents the electrons in the charge trap layer 732b from escaping to the control gate word line. The trapped electrons eventually leak into the active region 730R as a result of breakage of the ultrathin tunnel dielectric layer or by direct tunneling in the opposite direction. However, such loss of trapped electrons is relatively slow. Other combinations of charge trapping materials may also be used, in which case retention is more durable but requires regular write or read refresh operations to replenish the lost charge. A low-quality "semi-volatile" storage TFT is obtained. Since the vertical NOR strings of the present invention have relatively fast read access (ie, low latency), they should be used in some applications that currently require the use of dynamic random access memory (DRAM). Can be done. The vertical NOR string of the present invention has a great advantage that the cost per bit is significantly lower than that of a DRAM that cannot be incorporated into a three-dimensional stack. In addition, the vertical NOR string of the present invention consumes significantly less power than a DRAM that requires refreshing every few milliseconds because the refresh cycle only needs to be executed once every few minutes or hours. It has a great advantage. The three-dimensional semi-volatile storage TFT of the present invention selects an appropriate material as described above for the charge trap material, appropriately adapts the program / read / program prohibition / erasure conditions, and periodically data. Achieved by incorporating a refresh of.

NROM / Mirror Bit NOR TFT String

In another embodiment of the invention, the vertical NOR string can be programmed using a channel hot electron injection method similar to that used in two-dimensional NROM / mirror bit transistors known to those of skill in the art. Using the embodiment of FIG. 4A as an example, the programming conditions for channel hot electron injection can be 8V at the control gate (ie, word line 423p), 0V at the local source line 455, and 5V at the local drain line 454. The charge representing one bit is stored in the charge storage layer at one end of the channel region (of the body region 456) adjacent to the junction with the local bit line 454. By reversing the polarities of the local source line 455 and the local bit line 454, a charge representing the second bit is programmed and the charge at the opposite end of the channel region 456 adjacent to the junction with the local source line 455. It is stored in the storage layer. In order to read both bits, it is necessary to read them in the reverse order of the program, as is known to those skilled in the art. Channel hot electron programs are far less efficient than programs by direct tunneling or Fowler-Nordheim tunneling, making them unsuitable for large parallel programs possible by tunneling. However, each TFT has twice the bit density, which makes it attractive for applications such as archive memory. Erasing in the NROM TFT embodiment uses a conventional NROM erasing mechanism that utilizes interband tunneling-induced hot hole injection by neutralizing the charge of trapped electrons, i.e. -5 V local to the word line. This can be achieved by applying 0 V to the source line 455 and 5 V to the local bit line 454, respectively. Alternatively, the NROM TFT can be erased by applying a _{high positive substrate voltage V bb} to the body region 456 having a 0 V word line. Since the channel hot electron injection program requires a high program current, all embodiments of the vertical NROM TFT string use hard-wired local source and local bit wires, as in the embodiments of FIGS. 3A and 6C. There must be.

The above detailed description is provided to illustrate certain embodiments of the present invention and is not intended to be limiting. Various modifications and modifications are possible within the scope of the present invention. The present invention is described in the appended claims.

Claims (33)

It's a memory structure
A semiconductor substrate having a substantially flat surface and having a circuit for operating a memory circuit formed therein.
A plurality of active rows of semiconductor material formed above the semiconductor substrate, each active row extending along a first direction orthogonal to the flat surface of the semiconductor substrate and extending. , A first high-concentration dope region, a second high-concentration dope region, and one or more low-concentration dope regions adjacent to both the first high-concentration dope region and the second high-concentration dope region. , The active column is arranged in a two-dimensional array having a plurality of rows of active columns extending along a second direction and a plurality of rows of active columns extending along a third direction. The plurality of active rows and the plurality of active rows, which are parallel to the flat surface of the semiconductor substrate, in the second direction and the third direction.
A charge trap material provided on one or more surfaces in each active row and
A plurality of electrically isolated word wire conductors provided between the active rows forming the plurality of stacks, each of which extends longitudinally along the third direction. The active row, the charge trap material, and the word wire conductor cooperate with each other to form a plurality of variable threshold thin films, and each variable threshold thin film is the related word of the plurality of word wire conductors. A wire conductor, a portion of the low concentration dope region in the active row, the charge trap material between the portion of the low concentration dope region and the ward wire conductor, a first high concentration dope region, and a second high. With the plurality of word wire conductors including a concentration-doped region,
A first plurality of interconnect conductors and a second plurality of interconnector conductors extending longitudinally along the second direction above and below the active row, respectively, are provided.
(I) The first high-concentration doped region forms a local bit line and functions as a first drain or source terminal of the variable threshold thin film transistor, and the local bit line is the second plurality of interconnects. Selectively connected to the relevant interconnect conductor of the conductors,
(Ii) The related word line conductor functions as a gate terminal for providing a control voltage to the variable threshold thin film transistor.
(Iii) The second high-concentration doped region forms a local source line and functions as a second drain or source terminal of the variable threshold thin film transistor, and the local source line is the first plurality of interconnects. Connected to the relevant interconnect conductor of the conductors,
Memory structure. The memory structure according to claim 1.
The second plurality of interconnect conductors include a plurality of bit line segments below each row of the active column along the second direction.
A memory structure in which each bit line segment is selectively electrically isolated from each other and connects a predetermined number of local bit lines in each row of the active column. The memory structure according to claim 2.
Further with multiple region bit line segments,
A memory structure in which each bit line segment is selectively connected to each area bit line segment. The memory structure according to claim 2.
With multiple segment selection transistors
Each segment selection transistor is a memory structure that selectively connects a corresponding bit line segment to the circuit of the semiconductor substrate. The memory structure according to claim 4.
The circuit of the semiconductor substrate comprises at least a plurality of sense amplifiers arranged over the flat surface of the semiconductor substrate.
A memory structure in which each sense amplifier is connected to a corresponding bit line segment by a separate group of one or more segment selection transistors. The memory structure according to claim 4.
The segment selection transistor is a memory structure formed on the semiconductor substrate. The memory structure according to claim 2.
Each word line conductor provides gate terminals for variable threshold thin film transistors in the active row on either side of the word line conductor.
A memory structure in which the local bit lines of the active column adjacent to each other on either side of the word line conductor are associated with different bit line segments. The memory structure according to claim 1.
The first plurality of interconnect conductors include a plurality of source line segments above each row of the active column along the second direction.
Each source line segment is a memory structure that connects a predetermined number of local source lines in each row of the active column. The memory structure according to claim 8.
A memory structure in which each of the source line segments is selectively electrically isolated from each other. The memory structure according to claim 9.
Further equipped with a global source line and multiple segment selection transistors,
Each segment selection transistor is a memory structure that connects a predetermined number of source line segments to a global source line. The memory structure according to claim 10.
Each active row is a memory structure further comprising a precharge transistor for electrically connecting the local source line of the active row to the local bit line of the active row. The memory structure according to claim 11.
The local source line connected by each source line segment is a virtual voltage source during the read, program, program prohibition, or erase operation of one or more of the variable threshold thin film transistors in the active column associated with the source line segment. A memory structure that provides capacitance to function as. The memory structure according to claim 8.
The semiconductor substrate further includes a body bias voltage source.
A memory structure in which the low concentration doped region of each active row is connected to the body bias voltage source by a conductor provided above or below the active row. The memory structure according to claim 13.
The conductor above the active row is a memory structure comprising one of the first plurality of interconnect conductors. The memory structure according to claim 13.
A memory structure in which the conductor above the active row is routed along the third direction. The memory structure according to claim 8.
It further comprises a plurality of charge columns associated with each of the relevant source line segments of the plurality of source line segments.
Each of the charge rows has a first high-concentration dope region and a second high-concentration that are structurally substantially identical to the first high-concentration dope region and the second high-concentration dope region of each active row. Has a dope region and
Each of the charge trains further comprises a plurality of pass transistors that selectively connect the first high concentration dope region and the second high concentration dope region of the charge train, respectively.
A memory structure in which at least one of the first high-concentration doping region and the second high-concentration doping region is connected to the circuit of the semiconductor substrate. The memory structure according to claim 16.
Each of the charge rows is a memory structure formed between two source line segments adjacent to each other. The memory structure according to claim 16.
A memory in which one or more word line conductors of the plurality of word line conductors activate one or more pass transistors of the plurality of pass transistors in one or more charge rows of the plurality of charge rows. Structure. The memory structure according to claim 18.
A memory structure further comprising a global source line connecting the one or more word line conductors that activate the one or more pass transistors in the one or more charge trains. The memory structure according to claim 16.
Each charge row is a memory structure connected to a voltage source provided on the semiconductor substrate by a segment selection transistor of the semiconductor substrate. The memory structure according to claim 20.
The voltage source is a memory structure that supplies the erasing voltage of the source line during the erasing operation. The memory structure according to claim 1.
A memory structure in which the active rows are insulated from each other by an insulating dielectric material or an air gap. The memory structure according to claim 1.
A memory structure in which the word wire conductors of the stack are insulated from each other by an insulating dielectric material or an air gap. The memory structure according to claim 1.
A memory structure in which the variable threshold thin film transistors associated with each active row are arranged in parallel to form one or more NOR thin film transistor strings. The memory structure according to claim 1.
The word line conductors of each stack are arranged at different positions along the first direction to form steps in the stepped structure.
Each word wire conductor is connected to a corresponding one of the first plurality of interconnect conductors and the second plurality of interconnect conductors by a via in the stepped structure. .. The memory structure according to claim 25.
The word line conductors selected in the selected steps of the stepped structure in the stacks that are different from each other are in the corresponding one of the first plurality of interconnect conductors and the second plurality of interconnect conductors. A memory structure to be connected. A memory structure including a first modular memory structure and a second modular memory structure arranged on top of each other.
A memory structure in which each modular memory structure includes the memory structure according to claim 25. The memory structure according to claim 27.
The first modular memory structure and the second modular memory structure are memory structures that are insulated from each other by a dielectric layer. The memory structure according to claim 28.
The first modular memory structure and the active rows in the second modular memory structure are arranged along the first direction.
A memory structure in which the local source lines of the active column are connected by vias via the dielectric layer. The memory structure according to claim 1.
A memory structure further comprising a metal pylon embedded in one or both of the local source line and the local bit line of the active column. The memory structure according to claim 30.
The metal pylon is a memory structure containing one or more of titanium nitride, tungsten nitride, and tungsten. The memory structure according to claim 31.
The metal pylon is a memory structure formed by using atomic layer deposition technology. The memory structure according to claim 1.
The low concentration dope region in each active row comprises a first section and a second section.
The first section of the low concentration doped region serves as a channel region for the variable threshold thin film transistor in the active row.
The second section of the low concentration dope region is a memory structure having a dopant concentration several times that of the first section of the low concentration dope region.

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