CN102386188A - Memory architecture of 3D array with diode in memory string - Google Patents
Memory architecture of 3D array with diode in memory string Download PDFInfo
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- CN102386188A CN102386188A CN2011101890967A CN201110189096A CN102386188A CN 102386188 A CN102386188 A CN 102386188A CN 2011101890967 A CN2011101890967 A CN 2011101890967A CN 201110189096 A CN201110189096 A CN 201110189096A CN 102386188 A CN102386188 A CN 102386188A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The invention discloses a memory architecture of a 3D array with a diode in a memory string. The 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
Description
Technical field
The invention relates to high density memory Set, particularly about storage device with multilayer planar memory cell so that cubical array to be provided.
Background technology
When the critical dimension of the device in the integrated circuit is reduced to the limit of common memory cell technologies, the designer then then the multiple lamination planar technique of seeking memory cell reaching higher storage density, and each lower cost.For example; Thin-film transistor technologies has been applied among the charge capturing memory; Can consult paper " A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory " like Lai Dengren; IEEE Int ' l Electron Device Meeting, on December 11st～13,2006; And people's such as Jung paper " Three Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm Node "; IEEE Int ' l Electron Device Meeting, on December 11st～13,2006.
In addition; The plotted point array technique also has been applied among the anti-fuse memory; Can consult paper " 512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells ", IEEE J.of Solid-state Circuits, vol.38 like people such as Johnson; No.11, in November, 2003.In the described design of people such as Johnson, multilayer word line and bit line are used, and it has memory element in plotted point.This memory element comprises p+ polysilicon anode and is connected with word line, reaches n+ polysilicon negative electrode and is connected with bit line, and separated by anti-fuse materials between negative electrode and the anode.
By rely, Jung, etc. in the described technology of people, each accumulation layer is used the crucial lithography step of multiple tracks.Therefore, making this number that installs required crucial lithography step can be the multiple of its accumulation layer number that uses.Therefore, though can reach higher density through using cubical array, higher manufacturing cost has also limited this technological scope of application.
The another kind of technology of vertical NAND gate memory cell structure in charge capturing memory of using is also at people's such as Tanaka paper " Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory "; 2007Symposium on VLSI Technology Digest of Technical Papers; Pp.14～15; On June 12nd～14,2007, describe to some extent.In the structure that people such as Tanaka describe; Comprise multiple-grid utmost point field effect transistor structure; The vertical channel that it has similar NAND gate operation uses silica nitrogen-oxygen-silicon (SONOS) kenel charge capturing storage unit structure, to produce storage location at each grid/vertical channel interface.This storage organization is based on arrangement and constitutes multiple-grid utmost point memory cell as the columnar semiconductor material of vertical channel, has a lower selection grid near substrate, and higher selection grid side on it.A plurality of level control grids are to use the plane electrode layer that intersects with column and form.Plane electrode layer as level control grid does not need crucial photoetching, and therefore saves cost.Yet each vertical memory cell is still need many crucial lithography steps.In addition, the number of control grid is still to some extent restriction in the sandwich construction of the method, and it is by for example being that factors such as vertical channel conductivity, employed programming and erase operation decide.
Therefore a kind of three dimensional integrated circuits memory construction of low manufacturing cost need be provided, and it comprises reliably, very little memory element.
Summary of the invention
Technology described herein is a kind of storage device, comprises an ic substrate, a plurality of rectangular semi-conducting material laminations, many word lines, memory element and diode.These a plurality of rectangular semi-conducting material laminations extend this ic substrate, and these a plurality of laminations have the ridge shape and comprise that at least two rectangular semi-conducting materials are separated by insulating barrier and are the Different Plane position in a plurality of plan position approachs.These many word lines are arranged to and are orthogonal on these a plurality of laminations, and with these a plurality of laminations along shape, the intersection of so setting up a cubical array in the surface of these a plurality of laminations with this many word line plotted points is regional.This memory element is in this intersection zone, and it sets up the memory cell of accessible this cubical array via this rectangular semi-conducting material and these many word lines, and this memory element is arranged to serial between bit line structure and source electrode line.This diode and this serial couple, and are between memory cell serial and bit line structure and source electrode line wherein between one.
In certain embodiments, this serial right and wrong door serial.
In certain embodiments, the particular source polar curve in the specific bit line in this bit line structure, this source electrode and the combination selection of the particular word line in this many word lines can pick out the particular memory location in the memory cell of this cubical array.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this bit line structure.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this source electrode line.
Some embodiment comprises a serial selection wire and a ground connection selection wire.This serial selection wire is arranged to and is orthogonal on these a plurality of laminations, and with these a plurality of laminations along shape, so set up the serial choice device in surface and this serial selection wire plotted point of these a plurality of laminations.This ground connection selection wire is arranged to and is orthogonal on these a plurality of laminations, and with these a plurality of laminations along shape, so set up grounding selection device in surface and this ground connection selection wire plotted point of these a plurality of laminations.
In certain embodiments, this diode is coupled between this serial choice device and this bit line structure.In certain embodiments, this diode is coupled between this grounding selection device and this source electrode line.
In certain embodiments, the memory element in this intersection zone comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.
In certain embodiments, this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type zone in this rectangular semi-conducting material.In certain embodiments, this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type embolism contacts with this rectangular semi-conducting material.
Some embodiment comprises that logic do not choose the diode in the serial to apply reverse biased to this memory cell in programming during this memory cell.
Another object of the present invention is for providing a kind of storage device, and the memory cell that comprises an ic substrate and a cubical array is in this ic substrate.This cubical array comprises the lamination of NAND gate serial memory cell; And diode and this serial couple, and is between memory cell serial and bit line structure and source electrode line wherein between one.
Among some embodiment, the particular source polar curve in the specific bit line in this bit line structure, this source electrode and the combination selection of the particular word line in this many word lines can pick out the particular memory location in the memory cell of this cubical array.
In certain embodiments, this diode and this serial couple, and are between memory cell serial and this bit line structure.In certain embodiments, this diode and this serial couple, and are between memory cell serial and this source electrode line.
Some embodiment comprises that a serial choice device is between this bit line structure and this memory cell serial; And one grounding selection device between this source electrode line and this memory cell serial.
In certain embodiments, this diode is coupled between this serial choice device and this bit line structure.In certain embodiments, this diode is coupled between this grounding selection device and this source electrode line.
In certain embodiments, the charge-trapping structure in this intersection zone comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.
A purpose more of the present invention is that a kind of method of operating three-dimensional NAND gate flash memory is provided.Its step comprises and applies a programming adjustment bias voltage sequence to this three-dimensional NAND gate flash memory, and this cubical array comprises diode and this serial couples, and makes that this diode is between memory cell serial and bit line structure and source electrode line structure wherein between one.
One or more serial do not chosen is recharged, and wherein this is not chosen serial and does not comprise soon by the memory cell of this programming adjustment bias voltage programming.In various embodiment, this charging is to carry out from the source electrode line structure or from bit line structure.In various embodiment, this charging is via diode or does not carry out via diode.This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this.Program voltage will be applied to this and will not choose serial and this chooses serial via one or more word line of the memory cell that is about to be programmed by this programming adjustment bias voltage.
This memory element is arranged to serial between bit line structure and common source line, and comprises that diode and this serial couple, and is between the memory cell serial of separately serial and bit line structure and source electrode line wherein between one.First selects grid (for example grid SSL is selected in serial) can be coupled between corresponding bit lines structure and this memory cell serial, and second selects grid (for example ground connection is selected grid G SL) can be coupled between the corresponding common source line and this memory cell serial.This diode can couple between first and select between grid and this corresponding bit lines structure.This diode can couple between second and select between the grid common source line corresponding with this.
This three-dimensional memory devices comprises a plurality of ridge shape laminations, and it is to be separated by insulating barrier by a plurality of rectangular semi-conducting materials, is arranged to serial in the described herein example, and it can couple with sensing amplifier via decoding circuit.These a plurality of rectangular semi-conducting materials have the side of side surface in these a plurality of laminations.In this example, these many leads as word line can couple with column decoder, are arranged to be orthogonal on these a plurality of laminations.This lead has and the surface (for example basal surface) of these a plurality of laminations along shape.So cause in the intersection of setting up a multilayer with the side surface of this rectangular semi-conducting material and many lead plotted points regional along the surperficial configuration of shape.This memory element is placed in the side surface of rectangular semi-conducting material and the intersection zone between lead.Memory element is programmable, is similar to programmable resistance structure or charge-trapping structure described in following examples.Lamination that constitutes memory cell that is somebody's turn to do suitable shape lead, memory element and this rectangular semi-conducting material in the lamination in specific intersection zone.The result of this array structure can provide the memory cell of this cubical array.
These a plurality of ridge shape laminations and many leads are to utilize self-aligning mode to form memory cell.For example; Rectangular semi-conducting material in a plurality of ridge shape laminations can use single etching mask definition; Cause forming staggered raceway groove, it can be that the side surface of the rectangular semi-conducting material in dark relatively and the lamination is vertically or the side in alignment that tilts with the ridge that forms raceway groove.This memory element can use one or more layers material that comprehensively is deposited on the lamination to form, and uses other technology that does not need critical alignment step to form.In addition, many leads can utilize direct motion to be deposited on one or more layers material as memory element, use this single etching mask to define the etching technics of lead afterwards again.Consequently, only use an alignment procedures to define the rectangular semi-conducting material in the lamination, and an alignment procedures define many leads.
In addition, a kind of three-dimensional of energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) technology, NAND gate flash structures of burying passage, nothing knot of being based on also described here.
Design provides a kind of very efficient array decoded mode to three-dimensional perpendicular grid NAND gate quickflashing in the present invention.Its crystallite dimension goes in the present floating grid NAND gate quickflashing design and can density be extended to megabit.
Also three-dimensional NAND gate quickflashing design provides a kind of feasible circuit design framework to VHD in the present invention.
The object of the invention, characteristic, and embodiment, graphic being described of can in the chapters and sections of following execution mode, arranging in pairs or groups.
Description of drawings
Fig. 1 shows the sketch map of a three-dimensional storage organization described herein; It comprises that a plurality of rectangular semi-conducting materials plane is parallel with the Y axle and is arranged to a plurality of ridge shape laminations; One accumulation layer is in the side of rectangular semi-conducting material, and the many leads that have with the basal surface of the suitable shape of its a plurality of ridge shape laminations down.
The memory cell structure of Fig. 2 displayed map 1 is at the profile along the Z-X plane.
The memory cell structure of Fig. 3 displayed map 1 is at the profile along the Y-X plane.
Fig. 4 shows that the anti-fuse with Fig. 1 structure is the sketch map of basic memory.
Fig. 5 shows the sketch map of a three-dimensional NAND gate flash structure described herein; It comprises that a plurality of rectangular semi-conducting materials plane is parallel with the Y axle and is arranged to a plurality of ridge shape laminations; One charge-trapping accumulation layer is in the side of rectangular semi-conducting material, and many have with its under the lead of basal surface of a plurality of ridge shape lamination cisoids.
The memory cell structure of Fig. 6 displayed map 5 is at the profile along the Z-X plane.
The memory cell structure of Fig. 7 displayed map 5 is at the profile along the Y-X plane.
Fig. 8 shows the sketch map of the NAND gate flash memory with Fig. 5 and Figure 23 structure.
Fig. 9 shows the sketch map of the alternate embodiment of a three-dimensional NAND gate flash structure that is similar to Fig. 5, and wherein storage material layer removes between lead.
The memory cell structure of Figure 10 displayed map 9 is at the profile along the Z-X plane.
The memory cell structure of Figure 11 displayed map 9 is at the profile along the Y-X plane.
Figure 12 shows the generalized section of enforcement manufacturing like the technology phase I of the storage device among Fig. 1, Fig. 5 and Fig. 9.
Figure 13 shows the generalized section of enforcement manufacturing like the technology second stage of the storage device among Fig. 1, Fig. 5 and Fig. 9.
Figure 14 A shows the generalized section of enforcement manufacturing like the technology phase III of the storage device among Fig. 1.
Figure 14 B shows the generalized section of enforcement manufacturing like the technology phase III of the storage device among Fig. 5.
Figure 15 shows the generalized section of enforcement manufacturing like the technology phase III of the storage device among Fig. 1, Fig. 5 and Fig. 9.
Figure 16 shows the generalized section of enforcement manufacturing like the technology stage of the storage device among Fig. 1, Fig. 5 and Fig. 9.
Figure 17 shows the fast sketch map in simplification side of integrated circuit according to an embodiment of the invention, and wherein integrated circuit comprises the three-dimensional programmable resistance read-only memory array with row, row and plane decoding circuit.
Figure 18 shows the fast sketch map in simplification side of integrated circuit according to another embodiment of the present invention, and wherein integrated circuit comprises the three-dimensional NAND gate flash array with row, row and plane decoding circuit.
Figure 19 is a part of tunnelling electron microscope picture of three-dimensional NAND gate flash array.
Figure 20 shows to have diode in the three-dimensional NAND gate flash structure in the bit line structure of this serial and the profile between the storage serial.
Figure 21 shows to have diode in the three-dimensional NAND gate flash structure in the bit line structure of this serial and the sketch map between the storage serial, and it shows two memory cell planes, and each plane has 6 charge capturing storage units and is arranged to the NAND gate configuration.
Figure 22 shows the sequential sketch map of the programming operation that is similar to the array among Figure 20.
Figure 23 shows to have diode profile when carrying out read operation between the bit line structure of this serial and storage serial in the three-dimensional NAND gate flash structure.
Figure 24 shows to have diode profile when carrying out programming operation between the bit line structure of this serial and storage serial in the three-dimensional NAND gate flash structure.
Figure 25 shows to have diode in the three-dimensional NAND gate flash structure in the bit line structure of this serial and the sketch map between the storage serial, and it is to use polysilicon plug as diode.
Figure 26 shows to have diode in the three-dimensional NAND gate flash structure in the source electrode line structure of this serial and the profile between the storage serial.
Figure 27 shows to have diode in the three-dimensional NAND gate flash structure in the source electrode line structure of this serial and the sketch map between the storage serial, and it shows two memory cell planes.
Figure 28 is shown in the sequential sketch map of first example of the programming operation of the array among Figure 21.
Figure 29 is shown in the sequential sketch map of second example of the programming operation of the array among Figure 21.
Figure 30 is shown in the sequential sketch map of another example of the programming operation of the array among Figure 21.
Figure 31 shows a sketch map that is similar to the three-dimensional NAND gate flash structure among Figure 27, in this icon, shows to comprise in this serial that diode is formed between source electrode line structure and the storage serial.
Figure 32 is shown in the sequential sketch map of an example of the programming operation of the array among Figure 31.
Figure 33 A and Figure 33 B are the photograph of a part of tunnelling electron microscope of three-dimensional NAND gate flash memory.
Figure 34 is current/voltage (IV) performance plot of the polysilicon diode of experiment measuring.
Figure 35 reads current characteristics figure for the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Figure 36 is the programming suppression characteristic figure of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Figure 37 influences for program disturbance for the source electrode bias effect of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Figure 38 influences for program disturbance for the turn on gate voltage effects of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Figure 39 is the block erase switching current sketch map of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Figure 40 is the programming and the erase status current-voltage characteristic sketch map of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring, and this memory has different number mark program/erase cycle.
Figure 41 is the critical voltage distribution schematic diagram of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring, and this memory has the program/erase memory cell that check table distributes.
[main element symbol description]
10,110: insulating barrier
11～14,111～114: rectangular semi-conducting material
15,115: storage medium
16,17,116,117: lead
18,19,118,119: metal silicide
20,120: raceway groove
21～24,121～124: insulating material
25,26,125,126: active area
30～35,40～45,70～78,80,82,84: memory cell
51～56: rectangular semi-conducting material lamination
60 (60-1,60-2,60-3), 61,160～162: word line
86,87: source electrode line
90～95: zone-block selected transistor
97,397: tunnel dielectric layer
98,398: electric charge storage layer
99,399: stop dielectric layer
83: the serial selection wire
85,88,89: transistor is selected in serial
106,107,108: bit line
128,129,130: source/drain region
210,212,214: insulating barrier
211,213: semiconductor
215: storage material layer
250: ridge shape lamination
315: electric charge capture layer
225: lead
226,1426: metal silicide
875,975: integrated circuit
860: have the three-dimensional programmable resistance read-only memory array of diode in the storage serial
960: the three-dimensional NAND gate flash array of diode in the storage serial arranged
858,958: the plane decoder
859,959: the serial selection wire
861,961: column decoder
862,962: word line
863,963: row decoder
864,964: bit line
865,965,867,967: bus
866,966: sensing amplifier/data input structure
874,974: other circuit
869,969: state machine
868,968: bias voltage adjustment supply voltage
871,971: Data In-Line
872,972: DOL Data Output Line
410,1410: substrate
1412～1414: rectangular semi-conducting material
1415,1515: the zone
1425-1 is to 1425-n: lead
1427: serial selection wire SSL
1428: whole source electrode line GSL
The 1449:P+ injection zone
1450,1451,1550,1551: embolism
1491: electric conducting material
1492,1592: diode
1106: the serial selection wire
1110～1113: diode
1160～1162: lead
1170～1175,1180,1182: memory cell
1190,1191: ground connection is selected transistor
1196,1197: transistor is selected in serial
Embodiment
It is that collocation Fig. 1 describes to Figure 41 that embodiment below the present invention describes.
Fig. 1 shows the sketch map of one 2 * 2 memory cell part of a three-dimensional programmable resistance storage array, in the drawings packing material is omitted lamination and the lead of quadrature that constitutes the rectangular semi-conducting material of this cubical array with expression clearly.In this is graphic, only show two planes.Yet the number on plane can extend to very large number.As shown in fig. 1, this storage array is formed at has an insulating barrier 10 on the ic substrate of the semiconductor under it or other structure (not shown) top.This storage array comprises that the lamination 11,12,13,14 of a plurality of rectangular semi-conducting materials is each other by insulating material 21,22,23,24 separations.This lamination is that ridge shape and the Y direction in figure are extended, so rectangular semi-conducting material 11～14 can configuration be a bit line, and extends substrate.The bit line that rectangular semi-conducting material 11,13 can be used as on first memory plane, and the bit line that rectangular semi-conducting material 12,14 can be used as on second memory plane.One deck storage medium 15 for example is anti-fuse materials, in this example, is coated on the rectangular semi-conducting material, and in other example, is formed at the sidewall of rectangular semi-conducting material at least.Many leads 16,17 and these rectangular semi-conducting material lamination quadratures.Many lead 16,17 has and the surface of these rectangular semi-conducting material laminations along shape; And insert, and between rectangular semi-conducting material 11～14 laminations and many leads 16, the interface area of side surface plotted point part definition multiple tier array between 17 by among the defined raceway groove of these laminations (for example 20).Layer of metal silicide (for example tungsten silicide, cobalt silicide, titanium silicide) 18,19 is formed at the upper surface of many leads 16,17.
Fig. 2 is presented at lead 16 and the profile of rectangular semi-conducting material 14 confluces along memory cell Z-X plane.The both sides that active area 25,26 forms rectangular semi-conducting material 14 reach between lead 16 and rectangular semi-conducting material 14.In nature, anti-fuse storage material layer 15 has high resistance.After programming, this anti-fuse storage medium collapse causes one of interior active area 25,26 of anti-fuse storage medium or both to get back to a low resistance state.Among the described herein embodiment, each memory cell has the both sides that two active areas 25,26 form rectangular semi-conducting material 14.Fig. 3 is presented at lead 16,17 and the rectangular semi-conducting material 14 confluces profile along the memory cell X-Y plane.Show the current path of the word line of arbitrary routing of line 16 definition among the figure through anti-fuse storage material layer 15 to rectangular semi-conducting material 14.
Electronics mobile is to be shown by the dotted line among Fig. 3, gets into the rectangular semi-conducting material 14 of p types from n+ lead 16, and along rectangular semi-conducting material 14 (dotted arrow) to sensing amplifier, can measure to indicate the state of selected memory cell at the sensing amplifier place.In an exemplary embodiments, the silica that is to use about 1 nanometer thickness is as anti-fuse materials, and utilizes chip inner control circuit among Figure 17 to apply to comprise 5～7 volts of pulses and pulse duration to be about the programming pulse of 1 microsecond.And read pulse is to utilize chip inner control circuit among Figure 17 to apply to comprise 1～2 volt of pulse and the pulse duration relevant with configuration.This reads pulse can far be shorter than programming pulse.
Fig. 4 shows two memory cell planes, and each plane has six memory cell.These memory cell are indicated by the diode with the anti-fuse materials layer (dotted line representative) between negative electrode and anode to be represented.These two memory cell planes are by as the lead 60 of the first word line WLn and the second word line WLn+1 and 61 and define first and second layers of this array as first, second and the 3rd rectangular semi-conducting material lamination 51,52,53,54 of bit line BLn, BLn+1 and BLn+2 and 55,56 confluces respectively.First plane of memory cell is included in the memory cell 30,31 on the rectangular semi-conducting material lamination 52, in memory cell on the rectangular semi-conducting material lamination 54 32,33 and the memory cell on rectangular semi-conducting material lamination 56 34,35.Second plane of memory cell is included in the memory cell 40,41 on the rectangular semi-conducting material lamination 51, in memory cell on the rectangular semi-conducting material lamination 53 42,43 and the memory cell on rectangular semi-conducting material lamination 55 44,45.Shown in figure, lead 60 is as word line WLn, and it comprises that the material in the raceway groove between between lamination is corresponding among vertically extending 60-1,60-2,60-3 and Fig. 1, so that the rectangular semi-conducting material lamination of 3 illustrations in lead 60 and each plane is coupled.Array may be embodied to place like this and has many layers as describing, with constitute near or arrive the very highdensity memory of every chip megabit.
Fig. 5 shows the sketch map of one 2 * 2 memory cell part of a three-dimensional programmable resistance storage array, has packing material in the drawings with clearly expression and the lamination of the rectangular semi-conducting material that constitutes this cubical array and the lead relativeness of quadrature.In this is graphic, only show two-layer.Yet the number of level can extend to very large number.As shown in Figure 5, this storage array is formed at and has an insulating barrier 110 on the ic substrate of the semiconductor under it or other structure (not shown) top.This storage array comprises that the lamination 111,112,113,114 of a plurality of rectangular semi-conducting materials is each other by insulating material 121,122,123,124 separations.This lamination is that ridge shape and the Y direction in figure are extended, so rectangular semi-conducting material 111～114 can configuration be a bit line, and extends substrate.The bit line that rectangular semi-conducting material 111,113 can be used as on first memory plane, and the bit line that rectangular semi-conducting material 112,114 can be used as on second memory plane.
In first lamination between the insulating material 121 between rectangular semi-conducting material 111 and 112 and in second lamination insulating material 123 between rectangular semi-conducting material 113 and 114 have equivalent oxide thickness (EOT) more than or equal to about 40 nanometers, wherein equivalent oxide thickness (EOT) is that the thickness of this insulating material multiply by the oxidated layer thickness that the dielectric constant ratio of silica and insulating barrier is changed.Noun as used herein " about 40 nanometers " is the result who considers about 10% order of magnitude change in typical case's technology of installing like this.The interference between consecutive storage unit has significant effects to the thickness of this insulating barrier in this structure for reducing.In certain embodiments, the equivalent oxide thickness of insulating material (EOT) can minimum reach 30 nanometers and still can between adjacent layer, have enough isolation.
One deck storage medium 115 for example is the dielectric charge capturing structure, in this example, is coated on the rectangular semi-conducting material.Many leads 116,117 and these rectangular semi-conducting material lamination quadratures.Many lead 116,117 has and the surface of these rectangular semi-conducting material laminations along shape; And insert, and between rectangular semi-conducting material 111～114 laminations and many leads 116, the interface area of side surface plotted point part definition multiple tier array between 117 by among the defined raceway groove of these laminations (for example 120).Layer of metal silicide (for example tungsten silicide, cobalt silicide, titanium silicide) 118,119 is formed at the upper surface of many leads 116,117.
The metal oxide semiconductcor field effect transistor kenel of nano wire through provide nano wire or nano tube structure on lead 111～114 passage area and also become this kind mode by configuration; Paper " Impact of a Process Variation on Nanowire and Nanotube Device Performance " as people such as Paul; IEEE Transactions on Electron Device, Vo1.54, No.9; On September 11st～13,2007, draw at this and to be reference data.
Therefore, can form the SONOS kenel memory cell that configuration is the cubical array of NAND gate flash array.Source electrode, drain electrode and tunnel-shaped are formed in the rectangular semi-conducting material 111～114 of silicon, and storage material layer 115 comprises the tunnel dielectric layer 97 of silica (O), the electric charge storage layer 98 of silicon nitride (N), the lead 116,117 that stops dielectric layer 99 and polysilicon (S) of silica (O).
Rectangular semi-conducting material 111～114 can be a p type, semiconductor material and lead 116,117 can use identical or different semi-conducting material (for example p+ kenel).For example, rectangular semi-conducting material 111～114 can be a p type polysilicon, or p type epitaxial monocrystalline silicon, and lead 116,117 can use dense relatively doped p+polysilicon.
Alternatively, rectangular semi-conducting material 111～114 can be a n type, semiconductor material and lead 116,117 can use the semi-conducting material (for example p+ kenel) of identical or different conductivity.This n type, semiconductor material arrangement causes burying-charge capturing storage unit of the vague and general kenel of passage.For example, rectangular semi-conducting material 111～114 can be a n type polysilicon, or n type epitaxial monocrystalline silicon, and lead 116,117 can use dense relatively doped p+polysilicon.The doping content of the rectangular semi-conducting material of typical case's n type is about 10
18/ cm
3, the scope that can use embodiment is greatly about 10
17/ cm
3To 10
19/ cm
3Between.Using the rectangular semi-conducting material of n type is preferable selection for the embodiment that does not have knot, reaches so allow the higher electric current that reads because can improve along the conductance of NAND gate serial.
Therefore, this memory cell that comprises field-effect transistor has in the cubical array structure that charge storing structure is formed at this plotted point.Use the rectangular semi-conducting material and the conductor thickness of about 25 nanometer scale, and the spacing with ridge shape lamination also is about 25 nanometer scale, the device with tens of layers (for example 30 layers) can reach million (10 in single-chip
12) position capacity.
This storage material layer 115 can comprise other charge storing structure.For example, can use the SONOS charge storing structure of energy gap engineering (BE) to replace, it comprises dielectric tunnel layer 97, and when the 0V bias voltage, has the inverted U valence band between level.In one embodiment, this multilayer tunnel layer comprises that ground floor is called the tunneled holes layer, and the second layer is called can be with layer of compensation and the 3rd layer to be called separator.In this embodiment; Tunneled holes layer 97 comprises that silicon dioxide layer is formed at the side surface of rectangular semi-conducting material; It is capable of using like on-site steam generation (in-situ steam generation; ISSG) method forms, and optionally utilizes the nitric oxide annealing of deposition back or in deposition process, add nitric oxide production mode and carry out nitrogenize.The thickness of the silicon dioxide in the ground floor is less than 20 dusts, and is preferably less than 15 dusts, is 10 or 12 dusts in an exemplary embodiment.
In this embodiment, can be with layer of compensation to comprise silicon nitride layer is to be positioned on the tunneled holes layer, and it is that to utilize similarly be the technology of low-pressure chemical vapor deposition LPCVD, and (dichlorosilane, DCS) predecessor with ammonia forms to use dichlorosilanes down in 680 ℃.In other technology, can be with layer of compensation to comprise silicon oxynitride, it is to utilize similar technology and nitrous oxide predecessor to form.Can be with the thickness of the silicon nitride layer in the layer of compensation, and be preferably 25 dusts or littler less than 30 dusts.
In this embodiment, it is to be positioned to be with on the layer of compensation that separator comprises silicon dioxide layer, and it is that utilization similarly is that the mode that LPCVD high-temperature oxide HTO deposits forms.Silicon dioxide layer thickness in the separator is less than 35 dusts, and is preferably 25 dusts or littler.So three layers of tunnel dielectric layer have produced " fall U " valence band of shape can rank.
The valence band at first place can make electric field be enough to bring out tunneled holes through the thin zone between this first place and semiconductor body (or rectangular semi-conducting material) interface in rank; And its valence band that also is enough to promote behind first place can rank, with the tunneled holes phenomenon in the composite tunnel dielectric layer behind effective elimination first place.This kind structure; Except setting up this three layers of tunnel dielectric layer " fall U " valence band of shape; Also can reach the auxiliary high speed tunneled holes of electric field; It also can not exist or only bring out under the situation of little electric field for other operation purpose (similarly being from memory cell reading of data or the contiguous memory cell of programming) at electric field, effectively prevents charge loss to pass through through the composite tunnel dielectric layer structure.
In a representational device; Storage material layer 115 comprises energy gap engineering (BE) composite tunnel dielectric layer; Its thickness that comprises the silicon dioxide of ground floor is less than 2 nanometers, and the thickness of one deck silicon nitride layer is that the silicon dioxide layer thickness less than 3 nanometers and a second layer is less than 4 nanometers.In one embodiment; This composite tunnel dielectric layer comprises ultra-thin silicon oxide layer O1 (for example smaller or equal to 15 dusts), ultra-thin silicon nitride layer N1 (for example smaller or equal to 30 dusts) and ultra-thin silicon oxide layer O2 (for example smaller or equal to 35 dusts) and forms; And it can be under one 15 dust of starting at the interface of semiconductor body or rectangular semi-conducting material or littler compensation, and increasing about 2.6 electron-volts valence band can rank.Through low valence band ability zones, rank (high hole tunneling barrier) and high pass conduction band ability rank, the O2 layer can separate one second compensation (for example starting at about 30 dust to 45 dusts from interface) with N1 layer and electric charge capture layer.Because second place's distance interface is far away, the valence band that the electric field that is enough to bring out tunneled holes can improve behind second place can rank, so that it eliminates the tunneled holes potential barrier effectively.Therefore, the O2 layer is the auxiliary tunneled holes of electric interfering field seriously, can promote the ability that when hanging down electric field, blocks charge loss through engineering tunnelling dielectric structure simultaneously again.
The thickness that electric charge capture layer in the storage material layer 115 comprises silicon nitride layer in this embodiment is greater than 50 dusts, comprises for example, and the silicon nitride of about 70 dusts of thickness, and it is to utilize to form like the LPCVD mode.The present invention also can use other charge-trapping material and structure, comprises similarly being silicon oxynitride (Si
xO
yN
z), the nitride of high silicon content, the oxide of high silicon content, comprise seizure layer of embedded nano particle or the like.
The dielectric layer that stops in the storage material layer 115 is a silica in this embodiment, and its thickness is greater than 50 dusts, and is included in this embodiment Chinese style 90 dusts, and can use the wet furnace oxidation technology of silicon nitride being carried out the wet method conversion.The silica that then can use high-temperature oxide (HTO) or LPCVD depositional mode to form in other embodiments.Also can use other the dielectric layer material that stops for example is the high-k material of aluminium oxide.
In an exemplary embodiment, the thickness of the silicon dioxide in the tunneled holes layer is 13 dusts; Can with the silicon nitride layer thickness of layer of compensation 20 dusts; The silicon dioxide layer layer thickness of separator is 25 dusts; The silicon nitride layer thickness of electric charge capture layer is 70 dusts; And stop that dielectric layer can be the silica of thickness 90 dusts.The grid material of lead 116,117 can be p+ polysilicon (its work function is 5.1 electron-volts).
Fig. 6 is presented at the profile of the charge capturing storage unit of lead 116 and the formation of rectangular semi-conducting material 114 confluces along memory cell Z-X plane.Active area 125,126 forms the both sides of rectangular semi-conducting material 114 between lead 116 and rectangular semi-conducting material 114.In the described embodiment of Fig. 6, each memory cell is that the double gate field-effect transistor has the both sides that two active areas 125,126 form rectangular semi-conducting material 114.
Fig. 7 is presented at the profile of the charge capturing storage unit of lead 116 and the formation of rectangular semi-conducting material 114 confluces along the memory cell X-Y plane.Also show the current path that flow to rectangular semi-conducting material 114 among the figure.Flowing shown in dotted line among the figure of electronics is to flow to sensing amplifier along the rectangular semi-conducting material of p type, and it can be measured to indicate the state of selected memory cell.Between as the lead 116 of word line, source/drain region 128,129,130 between 117 being " not having knot ", just the dopant profile of source/drain electrode need be not different with the dopant profile of passage area under the word line.In this embodiment that " does not have knot ", the charge-trapping field-effect transistor can have p type channel design.In addition, in certain embodiments, the doping of source/drain electrode can utilize the mode of aiming at injection automatically to form after the definition word line.
In alternate embodiment; Rectangular semi-conducting material 111～114 can use shallow Doped n-type semiconductor body in the arrangement of " not having knot "; Cause forming burying-the channel field effect transistor of can under depletion-mode, operating, this charge capturing storage unit has nature and is offset to lower critical voltage distribution.
Fig. 8 shows two memory cell planes, and each plane has 9 charge capturing storage units and is arranged to the NAND gate configuration, and it is the representative illustration of a square, can comprise many planes and many word lines.These two memory cell planes are by the lead 160,161 and 162 as word line WLn-1, WLn and WLn+1, and it is respectively first, second and the 3rd rectangular semi-conducting material lamination.
First plane of memory cell comprises that memory cell 70,71 and 72 is in a NAND gate serial; And be positioned on the rectangular semi-conducting material lamination; And memory cell 73,74 and 75 is in a NAND gate serial; And be positioned on the rectangular semi-conducting material lamination, and memory cell 76,77 and 78 is in a NAND gate serial, and is positioned on the rectangular semi-conducting material lamination.In this illustration, second plane of memory cell is corresponding with cubical baseplane, and comprises that the mode that memory cell (for example 80,82 and 84) utilization is similar to first plane is arranged in the NAND gate serial.
Shown in figure; Lead 161 as word line WLn comprises the vertical extent part; Its with Fig. 5 in the raceway groove 120 between lamination material corresponding, so that the memory cell of the interface area in the raceway groove between between rectangular semi-conducting material in lead 161 and all planes (for example in first plane 71,74 and 77 of memory cell) is coupled.
Bit line and source electrode line are the opposite ends that is positioned at this storage serial.Bit line 106,107 is connected to the different laminations in the storage serial with 108 controls through bit line signal BLn-1, BLn and BLn+1.The NAND gate serial of the source electrode line 86 termination poincare half planes of in this arranges, controlling by signal SLn.The NAND gate serial of the source electrode line 87 termination lower half-planes of in this arranges, controlling similarly, by signal SLn+ 1.
In this arranged, serial selected transistor 85,88 and 89 to connect between separately NAND gate serial and bit line BLn-1, BLn and BLn+1.Serial selection wire 83 is parallel with word line.
In this arranged, zone-block selected transistor 90～95 coupled one of NAND gate serial and source electrode line.In this example, ground connection selection wire GSL is connected with zone-block selected transistor 90～95, and can use the mode that is similar to lead 160,161 and 162 to implement.In certain embodiments, this serial select transistor and zone-block selected transistor can use with memory cell in the identical dielectric lamination of gate oxide.In other embodiment, can use typical gate oxide to replace.In addition, passage length and width can be looked the needs of design and adjust to provide these transistors suitable handoff functionality.
Fig. 9 shows an alternative structure sketch map that is similar to Fig. 5, uses identical reference number in the drawings in the similar structures, and no longer describes.Fig. 9 and Fig. 5 different portions are that the side surface 113A, 114A of surperficial 110A and the rectangular semi-conducting material 113,114 of insulating barrier 110 exposes out after etching forms word line between as the lead of word line (for example 160).Therefore, storage material layer 115 etching and can not have influence on operation wholly or in part between word line.Yet, in some structure, do not need general etching as described herein to form the dielectric charge capturing structure through storage material layer 115.
Figure 10 shows the profile of the memory cell of similar Fig. 6 along the Z-X plane.Figure 10 and Fig. 6 are identical, the structure in displayed map 9 memory cell, and the profile of the structure of in this profile, implementing with Fig. 5 is identical.Figure 11 shows the profile of the memory cell of similar Fig. 7 along X-Y plane.Figure 11 and Fig. 7 different portions are that the storage medium among regional 128a, 129a and the 130a of the side surface (for example 114A) along rectangular semi-conducting material 114 is removed.
Figure 12 shows the basic technology stage flow chart of implementing three-dimensional storage array as described herein to Figure 16, and it only uses 2 array to constitute and aims at the very pattern mask step of key influence.In Figure 12, show intertonguing insulating barrier 210,212,214 and semiconductor layer 211,213 structure afterwards, for example semiconductor layer can use the doped semiconductor of comprehensive deposition to be formed at the array region of chip.According to the difference of embodiment, semiconductor layer can use polysilicon or the epitaxial monocrystalline silicon with n type or the doping of p type.Interlayer insulating film 210,212,214 can for example use silicon dioxide, other silica or silicon nitride.These layers can use many different modes to form, and comprise the technology such as low-pressure chemical vapor deposition (LPCVD) that industry is known.
Figure 13 shows the result of the first lithographic patterning step, and it is used for defining the rectangular semi-conducting material lamination 250 of a plurality of ridge shapes, and wherein this rectangular semi-conducting material is to be constituted and separated by insulating barrier 210,212,214 by semiconductor layer 211,213.Raceway groove with very dark and very high depth-to-width ratio can be formed at multilayer laminated between, it is to use the technology that is lithographically the basis and applies the carbon containing hard mask and reaction equation ion etching.
Figure 14 A and Figure 14 B show respectively and comprise for example to be the programmable resistance storage organization of anti-fuse storage unit structure and to comprise it for example being the profile in next stage among the charge-trapping storage organization embodiment able to programme of silica nitrogen-oxygen-silicon (SONOS) kenel memory cell structure.
Figure 14 A shows the result after the programmable resistance storage organization embodiment that comprises the anti-fuse storage unit structure of individual layer as shown in Figure 1 deposits a storage medium 215 comprehensively.Alternatively, can carry out oxidation technology and do not use comprehensive deposition to form oxide in the exposed side of rectangular semi-conducting material, wherein oxide is as storage medium.
Figure 14 B shows the programmable resistance storage organization embodiment result behind deposition one storage medium 315 comprehensively comprise multilayer charge-trapping structure as shown in Figure 4, and this multilayer charge-trapping structure comprises a tunnel layer 397, an electric charge capture layer 398 and a barrier layer 399.Shown in Figure 14 A and Figure 14 B, storage material layer the 235, the 315th utilizes along the shape mode to be deposited on the rectangular semi-conducting material lamination (250 among Figure 13) of ridge shape.
Figure 15 shows the result after electric conducting material is filled high-aspect-ratio raceway groove step, and this electric conducting material can for example be to have n type or the doping of p type, is used as the lead of word line, is deposited with cambium layer 225.In addition, in the embodiment that uses polysilicon, one deck silicide 226 is formed on the layer 225.Shown in figure, for example the high-aspect-ratio deposition techniques such as polysilicon of low-pressure chemical vapor deposition (LPCVD) use filling the raceway groove between between ridge shape lamination in this embodiment, even very narrow 10 nanometer scale raceway grooves with high-aspect-ratio are also feasible.
Figure 16 figure shows the result of the second lithographic patterning step, and it is used for defining in this three-dimensional storage array the many leads 260 as word line.This second lithographic patterning step is used the critical dimension of etching high-aspect-ratio raceway groove between between lead in this array of single mask definition, and need not execute the lamination of carving through the ridge shape.Polysilicon can use the etching technics that has polysilicon and silica or silicon nitride high selectivity to carry out etching.Therefore, alternatively etching technics can carry out by the use mask identical with etching semiconductor and insulating barrier, and this technology can stop at bottom insulation layer 210.
One optionally processing step comprise and form hard mask on many leads that these leads comprise word line, ground connection selection wire and serial selection wire.The material that this hard mask can use thick relatively nitride or other can blocks ions to inject forms.After hard mask forms, can carry out ion and inject increasing the doping content of rectangular semi-conducting material, and therefore reduce the resistance on the rectangular semi-conducting material current path.Through using control to inject energy, injection can cause passing the rectangular semi-conducting material in the end, and each in lamination above rectangular semi-conducting material.
Afterwards, removing hard mask exposes out with the silicide above the many leads.After an interlayer dielectric layer was formed at the array top, interlayer hole was formed and for example uses the embolism of tungsten to be filled in wherein.Be patterned and be connected as the upper metal line of bit line BL with decoding circuit.A three-dimensional decoding circuit is set up with the mode in scheme, uses a word line, a bit line, reaches the one source pole line and come access one to choose memory cell.Can consult title and be No. the 6906940th, the United States Patent (USP) of " Plane Decoding Method and Device for Three Dimensional Memories ".
For the selected negate fuse-type attitude memory cell of programming; Selected in this embodiment word line is biased to-7V; Do not choose word line and can be set at 0V, selected bit line also can be set at 0V, does not choose bit line and can be set at 0V; Selected source electrode line can be set at-3.3V, can not be set at 0V and choose source electrode line.In order to read a selected memory cell; Selected in this embodiment word line is biased to-1.5V; Do not choose word line and can be set at 0V, selected bit line also can be set at 0V, does not choose bit line and can be set at 0V; Selected source electrode line SL can be set at-3.3V, can not be set at 0V and choose source electrode line.
Figure 17 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 875 comprises using to have three-dimensional programmable resistance read-only memory described herein (RRAM) array 860 on the semiconductor substrate.One column decoder 861 couples and electrically links up with many word lines 862 along storage array 860 column direction arrangements.Row decoder 863 passes to the electrical ditch of the multiple bit lines of arranging along storage array 860 line directions 864 (or described before serial selection wire) memory cell from array 860 is read and the programming data operation.One plane decoder 858 therewith on array 860 planes before the capable selection wire 859 of described subject string (or described before bit line) couple.The address is to offer row decoder 863, column decoder 861 and plane decoder 858 by bus 865.Sensing amplifier in the square 866 and data input structure couple via data/address bus 867 and row decoder 863.Data offer Data In-Line 871 by the input/output end port on the integrated circuit 875, perhaps by the data source of integrated circuit 875 other inner/outer, input to the data input structure in the square 866.Other circuit 874 is contained within the integrated circuit 875, and is for example general with purpose processor or specific purposes application circuit, or module combinations is to provide the system single chip function of being supported by the programmable resistance memory cell array.Data, are provided to integrated circuit 875 via DOL Data Output Line 872 by the sensing amplifier in the square 866, or provide to other data terminal of integrated circuit 875 inner/outer.
Employed in the present embodiment controller has been to use bias voltage adjustment state machine 869, and has controlled by voltage source of supply or square 868 and produce or the application of the bias voltage adjustment supply voltage that provides, for example reads and program voltage.This controller specific purposes logical circuit capable of using and using is known like those skilled in the art.In alternate embodiment, this controller has comprised general purpose processor, and it can make in same integrated circuit, the operation of control device to carry out a computer program.In another embodiment, this controller is to be combined by specific purposes logical circuit and general purpose processor.
Figure 18 shows the rough schematic view of integrated circuit according to an embodiment of the invention.Wherein integrated circuit 975 comprises using to have three-dimensional NAND gate flash array array 960 described herein on the semiconductor substrate.One column decoder 961 couples and electrically links up with many word lines 962 along storage array 960 column direction arrangements.Row decoder 963 passes to the electrical ditch of the multiple bit lines of arranging along storage array 960 line directions 964 (or described before serial selection wire) memory cell from array 960 is read and the programming data operation.One plane decoder 958 therewith on array 960 planes before described serial selection wire 959 (or described before bit line) couple.The address is to offer row decoder 963, column decoder 961 and plane decoder 958 by bus 965.Sensing amplifier in the square 966 and data input structure couple via data/address bus 967 and row decoder 963.Data offer Data In-Line 971 by the input/output end port on the integrated circuit 975, perhaps by the data source of integrated circuit 975 other inner/outer, input to the data input structure in the square 966.In this illustrative embodiments, other circuit 974 is contained within the integrated circuit 975, and is for example general with purpose processor or specific purposes application circuit, or module combinations is to provide the system single chip function of being supported by the NAND gate flash array.Data, are provided to integrated circuit 975 via DOL Data Output Line 972 by the sensing amplifier in the square 966, or provide to other data terminal of integrated circuit 975 inner/outer.
Employed in the present embodiment controller has been to use bias voltage adjustment state machine 969; And controlled by voltage source of supply or square 868 and produce or the application of the bias voltage adjustment supply voltage that provides, for example read, programme, wipe, erase verification and program verification voltage.This controller specific purposes logical circuit capable of using and using is known like those skilled in the art.In alternate embodiment, this controller has comprised general purpose processor, and it can make in same integrated circuit, the operation of control device to carry out a computer program.In another embodiment, this controller is to be combined by specific purposes logical circuit and general purpose processor.
Figure 19 is the profile of a part of tunnelling electron microscope of 8 layers of vertical channel thin-film transistor energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) charge-trapping NAND gate device, and it is made, tests and arrange decoding with the mode that becomes Fig. 8 and Figure 23.This device is to utilize half spacing of 75 nanometers to form.Its passage is the n type polysilicon of about 18 nanometer thickness.Do not carry out extra knot injection and form no junction structure.Between semiconductor strips, being used for the insulating material of channel isolation is in Z-direction, and it is the silica that thickness is about 40 nanometers.The grid that is provided is the P+ polysilicon lines.This serial selection and grounding selection device have the passage length longer than memory cell.This testing apparatus has 32 word lines, does not have the NAND gate serial of knot.Because the employed channel etching of structure has the shape of inclination shown in forming; Have apart from wide silicon line in the bottom of raceway groove; And the insulating material between fine rule is etched manyly apart from polysilicon, so the width system of below fine rule is also wideer than the width of top fine rule among Figure 19.
Figure 20 shows to have the memory cell profile of diode (for example diode 1492) in this NAND gate serial semiconductor body among the embodiment.This structure comprises a plurality of ridge shape laminations, and it comprises that rectangular semi-conducting material 1414,1413,1412 is on the substrate on ridge shape lamination plane separately.Many are passed through with lamination quadrature and extension to 1425-n (for only showing two among the figure for simplicity) as the lead 1425-1 of word line, and as before described along shape be formed on the accumulation layer.As the lead of serial selection wire SSL 1427 and lead 1428 and other the line like this of source electrode line GSL are arranged to parallel with many leads as word line as a whole.It for example is that the electric conducting material 1491 with n type or p type DOPOS doped polycrystalline silicon forms that these leads can utilize, and uses for the lead that is used as word line.Silicide layer 1426 can be formed on the many leads as word line, serial selection wire SSL and whole source electrode line GSL.
In zone 1415, rectangular semi-conducting material 1414,1413,1412 is connected with other rectangular semi-conducting material in the same level via whole source electrode line interconnect, reaches to be connected with a plane decoder (not shown).Described ladder contact area and in whole source electrode line interconnect, extending before rectangular semi-conducting material is to use.
Diode (for example 1492) is positioned over the memory cell that is connected to 1425-n with lead 1425-1 and the embolism 1450 that bit line BLn and BLn+1 are connected with rectangular semi-conducting material 1414,1413,1412, between 1451.In this example illustrated, diode is to be formed by the P+ injection zone in the rectangular semi-conducting material (for example 1449 ).Embolism 1450,1451 can comprise DOPOS doped polycrystalline silicon, tungsten or other vertical interior interconnection technique.Top bit line BLn and BLn+1 connect between embolism 1450,1451 and column decode circuitry (not shown).
In structure shown in Figure 20, serial that need be in array is selected to form on grid and the common source selection grid and is contacted.
Figure 21 shows two memory cell planes, and each plane has 6 charge capturing storage units and is arranged to the NAND gate configuration, and it is the representative illustration of a square, can comprise many planes and many word lines.These two memory cell planes are by the lead 1160,1161 and 1162 as word line WLn-1, WLn and WLn+1, and it is respectively first, second and the 3rd rectangular semi-conducting material lamination.
First plane of memory cell comprises that memory cell 1170,1171 and 1172 is in a NAND gate serial; And be positioned on the rectangular semi-conducting material lamination; Reach memory cell 1173,1174 and 1175 in a NAND gate serial, and be positioned on the rectangular semi-conducting material lamination.In this illustration, second plane of memory cell is corresponding with cubical baseplane, and comprises that the mode that memory cell (for example 1182 and 1184) utilization is similar to first plane is arranged in the NAND gate serial.
Shown in figure; Lead 1161 as word line WLn comprises the vertical extent part; Its with Fig. 5 in the raceway groove 120 between lamination material corresponding, so that the memory cell of the interface area in the raceway groove between between rectangular semi-conducting material in lead 1161 and all planes (for example in first plane 1171,1174 of memory cell) is coupled.
Serial selects transistor 1196,1197 to connect between separately NAND gate serial and bit line BL1 and BL2.Similarly, in this arranged, the similar serial in this square baseplane selected transistor to connect between separately NAND gate serial and bit line BL1 and BL2, made the row decoding put on these bit lines.Serial selection wire 1106 selects transistor 1196,1197 to be connected with serial, and parallel with word line, as shown in Figure 20.
In this example, diode 1110,1111,1112,1113 is connected between this serial and the corresponding bit lines.
Ground connection is selected transistor 1190,1191 to be arranged in the opposite side in this NAND gate serial and is used for coupling at this a NAND gate serial and the common source utmost point reference line chosen in the layer.This common source reference line is the plane decoder for decoding in the structure thus.Ground connection selection wire GSL can use the mode that is similar to lead 1160,1161 and 1162 to implement.In certain embodiments, this serial select transistor and ground connection select transistor can use with memory cell in the identical dielectric lamination of gate oxide.In other embodiment, can use typical gate oxide to replace.In addition, passage length and width can be looked the needs of design and adjust to provide these transistors suitable handoff functionality.Below will describe programming operation, wherein Destination Storage Unit is the storage unit A among Figure 21, and respectively can to the representative with Destination Storage Unit A at same level/source electrode line and same column/word line; But the memory cell B of different rows/bit line; To with Destination Storage Unit A at same lines/bit line and same column/word line, but the memory cell C of Different Plane/source electrode line, to Destination Storage Unit A at same column/word line; But the memory cell D of different rows/bit line and Different Plane/source electrode line; To with Destination Storage Unit A at same level/source electrode line and same lines/bit line, but the memory cell E of different lines/word line considers the disturbed condition of memory cell.
Arrange according to this, this serial selection wire and common source selection wire can be in a cube be that the mode on basis is deciphered with the cube.This word line can be deciphered with the mode of classifying the basis as in row.This common source line can be in a plane be that the mode on basis is deciphered with the plane.This bit line can the mode with behavior base be deciphered in delegation.
Figure 22 shows the sequential sketch map of the programming operation that is similar to the array among Figure 20.Be divided into three main sections that are denoted as T1, T2 and T3 between this programming area.When the first of T1, ground connection selection wire GSL in this cube and the common source line CSL that does not choose (be shown in and be denoted as SL among the figure) are set to VCC, and its common source line CSL that approximately is 3.3V chooses then is retained in about 0V.In addition, this serial selection wire SSL also is retained in about 0V.So can reach the coupling effect of The selected flat and 0V and the plane of not choosing is suspension joint, causes difference between common source line of not choosing and common source selection wire to be not enough to open the grid of common source selection wire.After a bit of change-over time, in this circuit do not choose word line and other turn on gate (for example false word line and select grid) be coupled to one be about 10V turn-on voltage.Similarly, this chooses word line and is coupled to identical or approaching magnitude of voltage, and ground connection selection wire GSL and the common source line CSL that do not choose are retained in VCC.So can cause this square not choose the self-voltage rise effect of the body region in the plane.See also Figure 21, memory cell C and D have the voltage rise zone because of the result of this operation in interval T1.
In the T2 section, ground connection selection wire GSL and the common source line CSL that does not choose change back to 0V, and word line and turn on gate are retained in conducting voltage.After ground connection selection wire GSL and the common source line CSL that do not choose changed back to a bit of time of 0V, the serial selection wire SSL in this cube was converted to VCC, its can be as before described about 3.3V.Similarly, the bit line of not choosing also is converted to VCC.The bias voltage result of T2 in the time can cause at same level/source electrode line and same column/word line; But the passage of the memory cell of different rows/bit line (like memory cell B) and at same column/word line, but the passage of the memory cell of different rows/bit line and Different Plane/source electrode line (like memory cell D) is boosted through self-voltage rise.The channel voltage that boosts of memory cell C can not leaked by bit line BL because of this diode of meeting.After the T2 paragraph, serial selection wire SSL and the bit line of not choosing change back to 0V.
In the T3 section; After ground connection selection wire GSL and the common source line CSL that do not choose change back to 0V; It for example is the read/program potential of 20V that the voltage of choosing word line is promoted to one, and serial selection wire SSL, ground connection selection wire GSL, choose bit line, do not choose bit line, the common source line CSL that chooses and the common source line CSL that does not choose remain on 0V.Meeting forms the passage of a counter-rotating in the selected memory cell in the time of T1 and T2 section, even and therefore under the situation that serial is selected grid and selected the common source grid all to close, also can reach programming.Should be noted that with Destination Storage Unit A at same level/source electrode line and same lines/bit line, but the memory cell E of different lines/word line only can be applied to because of conducting voltage and not choose word line and be interfered.So the conducting voltage that is applied must enough low (for example less than 10V) be interfered to prevent the data that are stored in these memory cell.
After between programming area, all voltage is all got back to about 0V.
Different embodiments of structure is used drain electrode end (bit line) forward-sense among Figure 20.In various embodiment, this diode is in reading and programming and suppress lost current path when suppressing to operate.
Figure 23 shows the bias condition sketch map of the read operation that is similar to the array among Figure 20.Show the bias condition put on structure on the substrate 410 according to Figure 23, the memory cell in the cube on the plane read bias voltage for applying conducting voltage to not choosing word line, reach one and read reference voltage and be applied to one and choose word line.The common source line CSL that chooses and about 0V couple, and the common source line CSL that does not choose and about VCC couple, and ground connection selection wire GSL in this cube and serial selection wire SSL all couple with about 3.3V.Bit line BLn in this cube and BLn+1 then couple with the precharge class that is about 1.5V.
Page decoding in this example can be reached through the plane decoding of using common source line.Therefore, to a given bias condition, because common source line that each is chosen in the cube or plane have the page that the bit line that can be read has the identical bits number.The common source line CSL that chooses and about 0V couple or are set at reference voltage, and other common source line CSL then is set at about 3.3V.In the case, the common source line of not choosing is a suspension joint.Diode to not choosing up line path, plane prevents divergence.
In page read operation, each the bar word line on each plane in the cube is read once.Similarly, be that this programming rejection condition must be enough to the required programming number of times of this page program of the program of bearing in the programming operation on basis with the page in one, promptly each plane is once.Therefore, as far as a cube that comprises 8 memory cell, the programming rejection condition of not choosing memory cell must be enough to bear 8 program cycles.
Must be noted that the bias voltage that diode in this bit line serial need be online with the position slightly promotes the typical pressure drop of about 0.7V with the compensation diode.
Figure 24 shows the bias condition sketch map of a cubical erase operation.According to the bias condition that Figure 24 shows, word line and for example is-negative voltage of 5V couples, and common source line CSL and bit line and one for example be+positive voltage of 8V couples, reach ground connection selection wire GSL and for example to be+the suitable high break-over voltage of 8V couples.The puncture yardstick that so can suppress the source electrode line bias voltage.The ground connection selection wire GSL of other block and serial selection wire SSL then close.The required high voltage of bit line then can be satisfied by the bit line driver design.Alternatively, word line and serial selection wire can ground connection common source line CSL and ground connection selection wire GSL then for example be with one+high voltage of 13V couples.
Figure 25 shows an alternate embodiment, and wherein diode 1492 is to use the polysilicon plug 1550,1551 that is formed by the coordination p+ doping of using when forming embolism to form.In the case, diode is self-aligning and can reduce processing step.Other structure is identical with shown in Figure 20 then.In less than 40 nanometers the time, can use and reverse contact structures layout (like Figure 27).
When self-voltage rise, this PN diode must bear the channeling potential that boosts of an about 8V in tens of milliseconds.Estimation leakage current when the 8V reverse biased should be less than 100pA to bear this current potential that boosts.Certainly, disruptive potential should be far above 8V.A difficulty that helps prevent sensing than low turn-on voltage (approximately less than 0.7V).
Figure 26 shows an alternate embodiment, and wherein diode is the common source line CSL end that is placed on the memory cell serial.Therefore, in zone 1515, the source electrode line in each plane is coupled in together through p+ line or doping, in formation PN diode between the common source line decoder of each bar string line and the ground connection selection wire GSL.Other structure is identical with shown in Figure 20 then.
Different embodiments of structure is used the reverse sensing of source terminal (source electrode line) among Figure 26.In various embodiment, this diode is in reading and programming and suppress lost current path when suppressing to operate.
Figure 27 shows a cubical sketch map, in this icon, shows two planes of memory cell, corresponding common source line CSL0 and common source line CSL1; Two row of memory cell; Corresponding bit line BL0 and bit line BL1, four of memory cell is listed as, and corresponds respectively to the word line in graphic.Serial selection wire SSL in this cube and serial select grid to couple, and ground connection selection wire GSL and ground connection select grid to couple.Described self-voltage rise programming operation is used for programming before being similar to, and it has two stage program voltages and is applied to selected word line and can describes in more detail in following.Diode is coupled to corresponding memory cell serial together with between source electrode line CSL0 or the common source line CSL1.
In following discussion, regional bit line is another noun in expression one serial.In this structure, all common source line CSL can apply high voltage to suppress programming.When the common source line CSL that chooses became low level, the high voltage of regional bit line can not become low level.Which memory cell page buffer can determine to be programmed.When bit-line voltage is VDD, can not programme.When bit-line voltage is ground connection, then can programme.
As far as a NAND gate flash memory cell, can use Fu Le-Nuo Dehan electron tunneling that selected memory cell is programmed.In order to suppress the non-programming of choosing memory cell, should apply the high voltage so far regional bit line or the passage of memory cell.Suppress in order to reach programming, can apply programmed sequence like Figure 28 and Figure 29.
This programming operation comprises and applies high voltage to the common source line do not chosen, and applies VCC (about 3.3V) and extremely do not choose bit line.When word line changed to VCC or high-tension conducting voltage, the regional bit line of not choosing bit line was promoted to high voltage.The regional bit line of choosing bit line can be forced by common source line and be pulled to high voltage or by the bit line common source line to ground that is compelled to leave behind.When the word line of selected memory cell changed to read/program potential, all regional bit lines are suspension joint all.The electric energy that when programming operation, is applied must be enough to make by one do not choose bit line any electric current of causing of a zone online voltage class in position (from the VCC/ high voltage to ground) can not impact or cause the program disturbance situation to take place programming.
Figure 28 shows the programmed sequence of a five-stage.In step 1, the ground connection selection wire is opened ground connection and is selected grid, and the serial selection wire is closed serial selection grid.The high voltage of not choosing common source line is not to choosing regional bit lines charged in the plane to high voltage in this cube.The word line voltage of all word lines is raised to one first word line voltage.In step 2, the regional bit line of not choosing in the row applies the supply current potential to not choosing bit line and will choosing bit line ground connection through serial being selected the grid unlatching and being selected grid to close ground connection.In step 3, word line is biased to next conducting voltage and serial selects grid to be held open and ground connection selects grid to keep shut.So cause regional bit line and high voltage in the chosen area bit line not to couple.In step 4, share and choose regional bit lines charged that bit line and do not choose common source line to high voltage.In this stage, the serial selection wire is closed and the unlatching of ground connection selection wire.In step 5, word line voltage is biased to program voltage and serial selection wire and ground connection selection wire keep shut.
Figure 29 shows an alternative five-stage programmed sequence.In step 1, all regional bit lines are recharged to high voltage via the common source line in the bias voltage cube to high voltage, and the ground connection of opening in this cube is selected grid, and close serial and select grid.Afterwards, the ground connection of closing in this cube is selected grid, and opens serial and select grid, and it can drive regional bit line in the chosen area bit line to ground voltage.
In step 3, word line is biased to a conducting voltage and serial selects grid to be held open and ground connection selects grid to keep shut.So cause regional bit line in the chosen area bit line to keep ground connection and the regional bit line suspension joint in the chosen area bit line and not by boosting word line.In step 4, select grid through the ground connection of opening in this cube, and close serial and select grid to not choosing the common source line bias voltage, choosing regional bit lines charged that bit line and do not choose common source line to high voltage.In step 5, choose that word line receives program voltage and serial selects grid and ground connection to select grid to keep shut.Algorithm among Figure 29 can have preferable lifting suppression characteristic and consume more power compared to Figure 28.Can improve from high voltage from lifting region bit line LBL3 and promote to suppress the result, regional bit-line voltage like this can be higher and improved inhibition.By common source line change to high voltage and be discharged to ground the result can increase power consumption.
Therefore, in this operating technology, can suppress programming from the high voltage that source electrode line applied.When program voltage was applied in selected bit line and does not choose source electrode line and left behind to ground, this bit line that is programmed was a suspension joint.In addition, this bias voltage sequence is to apply to keep the mode that suppresses to programme of correctly boosting.When programming, be to get back to common source to prevent electric current with the current path of diode.
Because common source line is whole, common source line can once get final product whole array decoding.Relative, decoding serial selection wire then needs extra serial selection wire driver and contact area.
In various embodiment, number to each block that the storage array of this diode decoding reduces serial selection wire grid has only a serial selection wire structure, or each NAND gate serial has only a serial selection wire grid.So structure significantly reduces the difficulty in process degree, and has high symmetry and micro property.Do not need a large amount of serial selection wires during the memory cell number of layers of this framework in increasing three-dimensional storage array.Similarly, also only need a ground connection selection wire in a block.
This three-dimensional perpendicular gate devices is preferably used thin-film transistor energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) device.On the other hand, also can develop anti-fuse of use or the similar device of other memory technology (for example using other charge trapping devices) with high-dielectric coefficient dielectric layer.
Figure 30 shows the sequential sketch map of another example programming operation that is similar to the array among Figure 21.
When the T1 phase place, this source electrode line is through ground connection selection wire GSL and do not choose the online Vcc of source electrode and boosted by the oneself.
When the T2 phase place, this does not choose bit line through serial selection wire SSL and do not choose the online high voltage HV in position and boosted to high voltage HV.The channel voltage Vch of memory cell B also is raised.The channel voltage Vch that memory cell C is raised can not leak because of the diode on this bit line BL.
When the T3 phase place, storage unit A is programmed.Its inverting channel just forms when the T1 phase place.
Figure 31 shows a sketch map that is similar to the three-dimensional NAND gate flash structure among Figure 27, in this icon, shows to comprise in this serial that diode is formed between source electrode line structure and the storage serial.The position of these diodes can be used for supporting that programming suppresses.
Destination Storage Unit is the storage unit A among the figure; And will consider the disturbed condition of following memory cell: memory cell B representative and Destination Storage Unit A at same level/source electrode line and same column/word line; But the memory cell of different rows/bit line; Memory cell C representative and Destination Storage Unit A are at same lines/bit line and same column/word line; But the memory cell of Different Plane/source electrode line, memory cell D representative and Destination Storage Unit A are at same column/word line, but the memory cell of different rows/bit line and Different Plane/source electrode line; Memory cell E representative and Destination Storage Unit A are at same level/source electrode line and same lines/bit line, but the memory cell of different lines/word line.Memory cell E is switched on voltage Vpass interference and can ignores in many examples.
Figure 32 shows the sequential sketch map of an example programming operation that is similar to the array among Figure 31.
When the T1 phase place, this does not choose bit line (memory cell B and D) through serial selection wire SSL and do not choose position online voltage vcc and being boosted by the oneself.
When the T2 phase place, this does not choose source electrode line through ground connection selection wire GSL and do not choose the online high voltage HV of source electrode and boosted to high voltage HV.For example the channel voltage Vch that does not choose source electrode line of memory cell C is also directly promoted.When the voltage of source electrode line SL was 0V and ground connection selection wire GSL unlatching, for example the channel voltage Vch that has been raised of memory cell B can not leak because of the less electric leakage of the diode of the last reverse biased of this source electrode line SL.
When the T3 phase place, be still and be programmed though serial selection wire SSL is closed storage unit A.Its inverting channel just forms when the T1 phase place.
Figure 33 A and Figure 33 B are the photograph of a part of tunnelling electron microscope of three-dimensional NAND gate flash memory.
Be shown among the figure is the tunnelling electron micrograph of the virtual ground device of 75 nanometers, half spacings (4F2).Its channel width and length are respectively 30 and 40 nanometers, and channel height is 30 nanometers.Each device is the vertical channel device of bigrid (vertical gate), and wherein passage (burying lane device) is that shallow doped n type reads electric current with increase.The profile of this bit line BL is the shape that is fit to use plane ONO.Through this technology of suitable allotment to obtain less side walls collapse.And form a very smooth ONO at the sidewall of this bit line BL.
Figure 33 A is the profile of array on X-direction for this reason.Show among the figure that two charge-trapping energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) devices are formed at the sidewall of each passage.Each device is a double gate device.Channel current is flatly mobile, and grid is vertically to arrange.Has minimum ONO side walls collapse.
Figure 33 B is the profile of array on Y direction for this reason.Owing to spacing that tightens and less bitline width, the demonstration of the tunnelling electron micrograph of FIB comprises that polysilicon gate upward reaches the Dual Images of spacing in bit line (horizontal semiconductor strips).Its passage length of device in the icon approximately is 40 nanometers.
Figure 34 is current/voltage (IV) performance plot of the polysilicon diode of experiment measuring.
The forward of polysilicon PN diode and reverse current voltage (IV) characteristic are directly from the PN diode measurement that is connected with the three-dimensional NAND gate array of virtual ground NAND gate vertical gate.The height/width of this polysilicon is of a size of 30/30 nanometer.Leakage current-8 is far below 10pA, and it has met the demand that the oneself is boosted and helped to eliminate program disturbance.Apply source electrode bias voltage Vs, and the conducting voltage Vpass of 7V is on all word lines.This P+-N diode (30 nano-widths and 30 nanometer height) shows above 6 quantity and above successful On/Off ratio.This forward current is clamped down on by NAND gate serial series resistance.
Figure 35 reads current characteristics figure for the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
This three-dimensional NAND gate memory has 32 word lines.The Vpass of word line and Vread voltage are all 7V.Source electrode line voltage Vsl then changes in following numerical value: 2.5V, 2.0V, 1.0V, 0.5V and 0.1V.In this icon, source electrode line voltage Vsl causes suitable current sensor when surpassing 1.0V.What be applied to source terminal reads voltage (source terminal detection technology), is a positive voltage in the case.Required bias voltage PN diode thus promotes, and it needs enough cut-in voltages, makes the source electrode bias voltage that surpasses 1.5V just can produce enough electric currents that reads.
Figure 36 is the programming suppression characteristic figure of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
The typically programming suppression characteristic that shows storage unit A, B, C, D among the figure.In the case, Vcc=3.3V, HV=8V, Vpass=9V.In storage unit A is to apply to increase progressively step-by-step impulse ISSP method.Between this graphic interference-free coverage area that demonstrates above 5V.So be to cause by Diode Insulation Properties.
Figure 37 influences for program disturbance for the source electrode bias effect of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Source electrode line suppresses bias voltage (HV) and has influence for the program disturbance interval.Can minimum be reduced in the interference of memory cell C through HV＞7V.
Figure 38 influences for program disturbance for the turn on gate voltage effects of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Turn on gate voltage has influence for program disturbance.Can reduce the interference of memory cell C through Vpass＞6V.
Figure 39 is the block erase switching current sketch map of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring.
Source electrode line SL goes up different bias voltages can change the block erase transfer characteristic.Wipe is through applying a positive source electrode line bias voltage and all word line WL ground connection being reached.So expression is with the main body suspension joint of this three-dimensional NAND gate array.Drain selection line SSL/ ground connection selection wire GSL applies suitable positive voltage to avoid interference.In Figure 10, also show this and wipe transformation.This array does not use electric field enhancement effect (because cause of smooth ONO) in certain embodiments, makes this wipe mainly and injects support by energy gap engineering polysilicon-silica-silicon-nitride and silicon oxide-silica (BE-SONOS) tunneled holes.
Figure 40 is the programming and the erase status current-voltage characteristic sketch map of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring, and this memory has different number mark program/erase cycle.
This i-v curve shows and is lower than the less deterioration in the erase operation 10,000 times, particularly when 1000 times and one time.The deterioration of endurance is normally because the cause that Interface status (Dit) produces makes subcritical slope variation, and can't change between the memory block.Demonstrate through adjustment energy gap engineering polysilicon-silica-this device of silicon-nitride and silicon oxide-silica (BE-SONOS) lamination and to carry out the reasonable less deterioration compared with huge device after 10,000 erase operations.
Figure 41 is the critical voltage distribution schematic diagram of the polysilicon diode that is connected with three-dimensional NAND gate memory of experiment measuring, and this memory has the program/erase memory cell that check table distributes.
The check table of one single class memory cell be distributed in this with PN polysilicon diode that three-dimensional NAND gate memory is connected in use.(in this three-dimensional sensing) immediate memory cell is programmed to inverse state with the poorest disturbed condition of representative.In each layer, be to use traditional page program and programming inhibition method, and then other do not chosen source electrode line (memory cell C and D) and suppress.Carry out page program at other layer successively.In a cubical array, do not choose memory cell receive many times row stress and the row stress injury.
In many various embodiment, the diode of alternate embodiment is to be connected with drain electrode end (bit line) or source terminal (source electrode line), and has the role exchange with drain selection line SSL/ ground connection selection wire GSL and bit line/source electrode line.These replacement operation are in device class, to verify.Yet in circuit design, source electrode line has very little capacitive load, so can be better in the performance on speed and the power consumption when applying high voltage HV in source electrode line.
Preferred embodiment of the present invention and example disclose as above in detail, but are to be appreciated that above-mentioned example only as example, non-scope in order to the restriction patent.With regard to those skilled in the art, from can according to the claim scope of enclosing correlation technique being made amendment easily and make up.
Claims (25)
1. storage device comprises:
One ic substrate;
A plurality of rectangular semi-conducting material laminations extend this ic substrate, and these a plurality of laminations have the ridge shape and comprise that at least two rectangular semi-conducting materials are separated by insulating barrier and are the Different Plane position in a plurality of plan position approachs;
Many word lines are arranged to and are orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, the intersection of so setting up a cubical array in these a plurality of laminations and plotted point that should many word lines surfaces is regional;
Memory element is in this intersection zone, and it sets up the memory cell of accessible this cubical array via these a plurality of rectangular semi-conducting materials and these many word lines, and this memory element is arranged to serial between bit line structure and source electrode line; And
Diode and this serial couple, between memory cell serial and bit line structure and source electrode line wherein between one.
2. storage device according to claim 1, wherein this serial right and wrong door serial.
3. storage device according to claim 1; The combination selection of particular source polar curve in the specific bit line in this bit line structure, this source electrode line and the particular word line in this many word lines wherein can pick out the particular memory location in the memory cell of this cubical array.
4. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.
5. storage device according to claim 1, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.
6. storage device according to claim 1 more comprises:
One serial selection wire is arranged to and is orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, so set up the serial choice device in these a plurality of laminations and the surperficial plotted point of this serial selection wire; And
One ground connection selection wire is arranged to and is orthogonal on these a plurality of laminations, and have and these a plurality of laminations along the surface of shape, so set up grounding selection device in these a plurality of laminations and the surperficial plotted point of this ground connection selection wire.
7. storage device according to claim 6, wherein this diode is coupled between this serial choice device and this bit line structure.
8. storage device according to claim 6, wherein this diode is coupled between this grounding selection device and this source electrode line.
9. storage device according to claim 1, wherein this memory element comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.
10. storage device according to claim 1, wherein this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type zone in this rectangular semi-conducting material.
11. storage device according to claim 1, wherein this rectangular semi-conducting material comprises n type silicon and this diode comprises a p type embolism contacts with this rectangular semi-conducting material.
12. storage device according to claim 1 more comprises logic and does not choose the diode in the serial when programming this memory cell, to apply reverse biased to this memory cell.
13. a storage device comprises:
One ic substrate;
The memory cell of a cubical array is in this ic substrate, and this cubical array comprises:
The lamination of NAND gate serial memory cell; And
Diode and this serial couple, and are between memory cell serial and bit line structure and source electrode line wherein between one.
14. storage device according to claim 13; The combination selection of particular source polar curve in the specific bit line in this bit line structure, this source electrode line and the particular word line in this many word lines wherein can pick out the particular memory location in the memory cell of this cubical array.
15. storage device according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this bit line structure.
16. storage device according to claim 13, wherein this diode and this serial couple, and are between memory cell serial and this source electrode line.
17. storage device according to claim 13 more comprises:
One serial choice device is between this bit line structure and this memory cell serial; And
One grounding selection device is between this source electrode line and this memory cell serial.
18. storage device according to claim 17, wherein this diode is coupled between this serial choice device and this bit line structure.
19. storage device according to claim 17, wherein this diode is coupled between this grounding selection device and this source electrode line.
20. storage device according to claim 13, wherein this memory element comprises a tunnel layer, an electric charge capture layer and a barrier layer respectively.
21. a method of operating three-dimensional NAND gate flash memory comprises:
Apply a programming adjustment bias voltage sequence to this three-dimensional NAND gate flash memory, this cubical array comprises diode and this serial couples, and makes that this diode is between memory cell serial and bit line structure and source electrode line structure wherein between one.
22. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:
From one or more of source electrode line structure through one or more of this diode to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon the memory cell of being programmed by this programming adjustment bias voltage;
This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this;
Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.
23. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:
Not through this diode one or more and from one or more of source electrode line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise the memory cell of soon being programmed by this programming adjustment bias voltage;
This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And
Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.
24. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:
Through this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise soon the memory cell of being programmed by this programming adjustment bias voltage;
This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And
Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.
25. method according to claim 21, wherein this applies this programming adjustment bias voltage sequence and comprises:
Not through this diode one or more and from one or more of bit line structure to not choosing one or more charging of serial, wherein this is not chosen serial and does not comprise the memory cell of soon being programmed by this programming adjustment bias voltage;
This bit line structure and source electrode line structure are not chosen serial and comprised soon by one or more one choose serial and remove and couple of the memory cell of this programming adjustment bias voltage programming from this; And
Apply a program voltage via one or more word line of the memory cell that is about to be programmed and do not choose serial and this chooses serial to this by this programming adjustment bias voltage.
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| US13/011,717 | 2011-01-21 | ||
| US13/011,717 US8659944B2 (en) | 2010-09-01 | 2011-01-21 | Memory architecture of 3D array with diode in memory string |
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| WO2014153834A1 (en) * | 2013-03-26 | 2014-10-02 | Tsinghua University | Memory structure and method for forming same |
| CN104112745A (en) * | 2013-04-19 | 2014-10-22 | 旺宏电子股份有限公司 | Three-dimensional semiconductor structure and manufacturing method thereof |
| CN104347635A (en) * | 2013-08-07 | 2015-02-11 | 旺宏电子股份有限公司 | Semiconductor array arrangement comprising carrier supply |
| CN104576595A (en) * | 2013-10-16 | 2015-04-29 | 旺宏电子股份有限公司 | Integrated circuit and operation method thereof |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102386188B (en) | 2014-01-22 |
| JP2012054550A (en) | 2012-03-15 |
| KR20120022676A (en) | 2012-03-12 |
| JP5977003B2 (en) | 2016-08-24 |
| TW201212168A (en) | 2012-03-16 |
| TWI427744B (en) | 2014-02-21 |
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