TWI424558B - Display - Google Patents

Description

monitor

The present invention relates to a display including a substrate (display section) having a pixel region in which pixels are formed and a sensor region in which a light receiving element is formed. More particularly, the present invention relates to a method for improving light utilization efficiency in a program received by a plurality of light receiving elements in contact with or in proximity to light reflected by an object to be detected. Technology.

The present invention contains subject matter related to Japanese Patent Application No. JP 2007-328065 and No. 2008-274546, filed on Dec. In this article.

As a display device used in mobile phones, personal digital assistants (PDAs), digital still cameras, PC (personal computer) monitors, televisions, etc., liquid crystal displays, organic EL (electroluminescence) displays, and electrophoresis are known. The display and so on.

Along with the reduction in the thickness of the display, there has been a demand for a display having various functions, that is, in addition to the initial functions of displaying images and character information, there is, for example, a function of an input device for inputting a user's instruction or the like. As a device that satisfies this need, a display is known which detects a user's finger or a stylus (so-called stylus) in contact with or near the display screen.

The detection of the contact can be performed, for example, by a touch panel based on a resistive film system or a capacitive (static capacitance) system. A display is known in which a touch panel is added to the display surface side of a display panel such as a liquid crystal panel.

However, from the viewpoint of thinning the display panel, the addition of a touch panel is disadvantageous and causes an increase in cost. In particular, the resistive film system touch panel has a problem that the resistance value change can be detected only when the screen is pressed with a certain degree of force, causing the display screen to be deformed. In addition, the touch panel of the resistive film system is in principle a single-point detection type and thus has a limited use.

In recent years, in the field of liquid crystal displays, a touch panel function has been provided by employing a configuration in which a photo sensor is also formed on a transistor array substrate to control a driving voltage for a liquid crystal.

Regarding a display having a photosensor on a transistor array substrate, several detection methods are known, such as a method in which a finger or a stylus pen is recognized by detecting its shadow under external light. A method in which light of a backlight (light from a backlight) is reflected by a finger or a stylus and detects reflected light.

However, a method in which a finger or a stylus pen is recognized by detecting its shadow under external light has a problem that the function cannot be obtained in the dark. On the other hand, a method in which the backlight light is reflected by a finger or a stylus and detects reflected light has a problem that it is impossible to detect in the case of displaying perfect black.

In such a case, Japanese Patent Laid-Open Publication No. 2005-275644 (hereinafter referred to as Patent Document 1) proposes a liquid crystal display in which infrared light is emitted from a backlight and reflected infrared light is detected.

On the other hand, Japanese Patent Laid-Open Publication No. 2007-241303 (hereinafter referred to as Patent Document 2) proposes a liquid crystal display in which a reflector is provided under a semiconductor layer formed of polysilicon, and the semiconductor layer constitutes a PIN type. (p is essentially n-type) a diode, and the light is reflected by the semiconductor layer to increase the length of light absorption.

However, in the liquid crystal display described in Patent Document 1, there is a problem of material basis in the case of attempting to use a polysilicon film to realize an infrared sensor, as shown in FIG. In contrast, the absorbance in the infrared region is reduced, making it difficult to achieve the desired detection. In addition, since a visible light source is used as a backlight source, there is a problem that when an incident light corresponding to a higher sensitivity is incident on the photodiode, the infrared signal to be detected will be buried in the noise.

On the other hand, in the liquid crystal display described in Patent Document 2, there is a problem that although the light output is increased, the sensitivity is not increased unless a special design is made for the capacitance on the detecting side.

In addition to this, an improvement in one of the saturation characteristics of the sensor and an increase in sensor sensitivity is being required.

Further, the problems are not limited to the liquid crystal display described in Patent Documents 1 and 2, but are also related to other displays such as an organic EL display and a display using electrophoresis.

Therefore, it is necessary to improve the detection sensitivity of the above sensors and improve the saturation characteristics of the sensors.

According to an embodiment of the present invention, a display includes: a substrate having a pixel region in which a pixel is formed and a sensor region in which a photosensor portion is formed; an illumination segment, The substrate is used to illuminate the substrate from a surface side of the substrate; a thin film photodiode disposed in the sensor region, having at least one P-type semiconductor region and an N-type semiconductor region for receiving Light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate opposite to the film photodiode by an insulating film therebetween for suppressing The light generated by the illumination segment is directly incident on the thin film photodiode from the surface side and fixed to a predetermined potential; wherein in the thin film photodiode, perpendicular to the connection to the N-type semiconductor region The width of the P-type semiconductor region in one direction is different from the width of the N-type semiconductor region in a direction perpendicular to a direction connected to the P-type semiconductor region.

A display according to an embodiment of the present invention has the substrate, the illumination segment, the thin film photodiode, and the metal film.

The substrate has a pixel region in which pixels are formed and a sensor region in which a photosensor portion is formed.

The illumination segment illuminates the substrate from the surface side of the substrate.

The thin film photodiode system is disposed in the sensor region and has at least one P-type semiconductor region and an N-type semiconductor region for receiving light incident from the other surface side of the substrate.

The metal film is formed on the surface side of the substrate by opposing an insulating film and facing the thin film photodiode, for suppressing light generated from the illumination segment from the surface side. Directly incident on the thin film photodiode and fixed to a predetermined potential.

Here, in the thin film photodiode, a layout is employed such that the width of the P-type semiconductor region in a direction perpendicular to a direction connected to the N-type semiconductor region is different from being perpendicular to the connection to the P-type The width of the N-type semiconductor region in the direction of the direction of the semiconductor region.

According to another embodiment of the present invention, a display includes: a substrate having a pixel region in which a pixel is formed and a sensor region in which a photosensor portion is formed; an illumination segment The substrate is used to illuminate the substrate from a surface side of the substrate; a thin film photodiode disposed in the sensor region, having at least one P-type semiconductor region and an N-type semiconductor region for receiving Light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate with the insulating film interposed therebetween, for suppressing the film photodiode Light generated from the illumination segment is directly incident on the thin film photodiode from the surface side and fixed to a predetermined potential; wherein the thin film photodiode and the metal film are spaced apart from the insulating film a capacitance value of a parasitic capacitance of the P-type semiconductor region and the metal film opposite to each other is different from a parasitic capacitance of the N-type semiconductor region and the metal film including the insulating film interposed therebetween Capacitance value of capacitor .

A display according to another embodiment of the present invention has the substrate, the illumination segment, the thin film photodiode, and the metal film.

The substrate has a pixel region in which pixels are formed and a sensor region in which a photosensor portion is formed.

The illumination segment illuminates the substrate from the surface side of the substrate.

The thin film photodiode system is disposed in the sensor region and has at least one P-type semiconductor region and an N-type semiconductor region for receiving light incident from the other surface side of the substrate.

The metal film is formed on the surface side of the substrate by opposing an insulating film and facing the thin film photodiode, for suppressing light generated from the illumination segment from the surface side. Directly incident on the thin film photodiode and fixed to a predetermined potential.

Here, in the thin film photodiode and the metal film, the capacitance value of the parasitic capacitance of the P-type semiconductor region and the metal film, which are opposed to each other with the insulating film interposed therebetween, is different from the interval including the spacer. The capacitance value of the parasitic capacitance of the N-type semiconductor region and the metal film opposite to each other with the insulating film.

According to another embodiment of the present invention, a display includes: a substrate having a pixel region in which a pixel is formed and a sensor region in which a photosensor portion is formed; an illumination segment The substrate is used to illuminate the substrate from a surface side of the substrate; a thin film photodiode disposed in the sensor region, having at least one P-type semiconductor region and an N-type semiconductor region for receiving a light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate by an insulating film and opposite to the thin film photodiode Suppressing light generated from the illumination segment from directly incident on the thin film photodiode from the surface side and fixing to a predetermined potential; wherein in the thin film photodiode, from the one surface side and the other When one of the surface sides is inspected, the region of the overlap region of the P-type semiconductor region and the metal film is different from the region of the overlap region of the N-type semiconductor region and the metal film.

A display according to this additional embodiment of the present invention has the substrate, the illumination segment, the thin film photodiode, and the metal film.

The substrate has a pixel region in which pixels are formed and a sensor region in which a photosensor portion is formed.

The illumination segment illuminates the substrate from the surface side of the substrate.

The thin film photodiode system is disposed in the sensor region and has at least one P-type semiconductor region and an N-type semiconductor region for receiving light incident from the other surface side of the substrate.

The metal film is formed on the surface side of the substrate by opposing an insulating film and facing the thin film photodiode, for suppressing light generated from the illumination segment from the surface side. Directly incident on the thin film photodiode and fixed to a predetermined potential.

Here, in the thin film photodiode, when the one surface side and the other surface side are inspected, the region of the overlapping region of the P-type semiconductor region and the metal film is different from the N-type semiconductor region. The area of the overlap with the metal film.

According to the display of the embodiment of the present invention, in the thin film photodiode formed in the sensor region of the substrate, the width of the P-type semiconductor region and the width of the N-type semiconductor region are different from each other. This can reduce the parasitic capacitance between the thin film photodiode and the metal film to improve the detection sensitivity of the sensors and improve the saturation characteristics of the sensors.

Further, according to another display of the present invention, the capacitance value of the parasitic capacitance of the P-type semiconductor region and the metal film which are opposed to each other with the semiconductor film interposed therebetween is different from the interval including the interval. The capacitance value of the parasitic capacitance of the N-type semiconductor region and the metal film opposite to each other with the insulating film. This can reduce the parasitic capacitance between the thin film photodiode and the metal film to improve the detection sensitivity of the sensors and improve the saturation characteristics of the sensors.

In addition, according to another embodiment of the present invention, when the one surface side and the other surface side are inspected, the area of the overlapping area of the P-type semiconductor region and the metal film is different from the N A region of the overlapping region of the semiconductor region and the metal film. This results in a configuration in which the capacitance value of the P-type semiconductor region and the parasitic capacitance of the metal film, which are opposed to each other with the insulating film interposed therebetween, is different from that of the insulating film including the insulating film a capacitance value of the parasitic capacitance of the N-type semiconductor region and the metal film, thereby reducing the parasitic capacitance between the thin film photodiode and the metal film, and improving the detection sensitivity of the sensors And improve the saturation characteristics of these sensors.

A display in accordance with an embodiment of the present invention will now be described with reference to the drawings.

Incidentally, the explanation will be made in the following order.

(1) A first embodiment (a configuration in which a width of one anode region in a direction perpendicular to a direction connecting a cathode region is different from a cathode in a direction perpendicular to a direction connected to the anode region) Width of the area)

(2) Modified examples

(3) A second embodiment (a configuration in which an outer portion of an overlap region having a control gate has an extension portion extending in a direction perpendicular to a direction connected to the cathode region)

(4) A third embodiment (a configuration in which an I region is provided at one end portion of an anode region, and an I region portion has the same width as the width of the anode region)

(5) A fourth embodiment (a configuration in which a width of a P ⁺ region overlapping a control gate is less than a width of an overlap of the N ⁺ region and the control gate)

(6) Fifth embodiment (an example of a product to which the display is applied)

<First Specific Embodiment>

Now, a liquid crystal display is taken as an example and reference is made to the drawings, and a display of a first embodiment of the present invention will be described below.

The display in this embodiment is preferably applied to a so-called "transmissive" liquid crystal display in which the light system is projected from the side of the rear side surface (on the opposite side of a front side surface for displaying an image thereon) The side of a surface). Therefore, the following description is based on the assumption that the liquid crystal display is of a transmissive type.

(general configuration)

Figure 1 is a schematic general configuration diagram of a transmissive liquid crystal display.

The liquid crystal display 100 illustrated in FIG. 1 has, for example, a liquid crystal panel 200 as a display section of a "substrate"; a backlight 300 as an "illumination section"; and a data processing section 400.

For example, as shown in FIG. 1, the liquid crystal panel 200 has a TFT (Thin Film Transistor) array substrate 201, a color filter substrate 202 as a so-called "relative (reverse) substrate", and a liquid crystal layer 203. Hereinafter, the liquid crystal layer 203 is used as a center (or reference), and the side of the backlight 300 in the thickness direction of the liquid crystal panel 200 will be referred to as "one surface side" or "back side surface side", and the opposite side of the one surface side The side will be referred to as "the other surface side" or the "front side surface side".

For example, the TFT array substrate 201 and the color filter substrate 202 are opposed to each other with a pitch therebetween, and then the liquid crystal layer 203 is formed so as to be inserted between the TFT array substrate 201 and the color filter substrate 202. Further, although not specifically shown in the drawings, alignment films for aligning liquid crystal molecules in the liquid crystal layer 203 in an alignment direction are formed in pairs to sandwich the liquid crystal layer 203 therebetween. A color filter 204 is formed on the surface of the color filter substrate 202, which is on the side of the liquid crystal layer 203.

For example, a first polarizing plate 206 and a second polarizing plate 207 are respectively disposed on both sides of the liquid crystal panel 200 so as to face each other. Specifically, the first polarizing plate 206 is disposed on the rear side surface side of the TFT array substrate 201, and the second polarizing plate 207 is disposed on the front side surface side of the color filter substrate 202.

For example, the photo sensor portion 1 is provided on the other surface side of the TFT array substrate 201 facing the liquid crystal layer 203 as shown in FIG. The photosensor sections 1 (described later in detail) each include a thin film photodiode as a light receiving element and a read circuit thereof.

The light sensor portions 1 are formed to provide a function of a so-called touch panel in the liquid crystal panel 200. For example, when the liquid crystal panel 200 is viewed from the side (front side surface) of the display surface, the photosensor sections 1 are regularly arranged in an effective display area PA.

1 shows a cross section of a liquid crystal panel 200 in which the photosensor sections 1 are arranged in a matrix pattern in an effective display area PA. In FIG. 1, for example, a plurality of (four in the drawings) photosensor sections 1 are arranged at regular intervals. Although four photosensor sections 1 are shown for convenience in FIG. 1, this configuration is not limitative.

In the case where the position detecting function is limited to a portion of the effective display area PA, for example, the light sensor portions 1 are regularly arranged in a limited display area.

In the effective display area PA of the display plane (front side surface), as shown in FIG. 1, each of the areas of the liquid crystal panel 200 in which the photosensor sections 1 are formed is defined as a "sensor" Area (PA2)", and each of the other areas of the liquid crystal panel 200 is defined as "pixel area (PA1)". The pixel regions (PA1) are configuration regions of pixels to which a plurality of colors, such as red (R), green (G), and blue (B), are assigned pixel by pixel. The color distribution is determined by the transmission wavelength characteristics of the color filters facing the pixels, respectively.

For example, although omitted in FIG. 1, a pixel electrode and a common electrode (also referred to as a counter electrode) are formed in the pixel arrangement region (pixel region (PA1)). The pixel electrode and the common electrode system are each formed of a transparent electrode material. On the other surface side (liquid crystal layer side) of the TFT array substrate 201 and the counter liquid crystal side of the pixel electrodes, a common electrode common to all the pixels may be formed opposite to the pixel electrodes in some cases. Or alternatively, a configuration may be employed in some cases, wherein the pixel electrodes are formed on the other surface side of the TFT array substrate 201, and the common electrode system and the pixel electrodes are commonly used for all the pixels. A position on the side of the color filter substrate 201 is oppositely formed with a liquid crystal layer 203 therebetween.

In the pixel configuration area, although not shown in FIG. 1, an auxiliary capacitor is formed according to the pixel configuration for helping the liquid crystal capacitor between the pixel electrode and the counter electrode; a switching element, by A potential or the like applied to the pixel electrode is controlled in accordance with the potential of an input image signal.

For example, when a unit composed of a plurality of pixels respectively corresponding to a plurality of colors in a one-to-one correspondence manner is defined as a “pixel unit”, the number of the photosensor portions 1 and the pixel units therein are defined. The configuration density of the photosensor sections 1 is maximized in the case where the ratio of the number is 1:1. In this embodiment, the arrangement density of the photosensor sections 1 may be equal to or less than the maximum value.

The backlight 300 is disposed on, for example, the rear side surface side of the TFT array substrate 201. The backlight 300 faces the rear side surface of the liquid crystal panel 200 and emits illumination light to the effective display area PA of the liquid crystal panel 200.

The backlight 300 exemplarily shown in FIG. 1 has a light source 301; and a light guide plate 302 for diffusing light emitted from the light sources 301 to convert the light into surface light. The backlight 300 is classified into a side light type, a bottom type, and the like according to a (several) arrangement position of the light source 301 (s) of the light guide plates 302; here, a side light type is exemplified.

For example, on the rear side of the liquid crystal panel 200, the or the light sources 301 are disposed on one or both sides in the direction along the rear side surface of the liquid crystal panel 200. In other words, the light source 301 is disposed along one edge or two opposite edges of the liquid crystal panel 200 when viewed from the side (front side surface) of the display surface 200A. However, it should be noted here that the light source 301 may be disposed along three or more edges of the liquid crystal panel 200.

The light source 301 is composed, for example, of a cold cathode tube lamp in which UV light generated by arc discharge in a low pressure mercury vapor in a glass tube is converted into visible light and emits visible light rays by a fluorescent material. Or LED (light emitting diode), EL components, etc. 1 shows a situation in which a visible light source 301a (such as a white LED) and an IR (infrared) light source 301b are respectively disposed along the two opposite edges as the light sources 301.

The light guide plate 302 is composed of, for example, a light-transmissive acrylic plate, and guides light from each of the light sources 301 along its plane while achieving total reflection (from one side to the other side along the rear side surface of the liquid crystal panel 200). The light guide plate 302 is provided with a dot pattern (plurality of protrusions) (not shown) at its rear side surface, which is formed, for example, as part of the light guide plate 302 or by a member separate from the light guide plate 302. The guided light is scattered by the dot pattern to be projected onto the liquid crystal panel 200. Incidentally, a reflection sheet for reflecting light may be provided on the rear side surface side of the light guide plate 302, and a diffusion sheet or a sheet may be provided on the front side surface side of the light guide plate 302.

For example, the backlight 300 is configured as above, and it radiates surface light that is substantially uniform over the entire area of the effective display area PA of the liquid crystal panel 200.

In addition, for example, the data processing section 400 has a control block 401 and a position detection block 402, as shown in FIG. The data processing section 400 includes a computer and is operated by a program in which the computer controls various sections or sections in accordance with one (several) program. Therefore, the functions of the control block 401 and the position detecting block 402 are implemented by using program tasks and materials initially stored in a memory or a plurality of memories (not shown) or externally input.

The data processing section 400 may separately install its functions based on the inside and outside of the liquid crystal panel 200. 1 shows a case in which the data processing section 400 is disposed outside the liquid crystal panel 200 as, for example, a single IC (integrated circuit) or a plurality of ICs.

For example, the control block 401 performs control of image display, control of position sensors (data collection by light reception), and control of backlights.

As for the image display, for example, the control block 401 supervises and issues a command to a display driving circuit in the liquid crystal panel 200, thereby controlling image display in the liquid crystal panel 200. As for the control of the IR sensor, for example, the control block 401 supervises and issues a command to a sensor driving circuit in the liquid crystal panel 200, thereby controlling the detection of the position (and size) of the object to be detected. An example of the display driving circuit and the sensor driving circuit will be described later.

As for the control of the backlight, the control block 401 supplies a control signal to one of the power supply sections (not shown) of the backlight 300, thereby controlling the brightness and the like of the illumination light output from the backlight 300.

For example, when receiving an instruction from the control block 401, the position detecting block 402 detects an object (such as a user's finger or based on light receiving data transmitted through a sensor driving circuit in the liquid crystal panel 200). A stylus pen is touching or approaching the position. This detection is performed with respect to the effective display area PA of the liquid crystal panel 200.

(schematic configuration of the liquid crystal panel)

Fig. 2 is a block diagram showing a configuration example of one of the driving circuits in the liquid crystal panel.

As shown in FIG. 2, for example, the liquid crystal panel 200 has a display section 10 in which pixels (PIX) are arranged in a matrix pattern.

As also shown in FIG. 1, a peripheral area CA exists in the periphery of the effective display area PA. The peripheral area CA refers to a region of the TFT array substrate 201 excluding the effective display area PA. As shown in FIG. 2, a driving circuit represented by a plurality of functional blocks (including TFTs formed in common with the TFTs in the effective display area PA) is formed in the peripheral area CA.

The liquid crystal panel 200 has, for example, a vertical driver (V.DRV.) 11, a display driver (D-DRV.) 12, a sensor driver (S-DRV.) 13, and a selection switch array (SEL.SW). .) 14, and a DC-DC converter (DC / DC.CNV.) 15.

For example, the vertical driver 11 is a circuit having a function of a shift register or the like for scanning various control lines placed in the horizontal direction in the vertical direction to select (several) pixel lines.

Display driver 12 is a circuit having, for example, a signal common to the pixels of a data signal by sampling a data potential of an image signal and discharging the amplitude of the data signal to the pixels in the row direction. The function of the line.

The sensor driver 13 is a circuit that applies scanning of the control lines (similar to the control lines of the vertical driver 11) to the photosensor portions 1 dispersedly disposed at a predetermined density in the pixel arrangement region. The collection of sensor outputs (detection data) is performed in synchronization with the scanning of the control lines.

The switch array 14 is a control circuit that includes a plurality of TFT switches and that performs control of the display driver 12 to discharge the amplitude of the data signal and control of the sensor output from the display section 10.

The DC-DC converter 15 is a circuit that generates various DCs (Direct Current) from an input power source voltage at a potential necessary for driving the liquid crystal panel 200.

For example, input/output signals and other signals transmitted to and from the display driver 12 and the sensor driver 13 between the inside and the outside of the liquid crystal panel 200 are implemented by providing a flexible substrate 16 for the liquid crystal panel 200. .

In addition to the components shown in FIG. 2, for example, configurations for generating or externally inputting a clock signal, etc., are also included in the drive circuits.

(Example of a combination of pixels with a photosensor section)

As described above, for example, the pixels and the photosensor portions are regularly arranged in the effective display area PA. The regularity of the configuration is arbitrary; for example, a plurality of groups may be arranged in a matrix in the effective display area PA, wherein each group is composed of a plurality of pixels and a photo sensor portion. For example, each of the groups consists of three pixels (R, G, and B pixels) and a photosensor portion.

The color filter 204 shown in FIG. 1 has, for example, a plurality of filters, each of which substantially corresponds to a size in a plan view of a pixel and selectively transmits in each of the R, G, and B wavelength regions. Light; and a black matrix that shields the perimeter of the filters (all boundary portions) with a fixed width for preventing color mixing.

(Pattern and section structure of the pixel portion and the photo sensor portion)

3A shows an example of a plan view of a photosensor portion 1, and FIG. 3B shows an example of an equivalent circuit of the photosensor portion 1 corresponding to the pattern shown in FIG. 3A.

For example, as illustrated in FIG. 3B, the photo sensor portion 1 includes three transistors composed of an N-channel type thin film transistor (TFT) and a thin film photodiode PD as a light receiving element.

The three electro-crystalline systems reset a transistor TS, an amplifying transistor TA, and a reading transistor TR.

The thin film photodiode PD is formed, for example, as a light receiving element having sensitivity to invisible light such as infrared (IR) light and ultraviolet (UV) light. In the present embodiment, the thin film photodiode PD is a light receiving element that is sensitive to infrared light emitted by an IR light source 301b constituting the backlight 300. In the case where the backlight emits ultraviolet light, the thin film photodiode PD is designed to be sensitive to ultraviolet light.

In the thin film photodiode PD, for example, the anode is connected to a storage node SN which is connected to a supply line (hereinafter referred to as "VDD line") 31 of a power supply voltage VDD.

The thin film photodiode PD has a PIN structure or a PDN structure, as will be described later, and has a control gate CG for applying an electric field to an I (essential) region through an insulating film (the PIN structure) An intrinsic semiconductor region) or a D (doped) region (one N ^- region of the PDN structure). The thin film photodiode PD has a structure such that it is used in a reverse bias state and can optimize (usually maximize) sensitivity by controlling the gate CG to control the degree of depletion in this example.

In the reset transistor TS, for example, the drain is connected to the storage node SN, and the source is connected to a supply line (hereinafter referred to as "VSS line") 32 of a reference voltage VSS, and the gate is It is connected to a supply line (hereinafter referred to as "reset line") 33 of a reset signal (RESET). The reset transistor TS switches the storage node SN from a floating state to a state connected to the VSS line 32 to discharge the storage node SN, thereby resetting the amount of charge stored therein.

In the amplifying transistor TA, for example, the drain is connected to the VDD line 31, and the source is connected to one of the detecting potentials Vdet (or a detecting current Idet) through the reading transistor TR ( Hereinafter referred to as "detection line"), the gate is connected to the storage node SN.

In the read transistor TR, for example, the drain is connected to the source of the amplifying transistor TA, the source is connected to the detecting line 35, and the gate is connected to a read control signal (READ) A supply line (hereinafter referred to as "read control line") 34.

The amplifying transistor TA (for example) has a function of storing a positive charge generated in the thin film photodiode PD in the storage node SN, and amplifying the transistor when it is again placed in a floating state after resetting. TA will amplify and store the charge (light receiving potential). The read transistor TR is used to control the timing at which the light receiving potential amplified by the amplifying transistor TA is discharged to the detecting line 35. When a predetermined storage time has elapsed, the read control signal (READ) is activated and the read transistor TR is turned on, such that a voltage is applied to the source and the drain of the amplifying transistor TA, and the amplifying transistor is The gate potential of the moment turns on a current. Thereby, a potential change which increases in amplitude according to the light receiving potential appears on the detecting line 35, and the potential change is output as the detecting potential Vdet from the detecting line 35 to the outside of the photo sensor section 1. Alternatively, the detection current Idet whose value varies depending on the light receiving potential is output from the detecting line 35 to the outside of the photo sensor portion 1.

3A shows a top plan view of a TFT array substrate 201 before being adhered to the color filter substrate 202 as shown in FIG. 1 to seal a liquid crystal therebetween.

In the pattern diagram shown in Fig. 3A, the elements and nodes shown in Fig. 3B are denoted by the same reference numerals as those used in Fig. 3B, so that the electrical connection between the elements is clearly seen.

For example, the VDD line 31, the VSS line 32, and the detection line 35 are each formed of an aluminum (AL) wiring layer, and the reset line 33 and the read control line 34 are each composed of a gate metal (GM) ( For example, molybdenum (Mo) is formed. The gate metal (GM) is formed under the aluminum (AL) wiring layer. Four semiconductor layers, such as a polysilicon (PS) layer, are disposed in isolation on the upper side of the gate metal (GM) layer and on the underside of the aluminum (AL) layer. Each of the reset transistor TS, the read transistor TR, the amplifying transistor TA, and the thin film photodiode PD has a semiconductor layer such as a PS layer.

In a transistor, for example, a transistor structure is formed in which an N-type impurity is introduced into one side and the other side of a portion of a thin film semiconductor layer, for example, a PS layer Composition, the PS layer intersects the gate metal (GM) to form a source and a drain.

On the other hand, in a thin film photodiode PD, P-type and N-type impurities of opposite conductivity type are introduced to one side and the other side of the thin film semiconductor layer 36 composed of, for example, a PS layer, thereby A diode structure is formed. A P-type impurity region (P ⁺ region) forms an anode region (A region) which constitutes, for example, a storage node SN. On the other hand, an N-type impurity region (N ⁺ region) forms a cathode region (K region) of the thin film photodiode PD which is connected to the VDD line 31 on the upper side through, for example, a contact.

4 is a cross-sectional view schematically showing a portion of the photo sensor portion 1 and a pixel (PIX) in a liquid crystal of one of the FFS systems. 4 shows a cross section taken along line S1 to S1 of FIG. 3A and showing a portion of the photosensor portion 1 and a cross section of the pixel (PIX) (not shown).

The pixels within the liquid crystal in this particular embodiment are, for example, FFS (Field Edge Switching) systems. The liquid crystal of the FFS system is also called the liquid crystal of the "in-plane switching (IPS)-Pro" system.

As shown in FIG. 4, a transistor serving as a switching element SW is formed in a state of being buried in a plurality of multilayer insulating films on the TFT array substrate 201. The insulating film shown in FIG. 4 sequentially includes a double-layer gate insulating film 50, a double-layer first interlayer insulating film 51, a second interlayer insulating film (planar film) 52, and the like from the lower side. A third interlayer insulating film 53.

For example, a gate metal GM is formed under the gate insulating film 50, which is formed of molybdenum (Mo) or the like and becomes a vertical scanning line 44, and a thin film semiconductor layer 43 is formed on the gate insulating film 50. Including a polysilicon (PS) layer and the like.

The semiconductor layer 43 has a structure in which a P ^- region to be a channel formation region is located on the upper side of the gate metal GM, and an N ⁺ region to be a source/drain region is formed in the P ^- region. On both sides, a thin film transistor is thus configured.

For example, a pixel electrode 40 is formed at one of the source and drain regions formed in the semiconductor layer 43 and includes a transparent electrode layer that transmits through an internal wiring 42 and a contact 41. Segment by pixel by pixel.

Further, on the lower side of the pixel electrode 40, at a interface between the second interlayer insulating film 52 and the third interlayer insulating film 53, a common electrode 55 is formed so as to face the pixel electrode 40. The common electrode 55 is composed of a transparent electrode layer which is common to all the pixels.

In addition to this, a signal line 45A formed of aluminum or the like is connected to the other of the source and drain regions formed in the semiconductor layer 43.

In addition, for example, a color filter substrate 202 is stacked on the upper side of the TFT array substrate 201, and a liquid crystal layer 203, a certain alignment film 56, and a color filter 204 are sequentially disposed on the two substrates from the lower side. between.

Here, the liquid crystal layer 203 has a nematic liquid crystal.

The common electrode is fixed to a common potential at a potential, and an electric field applied to the liquid crystal is changed to a voltage applied between itself and the pixel electrode 40.

As shown in FIG. 1, on the outer surface of the TFT array substrate 201 and the color filter substrate 202 and in a cross-Nicol state, a first one is provided through a bonding agent in a stable contact state. The polarizing plate 206 and a second polarizing plate 207.

Further, examples of materials usable for the signal line 45A and the vertical scanning line 44 (gate metal (GM)) include aluminum (Al), molybdenum (Mo), chromium (Cr), tungsten (W), titanium (Ti), Lead (Pb), its composite layer (such as Ti/Al) and its alloy layer.

Now, the cross-sectional structure of the photo sensor section 1 will be explained below.

As shown in FIG. 4, the thin film photodiode PD is formed in a state of being buried in a plurality of multilayer insulating films including the two gate insulating films on the upper side of the TFT array substrate 201. 50. The two first interlayer insulating films 51, the second interlayer insulating film (planarizing film) 52, and the third interlayer insulating film 53.

For example, a control gate CG as a "metal film" is formed under the gate insulating film 50, and a thin film semiconductor layer 36 having polysilicon or the like is formed on the gate insulating film 50.

The semiconductor layer 36 has a structure in which an I region (essential semiconductor region) 36I is located above the control gate CG, and an anode region 36A having a P ⁺ region (P-type semiconductor region) has an N ⁺ region (N). A cathode region 36K of the type semiconductor region is located on both sides of the I region 36I. Further, in the present embodiment, a low concentration semiconductor region (N ^- region) 36N is formed between the I region 36I and the cathode region 36K, which contains an N-type impurity at a low concentration. In this manner, a thin film photodiode of the PIN structure is configured having a low concentration semiconductor region.

Further, a D region (N ^- region) is formed instead of the I region within the PDN structure.

The cathode region 36K is, for example, connected to the VDD line 31 through a contact plug 54 formed in the interlayer insulating film 51, which is formed on the first interlayer insulating film 51. The anode region 36A is connected to a wiring 39 at a portion (not shown) and is connected to the gate electrode of the amplifying transistor TA.

Further, on the first interlayer insulating film 51, the detecting line 35 and the VSS line 32 are arranged side by side at a position away from the VDD line 31.

For example, since the VDD line 31, the VSS line 32, and the detection line 35 are all formed of aluminum or the like and each has a large step, a second interlayer insulating film (planarizing film) 52 for planarizing the steps is formed. .

A common electrode 55 fixed to a common potential at a potential is formed on the second interlayer insulating film 52. Since the photo sensor portion 1 has no pixel electrode, the electric field applied to the liquid crystal cannot be controlled here, but the effect of fixing the liquid crystal by the common electrode 55 is obtained. The common electrode 55 is composed of a transparent electrode layer and is thus permeable to light therethrough.

In FIG. 4, a color filter 204 is provided together with a black matrix 21K at a boundary portion between the photo sensor portion 1 and the pixel (PIX), and a sensor opening SA is between the two black matrices 21K. Open. On the other hand, in the pixel (PIX), one of R, G, and B is displayed.

(Structure and light receiving characteristics of thin film photodiodes)

Fig. 5A is a plan view of a film photodiode PD of the PIN structure, and Fig. 5B is a cross-sectional view taken along line XX' of Fig. 5A. In FIG. 5B, the wiring such as the VDD line 31 and the configuration of the second interlayer insulating film 52 and the upper layers are omitted.

For example, a control gate 38 having a "metal film" is formed on the TFT array substrate 201, the two gate insulating films 50 are formed on the upper side thereof, and the semiconductor layer 36 is formed on the upper side thereof.

The semiconductor layer 36 has a pattern shape as shown in FIG. 5A. Specifically, an anode region 36A having a P ⁺ region (P-type semiconductor region); an I region (essential semiconductor region) 36I; a low concentration semiconductor region (N ^- region) 36N; and a cathode region 36K are disposed. It has an N ⁺ region (N-type semiconductor region). In this manner, a thin film photodiode of the PIN structure is configured having a low concentration semiconductor region.

Incidentally, in the case of the PDN structure, a D region (N ^- region) is formed instead of the I region.

Further, the layout of the above-described zone control gate 38 is as shown in Fig. 5A.

The first interlayer insulating film 51 is formed to cover the photodiode and is connected to the contact plug 54 through the contact hole CT reaching the anode region 36A and the cathode region 36K.

In the above photodiode, when a reverse bias is applied, a depletion layer is gradually formed (widened) inside the I region (or the D region). In order to facilitate the depletion process, back gate control is performed (the electric field is controlled by the control gate CG). It should be noted here that in the PIN structure, the depletion proceeds to about 10 μm from the P ⁺ region; on the other hand, in the PDN structure, substantially the entire region of the D region is depleted, which is advantageous because of having light. The area receiving the sensitivity is correspondingly widened. In this particular embodiment, each of the PIN structure and the PDN structure can be employed.

A thin film photodiode system having a position sensor having such a structure is designed to have a sensitivity to invisible light, a desired line-sensitivity peak.

The invisible light, for example, includes infrared light or ultraviolet light. Incidentally, according to the CIE (International Commission on Illumination), the boundary between the wavelength of ultraviolet light (which is also an example of invisible light) and visible light is 360 to 400 nm, and the boundary between the wavelength of visible light and infrared light is 760 to 830 nm. However, it should be noted here that it may be actually interpreted that light having a wavelength of not more than 350 is ultraviolet light, and light having a wavelength of not less than 700 nm is infrared light. Here, the wavelength range of the invisible light is in the range of not more than 350 nm and not less than 700 nm. However, it should be noted here that in the present embodiment, the boundary of the wavelength of the invisible light can be arbitrarily specified within the above range of 360 to 400 nm and 760 to 830 nm.

In the case where infrared light (IR light) is used as the invisible light, the thin film semiconductor layer 36 constituting the thin film photodiode PD having a sensitivity peak in the wavelength range of the IR light preferably has an energy band gap. It is smaller than the energy band gap (for example, 1.6 eV) of one of the light receiving elements for visible light. For example, the thin film photodiode PD can be fabricated from a polycrystalline germanium or crystalline germanium having a band gap of 1.1 eV between the valence band and the conduction band, which is smaller than the band gap of the light receiving element for visible light. (eg 1.6eV).

As for the band gap Eg, an optimum value is calculated from the equation Eg = h v , where h is the Plank's constant and v = 1 / λ (λ is the wavelength of light).

On the other hand, when the thin film semiconductor layer 36 is formed of amorphous germanium or microcrystalline germanium, light receiving capability (sensitivity) is simultaneously obtained for infrared light and ultraviolet light, since the semiconductor materials have several distributions of band gap steps. . Therefore, a thin film photodiode PD formed by using any of the semiconductor materials has a light receiving capability not only for visible light but also for invisible light (including infrared light and ultraviolet light), and is available A light receiving element that acts on visible light and invisible light.

From the foregoing, the thin film photodiode PD which can be preferably used in the present embodiment preferably has a semiconductor layer 36 which is formed of polycrystalline germanium, microcrystalline germanium, amorphous germanium or crystalline germanium.

In either manner, the thin film photodiode PD in the present embodiment is selected and designed such that the absorbance for, for example, infrared light and ultraviolet light will be higher than the light diode designed to receive visible light. These are the ones to manufacture.

Here, referring to FIG. 3, a light detecting operation of one of the photosensor portions having the above-described thin film photodiode will be discussed.

When a method is used in which a current generated when light is used to illuminate the thin film photodiode is stored in a storage capacitor in a pixel and converted into a voltage, the signal is amplified by amplifying the transistor TA Thus, when the signal is read, the sensor signal sensitivity (voltage) can be expressed as: (photocurrent) x (exposure time) / (current storage capacitor).

Accordingly, in order to increase the sensitivity of the sensor signal, the following methods are conceivable: (1) increasing the photocurrent, (2) extending the exposure time, and (3) reducing the current storage capacitance.

Particularly in the case of using a parasitic capacitance of a component as the current storage capacitor, the sensor signal sensitivity voltage can be improved by reducing the parasitic capacitance through a device structure.

(Example of layout of thin film photodiode)

A layout is employed in which the width Wp of the anode region (P ⁺ region) 36A in the direction perpendicular to the direction of 36K connected to the cathode region (N ⁺ region) is different from the 36A perpendicular to the anode region (P ⁺ region) The width of the cathode region (N ⁺ region) 36K in the direction of the direction Wn.

The above configuration can be made into a configuration in which the region of the overlap region of the anode region (P ⁺ region) 36A and the control gate 38 is different from the cathode region (N ⁺ region) when viewed from one surface side or the other surface side. The area of the overlap region of 36K and the control gate 38.

Specifically, the parasitic capacitance between the anode region (P ⁺ region) 36A or the cathode region (N ⁺ region) 36K and the control gate 38 can be reduced, since the anode region (P ⁺ region) 36A or the cathode region (N ⁺ The region 36K is reduced in width to reduce its overlap with the control gate 38.

Here, in the case where the overlap region just described is taken into consideration, the low concentration semiconductor region (N ^- region) 36N can be made part of the cathode region 36K. In the case where the region occupied by the low-concentration semiconductor region (N ^- region) 36N is extremely small and in the case where the concentration of the N-type impurity is extremely low, this region can be excluded from consideration. This also applies to the following.

In the present embodiment, for example, the control gate 38 is in a state of being connected to the cathode region (N ⁺ region) 36K. Here, in a direction perpendicular to the direction of the connection to the cathode region (N ⁺ region) and 36K of the anode region (P ⁺ region) is smaller than the width Wp line 36A is connected in a direction perpendicular to the anode region (P ⁺ region) 36A of the The width Wn of the cathode region (N ⁺ region) 36K in the direction.

With the configuration just described, a configuration can be obtained in which the area of the overlap region of the anode region (P ⁺ region) 36A and the control gate 38 is smaller than the cathode when viewed from the one surface side or the other surface side. The area of the overlap region of the region (N ⁺ region) 36K and the control gate 38. This ensures that the parasitic capacitance Cgp between the control gate 38 and the anode region (P ⁺ region) can be reduced.

Specifically, in the thin film photodiode PD, the ratio R1 of the width Wp of the anode region (P ⁺ region) 36A to the width Wn of the cathode region (N ⁺ region) is preferably In the range.

The reason why the ratio R1 is set to be better within the range just described will be explained in a later example.

Alternatively, in the case where the control gate 38 is connected to one of the configuration of the anode region (P ⁺ region) 36A, unlike the case of the illustrated photodiode, the following configuration is employed. The configuration to be employed is such that the width Wp of the anode region (P ⁺ region) 36A is greater than the direction perpendicular to the anode region (P ⁺ region) in a direction perpendicular to the direction connecting the cathode region (N ⁺ region) 36K. The width Wn of the cathode region (N ⁺ region) 36K in the direction of the direction of 36A.

Due to the configuration just described, the area of the overlap region of the anode region (P ⁺ region) 36A and the control gate 38 when viewed from the one surface side or the other surface side is larger than the cathode region (N ⁺ region) 36K and The area of the overlap region of the gate 38 is controlled. Similar to the above, this ensures that the parasitic capacitance Cgn between the control gate 38 and the cathode region (N ⁺ region) 36K can be reduced.

Specifically, in the thin film photodiode PD, the ratio R2 of the width Wn of the cathode region (N ⁺ region) 36K to the width Wp of the anode region (P ⁺ region) is preferably In the range.

The reason why the ratio R2 is set to be better within the range just described will be explained in a later example.

(connection of cathode region and gate electrode)

Figure 6A is a circuit diagram showing the parasitic capacitances present at the thin film photodiode and the control gate.

At the thin film photodiode and the control gate, the following parasitic capacitance exists.

(1) A parasitic capacitance Cgp between the control gate 38 and the anode region (P ⁺ region) 36A

(2) A parasitic capacitance Cgn between the control gate 38 and the cathode region (N ⁺ region) 36K

(3) A parasitic capacitance Cjnc between the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K

As described above, in the case where the control gate 38 is connected to the cathode region (N ⁺ region) 36K, the circuit diagram of Fig. 6A becomes as shown in Fig. 6B.

In other words, the parasitic capacitance Cgn between the control gate 38 and the cathode region (N ⁺ region) 36K becomes apparently disappeared. Accordingly, the current storage capacitor is composed of a parasitic capacitance Cgp between the control gate 38 and the anode region (P ⁺ region) 36A and between the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K. The sum of the parasitic capacitances Cjnc of the junctions is represented.

In contrast, the case where the control gate lines 38 connected to the anode region (P ⁺ region) 36A, and the control gate 38 and the anode region (P ⁺ region) 36A between the parasitic capacitance will become apparent Cgp disappeared. Accordingly, the current storage capacitor is between the parasitic capacitance Cgn between the control gate 38 and the cathode region (N ⁺ region) 36K and between the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K. The sum of the parasitic capacitances Cjnc of the junctions is represented.

With the above configuration in which the control gate 38 is connected to the cathode region (N ⁺ region) 36K or the anode region (P ⁺ region) 36A, the parasitic capacitance Cgn or the parasitic capacitance Cgp disappears remarkably. This reduces the parasitic capacitance and thus improves the sensor signal sensitivity voltage.

Here, as described above, the control gate 38 is connected to the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, and the parasitic capacitance formed between itself and the control gate 38 is formed. A larger one, that is, one of the higher capacitance values of the parasitic capacitances Cgp and Cgn. Therefore, the larger of the parasitic capacitances Cgp and Cgn disappears remarkably, thereby improving the parasitic capacitance reduction effect.

The thin film photodiode PD as described above has a parasitic capacitance Cgp which is opposed to the P-type semiconductor region (anode region (P ⁺ region) 36A) which is opposed to each other with the insulating film (gate insulating film 50) interposed therebetween. The metal film (control gate 38) is composed of. Further, the thin film photodiode PD has a parasitic capacitance Cgn which is opposed to the N-type semiconductor region (cathode region (N ⁺ region) 36K) which is opposed to each other with the insulating film (gate insulating film 50) interposed therebetween and the metal The membrane (control gate 38) is composed of.

In the present embodiment, when viewed from the one surface side and the other surface side, the region of the overlap region of the anode region (P ⁺ region) 36A and the control gate 38 is different from the cathode region (N ⁺ region) 36K. The area of the overlap with the control gate 38. This causes the capacitance values of the parasitic capacitance Cgp and the capacitance values of the parasitic capacitance Cgn to be different from each other.

Thus, in this configuration, the parasitic capacitance is reduced, i.e., the current storage capacitance is reduced, as compared to one of the thin film photodiodes configured in accordance with one of the related arts.

In addition, the control gate 38 is connected to the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, wherein the parasitic capacitance is large, that is, one of the parasitic capacitances Cgp and Cgn is larger, and the parasitic capacitance is The anode region or the cathode region itself is opposed to the control gate 38, which are opposed to each other with the gate insulating film 50 interposed therebetween.

This ensures that the larger of the parasitic capacitances Cgp and Cgn is significantly eliminated, whereby the parasitic capacitance can be further reduced, and the current storage capacitance can be further reduced.

As explained above, the sensor signal sensitivity can be increased by reducing the current storage capacitance as a parasitic capacitance, depending on the liquid crystal display including each of the photosensor portions of the thin film photodiode of the present embodiment.

In the above configuration, a change in the width Wp of the anode region (P ⁺ region) may have an influence on the sensitivity; therefore, an important factor is fully investigated to design this factor.

(Improvement of sensor sensitivity and improvement of saturation characteristics)

At the same time, in the case where the sensitivity of the photosensor portion is increased by reducing the parasitic capacitance of the thin film photodiode as described above, the saturation characteristic of the sensor will be affected.

In the present embodiment, the composition of the light incident on the thin film photodiode PD is accurately inspected in the manner described below, and the light which is desired to be detected in view of the operation of the thin film photodiode is as far as possible A plurality of incidents are incident on the thin film photodiode in an attempt to simultaneously obtain an improvement in one of the sensitivity of the sensor and an improvement in one of its saturation characteristics.

The thin film photodiode PD having sensitivity to invisible light as described above tends to decrease in S/N (signal-to-noise ratio) due to "stray light", and the stray light does not reach the object to be detected but in the liquid crystal panel 200. The reflection is internally repeated, thereby moving around to the side of the thin film photodiode PD.

For example, the light incident on the thin film photodiode is classified into the following: (1) optical noise entering the photodiode after reflection at an interface between the polarizing plate and the air; (2) reflection in the metal wiring Light noise entering the photodiode of the film after backlighting; (3) optical noise consisting of backlight directly entering the photodiode of the film; and (4) backlight reflected from the user's finger The light signal composed of light.

As described above, when invisible light emitted from a backlight impinges on and reflects on the wiring such as the VDD line 31, the VSS line 32, the detecting line 35, etc., the invisible light reaches the front side of the panel. The amount is reduced. In addition, before reaching the front side of the panel, part of the invisible light returns to the side of the thin film photodiode PD as stray light, and is received as a thin film photodiode PD as a noise component.

Here, the operation of the thin film photodiode is considered. In the case where the control gate 38 is connected to the cathode region (N ⁺ region) 36K, a depletion layer is formed near the boundary between the anode region (P ⁺ region) 36A and the I region 36I, so that the region is increased in the region. Optical sensitivity.

Therefore, preventing the backlight from deriving stray light into the I region 36I causes the stray light to be incident on a portion of the higher optical sensitivity of the thin film photodiode PD, improving the S/N and widening the dynamic range.

In the present embodiment, the control gate 38 provided in the thin film photodiode is a metal film, whereby incidence of stray light from the backlight can be prevented.

More specifically, the incidence of the stray light can be suppressed by using a configuration in which the control gate 38 is laid down under the higher optical sensitivity portion.

Specifically, the end portion of the anode region (P ⁺ region) 36A on the side of the cathode region (N ⁺ region) 36K and the end portion of the control gate 38 on the side of the anode region (P ⁺ region) The distance D between the portions is preferably in the range of 1.5 to 3.0 μm.

In addition, the cathode region (N ⁺ region) of the upper end portion 36K side 36A of the anode region (P ⁺ region) and the control gate on the side of the 36K cathode region (N ⁺ region) 38 of the electrode The distance between the end portions is preferably in the range of 1.5 to 3.0 μm.

The reason why the equidistance is set to be better within the range just described will be explained in a later example.

(operating)

Now, an illustrative operation example of one of the liquid crystal displays 100 will be described below.

In a pixel region, the backlight 300 is disposed on the rear side surface side of the liquid crystal panel 200. The illumination light from the backlight 300 is transmitted through the first polarizing plate 206, the TFT array substrate 201, the liquid crystal layer 203, the color filter 204, the color filter substrate 202, and the second polarizing plate 207 to be emitted from the front side surface for display. image.

In this transmission procedure, the light being transmitted is polarized into a first direction as it is transmitted through the first polarizing plate 206. When the light is transmitted through the liquid crystal layer 203, the polarization direction of the light being transmitted is changed by a predetermined angle in the molecular orientation direction by the optical anisotropy effect of one of the liquid crystal molecules. When light is transmitted through the second polarizing plate 207, the light being transmitted is polarized into a second direction which is shifted by a predetermined angle from the first direction.

During the process of the three polarization operations, the polarization angle during transmission through the liquid crystal layer 203 is independently changed pixel by pixel by controlling the intensity of the electric field applied to the liquid crystal layer 203 in accordance with the potential of the input image signal. Therefore, the light passing through each of the pixels undergoes modulation to obtain a luminance in accordance with the potential of the image signal, and then is emitted from the liquid crystal panel 200 for realizing a predetermined image display.

On the other hand, unlike the light transmitted through the pixels, the light passing through the portions of the photosensors in the sensor region does not undergo the modulation due to an electrical signal and is intact from the liquid crystal panel 200. Ground launch.

During image display, there is a situation in which, for example, a user's direction is prompted in the display content in accordance with an application. In this case, the user slightly touches the display screen using his finger or a stylus pen or the like.

When the user's finger or the stylus pen or the like as an object to be detected has touched or is in close proximity to the display screen, the light emitted from the liquid crystal panel 200 is reflected by the object and returned to the liquid crystal panel 200. The light (reflected light) thus returned undergoes repeated refraction and reflection at a layer interface existing in the liquid crystal panel 200 and a reflective object such as a wiring, so that the reflected light is generally advanced while being dispersed in the liquid crystal panel 200. Accordingly, the reflected light eventually reaches at least one of the plurality of photosensor portions 1 depending on the size of the object to be detected.

When a portion of the reflected light that has reached the photosensor portion 1 is incident on the thin film photodiode PD, and a predetermined reverse bias has been applied to the thin film photodiode, the thin film photodiode PD performs photoelectric conversion to An photo-electric charge is generated. The photo-electric charge is stored (accumulated) in a storage node SN, which is a current storage capacitor composed of an anode region (P ⁺ region) 36A and the like, and then output through an amplifying transistor TA connected to the storage node SN. . The amount of charge in this example represents light-receiving data that is proportional to the amount of received light. The light receiving data (the amount of charge) is output from the detecting line 35 as a detecting potential Vdet or a detecting current Idet in one of the reading circuits shown in FIG. 3B.

The detection potential Vdet or the detection current Idet is transmitted to the side of the sensor driver 13 by a switch array (SEL.SW.) 14 as shown in FIG. 2, where it is collected as light receiving data, and then The light receiving data thus collected is input to the position detecting block 402 in the data processing section 400 shown in FIG. From the side of the liquid crystal panel 200, a plurality of pairs of column and row addresses are sequentially supplied to the position detecting block 402 or the control block 401 in an instant manner based on the detecting potential Vdet or the detecting current Idet. Therefore, in the data processing section 400, the in-panel position information (detection potential Vdet or detection current Idet) of the object to be detected is stored in a memory in a state related to the column direction and the row direction address information. Within the body (not shown).

Based on the information in the memory, the liquid crystal display 100 superimposes the position information about the object to be detected and the display information, thereby determining that the user has displayed information based on using his finger or a stylus pen. Make a direction." Alternatively, it may be decided that "the user has entered the predetermined information by moving the stylus pen or the like on the display screen". Therefore, in the liquid crystal display 100, a function similar to that obtained by adding a touch panel to a liquid crystal display 200 can be realized for a thin display panel without adding any touch panel thereto. This display panel is referred to as an "in-cell touch panel."

(Method of forming a thin film photodiode)

Now, a method of forming a thin film photodiode provided in a photosensor portion in a liquid crystal display according to this embodiment will be described below.

Fig. 7A is a plan view showing a step in a procedure for forming a thin film photodiode provided in the liquid crystal display, and Fig. 7B is a cross-sectional view taken along line XX' of Fig. 7A.

For example, a metal film such as molybdenum is formed on a TFT array substrate 201 by sputtering or the like, and patterned into a control gate pattern to form a control gate 38.

Next, tantalum nitride and tantalum oxide are layered by, for example, CVD (Chemical Vapor Deposition) or the like to form a gate insulating film 50.

Subsequently, a semiconductor such as polysilicon is deposited, for example, by CVD or the like, and then patterned into a thin film photodiode pattern to form a semiconductor layer 36. The semiconductor layer 36 has a semiconductor which directly forms an intrinsic semiconductor region of a PIN diode unless a conductive impurity is introduced therein by ion implantation.

Fig. 8A is a plan view showing a step subsequent to the steps shown in Figs. 7A and 7B, and Fig. 8B is a cross-sectional view taken along line XX' of Fig. 8A.

Next, a photoresist film is formed over the entire region on the upper side of the semiconductor layer 36 by, for example, coating or the like. Subsequently, light is used to illuminate the TFT array substrate 201 from the one surface side (rear side surface) over the entire area to expose the photoresist film to the light using the control gate 38 as a mask, thereby being patterned in a pattern The pattern forms a photoresist mask M1 to protect a semiconductor portion from an intrinsic semiconductor region.

By exposing to light when the control gate 38 is used as a mask, the photoresist mask M1 can be patterned in a self-aligned manner with respect to the control gate 38.

Fig. 9A is a plan view showing a step subsequent to the steps shown in Figs. 8A and 8B, and Fig. 9B is a cross-sectional view taken along line XX' of Fig. 9A.

Subsequently, for example, ion implantation of an N-type conductive impurity at a low concentration is performed using the photoresist mask M1 as a mask to form a low-concentration semiconductor region 36N which contains the N-type at a low concentration Conductive impurities.

In this example, the portion protected by the photoresist mask M1 becomes an I region (essential semiconductor region) 36I.

Fig. 10A is a plan view showing a step subsequent to the steps shown in Figs. 9A and 9B, and Fig. 10B is a cross-sectional view taken along line XX' of Fig. 10A.

Then, for example, when the photoresist mask M1 is held as it is, a photoresist mask M2 is patterned by a photolithography step, which adopts a pattern to open a region to become an anode region (P ⁺ region). 36A. Here, the photoresist mask M2 is set so as to partially overlap the photoresist mask M1 such that the photoresist mask M1 and the photoresist mask M2 are combined in a pattern for protecting the anode region (P ⁺ region) 36A. section.

Subsequently, for example, a photoresist mask M1 and a photoresist mask M2 are used as a mask, and a P-type conductive impurity is introduced into the low-concentration semiconductor region 36N in the exposed portion at a high concentration by ion implantation. The anode region (P ⁺ region) 36A is formed to contain the P-type conductive impurities at a high concentration.

The position of the end portion of the anode region (P ⁺ region) 36A is determined by the photoresist mask M1, and thus the anode region (P ⁺ region) 36A is formed in a self-aligned manner with respect to the control gate 38.

Fig. 11A is a plan view showing a step subsequent to the steps shown in Figs. 10A and 10B, and Fig. 11B is a cross-sectional view taken along line XX' of Fig. 11A.

Next, for example, the photoresist mask M1 and the photoresist mask M2 are stripped, and then a photoresist mask M3 is patterned by a photolithography step, which adopts a pattern to form an opening portion to become a cathode region (N ⁺ area) 36K. Here, in order to ensure that a low concentration semiconductor region 36N is left between the cathode region (N ⁺ region) 36K and the I region 36I, a photoresist mask M3 is formed to protect the low concentration semiconductor region 36N over a predetermined width.

Subsequently, for example, a photoresist mask M3 is used as a mask, and an N-type conductive impurity is introduced into the low-concentration semiconductor region 36N in the exposed portion at a high concentration by ion implantation to form a cathode region (N). ⁺ region) 36K, which contains the N-type conductive impurities at a high concentration.

In a subsequent step, for example, the photoresist mask M3 is peeled off. Next, for example, by CVD, on the upper side of the semiconductor layer 36 including the anode region (P ⁺ region) 36A, the I region (essential semiconductor region) 36I, the low concentration semiconductor region 36N, and the cathode region (N ⁺ region) 36K. A first interlayer insulating film 51 is formed over the entire region. Subsequently, contact holes reaching the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, respectively, are turned on, and then each of the contact holes is filled with a conductor layer to form a contact plug 54.

In the above manner, a thin film photodiode provided in the photosensor portion of the liquid crystal display according to the present embodiment as shown in Figs. 5A and 5B can be formed.

<Modification example>

Figure 12A is a plan view of one of the thin film photodiodes PD of the PIN structure, and Figure 12B is a cross-sectional view taken along line XX' of Figure 12A.

The thin film photodiode PD is a photodiode having substantially the same configuration as that shown in FIGS. 5A and 5B. In this configuration, the width Wp of the one anode region (P ⁺ region) 36A in the direction perpendicular to the direction connected to the cathode region (N ⁺ region) 36K is smaller than the perpendicular to the anode region (P ⁺ region). The width Wn of the cathode region (N ⁺ region) 36K in the direction of the direction of 36A. In the vicinity of the end portion of the anode region (P ⁺ region) 36A on the side of the cathode region (N ⁺ region) 36K, an anode region (P ⁺ region) portion 36AW having a cathode region (N ⁺ region) is provided. A width of 36K width Wn (or the width of the I region (essential semiconductor region) 36I).

This makes it possible to suppress the decrease of the photocurrent flowing between the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K due to the narrowing of the width of the anode region (P ⁺ region) 36A. Further, it is also possible to suppress the effect of increasing the sensitivity due to the narrowing of the width Wp of the anode region (P ⁺ region) 36A.

In addition to this, there is an advantage in that the matching or alignment error influence of the intermediate surface position in the manufacturing step is smaller than those in the configurations shown in FIGS. 5A and 5B.

<Example 1>

As a thin film photodiode shown in FIGS. 5A and 5B, a thin film photodiode according to a prior art example is produced, in which the width Wp of the anode region (P ⁺ region) 36A and the width of the cathode region (N ⁺ region) 36 ^K are used. Wn is equal to 100 μm.

Here, by short-circuiting the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, the dependence of the gate capacitance Cg on the voltage Vg applied to the control gate from the gate terminal inspection is examined. Here, the width of the I region 36I arranged so as to be inserted between the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K is changed to 4.5 μm (a), 5.5 μm (b), and 6.5 μm, respectively. c), 7.5 μm (d), 8.5 μm (e), and 9.5 μm (f). In this case, the overlap between the control gate and the cathode region (N ⁺ region) 36K and the overlap between the control gate and the anode region (P ⁺ region) 36A are unchanged.

The results of the above examination are shown in FIG.

In the case where a certain degree of voltage is applied to the control gate, the gate capacitance Cg is larger as the width of the I region 36I is larger. However, when the voltage on the control gate is set to 0 V, the gate capacitance Cg is constant (about 150 fF) independently of the width of the I region 36I.

Figure 14 shows the gate capacitance Cg from (a) the gate capacitance Cg when a gate voltage is applied 10V and (b) the gate capacitance Cg when a gate voltage is applied to 0V by drawing the width L of the I region 36I. A diagram of the graph obtained by the above results.

When the gate voltage is applied 10V, the gate capacitance Cg is larger as the width of the I region 36I is larger.

When the gate voltage is 0 V, the gate capacitance Cg is constant (about 150 fF) independently of the width of the I region 36I.

In the above results, the gate capacitance increasing with the width of the I region 36I corresponds to the channel capacitance. On the other hand, it is considered that the gate capacitance Cg is independent of the width of the I region 36I and is constant due to a parasitic capacitance which is caused by the overlap between the control gate and the cathode region (N ⁺ region) 36K. The overlap between the control gate and the anode region 36A (P ⁺ region) is determined.

<Example 2>

Based on the configuration of the thin film photodiode shown in FIGS. 5A and 5B, a film is formed by setting the width Wn of the cathode region (N ⁺ region) 36K to 100 μm and varying the width Wp of the anode region (P ⁺ region) 36A. The photodiode is measured, and the variation of the parasitic capacitance Cp which varies with the width Wp is measured.

These results are shown in Fig. 15, in which (a) shows the parasitic capacitance when viewed from the control gate 38, and (b) shows the parasitic capacitance when viewed from the anode region (P ⁺ region) 36A.

As seen from the figure, in the case where the control gate 38 and the cathode region (N ⁺ region) 36K are connected to each other, the parasitic capacitance component when viewed from the control gate 38 is viewed from the anode region (P ⁺ region) 36A. The parasitic capacitance component is simultaneously reduced as the width of the anode region (P ⁺ region) 36A decreases. Thus, it has been confirmed that reducing the number of overlaps between the control gate 38 and the anode region (P ⁺ region) 36A and the number of overlaps between the control gate 38 and the cathode region (N ⁺ region) 36K is one for reducing parasitics. An effective technique for capacitors.

In this case, as described above, since the sensor signal sensitivity (voltage) is represented by (photocurrent) × (exposure time) / (current storage capacitor), the capacitance can be reduced at a constant photocurrent. Next, the sensitivity of the sensor can be improved.

<Example 3>

In the same manner as in Example 2, based on the configuration of the thin film photodiode shown in FIGS. 5A and 5B, by changing the width Wp of the anode region (P ⁺ region) 36A while maintaining the cathode region (N ⁺ region) A film photodiode was fabricated with a width Wn of 36 K at a constant value of 100 μm. Using the thin film photodiode thus obtained, the variation of the photocurrent Inp with the width Wp was measured.

These results are shown in Figure 16. In the case where the photocurrent Inp is proportional to the width Wp of the anode region (P ⁺ region) 36A, the data is necessarily drawn on a dotted line passing through the origin in the drawing. However, actually, it is found that a photoelectric current larger than that expected from the proportional (linear) flow even when the width Wp of the anode region (P ⁺ region) 36A is narrowed.

Specifically, in the case where the width Wn of the cathode region (N ⁺ region) 36K and the width Wp of the anode region (P ⁺ region) 36A are narrowed, the photocurrent does not show any extreme decrease, but does not remain. Constant. Thus, it has been shown that a reduction in the width Wn of the cathode region (N ⁺ region) 36K or the anode region (P ⁺ region) 36A can contribute to an increase in sensitivity.

<Example 4>

As described above, the sensor signal sensitivity (voltage) can be expressed by (photocurrent) x (exposure time) / (current storage capacitor). In view of this, the film photodiode obtained by varying the width Wp of the anode region (P ⁺ region) 36A while maintaining the width Wn of the cathode region (N ⁺ region) 36 ^K at 100 μm is estimated at a constant exposure time. Relative sensitivity RS (relative value).

These results are shown in Figure 17. It can be seen that the relative sensitivity greatly increases as the width Wp of the anode region (P ⁺ region) 36A becomes narrow.

However, when the width Wp of the anode region (P ⁺ region) 36A becomes too small, a problem arises because the sensitivity will largely vary depending on the width Wp of the actually formed anode region (P ⁺ region).

Taking this into consideration, in order to ensure the sensitivity of the sensor is increased, but the sensitivity dispersion is not increased, the width Wp of the anode region (P ⁺ region) 36A is preferably from 30 μm (inclusive) to 100 μm (excluded). Within the range, the width Wn of the cathode region (N ⁺ region) 36K is 100 μm.

In other words, in the thin film photodiode PD, the ratio R1 of the width Wp of the anode region (P ⁺ region) 36A to the width Wn of the cathode region (N ⁺ region) 36K is preferably In the range.

<Example 5>

The change in the terminal for the cathode region by (N ⁺ region) of the end portion 36A of the anode region (P ⁺ region) on the side of the control gate and 36K on the side 36A of the anode region (P ⁺ region) 38 of the electrode A simulation was performed on the thin film photodiode made by the distance D between the parts. Here, the relative light amount RL (relative value) obtained by the simulation corresponds to a noise component incident on the thin film photodiode after reflecting the backlight light on a wiring or the like.

These results are shown in Figure 18. It has been found that the relative amount of light RL decreases as the distance D increases.

Here, an actual optical signal level SIG is shown in the figure. It was found that the optical signal level value is larger than the noise component when the distance D is set to not less than 0.5 μm.

<Example 6>

With respect to the thin film photodiode shown in Figs. 5A and 5B, the following estimation was made on the assumption that the width Wn of the cathode region (N ⁺ region) 36K was 100 μm and the width Wp of the anode region (P ⁺ region) 36A was 30 μm.

Here, the end portion of the anode region (P ⁺ region) 36A on the side of the cathode region (N ⁺ region) 36K and the end portion of the control gate 38 on the side of the anode region (P ⁺ region) The distance between D. For these thin film photodiodes, the relative sensitivity RS (relative value) is estimated at a constant exposure time.

These results are shown in Figure 19. It has been found that the relative light quantity RS decreases as the distance D increases.

As seen in this figure, the preferred system on the cathode region (N ⁺ region) of the end portion of the anode region (P ⁺ region) 36A on the side of the side of 36K in the anode region (P ⁺ region) of 36A The distance D between the end portions of the control gate 38 is set to be in the range of 1.5 to 3.0 μm. This makes it possible to achieve dispersion stability of the sensor sensitivity.

<Example 7>

As for the thin film photodiode shown in Figs. 5A and 5B, the following estimation was carried out under the assumption that the width Wn of the cathode region (N ⁺ region) 36K was 100 μm and the width Wp of the anode region (P ⁺ region) 36A was 30 μm.

Here, the end portion of the anode region (P ⁺ region) 36A on the side of the cathode region (N ⁺ region) 36K and the end portion of the control gate 38 on the side of the anode region (P ⁺ region) 36A are changed. The distance D between the parts. For the thin film photodiodes, the amount of light L _SAT (relative value) at which the signal of the photosensor portion is saturated is estimated.

These results are shown in Figure 20. As seen in this figure, the preferred system on the cathode region (N ⁺ region) of the end portion of the anode region (P ⁺ region) 36A on the side of the side of 36K in the anode region (P ⁺ region) of 36A The distance D between the end portions of the control gate 38 is set to be in the range of 1.5 to 3.0 μm. It was found that this setting improved the saturation characteristic by a factor of 2.5 as compared with the case where D = -0.2 μm.

Therefore, it has been found that in addition to the sensitivity characteristics of the sensor, the dynamic range is improved.

According to the specific embodiment and its modified example, in each of the thin film photodiodes formed in the sensor region of the display section (substrate), the width of the P-type semiconductor region and the N-type The widths of the semiconductor regions are different from each other. This can reduce the parasitic capacitance between the thin film photodiode and the metal film, thereby improving the detection sensitivity of the sensor and improving the saturation characteristics of the sensor.

<Second Specific Embodiment>

Figure 21A is a plan view showing a film photodiode PD of one of the PIN structures according to the present embodiment, and Figure 21B is a cross-sectional view taken along line XX' of Figure 21A. In FIG. 21B, the wiring such as the VDD line 31 and the configuration of the second interlayer insulating film 52 and the upper layers are omitted. The display in this embodiment has the same configuration as that in the first embodiment except for the configuration of the thin film photodiode PD.

For example, a control gate 38 having a "metal film" is formed on a TFT array substrate 201, two gate insulating films 50 are formed on the upper side thereof, and a semiconductor layer 36 is formed on the other upper side.

The semiconductor layer 36 has a pattern shape as shown in FIG. 21A. Specifically, an anode region 36A having a P ⁺ region (P-type semiconductor region), an I region (essential semiconductor region) 36I, a low concentration semiconductor region (N ^- region) 36N, and a cathode region are respectively disposed. 36K, which has an N ⁺ region (N-type semiconductor region). A thin film photodiode of the PIN structure is thus configured having a low concentration semiconductor region.

In this layout, perpendicular to the one direction is connected to the cathode region (N ⁺ region) and 36K of direction width Wp of the anode region (P ⁺ region) 36A of the perpendicular to the connection to the anode region (P ⁺ region) direction in 36A of The width Wn of the cathode region (N ⁺ region) 36K in the direction is different from each other.

In addition, the layout of the control gates 38 with respect to these regions is as shown in FIG. 21A.

Here, the anode region is provided outside the overlap region of the anode region (P ⁺ region) 36A and the control gate 38, and an extension portion 36AL extends upward in a direction perpendicular to the direction connecting the cathode region (N ⁺ region) 36K. .

Further, a first interlayer insulating film 51 is formed to cover the photodiode and is connected to the contact plug 54 through a contact hole CT reaching the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K. A contact hole reaching the anode region (P ⁺ region) 36A is provided in the extended portion 36AL.

In this embodiment, a configuration may be employed in which the area of the overlap region of the anode region (P ⁺ region) 36A and the control gate 38 is different from the cathode region when viewed from the one surface side or the other surface side. (N ⁺ zone) 36K and the area of the overlap region of one of the control gates 38. This causes the capacitance value of the parasitic capacitance Cgp to be different from the capacitance value of the parasitic capacitance Cgn.

Thus, a configuration is obtained in which the parasitic capacitance is reduced, i.e., the current storage capacitance is reduced, as compared to a thin film photodiode configured in accordance with one of the related art.

In addition, preferably, the control gate 38 is connected to the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, wherein the parasitic capacitance is large, that is, the parasitic capacitances Cgp and Cgn are larger. The parasitic capacitance is formed between the anode region or the cathode region itself and the control gate 38 which are opposed to each other with the gate insulating film 50 interposed therebetween. In the present embodiment, control gate 38 is coupled to a cathode region (N ⁺ region) 36K.

This ensures that the larger of the parasitic capacitances Cgp and Cgn is significantly eliminated, and the parasitic capacitance can be further reduced, thereby further reducing the current storage capacitance.

According to the liquid crystal display including each of the photosensor portions having the thin film photodiodes of the present embodiment, as described above, the sensor signal sensitivity can be increased by reducing the current storage capacitor as a parasitic capacitance. .

In the thin film photodiode of the present embodiment, the structure of the anode region (P ⁺ region) 36A outside the region overlapping the control gate 38 is substantially arbitrary.

On the other hand, for reasons to be explained later, it is preferred not to provide the extension portion 36AL or it is as short as possible, and this can be applied, for example, to the addition of some of the opening portions of the contact holes. Restricted situation.

<Example 8>

A thin film photodiode of the display according to the first embodiment and a thin film photodiode of the display according to the second embodiment are fabricated. Here, the fabrication is carried out by varying the width Wp of the anode region (P ⁺ region) 36A while maintaining the width Wn of the cathode region (N ⁺ region) 36K at a constant value of 100 μm. For these thin film photodiodes, the variation in parasitic capacitance with width Wp was measured.

The results are shown in Fig. 22, wherein (a) is the parasitic capacitance when viewed from the anode region (P ⁺ region) 36A in the thin film photodiode configured in accordance with the first embodiment, and (b) The parasitic capacitance when viewed from the anode region (P ⁺ region) 36A in the thin film photodiode configured according to the second embodiment.

The amount of parasitic capacitance can be reduced by narrowing the width Wp of the anode region (P ⁺ region) 36A to be larger in the thin film photodiode configured in accordance with the first embodiment. Therefore, in view of increasing the sensitivity of the sensor signal by reducing the current storage capacitance, the configuration according to the first embodiment is preferred.

<Third embodiment>

Figure 23A is a plan view of one of the thin film photodiodes PD of the PIN structure in the present embodiment, and Figure 23B is a cross-sectional view taken along line XX' of Figure 23A. In FIG. 23B, the wiring such as the VDD line 31 and the configuration of the second interlayer insulating film 52 and the upper layers are omitted. The display in this embodiment has the same configuration as that in the first embodiment except for the configuration of the thin film photodiode PD.

For example, a control gate 38 having a "metal film" is formed on a TFT array substrate 201, a gate insulating film 50 is formed on the upper side thereof, and a semiconductor layer 36 is formed on the other upper side.

The semiconductor layer 26 has a pattern shape as shown in Fig. 23A. Specifically, an anode region 36A having a P ⁺ region (P-type semiconductor region); an I region (essential semiconductor region) 36I; a low concentration semiconductor region (N ^- region) 36N; and a cathode region 36K are disposed. It has an N ⁺ region (N-type semiconductor region). A thin film photodiode of the PIN structure is thus configured having a low concentration semiconductor region.

In this layout, perpendicular to the one direction is connected to the cathode region (N ⁺ region) and 36K of direction width Wp of the anode region (P ⁺ region) 36A of the perpendicular to the connection to the anode region (P ⁺ region) direction in 36A of The width Wn of the cathode region (N ⁺ region) 36K in the direction is different from each other.

In addition, the layout of the control gates 38 with respect to these regions is as shown in FIG. 23A.

In addition to this, the first insulating film 51 is formed so as to cover the photodiode and is connected to the contact plug 54 through the contact hole CT reaching the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K. .

Here, in the vicinity of the end portion of the I region 36I on the side of the anode region (P ⁺ region) 36A, an I region portion 36IW having a width corresponding to the width Wp of the anode region (P ⁺ region) 36A is provided. .

In this embodiment, similar to the area in which the anode region (P ⁺ region) 36A overlaps with one of the control gates 38 when viewed from the one surface side or the other surface side in the first embodiment. The regions of the cathode region (N ⁺ region) 36K and the overlap region of one of the control gates 38 are different from each other. This results in a configuration in which the capacitance value of the parasitic capacitance Cgp is different from the capacitance value of the parasitic capacitance Cgn.

Thus, a configuration is obtained in which the parasitic capacitance is reduced, i.e., the current storage capacitance is reduced, as compared to a thin film photodiode configured in accordance with the related art.

In addition, preferably, the control gate 38 is connected to the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, wherein the parasitic capacitance is large, that is, one of the parasitic capacitances Cgp and Cgn is larger. The parasitic capacitance is formed between the anode region or the cathode region itself and the control gate 38 which are opposed to each other with the gate insulating film 50 interposed therebetween. In the present embodiment, control gate 38 is coupled to a cathode region (N ⁺ region) 36K.

This ensures that the larger of the parasitic capacitances Cgp and Cgn is significantly eliminated, and the parasitic capacitance can be further reduced, thereby further reducing the current storage capacitance.

As described above, according to the liquid crystal display including each of the photosensor portions having the thin film photodiodes of the present embodiment, the sensor signal sensitivity can be increased by reducing the current storage capacitance as a parasitic capacitance. .

Specifically, in the thin film photodiode according to the present embodiment, the anode region (P ⁺ region) 36A and the control gate 38 are compared with those in the thin film photodiode in the first embodiment. The overlap between the regions is narrowed such that the parasitic capacitance Cgp is reduced more in this particular embodiment than in the first embodiment.

In addition, since the interface between the I region 36I and the anode region (P ⁺ region) 36A is provided in the portion of the width Wp, there is an advantage that the influence of the matching or alignment error of the intermediate surface position in the fabrication steps is Less than those in the first embodiment.

In the above configuration, the variation of the width Wp of the anode region (P ⁺ region) 36A may have an influence on the sensitivity, and therefore important factors are sufficiently investigated to design this factor.

Further, using the I region 36I having a portion having the width Wp, the loss due to recombination may become larger than in the first embodiment. In the case where the loss is large, it is more important to reduce the area of the I-zone portion 36IW and investigate within a range to have little influence.

<Fourth embodiment>

Figure 24A is a plan view of one of the thin film photodiodes PD of the PIN structure in the present embodiment, and Figure 24B is a cross-sectional view taken along line XX' of Figure 24A. In FIG. 24B, the wiring such as the VDD line 31 and the configuration of the second interlayer insulating film 52 and the upper layers are omitted. The display in this embodiment has the same configuration as that in the first embodiment except for the configuration of the thin film photodiode PD.

For example, a control gate 38 having a "metal film" is formed on a TFT array substrate 201, two gate insulating films 50 are formed on the upper side thereof, and a semiconductor layer 36 is formed on the other upper side.

The semiconductor layer 36 has a pattern shape as shown in Fig. 24A. Specifically, an anode region 36A having a P ⁺ region (P-type semiconductor region), an I region (essential semiconductor region) 36I, a low concentration semiconductor region (N ^- region) 36N, and a cathode region are respectively disposed. 36K, which has an N ⁺ region (N-type semiconductor region). A thin film photodiode of the PIN structure is thus configured having a low concentration semiconductor region.

Further, a first interlayer insulating film 51 is formed to cover the photodiode and is connected to the contact plug 54 through a contact hole CT reaching the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K.

Here, the width Lp overlapping between the anode region (P ⁺ region) 36A and the control gate 38 when viewed from the one surface side or the other surface side is set smaller than the cathode region (N ⁺ region) 36K and The width Ln of the overlap between the gates 38 is controlled.

Similarly, in the first embodiment, this results in an area where the anode region (P ⁺ region) 36A overlaps with one of the control gates 38 and the cathode region (N) when viewed from the one surface side or the other surface side. ^The area of the overlap region of the ^+K ) 36K and the control gate 38 is different from each other. Thereby, the capacitance value of the parasitic capacitance Cgp is different from the capacitance value of the parasitic capacitance Cgn.

Thus, a configuration is obtained in which the parasitic capacitance is reduced, i.e., the current storage capacitance is reduced, as compared to a thin film photodiode configured in accordance with the related art.

In addition, preferably, the control gate 38 is connected to the anode region (P ⁺ region) 36A and the cathode region (N ⁺ region) 36K, wherein the parasitic capacitance is large, that is, one of the above parasitic capacitances Cgp and Cgn is larger. The parasitic capacitance is formed between the anode region or the cathode region itself and the control gate 38 which are opposed to each other with the gate insulating film 50 interposed therebetween. In short, the control gate 38 is preferably connected to the larger of the parasitic capacitances Cgp and Cgn described above. In the present embodiment, control gate 38 is coupled to a cathode region (N ⁺ region) 36K.

This ensures that the larger of the parasitic capacitances Cgp and Cgn is significantly eliminated, and the parasitic capacitance can be further reduced, thereby further reducing the current storage capacitance.

As described above, according to the liquid crystal display including each of the photosensor portions having the thin film photodiodes of the present embodiment, the sensor signal sensitivity can be increased by reducing the current storage capacitance as a parasitic capacitance. .

In particular, the thin film photodiode according to this embodiment has an advantage that the loss due to recombination is smaller than in the first embodiment.

The effect of the width Wp variation of the anode region (P ⁺ region) 36A on the sensitivity is also smaller than that of the first embodiment.

In addition, since the interface between the I region 36I and the anode region (P ⁺ region) 36A is provided in the portion of the width Wp, there is an advantage that the influence of the matching or alignment error of the intermediate surface position in the fabrication steps is Less than those in the first embodiment.

<Example 9>

By changing the width based on the configuration of the thin film photodiode of the display of the fourth embodiment in which the width Wn of the cathode region (N ⁺ region) 36K and the width Wp of the anode region (P ⁺ region) 36A are equal to each other (Wavelength) to produce a thin film photodiode. Here, the width Lp overlapping between the anode region (P ⁺ region) 36A and the control gate 38 and the width Ln overlapping between the cathode region (N ⁺ region) 36K and the control gate 38 are set to 0.5 μm, respectively. With 1.5μm.

Using these thin film photodiodes, the parasitic capacitance Cgp between the control gate 38 and the anode region (P ⁺ region) 36A as a function of wavelength is measured and between the control gate 38 and the cathode region (N ⁺ region) 36K. The variation of the parasitic capacitance Cgn.

These results are shown in Figure 25.

As seen in the figure, both Cgp and Cgn increase as the wavelength increases. However, Cgn is larger in slope for this wavelength, and Cgn is larger than Cgp by a larger number.

Here, as shown in the fourth embodiment, the connection between the control gate 38 and the cathode region (N ⁺ region) 36K causes the presence of only Cgp (which is the smaller of the parasitic capacitances Cgp and Cgn). The conditions of the case. This makes it possible to further reduce the parasitic capacitance and increase the sensitivity of the sensor signal by reducing the current storage capacitance.

<Fifth Embodiment>

(example of the product obtained by applying the display)

These specific embodiments and their modifications can be applied as part of a character/image display in the various products listed below.

For example, it can be applied to a monitor of a television set, a personal computer or the like, a mobile device having a video reproduction function (such as a mobile phone, a game machine, a PDA, etc.), an imaging device (such as a still camera, a video camera, etc.), On-board equipment (such as car navigation units) and so on.

Further, in the case where infrared rays are used as invisible light, a person's body temperature distribution can be detected as an infrared pattern. Thus, embodiments of the present invention are applicable to the efficient use of infrared light in the identification of veins in a human finger.

In this case, instead of the liquid crystal panel 200, a vein discriminating unit is provided, which includes a vein discriminating panel through which the vein discriminating panel can transmit light from the backlight and based on the surface emitted from the backlight and touching the vein discriminating panel Infrared rays reflected by human fingers perform vein identification.

<First Application Example>

Figure 26 is a perspective view of a television set as a first application example. A television set according to this application example includes an image display screen section 101 having a front panel 102, a filter glass 103, etc., and the display described above is applicable to the image display screen section 101.

<Second Application Example>

27A and 27B illustrate a digital camera as a second application example, in which Fig. 27A is a perspective view from the front side, and Fig. 27B is a perspective view from the rear side. The digital camera according to this application example includes a flash firing section 111, a display section 112, a menu switch 113, a shutter button 114, and the like, and the above-described displays are applicable to the display section 112.

<Third application example>

Figure 28 is a perspective view of one of the notebook size personal computers as a third application example. A notebook-sized personal computer according to this application example has a main body 121 including a keyboard 122 that operates when a character or the like is input, a display section 123 for displaying an image or the like, and the display described above It can be applied to the display section 123.

<Fourth Application Example>

Figure 29 is a perspective view of a video camera as a fourth application example. A video camera according to this application example includes a main body section 131; a lens 132 for photographing an object, which is located at a front side surface; and a start/stop switch 133 which is used when photographing; Sections 134 and the like are displayed, and the displays described above are applicable to display section 134.

<Fifth Application Example>

30A to 30G illustrate a mobile terminal device, such as a mobile phone, as a fifth application example. In the illustrations, Fig. 30A is a front view of the mobile phone in an open state, Fig. 30B is a side view thereof, and Fig. 30C is a front view of the mobile phone in a closed state, Fig. 30D A left side view, FIG. 30E is a right side view, FIG. 30F is a top view thereof, and FIG. 30G is a bottom view thereof. The mobile phone according to this application example includes an upper casing 141, a lower casing 142, a connecting section (here, a hinge section) 143, a display 144, a sub-display 145, an image lamp 146, and a camera 147. And the like, and the displays described above are applicable to display 144 and sub-display 145.

A display according to a specific embodiment of the present invention is not limited to the ones described above.

For example, in the above embodiment, the control gate is connected to the side of the cathode region (N ⁺ region) 36K and the width of the anode region (P ⁺ region) 36A is set to be smaller than the cathode region (N ⁺ region) 36K. Width, this configuration is not restrictive. For example, a configuration is possible in which the control gate is connected to the side of the anode region (P ⁺ region) 36A, and the width of the cathode region (N ⁺ region) 36K is set to be smaller than the anode region (P ⁺ region) 36A. The width.

In this case, for the same reason as described above, the ratio R2 of the width Wn of the cathode region (N ⁺ region) 36K to the width Wp of the anode region (P ⁺ region) 36A in the thin film photodiode PD is preferable. in In the range.

In addition, for the same reason as described above, the cathode region (N ⁺ region) of the upper end portion 36K side 36A of the anode region (P ⁺ region) and the cathode region (N ⁺ region) of 36K The distance between the end portions of the control gates 38 on the side is preferably in the range of 1.5 to 3.0 μm.

Moreover, although a liquid crystal display is described in the above specific embodiments, this is not limitative, and other displays such as an organic EL display and an electronic paper based display may be applied to the display according to the embodiment of the present invention.

In addition to the above, various modifications may be made without departing from the scope or spirit of the invention.

1. . . Light sensor section

10. . . Display section

11. . . Vertical drive (V.DRV.)

12. . . Display driver (D-DRV.)

13. . . Sensor Driver (S-DRV.)

14. . . Select switch array (SEL.SW.)

15. . . DC-DC converter (DC/DC.CNV.)

16. . . Flexible substrate

21K. . . Black matrix

31. . . Supply line / VDD line

32. . . Supply line / VSS line

33. . . Supply line / reset line

34. . . Supply line / read control line

35. . . Detection line

36. . . Thin film semiconductor layer

36A. . . Anode zone (P ⁺ zone)

36AL. . . Extension

36AW. . . Anode region (P ⁺ region)

36I. . . Zone I (essential semiconductor zone)

36K. . . Cathode area (N ⁺ area)

36IW. . . Part I

36N. . . Low concentration semiconductor region (N ^- region)

38. . . Control gate

39. . . wiring

40. . . Pixel electrode

41. . . contact

42. . . Internal wiring

43. . . Thin film semiconductor layer

44. . . Vertical scan line

45A. . . Signal line

50. . . Double gate insulating film

51. . . Double layer first interlayer insulating film

52. . . Second interlayer insulating film (planar film)

53. . . Third interlayer insulating film

54. . . Contact plug

55. . . Common electrode

56. . . Oriented (aligned) film

100. . . LCD Monitor

101. . . Image display screen section

102. . . Front panel

103. . . Filter glass

111. . . Flash firing section

112. . . Display section

113. . . Menu switch

114. . . Shutter button

121. . . main body

122. . . keyboard

123. . . Display section

131. . . Body section

132. . . lens

133. . . Start/stop switch

134. . . Display section

141. . . Upper housing

142. . . Lower housing

143. . . Connection section / hinge section

144. . . monitor

145. . . Sub display

146. . . Image light

147. . . camera

200. . . LCD panel

201. . . TFT (thin film transistor) array substrate

202. . . Color filter substrate

203. . . Liquid crystal layer

204. . . Color filter

206. . . First polarizer

207. . . Second polarizer

300. . . Backlight

301. . . light source

301a. . . Visible light source

301b. . . IR (infrared) light source

302. . . Light guide

400. . . Data processing section

401. . . Control block

402. . . Position detection block

CA. . . Surrounding area

CG. . . Control gate

CT. . . Contact hole

GM. . . Gate metal

M1. . . Photoresist mask

M2. . . Photoresist mask

M3. . . Photoresist mask

PA. . . Effective display area

PA1. . . Pixel area

PA2. . . Sensor area

PD. . . Thin film photodiode

PIX. . . Pixel

SA. . . Sensor opening

SN. . . Storage node

SW. . . Switching element

TA. . . Amplifying the transistor

TR. . . Reading transistor

TS. . . Reset transistor

1 is a schematic, general configuration diagram of a liquid crystal display according to a first embodiment of the present invention;

Figure 2 is a block diagram showing the configuration of a driving circuit in a liquid crystal display according to a first embodiment of the present invention;

3A is a plan view showing one of the photosensor portions provided in the liquid crystal display according to the first embodiment of the present invention, and FIG. 3B is equivalent to one of the photosensor portions corresponding to the pattern in FIG. 3A. Circuit diagram

4 is a schematic cross-sectional view showing a portion of a photosensor provided in a liquid crystal display according to a first embodiment of the present invention and a portion of a pixel in a liquid crystal of an FFS (Field Edge Switching) system Figure

5A is a plan view showing one of the photodiodes of a PIN structure in the liquid crystal display according to the first embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line XX' of FIG. 5A. ;

6A and 6B are circuit diagrams showing parasitic capacitances present at a thin film photodiode and a control gate in accordance with a first embodiment of the present invention;

Figure 7A is a plan view showing a step in the process of forming a thin film photodiode provided in a liquid crystal display according to the first embodiment of the present invention, and Figure 7B is taken along the line X-X' of Figure 7A. a cross-sectional view taken;

Figure 8A is a plan view showing a step subsequent to the steps shown in Figures 7A and 7B, and Figure 8B is a cross-sectional view taken along line XX' of Figure 8A;

Figure 9A is a plan view showing a step subsequent to the steps shown in Figures 8A and 8B, and Figure 9B is a cross-sectional view taken along line XX' of Figure 9A;

Figure 10A is a plan view showing a step subsequent to the steps shown in Figures 9A and 9B, and Figure 10B is a cross-sectional view taken along line XX' of Figure 10A;

Figure 11A is a plan view showing a step subsequent to the steps shown in Figures 10A and 10B, and Figure 11B is a cross-sectional view taken along line XX' of Figure 11A;

12A is a plan view showing one of the photodiodes of a PIN structure in a liquid crystal display according to a modification of one embodiment of the present invention, and FIG. 12B is taken along line X-X' of FIG. 12A. a sectional view;

13 is a diagram showing dependence of a gate capacitance on a voltage applied to a control gate when viewed from a gate terminal according to Example 1;

Figure 14 is a diagram obtained by plotting the results of Figure 13;

Figure 15 is a diagram showing the dependence of parasitic capacitance on the width of the anode region according to Example 2;

Figure 16 is a diagram showing the dependence of the photoelectric current on the width of the anode region according to Example 3;

Figure 17 is a diagram showing the dependence of relative sensitivity on the width of the anode region according to Example 4;

Figure 18 is a diagram showing the dependence of the relative amount of light corresponding to the noise component on the distance between one end portion of an anode region and one end portion of a control gate according to Example 5;

Figure 19 is a diagram showing the dependence of the relative sensitivity on the distance between the end portion of the anode region and the end portion of the control gate according to Example 6;

Figure 20 is a diagram showing the dependence of the amount of light used for signal saturation at the photosensor portion on the distance between the end portion of the anode region and the end portion of the control gate, according to Example 7;

21A is a plan view showing a photodiode of a PIN structure in a liquid crystal display according to a second embodiment of the present invention, and FIG. 21B is a view taken along line X-X' of FIG. 21A. Sectional view

Example 8 FIG. 22 system according to the display width dependency of the parasitic capacitance of the anode region (P ⁺ region) of the anode region when viewing from a (P ⁺ region) a schema;

Figure 23A is a plan view showing one of the photodiodes of a PIN structure in a liquid crystal display according to a third embodiment of the present invention, and Figure 23B is a view taken along line X-X' of Figure 23A. Sectional view

Figure 24A is a plan view showing one of the photodiodes of a PIN structure in a liquid crystal display according to a fourth embodiment of the present invention, and Figure 24B is a view taken along line X-X' of Figure 24A. Sectional view

Figure 25 is a graph showing the dependence of parasitic capacitance on wavelength according to Example 9;

Figure 26 is a perspective view of a television set as a first application example according to a fifth embodiment of the present invention;

27A and 27B illustrate a digital camera as a second application example according to a fifth embodiment of the present invention, wherein FIG. 27A is a perspective view from the front side, and FIG. 27B is a perspective view from the rear side;

Figure 28 is a perspective view of a notebook-sized personal computer as a third application example according to a fifth embodiment of the present invention;

Figure 29 is a perspective view of a video camera as a fourth application example according to a fifth embodiment of the present invention;

30A to 30G illustrate a mobile phone as a fifth application example according to a fifth embodiment of the present invention, wherein FIG. 30A is a front view of the mobile phone in an open state, and FIG. 30B is a side view thereof. Figure 30C is a front view of the mobile phone in a closed state, Figure 30d is a left side view, Figure 30E is a right side view, Figure 30F is a top view thereof, and Figure 30G is a bottom view thereof.

36. . . Thin film semiconductor layer

36A. . . Anode zone (P ⁺ zone)

36I. . . Zone I (essential semiconductor zone)

36K. . . Cathode area (N ⁺ area)

36N. . . Low concentration semiconductor region (N ^- region)

38. . . Control gate

50. . . Double gate insulating film

51. . . Double layer first interlayer insulating film

54. . . Contact plug

201. . . TFT (thin film transistor) array substrate

CT. . . Contact hole

Claims (20)

A display comprising: a substrate having a pixel region defining a pixel therein, and a sensor region defining a photosensor portion therein; an illumination segment configured to be One surface of the substrate illuminates the substrate; a thin film photodiode disposed in the sensor region, having at least one positive semiconductor region, and a negative semiconductor region, and configured to receive from Light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate by being opposed to the thin film optical diode with an insulating film interposed therebetween, and configured The light generated from the illumination segment is directly incident on the thin film photodiode from the surface side and fixed to a predetermined potential, wherein in the thin film photodiode, perpendicular to the negative connection The width of the positive semiconductor region in one direction of the direction of the semiconductor region is different from the width of the negative semiconductor region in a direction perpendicular to the direction connected to the positive semiconductor region. The display of claim 1, wherein in the thin film photodiode, when viewed from one of the surface side and the other surface side, the area of the positive semiconductor region and the overlap region of the metal film are different And a region of the negative semiconductor region overlapping the one of the metal films. The display of claim 1, wherein the metal film is connected to the negative semiconductor region, and in the thin film photodiode, the positive semiconductor region is perpendicular to a direction perpendicular to a direction connected to the negative semiconductor region. The width is less than the width of the negative semiconductor region in a direction perpendicular to the direction of connection to the positive semiconductor region. The display of claim 3, wherein in the thin film photodiode, when viewed from one of the surface side and the other surface side, a region of the overlapping region of the positive semiconductor region and the metal film is smaller than A region of the negative semiconductor region and an overlap region of the metal film. The display of claim 3, wherein in the thin film photodiode, a ratio R1 of the width of the positive semiconductor region to the width of the negative semiconductor region is Within the scope. The display of claim 1, wherein the metal film is connected to the positive semiconductor region, and in the thin film photodiode, the positive semiconductor region in a direction perpendicular to a direction connected to the negative semiconductor region The width is greater than the width of the negative semiconductor region in a direction perpendicular to the direction of connection to the positive semiconductor region. The display of claim 6, wherein in the thin film photodiode, when viewed from one of the surface side and the other surface side, a region of the overlapping region of the positive semiconductor region and the metal film is smaller than A region of the negative semiconductor region and an overlap region of the metal film. The display of claim 6, wherein in the thin film photodiode, a ratio R2 of the width of the negative semiconductor region to the width of the positive semiconductor region is 0.3 Within the range of R2 < 1. The display of claim 1, wherein the thin film photodiode has an intrinsic semiconductor region and/or a low concentration semiconductor region between the negative semiconductor region and the positive semiconductor region, the low concentration semiconductor region having a lower concentration A concentration of a conductive impurity of a concentration of a conductive impurity of the negative semiconductor region and the positive semiconductor region. The display of claim 1, wherein the semiconductor region including the positive semiconductor region and the negative semiconductor region constituting the thin film photodiode is formed of a polysilicon, a microcrystalline germanium, an amorphous germanium or a crystalline germanium. The display of claim 1, wherein the illumination segment emits invisible light, and the thin film photodiode is sensitive to the invisible light. The display of claim 1, wherein a distance between one end portion of the positive-type semiconductor region on the negative-type semiconductor region side and one end portion of the metal film on the positive-type semiconductor region is 1.5 to Within the range of 3.0 μm. The display of claim 1, wherein a distance between one end portion of the negative semiconductor region on the side of the positive semiconductor region and one end portion of the metal film on the negative semiconductor region is 1.5 to Within the range of 3.0 μm. A display comprising: a substrate having a pixel region defining a pixel therein, and a sensor region defining a photosensor portion therein; an illumination segment configured to be One surface of the substrate illuminates the substrate; a thin film photodiode disposed in the sensor region, having at least one positive semiconductor region, and a negative semiconductor region, and configured to receive from Light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate by being opposed to the thin film optical diode with an insulating film interposed therebetween, and configured The light generated from the illumination segment is directly incident on the thin film photodiode from the surface side and fixed to a predetermined potential, wherein the thin film photodiode and the metal film are spaced apart from each other. a capacitance value of the parasitic capacitance of the positive-type semiconductor region and the metal film opposite to each other of the insulating film is different from the negative-type semiconductor region and the metal film including the insulating film interposed therebetween a parasitic capacitance Value. The display of claim 14, wherein the metal film is connected to one of a higher capacitance value of a parasitic capacitance of the positive semiconductor region and the negative semiconductor region, and the capacitance value of the parasitic capacitance is included in the interval The insulating film is opposed to each other between the positive or negative semiconductor region itself and the metal film. The display of claim 15, wherein the metal film is connected to the negative semiconductor region, and in the thin film photodiode, the positive semiconductor region is perpendicular to a direction perpendicular to a direction connected to the negative semiconductor region The width is less than the width of the negative semiconductor region in a direction perpendicular to the direction of connection to the positive semiconductor region. A display comprising: a substrate having a pixel region defining a pixel therein, and a sensor region defining a photosensor portion therein; an illumination segment configured to be One surface of the substrate illuminates the substrate; a thin film photodiode disposed in the sensor region, having at least one positive semiconductor region, and a negative semiconductor region, and configured to receive from Light incident on the other surface side of the substrate; and a metal film formed on the surface side of the substrate by being opposed to the thin film optical diode with an insulating film interposed therebetween, and configured The light generated from the illumination segment is directly incident on the thin film photodiode from the surface side and fixed to a predetermined potential, wherein in the thin film photodiode, from the one surface side and the other When one of the surface sides is inspected, the region of the overlap region of the positive semiconductor region and the metal film is different from the region of the overlap region of the negative semiconductor region and the metal film. The display of claim 17, wherein in the thin film photodiode, the width of the positive semiconductor region in a direction perpendicular to a direction connected to the negative semiconductor region is different from being perpendicular to the connection to the positive The width of the negative semiconductor region in the direction of the direction of the semiconductor region. The display of claim 17, wherein the metal film is connected to the positive semiconductor region, and in the thin film photodiode, the positive semiconductor region is perpendicular to a direction perpendicular to a direction connected to the negative semiconductor region The width is greater than the width of the negative semiconductor region in a direction perpendicular to the direction of connection to the positive semiconductor region. The display of claim 17, wherein the thin film photodiode has an intrinsic semiconductor region and/or a low concentration semiconductor region between the negative semiconductor region and the positive semiconductor region, the low concentration semiconductor region having a lower concentration A concentration of a conductive impurity of a concentration of a conductive impurity of the negative semiconductor region and the positive semiconductor region.