JP4737956B2 - Display device and photoelectric conversion element - Google Patents

Display device and photoelectric conversion element Download PDF

Info

Publication number
JP4737956B2
JP4737956B2 JP2004245521A JP2004245521A JP4737956B2 JP 4737956 B2 JP4737956 B2 JP 4737956B2 JP 2004245521 A JP2004245521 A JP 2004245521A JP 2004245521 A JP2004245521 A JP 2004245521A JP 4737956 B2 JP4737956 B2 JP 4737956B2
Authority
JP
Japan
Prior art keywords
formed
region
semiconductor region
electrode
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2004245521A
Other languages
Japanese (ja)
Other versions
JP2006003857A (en
Inventor
村 卓 中
田 典 生 多
田 正 浩 多
Original Assignee
東芝モバイルディスプレイ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2003300467 priority Critical
Priority to JP2003300476 priority
Priority to JP2003300467 priority
Priority to JP2003300476 priority
Priority to JP2003421026 priority
Priority to JP2003421026 priority
Priority to JP2004150826 priority
Priority to JP2004150826 priority
Priority to JP2004245521A priority patent/JP4737956B2/en
Application filed by 東芝モバイルディスプレイ株式会社 filed Critical 東芝モバイルディスプレイ株式会社
Publication of JP2006003857A publication Critical patent/JP2006003857A/en
Application granted granted Critical
Publication of JP4737956B2 publication Critical patent/JP4737956B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F2001/13312Circuits comprising a photodetector not for feedback

Description

  The present invention relates to a display device having an image capturing function.

  The liquid crystal display device includes an array substrate on which signal lines, scanning lines, and pixel TFTs are arranged, and a drive circuit that drives the signal lines and the scanning lines. With the recent progress and development of integrated circuit technology, a process technology for forming a part of a drive circuit on an array substrate has been put into practical use. As a result, the entire liquid crystal display device can be made light and thin, and it is widely used as a display device for various portable devices such as mobile phones and notebook computers.

  By the way, a display device having an image capturing function in which a contact area sensor (photoelectric conversion element) that captures an image is arranged on an array substrate has been proposed (see, for example, Patent Documents 1 and 2).

  A conventional display device having this type of image capturing function detects the voltage across the capacitor by changing the charge amount of the capacitor connected to the photoelectric conversion element according to the amount of light received by the photoelectric conversion element. The image is captured.

Recently, a technology for forming a pixel TFT and a driving circuit on the same glass substrate by a polycrystalline silicon process has progressed, and the above-described photoelectric conversion element can be easily formed in each pixel by forming a polycrystalline silicon process. It can be formed.
Japanese Patent Laid-Open No. 2001-292276 JP 2001-339640 A

However, it is difficult to obtain a sufficient photocurrent with a photoelectric conversion element using polycrystalline silicon. Conventionally, a technology for forming a photoelectric conversion element using amorphous silicon is known, but an amorphous silicon process must be provided separately from a pixel TFT and a drive circuit formed by a polysilicon process. There is a disadvantage that it is costly. Also,
The present invention has been made in view of the above problems, and an object thereof is to provide a display device capable of obtaining a sufficient photocurrent without incurring manufacturing costs.

One embodiment of the present invention is a display element provided inside each pixel formed in the vicinity of each intersection of a signal line and a scanning line arranged in rows and columns,
A photoelectric conversion element,
The photoelectric conversion element is
First, second and third semiconductor regions disposed adjacent to each other in the horizontal direction of the substrate;
A first electrode connected to the first semiconductor region;
A second electrode connected to the third semiconductor region,
The first semiconductor region is formed by implanting a first conductivity type impurity by a first dose amount,
The third semiconductor region is formed by implanting a second conductivity type impurity by a second dose amount,
In the second semiconductor region, the first conductivity type impurity and the second conductivity type are formed so that a depletion layer spreads from a boundary with the third semiconductor region toward a boundary direction with the first semiconductor region. Impurities are formed by implanting a smaller amount than the first dose and the second dose ,
The length of the second semiconductor region in the substrate horizontal plane direction is longer than the length of the first semiconductor region and the third semiconductor region in the substrate horizontal plane direction .

One embodiment of the present invention includes a first semiconductor region, a second semiconductor region, and a third semiconductor region which are formed on an insulating substrate and are arranged adjacent to each other in the substrate horizontal direction.
A first insulating layer formed on an upper surface of the first, second and third semiconductor regions;
A gate electrode formed on a part of the upper surface of the first insulating layer;
A second insulating layer formed on upper surfaces of the first insulating layer and the gate electrode;
An electrode layer connected to the first and third semiconductor regions via a contact formed in a part of the first and second insulating layers,
The first semiconductor region is formed by implanting a first conductivity type impurity by a first dose amount,
The third semiconductor region is formed by implanting a second conductivity type impurity by a second dose amount,
In the second semiconductor region, the first conductivity type impurity and the second conductivity type are formed so that a depletion layer spreads from a boundary with the third semiconductor region toward a boundary direction with the first semiconductor region. Impurities are formed by implanting a first dose amount and a third dose amount smaller than the second dose amount ,
The length of the second semiconductor region in the substrate horizontal plane direction is longer than the length of the first semiconductor region and the third semiconductor region in the substrate horizontal plane direction .

  According to the present invention, since the low-concentration second semiconductor region is arranged between the first and third semiconductor regions arranged in the horizontal direction of the substrate, the depletion layer spreads in the second semiconductor region, As the photoelectric conversion efficiency improves, the S / N ratio also improves.

  Hereinafter, a display device and a photoelectric conversion element according to the present invention will be specifically described with reference to the drawings.

  FIG. 1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention. The display device of FIG. 1 has an image capturing function, and includes a glass substrate 31 and a semiconductor substrate 32. On the glass substrate 31, a pixel array section 1 in which signal lines and scanning lines are arranged, a signal line driving circuit 2 for driving signal lines, a scanning line driving circuit 3 for driving scanning lines, and an image are captured. And a detection output circuit 4 for outputting the signal. These circuits are formed by, for example, polysilicon TFTs. The signal line drive circuit 2 includes a D / A conversion circuit (not shown) that converts digital pixel data into an analog voltage suitable for driving the display element. The D / A conversion circuit may have a known configuration. On the semiconductor substrate 32, a logic IC 33 for performing display control and image capture control is mounted. The glass substrate 31 and the semiconductor substrate 32 transmit and receive various signals through, for example, an FPC.

  FIG. 2 is a block diagram showing a part of the pixel array unit 1. 2 includes a pixel TFT 11 formed in the vicinity of each intersection of a signal line and a scanning line arranged in rows and columns, a liquid crystal capacitor C1 connected between one end of the pixel TFT 11 and the Cs line, and The auxiliary capacitor C2 and two image capturing sensors 12a and 12b provided for each pixel TFT11 are provided. The sensors 12a and 12b are connected to a power line and a control line (not shown).

  Although FIG. 2 shows an example in which two sensors 12a and 12b are provided for each pixel in order to increase the resolution of image capture, the number of sensors is not particularly limited.

  FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail. As shown in FIG. 3, the sensor 12a includes a photodiode D1 and a sensor switching transistor Q1. The sensor 12b includes a photodiode D2 and a sensor switching transistor Q2. The photodiodes D1 and D2 output an electrical signal corresponding to the amount of received light. The sensor switching transistors Q1 and Q2 alternately select any one of the plurality of photodiodes D1 and D2 in one pixel.

  Each pixel includes two sensors 12a and 12b, a capacitor C3 shared by the two sensors 12a and 12b in the same pixel, and a buffer (BUF) that outputs binary data corresponding to the accumulated charge of the capacitor C3 to the detection line. ) 13, a transistor Q3 that controls writing to the buffer 13, and a reset transistor Q4 that initializes the buffer 13 and the capacitor C3.

  The buffer 13 is composed of a static RAM (SRAM). For example, as shown in FIG. 4, two inverters IV1 and IV2 connected in series, an output terminal of a subsequent inverter IV2, and an input terminal of a previous inverter IV1 And an output transistor Q6 connected to the output terminal of the subsequent stage inverter.

  When the signal SPOLB is at a high level, the transistor Q5 is turned on and the two inverters IV1 and IV2 perform a holding operation. When the signal OUTi is at a high level, the retained data is output to the detection line.

  The display device of the present embodiment can perform a normal display operation, and can also capture an image similar to a scanner. When a normal display operation is performed, the transistor Q3 is set to an off state, and valid data is not stored in the buffer 13. In this case, the signal line voltage from the signal line driving circuit 2 is supplied to the signal line, and display according to the signal line voltage is performed.

  On the other hand, when image capture is performed, an image capture target (for example, a paper surface) 22 is arranged on the upper surface side of the array substrate 21 as shown in FIG. 5, and light from the backlight 23 is transmitted to the counter substrate 24 and the array substrate 21. Irradiates the paper surface 22 via The light reflected by the paper surface 22 is received by the sensors 12a and 12b on the array substrate 21, and an image is captured. At this time, the display is not affected by the operation for image capture.

  The captured image data is stored in the buffer 13 as shown in FIG. 3, and then sent to the logic IC 33 shown in FIG. 1 via the detection line. The logic IC 33 receives the digital signal output from the display device of the present embodiment and performs arithmetic processing such as data rearrangement and noise removal in the data.

  6 is a sectional view showing the structure of the photodiodes D1 and D2 shown in FIG. 3, FIG. 7 is a top view of the photodiodes D1 and D2, FIG. 8 is a perspective view of the photodiodes D1 and D2, and FIG. It is a figure which shows the mode of the depletion layer formed in D2. As shown in FIGS. 6 to 8, the photodiodes D <b> 1 and D <b> 2 include a silicon film 41 having a thickness of about 150 nm formed on the glass substrate 21 and a semiconductor layer 42 having a thickness of about 50 nm formed on the silicon film 41. A silicon oxide film (first insulating film) 43 having a thickness of about 50 to 150 nm formed on the upper surface of the semiconductor layer 42; a gate electrode 44 having a thickness of about 300 nm formed on the silicon oxide film 43; And a silicon oxide film 45 formed on the upper surface of the gate electrode 44 and the silicon oxide film 43.

The silicon film 43 is formed of silicon nitride, silicon oxide, or a laminated film thereof by, for example, a plasma CVD method. The semiconductor layer 42 is formed using polysilicon (polycrystalline silicon) as a material, and has a p + region 46, a p − region 47, and an n + region 48 that are adjacently disposed in the horizontal direction of the substrate. Boron ions are implanted into the p + region 46 at a high concentration of about 1 × 10 19 atm / cm 3 , for example. For example, phosphorus ions are implanted into the n + region 48 at a high concentration of about 1 × 10 19 atm / cm 3 . Boron ions are implanted into the p − region 47 at a low concentration of about 1 × 10 15 atm / cm 3 , for example. The concentration ratio between the n + region 48 and the p − region 47 is 2 digits or more, preferably about 4 digits. However, if the impurity concentration of the p − region 47 is too low, such a disadvantage that the performance (for example, mobility) of the TFT formed at the same time is extremely deteriorated is not preferable.

  The gate electrode 44 is formed of, for example, a MoW (molybdenum / tungsten) alloy. On the upper surface of the silicon oxide film 43, an anode electrode 50 connected to the p + region 46 through the contact 49 and a cathode electrode 52 connected to the n + region 48 through the contact 51 are formed. The anode electrode 50 and the cathode electrode 52 are made of a laminated film of Mo (molybdenum) and Al (aluminum), and the tips thereof have a film thickness of about 600 nm. The wiring of the anode electrode 50 needs to block the p− region 47 in order to block direct light from the backlight.

  The anode electrode 50 is supplied with a bias voltage Vnp (= + 5 V: n is higher than p), the cathode electrode 52 is grounded, and the gate electrode 44 has a gate voltage Vgp (= -5 V: g with respect to p). Low potential).

  The photodiodes D1 and D2 of this embodiment are formed by a p + region 46, a p− region 47, and an n + region 48. Hereinafter referred to as a PPN structure. In FIG. 6, the substrate horizontal length of the p − region 47 is longer than the substrate horizontal length of the p + region 46 and the n + region 48. As a result, as shown in FIG. 9, the depletion layer 53 formed between the p + region 46 and the n + region 48 extends widely to the p − region 47 side, and the photo-current conversion efficiency is improved.

  Instead of the p− region 47, an n− region 54 may be provided as shown in FIG. Also in this case, the depletion layer 53 extends to the n − layer, and the light-current conversion efficiency is also improved.

  Here, in order to improve the light-current conversion efficiency, it is better not to provide an n− region between the p− region 47 and the n + region 48. The higher the impurity concentration ratio between the p − region 47 and the n + region 48, the better the depletion layer 53 extends to the p − region 47. On the other hand, an n-region may be provided when the light-current conversion efficiency is not so high.

  11 and 12 are diagrams showing the electrical characteristics of the photodiodes D1 and D2. FIG. 11 shows the substrate horizontal length (μm) (horizontal) of the p− region 47 when a bias voltage Vnp (= + 5V: n is higher than p) is applied to the anode electrode 50 and Vgp = −5V. (Axis) and the current (logarithmic value) (vertical axis) flowing through the photodiodes D1 and D2. FIG. 12 shows the relationship between the gate voltage Vgp (horizontal axis) when the bias voltage Vnp (= 5 V) is applied to the anode electrode 50 and the current (logarithmic value) (vertical value) flowing through the photodiodes D1 and D2. Yes.

  FIG. 11 shows a curve during light irradiation and a curve during non-light irradiation. The current during non-light irradiation is substantially constant regardless of the length of the p-region 47, whereas the light irradiation is performed. The current increases as the length of the p − region 47 in the horizontal direction of the substrate increases. This is because the depletion layer 53 formed in the photodiodes D1 and D2 extends. From this, it can be seen that the photo-current conversion efficiency is superior as the photodiodes D1 and D2 as the p-region 47 is longer in the horizontal direction of the substrate.

  Also, as shown in FIG. 12, when the gate voltage exceeds about 0 V, the currents of the photodiodes D1 and D2 are reduced, so that the current variation due to the process difference increases for each of the photodiodes D1 and D2. In order to increase the current during light irradiation and reduce the dark current, the gate voltage is preferably set to 0 V or less.

  On the other hand, when the gate has a negative voltage, current variations in the photodiodes D1 and D2 are reduced. It can be seen that when it is desired to reduce the current when light is not irradiated, the gate voltage is preferably a negative voltage. This is particularly effective for normal operation when the ambient temperature is high. This is because as the temperature rises, the current when no light is irradiated increases and the S / N ratio is impaired. Specifically, when using at a room temperature of 5 ° C., the gate voltage should be 0V, and when operating at a room temperature of 40 ° C., the gate voltage should be -5V. This adjustment may be manual or automatic.

  FIG. 13 is a diagram showing the electrical characteristics of the photodiodes D1 and D2 including the p + region 46, the p− region 47, and the n + region 48 shown in FIG. 6, and FIG. 14 shows the p + region 46, p shown for comparison. FIG. 4 is a diagram showing electrical characteristics of photodiodes D1 and D2 each including a − region 47 and an n + region 48. 13 and 14 show a curve representing the change in photocurrent when the length of the p-region 47 is changed, a curve representing the change in dark current, and a curve representing the change in photocurrent / dark current. It is shown.

  In general, as the photocurrent increases, the photodiodes D1 and D2 can be miniaturized, so that the aperture ratio of each pixel can be improved. Also, the smaller the dark current, the better the S / N ratio.

  As shown in these drawings, the photodiodes D1 and D2 in FIG. 6 have photocurrent and photocurrent compared to the photodiodes D1 and D2 in the p + region 46, the p− region 47, the n− region 54, and the n + region 48. It can be seen that the values of the photocurrent / dark current both increase and the electrical characteristics are excellent.

  Next, manufacturing steps of the photodiodes D1, D2, n-channel TFT, and p-channel TFT formed on the display device by a low-temperature polysilicon process will be described in order. Note that the photodiodes D1 and D2, the n-channel TFT, and the p-channel TFT are formed in parallel.

  FIG. 15 is a diagram showing a manufacturing process of the photodiodes D1 and D2. First, an undercoat layer 51 made of SiNx, SiOx or the like is formed on the glass substrate 21 by a CVD method. Next, an amorphous silicon film is formed on the undercoat layer 51 by PECVD or sputtering. Next, the amorphous silicon film is crystallized by irradiating a laser to form a polysilicon film 52. Next, the polysilicon film 52 is patterned, and a first insulating layer 43 made of a SiOx film is formed on the upper surface by PECVD method, ECR-CVD method or the like. Then, low-concentration boron ions are implanted in the vicinity of the photodiodes D1 and D2 formation region of the polysilicon film 52 to form the p− region 52 (FIG. 15A).

  Next, using the resist 53 or the like as a mask, phosphorus ions are implanted into a part of the polysilicon film to form an n + region 48 (FIG. 15B). Next, boron ions are implanted into a part of the polysilicon film to form a p + region 46 (FIG. 15C).

  Next, a first metal layer is formed on the upper surface of the first insulating layer 43 and patterned to form a first gate electrode 44. Next, using a resist as a mask, boron ions are implanted as impurities into the photodiode D1 and D2 formation regions to form a p + region 46 in part of the polysilicon film (FIG. 15D).

  Next, low-concentration phosphorus ions are implanted into part of the polycrystalline silicon film of the n-channel TFT using the resist as a mask. At this time, since the PPN element is masked with the resist, the n − region is not formed.

  Subsequently, hydrogenation of the p − region 47 is performed. Here, hydrogenation is a process in which a substrate is exposed to hydrogen plasma. This process is performed using a CVD apparatus. By hydrogenation, dangling bonds in the TFT channel region formed of the polysilicon film can be terminated, and the leakage current of the TFT is suppressed. When the substrate is exposed to hydrogen plasma, the hydrogen is blocked by the gate electrode 44 and enters the polysilicon film from a portion where the gate electrode 44 is not present.

  Next, the second insulating layer 45 is formed on the upper surface of the first insulating layer 43. Thereafter, contact holes are formed to form the electrodes of the photodiodes D1 and D2, and the p + region 46 and the n + region 48 are exposed, and a second metal layer is formed in the exposed region, and this is formed. Patterning into a shape (FIG. 15E).

  On the other hand, FIG. 16 shows a manufacturing process of an n-channel TFT, and FIG. 17 shows a manufacturing process of a p-channel TFT. Hereinafter, the manufacturing process of the n-channel TFT and the p-channel TFT will be described with reference to FIGS.

  First, an undercoat layer 51 made of SiNx, SiOx or the like is formed on the glass substrate 21 by a CVD method. Next, an amorphous silicon film is formed on the undercoat layer 51 by PECVD or sputtering, and the amorphous silicon film is crystallized by irradiating a laser to form a polysilicon film 52. Next, after patterning the polysilicon film 52, a first insulating layer 43 made of a SiOx film formed by a PECVD method, an ECR-CVD method or the like is formed on the upper surface thereof. Then, low-concentration boron ions are implanted as impurities into the n-channel TFT formation region and the p-channel TFT formation region of the polysilicon film 52 to form p − regions (FIGS. 16A and 17A). .

  Next, using the resist 53 as a mask, phosphorus ions are implanted into the n-channel TFT formation region to form an n + region 54 in a portion of the polysilicon film (FIG. 16B). Also, phosphorus ions are prevented from being implanted into the p-channel TFT formation region by the resist 53 (FIG. 17B).

  Next, a first metal layer is formed on the upper surface of the first insulating layer 43 in the p-channel TFT formation region using Mo-Ta, Mo-W, or the like, and is patterned to form the gate electrode 55. . Next, using the gate electrode 55 as a mask, boron ions are implanted as impurities into the p-channel TFT formation region to form a p + region 57 (FIG. 17C). At this time, the n-channel TFT formation region is covered with the first metal layer 56 so that boron ions are not implanted (FIG. 16C).

  Next, after forming a gate electrode 55 in the n-channel TFT formation region, low-concentration phosphorus ions are implanted into the n-channel TFT formation region using the gate electrode 55 as a mask to form an n − region 59. The polysilicon film located immediately below the portion masked by the resist 58 remains the p − region 52 (FIG. 16D). .

  Next, the hydrogenation described above is performed in the CVD apparatus to terminate dangling bonds in the TFT channel formation region in the polysilicon film, thereby suppressing the leakage current of the TFT.

  Next, the second insulating layer 60 is formed on the upper surface of the first insulating layer 43 made of SiOx in the same CVD apparatus. Next, contact holes are formed in the electrode formation region of the n-channel TFT and the electrode formation region of the p-channel TFT, respectively, and a second metal layer is formed in the contact hole. Next, the second metal layer is patterned to form the source electrode 61 and the drain electrode 62. Finally, a SiN film is formed as a passivation film, and an n-channel TFT and a p-channel TFT are completed (FIGS. 16 (e) and 17 (e)).

  As described above, in this embodiment, a low concentration region composed of the p − region 47 or the n − region is formed between the p + region 46 and the n + region 48 constituting the photodiodes D1 and D2, and this low concentration is formed. In order to make the substrate horizontal length of the region longer than that of the p + region 46 and the n + region 48, the depletion layer 53 formed between the p + region 46 and the n + region 48 extends to the low concentration region. As a result, the photoelectric current is increased and the photoelectric conversion efficiency is improved, and the S / N ratio is improved.

  In the above-described embodiment, the example in which the photoelectric conversion element is configured by a photodiode has been described. However, the photoelectric conversion element may be configured by a TFT. In this case, the same effect as that of the above-described embodiment can be obtained by making the gate length of the TFT serving as the photoelectric conversion element longer than other TFTs (pixel display, TFT for driving circuit, etc.).

  Further, if the bias voltage Vnp and the gate voltage Vgp of the photodiode are set to Vgp = Vnp, the current variation can be reduced. Specifically, the gate electrode is connected to the n + side electrode. FIG. 18 shows the IV characteristics of the photodiode when Vgp = Vnp. A thick line in FIG. 18 represents a characteristic curve of Vgp = Vnp.

(Second Embodiment)
The second embodiment is characterized in that a light shielding layer is arranged so that a light leakage current does not flow through the photodiode for image capture.

  FIG. 19 is a cross-sectional view showing a cross-sectional structure of a display device according to the second embodiment of the present invention. As illustrated, in the display device, a backlight (B / L) 22 is disposed below the array substrate 21, and a counter substrate 24 is disposed above the array substrate 21 with a liquid crystal layer 23 interposed therebetween. The image capturing object 25 (for example, a paper surface) is disposed above the counter substrate 24.

  Light from the backlight 22 passes through the array substrate 21 and the counter substrate 24 and is irradiated to the image capturing object 25. Reflected light from the image capture object 25 is received by the photodiodes D1 and D2 on the array substrate 21 and image capture is performed. At this time, there is no possibility that the display is affected by the image capturing operation.

  The captured image data is stored in the buffer 13 as shown in FIG. 3, and then sent to the logic IC 33 shown in FIG. 1 via the detection line. The logic IC 33 receives the digital signal output from the display device of the present embodiment and performs arithmetic processing such as data rearrangement and noise removal in the data.

  In the present embodiment, the photodiodes D1, D2 are arranged so that the photodiodes D1, D2 formed in the array substrate 21 receive direct light from the backlight 22 and no light leakage current flows through the photodiodes D1, D2. A light shielding layer 20 is disposed on the lower surface side of the substrate.

  By the way, a display device for an electronic device used in an environment that easily receives external light such as a mobile phone has a reflective electrode that reflects external light in order to improve the visibility of the display device even in a strong external light state. Provided. FIG. 20 shows a cross-sectional structure of the display device of this embodiment in the case of having a reflective electrode, and FIG. 21 shows a plan view in this case.

  As shown in FIGS. 20 and 21, the reflective electrode 26 is connected to the transparent electrode 27 on the array substrate 21 and is disposed at a position higher than the transparent electrode 27. As shown in the plan view of FIG. 21, the reflective electrode 26 is formed along the outer periphery of the pixel. External light passes through the counter substrate 24 and is reflected by the reflective electrode 26. In this case, the luminance of each pixel is proportional to the product of “intensity of external light” and “transmittance of the liquid crystal layer”. The transmittance of the liquid crystal layer varies depending on the voltage applied to the pixel electrode. An arbitrary pattern can be displayed by changing the voltage applied to the pixel electrode for each pixel.

  On the other hand, FIG. 22 is a cross-sectional view in which the positional relationship between the array substrate 21 and the counter substrate 24 is reversed from that in FIG. 20, and FIG. In this case, the reflective electrode 26 is disposed on the counter substrate 24 side. More specifically, as shown in the plan view of FIG. 23, since the reflective electrode 26 is provided near the center of the pixel, the aperture ratio is deteriorated. The aperture ratio is better in FIG. 21 than in FIG.

  In the present embodiment, a TFT (for pixel display and driving circuit) and a photodiode are formed using a polysilicon process. When forming a photodiode, a semiconductor layer made of polysilicon is used as compared with a normal TFT. The crystallinity of this is intentionally deteriorated. The reason for this is that TFTs should increase crystallization in the polysilicon film and increase the on-current, whereas photodiodes can absorb a wider wavelength spectrum if crystallization in the polysilicon film does not progress. This is because the photoelectric conversion efficiency is improved. In other words, the light leakage current is caused by the generation of electrons and holes when light having an energy larger than a predetermined energy gap Eg is incident, but there are many various energy gaps in a state where crystallization does not proceed. This is because photoelectric conversion is possible even for light of various wavelengths.

  In addition, as shown in an enlarged view in FIG. 24, in this embodiment, a light shielding layer 20 made of a metal film is disposed below the photodiodes D1 and D2. Accordingly, when the amorphous silicon in the regions where the photodiodes D1 and D2 are formed is irradiated with laser to form polysilicon, the energy of the laser escapes from the amorphous silicon through the light shielding layer 20, and therefore, compared with the case without the light shielding layer 20. As a result, crystallization of amorphous silicon is difficult to proceed. For this reason, the crystallinity of the semiconductor layer of the photodiode can be made worse than that of the TFT in the present embodiment without any special device.

  Note that poor crystallinity means that the crystal size varies greatly and the defect density is large.

  Next, manufacturing steps of the photodiodes D1 and D2, the n-channel TFT, and the p-channel TFT formed on the display device by the polysilicon process will be described in order. Note that the photodiodes D1 and D2, the n-channel TFT, and the p-channel TFT are formed in parallel.

  FIG. 25 is a diagram showing manufacturing steps of the photodiodes D1 and D2. First, after forming the light shielding layer 20 on the glass substrate 21, an undercoat layer 51 made of SiNx, SiOx, or the like is formed by a CVD method. Next, an amorphous silicon film is formed on the undercoat layer 51 by PECVD or sputtering. Next, the amorphous silicon film is crystallized by irradiating a laser to form a polysilicon film 52. At this time, as described above, since the light shielding layer 20 is provided, the energy of the laser escapes to the light shielding layer 20 without changing the laser irradiation condition between the TFT portion and the photodiode portion. The crystallization of the amorphous silicon film is difficult to proceed.

  Next, the polysilicon film 52 is patterned, and a first insulating layer 43 made of a SiOx film is formed on the upper surface by PECVD method, ECR-CVD method or the like. Then, low-concentration boron ions are implanted in the vicinity of the photodiode D1 and D2 formation regions to form the p − region 52 (FIG. 25A).

  Next, using the resistor 53 as a mask, phosphorus ions are implanted into part of the polysilicon film to form an n + region 48 (FIG. 25B). Next, boron ions are implanted into part of the polysilicon film to form a p + region 46 (FIG. 25C).

  Next, a first metal layer is formed on the upper surface of the first insulating layer 43 and patterned to form a first gate electrode 44. Next, using a resist as a mask, low-concentration phosphorus ions are implanted into a portion of the polycrystalline silicon film of the n-channel TFT to form an n − region 49.

  Subsequently, hydrogenation of the p − region 52 is performed. Here, hydrogenation is a process in which a substrate is exposed to hydrogen plasma. This process is performed using a CVD apparatus. By hydrogenation, dangling bonds in the TFT channel region formed of the polysilicon film can be terminated, and the leakage current of the TFT is suppressed. When the substrate is exposed to hydrogen plasma, the hydrogen is blocked by the gate electrode 44 and enters the polysilicon film from a portion where the gate electrode 44 is not present.

  Next, the second insulating layer 45 is formed on the upper surface of the first insulating layer 43. Thereafter, contact holes are formed to form the electrodes of the photodiodes D1 and D2, and the p + region 46 and the n + region 48 are exposed, and a second metal layer is formed in the exposed region, and this is formed. The anode electrode 50 and the cathode electrode 52 are formed by patterning into a shape (FIG. 25E).

  As described above, in this embodiment, the backlight 22 is disposed below the array substrate 21 and the light shielding layer 20 is provided on the lower surface side of the photodiodes D1 and D2 in the array substrate 21. Can be prevented from entering the photodiodes D1 and D2, and the light leakage current can be suppressed.

  In addition, since the crystallinity of the semiconductor layer made of polysilicon constituting the photodiode is intentionally deteriorated, light of a wide wavelength spectrum can be absorbed, and the photoelectric conversion efficiency can be improved.

  In the above-described embodiment, the example in which the photodiodes D1 and D2 having the p + region 46, the p − region 52, the n − region 49, and the n + region 48 are formed has been described, but the p − region 52 and the n − region 49 are formed. You may form the photodiode of a structure without this. For example, in the case of a photodiode including a p + region 46, a p − region 52, and an n + region 48, a depletion layer is formed in the p − region 52 by making the p − region 52 longer than the other regions 46 and 45. Spread and improve photoelectric conversion efficiency, and improve the S / N ratio.

  In the above-described embodiment, the example in which the photoelectric conversion element is configured by a photodiode has been described. However, the photoelectric conversion element may be configured by a TFT. In this case, the same effect as that of the above-described embodiment can be obtained by making the gate length of the TFT serving as the photoelectric conversion element longer than other TFTs (pixel display, TFT for driving circuit, etc.).

(Third embodiment)
In the third embodiment, the area of the light shielding layer for shielding direct light from the backlight is further reduced.

  FIG. 26 is a cross-sectional view of a display device according to the third embodiment of the present invention. FIG. 26 shows a cross-sectional structure of a liquid crystal display device 101 as an example of a display device. The liquid crystal display device 101 of FIG. 26 has an image capturing function. The liquid crystal display device 101 includes an active matrix type array substrate 102 having a substantially rectangular flat plate shape as a circuit board. The array substrate 102 includes a glass substrate (transparent substrate) 103 which is a substantially transparent rectangular flat plate-like insulating substrate. On one main surface of the glass substrate 103, an undercoat layer 104 made of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed. This undercoat layer 104 prevents impurities from diffusing into each element formed on the glass substrate 103.

  On the undercoat layer 104, an n-channel (n-ch) thin film transistor (TFT) 105 for pixel display, a p-channel (p-ch) thin film transistor 106 for pixel display, and an image capture Photoelectric conversion elements (photosensors) 7 are formed in a matrix.

  Each of these thin film transistors 105 and 106 has a p− region active layer (semiconductor layer) 111 formed on the undercoat layer 104. The active layer 111 is formed of a polycrystalline semiconductor (polysilicon). The polysilicon of the active layer 111 is formed by crystallizing amorphous silicon by laser annealing.

  A channel region 112 is formed in the central portion of the active layer 111. On both sides of the channel region 112, a source region 113 and a drain region 114 made of an n + region or a p + region are arranged to face each other. LDD (Lightly Doped Drain) regions 115 and 116 which are n − regions are formed between the channel region 112 of the n-channel type thin film transistor 105 and the source region 113 and the drain region 114.

  On the undercoat layer 104 including each of the channel region 112, the source region 113, the drain region 114, and the LDD regions 115 and 116, an insulating gate insulating film (silicon oxide film) 117 is formed.

  A gate electrode 118 formed of a first metal is formed on the gate insulating film 117 facing each channel region 112. These gate electrodes 118 are opposed to the channel regions 112 of the thin film transistors 105 and 106 through the gate insulating film 117, and have a width dimension substantially equal to the width dimension of the channel regions 112.

  On the other hand, on the undercoat layer 104, a PIN type optical sensor 107 is formed adjacent to the thin film transistor 106. The optical sensor 107 is formed in the same manufacturing process as the thin film transistors 105 and 106 and is arranged in the same plane as the thin film transistors 105 and 106 on the glass substrate 103.

  The optical sensor 107 includes a light receiving unit 121 that is formed of amorphous silicon and is an I layer of a photoelectric conversion unit. The light receiving portion 121 is formed in the same process as the active layer 111 of each thin film transistor 105 and 106, and is laminated on the undercoat layer 104. The light receiving unit 121 includes a first light receiving unit 122 and a second light receiving unit 123 each having a p− region.

  FIG. 27 is a top view of the periphery of the light receiving unit 121. As shown in FIG. 27, each of the first light receiving unit 122 and the second light receiving unit 123 is formed in an elongated rectangular flat plate having substantially the same size, and the sides in the width direction facing each other are connected to each other. Have been electrically connected.

  An n + region 124 that functions as an n-type electrode region made of polysilicon is provided on the opposite side of the second light receiving portion 123 with the first light receiving portion 122 interposed therebetween. The n + region 124 includes an elongated rectangular flat plate-shaped connecting piece portion 124 a having a longitudinal dimension substantially equal to the longitudinal dimension of the first light receiving portion 122. The longitudinal direction of the connecting piece portion 124 a is substantially parallel to the longitudinal direction of the first light receiving portion 122, and the end portion in the width direction of the connecting piece portion 124 a is connected to the end portion in the width direction of the first light receiving portion 122. And are electrically connected.

  At the other end in the width direction of the connecting piece 124a, an elongated rectangular conductive piece 124b extending in the width direction of the connecting piece 124a is provided. The conductive piece portion 124b protrudes from the other end portion in the width direction of the connecting piece portion 124a along the width direction of the connecting piece portion 124a. The conduction piece 124b is provided near one end in the longitudinal direction of the connection piece 124a.

  On the opposite side of the first light receiving portion 122 with the second light receiving portion 123 interposed therebetween, a p + region 125 that functions as a p-type electrode region formed of polysilicon is provided. The p + region 125 includes an elongated rectangular flat plate-shaped connecting piece 125 a having a longitudinal dimension substantially equal to the longitudinal dimension of the second light receiving portion 123. The longitudinal direction of the connecting piece portion 125 a is substantially parallel to the longitudinal direction of the second light receiving portion 123, and the end portion in the width direction of the connecting piece portion 125 a is connected to the end portion in the width direction of the second light receiving portion 123. And are electrically connected.

  At the other end portion in the width direction of the connecting piece portion 125a, an elongated rectangular conductive piece portion 125b extending along the width direction of the connecting piece portion 125a is provided. The conduction piece portion 125b protrudes from the other end portion in the width direction of the connection piece portion 125a along the width direction of the connection piece portion 125a. The conduction piece portion 125b is provided at the other end portion in the longitudinal direction of the connection piece portion 125a.

  Here, each of n + region 124 and p + region 125 is used as a pair of electrode portions of photosensor 107. Each of the n + region 124 and the p + region 125 is formed on the undercoat layer 104 that is the same layer as each of the first light receiving unit 122 and the second light receiving unit 123.

  As shown in FIG. 26, a gate insulating film 117 is formed on the upper surfaces of the first light receiving portion 122, the second light receiving portion 123, the n + region 124 and the p + region 125, and the undercoat layer 104. Yes. On the gate insulating film 117 facing the second light receiving portion 123, a gate electrode 126 formed in the same layer is formed in the same process as the gate electrode 118 of the thin film transistors 105 and 106. The gate electrode 126 has a width dimension substantially equal to the width dimension of the second light receiving portion 123 and is formed of a first metal. That is, the gate electrode 126 is provided above the second light receiving portion 123 via the gate insulating film 117 and covers the second light receiving portion 123.

  On the gate insulating film 117 including the gate electrode 126 and the gate electrodes 118 of the thin film transistors 105 and 106, an interlayer insulating film (silicon oxide film) 131 which is a second insulating layer is formed. The interlayer insulating film 131 and the gate insulating film 117 are provided with a plurality of contact holes 132, 133, 134, 135, 136, and 137 penetrating through the interlayer insulating film 131 and the gate insulating film 117, respectively.

  Each of the contact holes 132 and 133 is provided on the source region 113 and the drain region 114 disposed on both sides of the gate electrode 118 of the n-channel thin film transistor 105. The contact hole 132 is open to communicate with the source region 113 of the n-channel thin film transistor 105. The contact hole 133 is open to communicate with the drain region 114 of the n-channel thin film transistor 105.

  Each of the contact holes 134 and 135 is provided on the source region 113 and the drain region 114 disposed on both sides of the gate electrode 118 of the p-channel type thin film transistor 106. The contact hole 134 is open to communicate with the source region 113 of the p-channel thin film transistor 106. The contact hole 135 is open to communicate with the drain region 114 of the p-channel type thin film transistor 106.

  Contact holes 136 and 137 are provided on n + region 124 and p + region 125 disposed on both sides of light receiving portion 121 of optical sensor 107. The contact hole 136 is open to communicate with an intermediate portion in the width direction of the tip portion along the longitudinal direction of the conduction piece portion 125b of the n + region 124. Contact hole 137 communicates with and opens an intermediate portion in the width direction of the tip portion along the longitudinal direction of conductive piece portion 125 b of p + region 125.

  In the contact holes 132 and 134 communicating with the source region 113 of each thin film transistor 105 and 106, a source electrode 141 that is a signal line is provided. These source electrodes 141 are formed of the second metal, and are electrically connected to the source regions 113 of the thin film transistors 105 and 106 through the contact holes 132 and 134 to be conductive.

  In the contact holes 133 and 135 communicating with the drain region 114 of each thin film transistor 105 and 106, a drain electrode 142 connected to the signal line is provided. These drain electrodes 142 are formed of the second metal, and are electrically connected to the drain regions 114 of the thin film transistors 105 and 106 through the contact holes 133 and 135 to be conductive.

  In the contact hole 136 communicating with the n + region 124 of the optical sensor 107, an n-type electrode 143 formed of a second metal is laminated and provided. The n-type electrode 143 is electrically connected to the conductive piece 124 b of the n + region 124 through the contact hole 136 and is conductive, and functions as a cathode of the photosensor 107. As shown in FIG. 27, this n-type electrode 143 protrudes on the interlayer insulating film 131 toward the distal end side along the longitudinal direction of the conductive piece portion 124b of the n + region 124.

  A contact hole 137 communicating with the p + region 125 of the optical sensor 107 is provided with a p-type electrode 144 made of a second metal. The p-type electrode 144 is electrically connected to the conductive piece 124b of the p + region 125 through the contact hole 137 and is conductive, and functions as an anode of the photosensor 107. This p-type electrode 144 protrudes on the interlayer insulating film 131 toward the other end side in the longitudinal direction of the connecting piece portion 125 a of the p + region 125.

  On the interlayer insulating film 131 facing the first light receiving part 122 of the optical sensor 107, a light-shielding layer 145 having an elongated rectangular flat plate shape is formed. The light blocking layer 145 is provided to block direct light from a backlight (not shown) disposed on the back side of the counter substrate 151.

  The light shielding layer 145 is disposed to face the first light receiving unit 122 so that only the first light receiving unit 122 can be shielded from light. The light shielding layer 145 extends along the longitudinal direction of the first light receiving unit 122 and has a longitudinal dimension larger than the longitudinal dimension of the first light receiving unit 122. The light shielding layer 145 has a width dimension larger than the width dimension of the first light receiving portion 122. That is, the light shielding layer 145 extends in the width direction from the first light receiving portion 122 side of the n + region 124 to the first light receiving portion 122 side of the second light receiving portion 123 with the first light receiving portion 122 as the center. Covering along.

  In other words, the light shielding layer 145 includes approximately one third of the base end side in the longitudinal direction of the conductive piece portion 124b of the n + region 124, the connecting piece portion 124a of the n + region 124, and the first light receiving portion. 122 and approximately half of one side in the width direction of the second light receiving portion 123 are covered. That is, the light shielding layer 145 exposes at least a part of each of the second light receiving portion 123 and the p + region 125.

  The light shielding layer 145 has a longitudinal dimension larger than the longitudinal dimension of the gate electrode 126 of the optical sensor 107. Further, the light shielding layer 145 has a center in the longitudinal direction of the light shielding layer 145 on the center in the longitudinal direction of each of the connecting piece portion 124a of the n + region 124, the first light receiving portion 122, and the second light receiving portion 123. Is located. Therefore, the light shielding layer 145 has the first light receiving portion 122 rather than the both end portions in the longitudinal direction of the connecting piece portion 124 a of the n + region 124, the first light receiving portion 122, and the second light receiving portion 123. It protrudes toward the longitudinal direction.

  That is, the light shielding layer 145 first receives light so as to reliably block the incident on the first light receiving unit 122 by direct light from a backlight (not shown) that enters through the counter substrate 151. The n + region 124 and the second light receiving portion 123 are partially covered with the portion 122 as the center.

  In other words, the light shielding layer 145 exposes the p + region 125 side of the second light receiving portion 123 and the p + region 125 upward. That is, the light shielding layer 145 does not cover each of the other half in the width direction of the second light receiving portion 123 and the p + region 125, and the width direction of the second light receiving portion 123. The upper part of about one-half of the other side and the p + region 125 is exposed.

  Further, the light shielding layer 145 is formed of a second metal that is the same material as each of the n-type electrode 143 and the p-type electrode 144. That is, the light shielding layer 145 is formed by the same process as each of the n-type electrode 143 and the p-type electrode 144. Therefore, the light shielding layer 145 is formed on the interlayer insulating film 131 that is the same layer as each of the n-type electrode 143 and the p-type electrode 144.

  On the other hand, on the interlayer insulating film 131 including the source electrode 141 and drain electrode 142 of each thin film transistor 105, 106 and the n-type electrode 143, p-type electrode 144, and light shielding layer 145 of the optical sensor 107, these thin film transistors 105, 106 are formed. A passivation film 146 made of a silicon nitride film is formed so as to cover each of the optical sensors 107.

  The passivation film 146 is provided with a contact hole 147 that penetrates the passivation film 146. The contact hole 147 is open to communicate with the source electrode 141 of the n-channel thin film transistor 105.

  A pixel electrode 148 is formed on the passivation film 146 including the contact hole 147. The pixel electrode 148 is electrically connected to the source electrode 141 of the n-channel thin film transistor 105 through the contact hole 147.

  Note that the pixel electrode 148 is controlled by the n-channel thin film transistor 105. An alignment film 149 is formed on the passivation film 146 including the pixel electrode 148.

  On the other hand, a rectangular flat plate-shaped counter substrate 151 is disposed so as to face the array substrate 102 and function as a common substrate. The counter substrate 151 includes a substantially transparent rectangular flat glass substrate 152. A counter electrode 153 serving as a common electrode is provided on one main surface of the glass substrate 152 facing the array substrate 102. An alignment film 154 is formed on the counter electrode 153. A liquid crystal 155 is interposed and sealed between the alignment film 154 of the counter substrate 151 and the alignment film 149 of the array substrate 102.

  On the opposite side of the array substrate 102 from the side on which the counter substrate 151 is disposed facing, a backlight (not shown) as a back light source is disposed facing the array substrate 102. In this backlight, planar light is incident on the array substrate 102, and an image displayed on the array substrate 102 can be visually observed by controlling the pixel electrode 148 by the thin film transistors 105 and 106 on the array substrate 102. To.

  29 to 37 are views showing manufacturing steps of the liquid crystal display device according to the third embodiment. Hereinafter, the manufacturing method of the liquid crystal display device of this embodiment will be described with reference to these drawings. First, as shown in FIG. 28, as a plasma CVD process, an undercoat layer 104 made of a silicon nitride film (SiNx), a silicon oxide film (SiOx), or the like is formed on a glass substrate 103 by a plasma CVD (Chemical Vapor Deposition) method. To do.

  Next, an amorphous silicon film 161, which is an amorphous semiconductor layer, is deposited on the glass substrate 103 by a PE-CVD process using a PE (Plasma Enhanced) -CVD method or a sputtering process using a sputtering method.

  Thereafter, as a laser irradiation step, as shown in FIG. 29, the amorphous silicon film 161 is irradiated with an excimer laser beam and laser-annealed to crystallize the amorphous silicon film 161 into a polysilicon film 62.

  Next, as shown in FIG. 30, as a dry etching step, the polysilicon film 162 is patterned into an island shape by dry etching.

  Thereafter, as a first ion doping step, low-concentration boron (B) is ion-doped on the entire surface of each of the patterned island-like polysilicon films 162, and each of these island-like polysilicon films 162 is p-doped. As regions, the light receiving portion 121 of the optical sensor 107 and the channel regions 112 of the thin film transistors 105 and 106 are formed.

  Next, as a gate insulating film forming step, as shown in FIG. 31, a PE-CVD method, an ECR (Electron-Cyclotron Resonance) -CVD method, or the like is formed on the undercoat layer 104 including the island-shaped polysilicon film 162. Then, a gate insulating film 117 made of a silicon oxide film (SiOx) is formed.

  Thereafter, as a first resist forming step, as shown in FIG. 32, on the light receiving portion 121 of the optical sensor 107 and the polysilicon film 162 to be the p + region 125, and the active layer 111 of the p-channel type thin film transistor 106, A resist 163 is formed on the polysilicon film 162 to be formed and on the polysilicon film 162 to be the channel region 112 and the LDD regions 115 and 116 of the n-channel thin film transistor 105.

  In this state, as the second ion doping process, using this resist 163 as a mask, the polysilicon film 162 to be the n + region 124 of the optical sensor 107 and the source region 113 and the drain region of the n-channel thin film transistor 105 are used. Each of the polysilicon film 162 to be 114 is ion-doped with high-concentration phosphorus (P) to form an n + layer, so that the n + region 124 of the photosensor 107 and the source region 113 and drain of the n-channel thin film transistor 105 are formed. Each of the regions 114 is formed.

  Next, as shown in FIG. 33, after removing the resist 163, as a first metal forming step, a molybdenum-tantalum alloy (Mo-Ta), a molybdenum-tungsten alloy (Mo-W), or the like is formed on the gate insulating film 117. To form a first metal layer 164.

  Thereafter, as shown in FIG. 34, as a first patterning step, the first metal layer 164 is patterned to form a portion that becomes the p + region 125 of the optical sensor 107 and a source region 113 of the p-channel type thin film transistor 106. Each of the portions to be the drain region 114 is opened.

  In this state, as a third ion doping process, using the patterned first metal layer 164 as a mask, the polysilicon film 162 in the portion that becomes the p + region 125 of the optical sensor 107 and the source of the p-channel type thin film transistor 106 are used. The p + region 125 of the photosensor 107 is formed as a p + layer by ion-doping boron (B) at a high concentration into each of the polysilicon film 162 in the region 113 and the drain region 114.

  At this time, in the p-channel thin film transistor 106, the patterned first metal layer 164 becomes the gate electrode 118.

  Further, as shown in FIG. 35, as the second patterning step, the first metal layer 164 is further patterned to form the n + region 124 and the first light receiving portion 122 of the optical sensor 107, and the n channel. The portions that become the source region 113, the drain region 114, and the LDD regions 115 and 116 of the thin film transistor 105 are further opened.

  Thereafter, as a second resist formation step, a resist mask 165 is formed on the gate insulating film 117 including the first metal layer 164 to be the gate electrode 126 of the optical sensor 107, and the optical sensor 107 is formed using the resist mask 165. The polysilicon film 162 to be the n + region 124, the light receiving portion 121 and the p + region 125 is covered.

  In this state, as a fourth ion doping step, using the patterned first metal layer 164 and resist mask 165 as masks, a portion to be the source region 113 and the drain region 114 of the p-channel thin film transistor 106, and n The source region 113, the drain region 114, and the LDD regions 115, 116 of the channel-type thin film transistor 105 are each ion-doped with low-concentration phosphorus to form an n − layer, thereby forming the source region 113 of the n-channel thin film transistor 105. The drain region 114 and the LDD regions 115 and 116, and the source region 113 and the drain region 114 of the p-channel type thin film transistor 106 are formed.

  At this time, in each of the n-channel thin film transistor 105 and the optical sensor 107, the patterned first metal layer 164 becomes the gate electrodes 118 and 126. Further, the light receiving portion 121 of the optical sensor 107 is constituted by a low-concentration impurity implantation region of a p− region and becomes a PIN type.

  Next, as the thermal activation process, in order to activate each impurity doped in the first to fourth ion doping processes, the light receiving unit 121, the n + region 124 and the p + region 125 of the optical sensor 107, and the p channel Each of the source region 113 and drain region 114 of the n-type thin film transistor 106 and the source region 113, drain region 114 and LDD regions 115 and 116 of the n-channel thin film transistor 105 are annealed at about 500 ° C.

  Thereafter, as a hydrogenation step, the glass substrate 103 on which the light receiving portion 121, the n + region 124 and the p + region 125 of the photosensor 107, and the active layer 111 of the thin film transistors 105 and 106 are formed is not illustrated. The glass substrate 103 is inserted into a plasma CVD apparatus and exposed to hydrogen plasma to be hydrogenated.

  Thereafter, as shown in FIG. 36, as a plasma CVD process, in the same plasma CVD apparatus as the hydrogenated plasma CVD apparatus, the gate insulating film 117 including the gate electrodes 118 and 126 of the optical sensor 107 and the thin film transistors 105 and 106, respectively. A silicon oxide film or the like is formed thereon to form an interlayer insulating film 131.

  Next, as shown in FIG. 37, contact holes 132, 133, 134, 135, 136, and 137 are formed in the interlayer insulating film 131, and the n + region 124 and the p + region 125 of the optical sensor 107, the p channel thin film transistor 106, and the n channel thin film transistor are formed. Each of the source region 113 and the drain region 114 is exposed.

  Thereafter, as a second metal layer forming step, a second metal layer 166 is formed on the entire surface of the interlayer insulating film 131 including the contact holes 132, 133, 134, 135, 136, and 137.

  Next, the second metal layer 166 is patterned so that the n-type electrode 143, the p-type electrode 144, and the light shielding layer 145 of the optical sensor 107, the source electrode 141 and the drain electrode 142 of the p-channel thin film transistor 106, and the n-channel Each of the source electrode 141 and the drain electrode 142 of the thin film transistor 105 is formed.

  Next, as a passivation film forming step, the n-type electrode 143, the p-type electrode 144, and the light shielding layer 145 of the photosensor 107, the source electrode 141 and the drain electrode 142 of the p-channel thin film transistor 106, and the n-channel thin film transistor 105 are formed. A passivation film 146 made of a silicon nitride (SiN) film is formed on the interlayer insulating film 131 including the source electrode 141 and the drain electrode 142, thereby completing the thin film transistors 105 and 106 and the photosensor 107.

  Thereafter, as shown in FIG. 26, a contact hole 147 is formed in the passivation film 146 to expose the drain electrode 142 of the n-channel type thin film transistor 105.

  In this state, a pixel electrode 148 is formed on the passivation film 146 including the contact hole 147, and then an alignment film 149 is formed on the passivation film 146 including the pixel electrode 148 to complete the array substrate 102.

  Next, after attaching the alignment film 154 side of the counter substrate 151 to the alignment film 149 side of the array substrate 102, a liquid crystal is interposed between the alignment film 149 of the array substrate 102 and the alignment film 154 of the counter substrate 151. 155 is injected, inserted, and sealed to complete the liquid crystal display device 101.

  Thereafter, a backlight is attached to the opposite side of the array substrate 102 across the counter substrate 151 of the liquid crystal display device 101.

  As described above, the depletion layer 168 that generates a photocurrent in the optical sensor 107 extends from the interface between the light receiving unit 121 and the n + region 124 to each of the light receiving unit 121 and the n + region 124. It extends long to the light receiving portion 121 side having a low concentration, and does not extend much to the n + region 124 side having a high impurity concentration.

  Further, when the voltage (Vgp) applied between the p + region 125 and the gate electrode 126 is 0 V, as shown in FIG. 38, the depletion layer 168 extends toward the light receiving portion 121 side as shown in FIG. It reaches not only the light receiving part 122 but also the intermediate part of the second light receiving part 123. In this case, the light receiving portion 121 side of the depletion layer 168 is shielded by the gate electrode 126, and the n + region 124 side of the depletion layer 168 is shielded by the light shielding layer 145.

  On the other hand, when the voltage (Vgp) applied between the p + region 125 and the gate electrode 126 is −5 V, as shown in FIG. 39, the voltage at the second light receiving portion 123 is the p-type electrode 144. Since the depletion layer 168 in the light receiving portion 121 is only the first light receiving portion 122, the light receiving portion 121 side and the n + region 124 side of the depletion layer 168 are respectively light shielding layers. The light is shielded at 145.

  As a result, it is not necessary to cover the p + region 125 with the light shielding layer 145, and the area of the light shielding layer 145 is exposed by exposing the p + region 125 without covering the p + region 125 with the light shielding layer 145. Can be reduced. Therefore, since the aperture ratio of each pixel can be prevented from being lowered by the light shielding layer 145, the liquid crystal display device 101 incorporating both high-quality display and high-performance reading function can be manufactured.

  Further, the manufacturing process can be simplified by forming the light shielding layer 145 with the same material as the n-type electrode 143 and the p-type electrode 144 in the same process.

  FIG. 40 is a layout diagram showing a first example of a specific location where the light shielding layer 145 is formed. In FIG. 40, the light shielding layer 145 is formed using the signal line 171 electrically connected to the thin film transistors 105 and 106. In this case, the optical sensor 107 is provided opposite to the lower side of each signal line 171.

  The light shielding layer 145 in FIG. 40 is formed integrally with the signal line 171 formed in the same layer, and is formed by the same material and the same process as the n-type electrode 143 and the p-type electrode 144. The light shielding layer 145 is formed in an elongated rectangular flat plate shape in which both sides of a part of the signal line 171 are expanded in the width direction. Further, the light shielding layer 145 extends along the longitudinal direction of the signal line 171 and is provided at the center of the signal line 171. A plurality of auxiliary capacitance lines 172, scanning lines 173, and sensor control lines 174 are wired in parallel with each other so as to be orthogonal to the signal lines 171.

  FIG. 41 is a layout diagram showing a second example of a specific location where the light shielding layer 145 is formed. In FIG. 41, the light shielding layer 145 is formed using a sensor control line 174 that supplies a voltage to the optical sensor 107. In this case, the optical sensor 107 is provided to face the lower side of each sensor control line 174.

  The light shielding layer 145 of each optical sensor 107 is formed integrally with the sensor control line 174 and is formed of the same material and the same process as the n-type electrode 143 and the p-type electrode 144.

  The light shielding layer 145 in FIG. 41 is formed in an elongated rectangular flat plate shape in which both sides of a part of the sensor control line 174 are expanded in the width direction. Further, the light shielding layer 145 has a longitudinal direction along the longitudinal direction of the sensor control line 174, and is provided at the center of the sensor control line 174.

  In FIG. 41, at each portion where each signal line 171 intersects with the sensor control line 174, a dividing portion 175 is formed by dividing the signal line 171 at a predetermined interval along the width direction. A contact hole 176 is formed at each end in the longitudinal direction of each signal line 171 via the dividing portion 175. These contact holes 176 are opened to the end portions of the signal lines 171. In the contact holes 176, connection wiring portions 177 are formed which electrically connect the signal lines 171 separated by the separation portions 175 to be electrically connected. The connecting wiring portion 177 connects the signal lines 171 cut by the dividing portion 175 along the longitudinal direction. Further, the connection wiring portion 177 is formed in a layer different from the layer in which the signal line 171 is formed.

  40 and 41, the light shielding layer 145 of the optical sensor 107 is formed integrally with the signal line 171 or the sensor control line 174 by using the signal line 171 or the sensor control line 174. Therefore, it is possible to suppress a decrease in the aperture ratio of each pixel due to the light shielding layer 145. For this reason, display quality and reading performance can be improved.

  When a voltage of 5V is applied to the n + region 124 of each photosensor 107 of the liquid crystal display device 101 (Vnp = 5V), the potential of the light shielding layer 145 of each photosensor 107 is about as shown in FIG. Above 2 V, the photocurrent in the light receiving part 121 of these photosensors 107 is high. On the other hand, when the potential of the light shielding layer 145 of each photosensor 107 becomes lower than about 2V, the photocurrent in the light receiving unit 121 of these photosensors 107 decreases.

  At this time, when these photosensors 107 are actual devices, the potential of the n + region 124 of each of the photosensors 107 varies in the range of 2.5V to 5V. If the potential of the light shielding layer 145 of each of the photosensors 107 is within the fluctuation range of the potential of the n + region 124, the photosensitivity of these photosensors 107 can be prevented from being lowered.

  At the same time, when the potential of the light shielding layer 145 of these photosensors 107 is the same as the potential of the n + region 124 of these photosensors 107, the charge applied to the light shielding layer 145 of these photosensors 107 is different from other power sources. Therefore, it is possible to eliminate the necessity of providing a new power supply wiring necessary for the operation. For this reason, it is possible to avoid a decrease in the aperture ratio due to the provision of these new power supply wirings, and it is possible to suppress a decrease in the aperture ratio of each pixel of the array substrate 102. As a result, since it is possible to prevent a decrease in photosensitivity without reducing the aperture ratio, the liquid crystal display device 101 having a high-performance reading function and a high-quality display can be realized.

  In each of the above embodiments, the array substrate 102 used in the liquid crystal display device 101 has been described. However, even a circuit substrate used in an organic EL (ElectroLuminescence) element can be used correspondingly.

  In each of the above embodiments, the TFT described on the array substrate 102 is a so-called top gate type (TFT in which a channel, a gate insulating film, and a gate electrode are formed in this order on the array substrate). Bottom gate type TFT (applicable by appropriately modifying a TFT in which a gate electrode, a gate insulating film, and a channel are formed in this order on an array substrate.

1 is a schematic configuration diagram of a first embodiment of a display device according to the present invention. FIG. 3 is a block diagram showing a part of the pixel array unit 1. FIG. 3 is a circuit diagram showing a part of FIG. 2 in detail. The circuit diagram which shows the internal structure of SRAM. The figure which shows the mode of image taking-in. FIG. 4 is a cross-sectional view showing a structure of photodiodes D1 and D2 shown in FIG. The top view of photodiode D1, D2. The perspective view of photodiode D1, D2. The figure which shows the mode of the depletion layer formed in photodiode D1, D2. Sectional drawing of the photodiode which provided n- area | region instead of p- area | region. The figure which shows the electrical property of photodiode D1, D2. The figure which shows the electrical property of photodiode D1, D2. FIG. 7 is a diagram illustrating electrical characteristics of photodiodes D1 and D2 including a p + region 46, a p− region 47, and an n + region 48 illustrated in FIG. 6. The figure which shows the electrical property of photodiode D1, D2 which consists of the p <+> area | region 46, the p <-> area | region 47, and the n <+> area | region 48 shown for a comparison. The figure which shows the manufacturing process of photodiode D1, D2. The figure which shows the manufacturing process of n channel TFT. The figure which shows the manufacturing process of p channel TFT. The figure which shows the IV characteristic of the photodiode at the time of setting Vgp = Vnp. Sectional drawing which shows the cross-section of a display apparatus. The figure which shows the cross-section of the display apparatus of this embodiment. The top view of the display apparatus of this embodiment. FIG. 7 is a cross-sectional view when the positional relationship between the array substrate 21 and the counter substrate 24 is opposite to that in FIG. 6. FIG. 7 is a plan view when the positional relationship between the array substrate 21 and the counter substrate 24 is reversed from that in FIG. 6. The figure which has arrange | positioned the light shielding layer 20 which consists of a metal film under the photodiodes D1 and D2. The figure which shows the manufacturing process of photodiode D1, D2. It is explanatory sectional drawing which shows 3rd Embodiment of the liquid crystal display device of this invention. FIG. 27 is an explanatory top view showing an optical sensor of the liquid crystal display device of FIG. 26. FIG. 27 is an explanatory cross-sectional view illustrating a state where an amorphous semiconductor film is formed over a light-transmitting substrate of the liquid crystal display device of FIG. FIG. 28 is a process cross-sectional view illustrating a manufacturing process of the liquid crystal display device of FIG. 27. FIG. 30 is a process cross-sectional view subsequent to FIG. 29; FIG. 31 is a process cross-sectional view following FIG. 30. FIG. 32 is a process cross-sectional view following FIG. 31. FIG. 33 is a process cross-sectional view following FIG. 32. FIG. 34 is a process cross-sectional view following FIG. 33. FIG. 35 is a process cross-sectional view following FIG. 34. FIG. 36 is a process cross-sectional view following FIG. 35. FIG. 37 is a process cross-sectional view following FIG. 36. An explanatory perspective view showing operation in case a voltage between a p-type electrode part of a photoelectric conversion element and a gate electrode is 0V. An explanatory perspective view showing operation in case a voltage between a p type electrode part and a gate electrode of a photoelectric conversion element is -5V. The layout figure which shows the 1st example of the specific formation location of the light shielding layer 145. FIG. The layout figure which shows the 2nd example of the specific formation location of the light shielding layer 145. FIG. The figure which shows the relationship between the electric potential of a light-shielding part, and a photocurrent.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel array part 2 Signal line drive circuit 3 Scan line drive circuit 4 Detection output circuit 11 Pixel TFT
12a, 12b Sensor 13 Buffer 33 Logic IC
41 Silicon film 42 Semiconductor layer 43 Silicon oxide film 44 Gate electrode 45 Silicon oxide film 46 p + region 47 p- region 48 n + region 49 Contact 50 Anode electrode 52 Cathode electrodes D1, D2 Photodiode

Claims (7)

  1. A display element provided inside each pixel formed in the vicinity of each intersection of a signal line and a scanning line arranged in rows and columns;
    A photoelectric conversion element,
    The photoelectric conversion element is
    First, second and third semiconductor regions disposed adjacent to each other in the horizontal direction of the substrate;
    A first electrode connected to the first semiconductor region;
    A second electrode connected to the third semiconductor region,
    The first semiconductor region is formed by implanting a first conductivity type impurity by a first dose amount,
    The third semiconductor region is formed by implanting a second conductivity type impurity by a second dose amount,
    In the second semiconductor region, the first conductivity type impurity and the second conductivity type are formed so that a depletion layer spreads from a boundary with the third semiconductor region toward a boundary direction with the first semiconductor region. Impurities are formed by implanting a smaller amount than the first dose and the second dose ,
    The length of the second semiconductor region in the substrate horizontal plane direction is longer than the length of the first semiconductor region and the third semiconductor region in the substrate horizontal plane direction .
  2. It said first, second and third semiconductor regions, the display device according to claim 1, characterized in that it is formed of polycrystalline silicon.
  3. A first semiconductor region, a second semiconductor region, and a third semiconductor region, which are formed on an insulating substrate and arranged adjacent to each other in the horizontal direction of the substrate;
    A first insulating layer formed on an upper surface of the first, second and third semiconductor regions;
    A gate electrode formed on a part of the upper surface of the first insulating layer;
    A second insulating layer formed on upper surfaces of the first insulating layer and the gate electrode;
    An electrode layer connected to the first and third semiconductor regions via a contact formed in a part of the first and second insulating layers,
    The first semiconductor region is formed by implanting a first conductivity type impurity by a first dose amount,
    The third semiconductor region is formed by implanting a second conductivity type impurity by a second dose amount,
    In the second semiconductor region, the first conductivity type impurity and the second conductivity type are formed so that a depletion layer spreads from a boundary with the third semiconductor region toward a boundary direction with the first semiconductor region. Impurities are formed by implanting a first dose amount and a third dose amount smaller than the second dose amount ,
    The length of the second semiconductor region in the substrate horizontal plane direction is longer than the length of the first semiconductor region and the third semiconductor region in the substrate horizontal plane direction .
  4. 4. The photoelectric conversion element according to claim 3 , wherein a positive bias voltage is applied to the electrode layer, and the gate electrode is set to approximately 0V.
  5. The photoelectric conversion element according to claim 3 , wherein a positive bias voltage is applied to the electrode layer, and a negative gate voltage is applied to the gate electrode.
  6. The photoelectric conversion element according to claim 3 , wherein a positive bias voltage is applied to the electrode layer, and a gate voltage that decreases as the temperature increases is applied to the gate electrode.
  7. The photoelectric conversion element according to claim 3 , wherein a bias voltage applied to the electrode layer and a gate voltage applied to the gate electrode are equal.
JP2004245521A 2003-08-25 2004-08-25 Display device and photoelectric conversion element Active JP4737956B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2003300467 2003-08-25
JP2003300476 2003-08-25
JP2003300467 2003-08-25
JP2003300476 2003-08-25
JP2003421026 2003-12-18
JP2003421026 2003-12-18
JP2004150826 2004-05-20
JP2004150826 2004-05-20
JP2004245521A JP4737956B2 (en) 2003-08-25 2004-08-25 Display device and photoelectric conversion element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004245521A JP4737956B2 (en) 2003-08-25 2004-08-25 Display device and photoelectric conversion element

Publications (2)

Publication Number Publication Date
JP2006003857A JP2006003857A (en) 2006-01-05
JP4737956B2 true JP4737956B2 (en) 2011-08-03

Family

ID=35772270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004245521A Active JP4737956B2 (en) 2003-08-25 2004-08-25 Display device and photoelectric conversion element

Country Status (1)

Country Link
JP (1) JP4737956B2 (en)

Families Citing this family (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4946601B2 (en) * 2006-05-15 2012-06-06 ソニー株式会社 Imaging device and its drive method, display device, and electronic device
JP5100076B2 (en) 2006-10-04 2012-12-19 株式会社ジャパンディスプレイウェスト Display device
WO2008044370A1 (en) * 2006-10-11 2008-04-17 Sharp Kabushiki Kaisha Liquid crystal display
US8013955B2 (en) * 2006-10-11 2011-09-06 Sharp Kabushiki Kaisha Liquid crystal display with opening in reflective electrode
US8164719B2 (en) 2006-10-13 2012-04-24 Sharp Kabushiki Kaisha Liquid crystal display device
CN101523273B (en) 2006-10-19 2012-02-01 夏普株式会社 Display apparatus
JP4497328B2 (en) 2006-10-25 2010-07-07 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
KR101309174B1 (en) * 2006-11-15 2013-09-23 삼성디스플레이 주식회사 Display and method for manufacturing the same
JP2008153427A (en) 2006-12-18 2008-07-03 Hitachi Displays Ltd High sensitive optical sensor element and optical sensor device using it
JP4899856B2 (en) 2006-12-27 2012-03-21 セイコーエプソン株式会社 Liquid crystal device and electronic device
JP2008171871A (en) 2007-01-09 2008-07-24 Hitachi Displays Ltd Highly sensitive photo-sensor element and photo-sensor device using the same
JP2008226903A (en) * 2007-03-08 2008-09-25 Toshiba Corp Optical sensor element and its driving method
WO2008132862A1 (en) * 2007-04-25 2008-11-06 Sharp Kabushiki Kaisha Semiconductor device, and its manufacturing method
CN101595514B (en) * 2007-04-25 2011-11-30 夏普株式会社 Display device and method for manufacturing the same
JP5125222B2 (en) * 2007-05-18 2013-01-23 セイコーエプソン株式会社 Liquid crystal device and electronic device
JP5073741B2 (en) * 2007-05-18 2012-11-14 シャープ株式会社 Display device
JP5225985B2 (en) * 2007-05-18 2013-07-03 シャープ株式会社 Display device
JP5298461B2 (en) 2007-05-29 2013-09-25 セイコーエプソン株式会社 Liquid crystal device and electronic device
WO2008156024A1 (en) 2007-06-21 2008-12-24 Sharp Kabushiki Kaisha Photodetector and display device provided with same
CN101669217B (en) 2007-06-21 2012-04-25 夏普株式会社 Photodetector and display device provided with same
KR100840098B1 (en) * 2007-07-04 2008-06-19 삼성에스디아이 주식회사 Organic light emitting device and method of manufacturing the same
WO2009011147A1 (en) * 2007-07-13 2009-01-22 Sharp Kabushiki Kaisha Liquid crystal display device
JP5068320B2 (en) 2007-08-21 2012-11-07 シャープ株式会社 Display device
JP5154365B2 (en) * 2007-12-19 2013-02-27 株式会社ジャパンディスプレイウェスト Display device
JP4811397B2 (en) * 2007-12-25 2011-11-09 ソニー株式会社 Light receiving element and display device
JP5285365B2 (en) * 2007-12-25 2013-09-11 株式会社ジャパンディスプレイウェスト Light receiving element and display device
KR101612719B1 (en) * 2007-12-25 2016-04-15 가부시키가이샤 재팬 디스프레이 Light-receiving element and display device
US20100295756A1 (en) * 2008-01-31 2010-11-25 Keisuke Yoshida Display device and active matrix substrate
JP2009198703A (en) 2008-02-20 2009-09-03 Sony Corp Liquid crystal display device and method of manufacturing the same
KR101458569B1 (en) 2008-03-13 2014-11-12 삼성디스플레이 주식회사 Display device
GB2459647A (en) * 2008-04-28 2009-11-04 Sharp Kk Photosensitive structure with a light shading layer
JP5137680B2 (en) 2008-05-08 2013-02-06 株式会社ジャパンディスプレイウェスト Liquid crystal display
RU2457550C1 (en) * 2008-06-03 2012-07-27 Шарп Кабусики Кайся Display device
BRPI0913338A2 (en) 2008-06-03 2015-11-24 Sharp Kk video device
US8427464B2 (en) 2008-07-16 2013-04-23 Sharp Kabushiki Kaisha Display device
JP5258891B2 (en) * 2008-09-02 2013-08-07 シャープ株式会社 Display device
EP2323020A4 (en) 2008-09-02 2013-05-01 Sharp Kk Display device
JP2010073974A (en) * 2008-09-19 2010-04-02 Toshiba Corp Photo-detector, photo-detection device, and display device with photo-detection function
JP5275739B2 (en) * 2008-10-03 2013-08-28 株式会社ジャパンディスプレイウェスト Sensor element and driving method thereof
US20110194036A1 (en) * 2008-10-09 2011-08-11 Sharp Kabushiki Kaisha Photodiode, photodiode-equipped display device, and fabrication method therefor
JP5314040B2 (en) * 2008-10-23 2013-10-16 シャープ株式会社 Manufacturing method of semiconductor device
WO2010050161A1 (en) * 2008-10-27 2010-05-06 シャープ株式会社 Semiconductor device, method for manufacturing same, and display device
DE102008054481A1 (en) * 2008-12-10 2010-06-17 Robert Bosch Gmbh Sensor and method for its production
WO2010084725A1 (en) * 2009-01-23 2010-07-29 シャープ株式会社 Semiconductor device, method for manufacturing same, and display device
WO2010097984A1 (en) 2009-02-27 2010-09-02 シャープ株式会社 Optical sensor and display device provided with same
JP5421355B2 (en) 2009-03-02 2014-02-19 シャープ株式会社 Display device
WO2010100824A1 (en) * 2009-03-03 2010-09-10 シャープ株式会社 Photodiode, display device provided with photodiode, and methods for manufacturing the photodiode and the display device
WO2010103802A1 (en) * 2009-03-13 2010-09-16 シャープ株式会社 Semiconductor device and method for manufacturing same
JP5330877B2 (en) * 2009-03-26 2013-10-30 株式会社東芝 Photodetection device and display device
US8415678B2 (en) 2009-05-21 2013-04-09 Sharp Kabushiki Kaisha Semiconductor device and display device
JP2012164686A (en) 2009-06-16 2012-08-30 Sharp Corp Optical sensor and display device
WO2011001874A1 (en) 2009-06-30 2011-01-06 シャープ株式会社 Sensor circuit and display device
WO2011040273A1 (en) * 2009-09-30 2011-04-07 シャープ株式会社 Semiconductor device and method for producing same, and display device provided with semiconductor device
WO2011043183A1 (en) 2009-10-07 2011-04-14 シャープ株式会社 Semiconductor device, process for production of the semiconductor device, and display device equipped with the semiconductor device
BR112012012984A2 (en) * 2009-11-30 2017-06-20 Sharp Kk video device.
WO2011065558A1 (en) 2009-11-30 2011-06-03 シャープ株式会社 Display device
EP2562625A1 (en) 2010-05-20 2013-02-27 Sharp Kabushiki Kaisha Display with touch-sensor
WO2012014861A1 (en) 2010-07-27 2012-02-02 シャープ株式会社 Display device
KR101735587B1 (en) 2010-09-06 2017-05-25 삼성디스플레이 주식회사 Photo sensor, method of manufacturing photo sensor and display apparatus
JP2015102642A (en) 2013-11-22 2015-06-04 セイコーエプソン株式会社 Circuit board, electro-optical device having input function, and electronic apparatus
CN104538400B (en) * 2014-12-16 2017-08-04 深圳市华星光电技术有限公司 A kind of LTPS array base paltes

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522516A (en) * 1991-07-17 1993-01-29 Fuji Xerox Co Ltd Image sensor
JPH05121715A (en) * 1991-10-25 1993-05-18 Hitachi Ltd Close contact type two-dimensional photosensor and manufacture thereof
JPH09199752A (en) * 1996-01-22 1997-07-31 Canon Inc Photoelectric conversion system and image reader
JPH116991A (en) * 1997-04-22 1999-01-12 Matsushita Electric Ind Co Ltd Liquid crystal display device provided with image read-out function and image reading method
JPH1184426A (en) * 1997-09-12 1999-03-26 Semiconductor Energy Lab Co Ltd Liquid crystal display device with built-in image sensor
JPH11326954A (en) * 1998-05-15 1999-11-26 Semiconductor Energy Lab Co Ltd Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522516A (en) * 1991-07-17 1993-01-29 Fuji Xerox Co Ltd Image sensor
JPH05121715A (en) * 1991-10-25 1993-05-18 Hitachi Ltd Close contact type two-dimensional photosensor and manufacture thereof
JPH09199752A (en) * 1996-01-22 1997-07-31 Canon Inc Photoelectric conversion system and image reader
JPH116991A (en) * 1997-04-22 1999-01-12 Matsushita Electric Ind Co Ltd Liquid crystal display device provided with image read-out function and image reading method
JPH1184426A (en) * 1997-09-12 1999-03-26 Semiconductor Energy Lab Co Ltd Liquid crystal display device with built-in image sensor
JPH11326954A (en) * 1998-05-15 1999-11-26 Semiconductor Energy Lab Co Ltd Semiconductor device

Also Published As

Publication number Publication date
JP2006003857A (en) 2006-01-05

Similar Documents

Publication Publication Date Title
JP6682028B2 (en) Liquid crystal display
US8629451B2 (en) Display device
JP2016085222A (en) Semiconductor device
US5966193A (en) LCD device having coupling capacitances and shielding films
KR100448902B1 (en) Display device
US7205568B2 (en) Solid state image pickup apparatus and radiation image pickup apparatus
US6335540B1 (en) Semiconductor device and process for fabricating the same
KR100918138B1 (en) Display device and method of manufacturing the same
US7514762B2 (en) Active matrix pixel device with photo sensor
JP4027465B2 (en) Active matrix display device and manufacturing method thereof
KR101343293B1 (en) Circuit board and display device
US8207591B2 (en) Photoelectric conversion device
TWI235351B (en) Suppression of leakage current in image acquisition
US6692984B2 (en) Method of manufacturing a semiconductor device
KR100650109B1 (en) Thin film phototransistor, active matrix substrate using the phototransistor, and image scanning device using the substrate
US8309960B2 (en) Display device
US7898619B2 (en) Liquid crystal display
KR101280743B1 (en) Circuit board and display device
US7863660B2 (en) Photodiode and display device
US6825492B2 (en) Method of manufacturing a semiconductor device
JP5567770B2 (en) Display device and manufacturing method of display device
US8164719B2 (en) Liquid crystal display device
JP5844858B2 (en) Manufacturing method of semiconductor device and semiconductor device
JP4646951B2 (en) Display device with sensor
JP4271268B2 (en) Image sensor and image sensor integrated active matrix display device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070726

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101129

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110104

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110307

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110405

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110426

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4737956

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140513

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250