TWI411964B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI411964B
TWI411964B TW096103361A TW96103361A TWI411964B TW I411964 B TWI411964 B TW I411964B TW 096103361 A TW096103361 A TW 096103361A TW 96103361 A TW96103361 A TW 96103361A TW I411964 B TWI411964 B TW I411964B
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Taiwan
Prior art keywords
antenna
semiconductor device
electrode
circuit
power supply
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TW096103361A
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Chinese (zh)
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TW200802119A (en
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Tamae Takano
Nobuharu Ohsawa
Kiyoshi Kato
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Semiconductor Energy Lab
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Publication of TW200802119A publication Critical patent/TW200802119A/en
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Publication of TWI411964B publication Critical patent/TWI411964B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07784—Antenna details the antenna being of the inductive type the inductive antenna consisting of a plurality of coils stacked on top of one another
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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    • H01—ELECTRIC ELEMENTS
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    • H01—ELECTRIC ELEMENTS
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    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
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    • H01Q9/04—Resonant antennas
    • H01Q9/16—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/26—Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength
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    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
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Abstract

When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

Description

半導體裝置Semiconductor device

本發明係關於利用無線通信進行資料交換的半導體裝置。本發明特別關於利用電磁感應方式及無線通信進行資料交換的半導體裝置。The present invention relates to a semiconductor device that performs data exchange using wireless communication. More particularly, the present invention relates to a semiconductor device that performs data exchange using electromagnetic induction and wireless communication.

此外，在本說明書中，半導體裝置是指藉由利用半導體特性而作用的所有裝置，電光學裝置、半導體電路及電子設備都是半導體裝置。Further, in the present specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

近年來，利用無線通信進行資料交換的半導體裝置的個體識別技術引人注目。使用了半導體裝置的個體識別技術開始適用於各個物件的生產或管理等，還開始應用於個人認證。這種半導體裝置還被稱為RFID(射頻識別)標簽、IC(積體電路)標簽、IC晶片、RF標簽、無線標簽、和電子標簽。In recent years, individual identification technology of semiconductor devices that use wireless communication for data exchange has attracted attention. Individual identification technology using semiconductor devices has begun to be applied to the production or management of individual articles, and has also begun to be applied to personal authentication. Such semiconductor devices are also referred to as RFID (Radio Frequency Identification) tags, IC (integrated circuit) tags, IC chips, RF tags, wireless tags, and electronic tags.

參照圖10說明利用電磁感應方式進行資料交換的半導體裝置(參照專利文件1)。半導體裝置301具備線圈狀天線部302和半導體電路部303。半導體電路部303的端子304電連接到線圈狀天線部302的一端305。半導體電路部303的端子306電連接到線圈狀天線部302的另一端307。A semiconductor device that performs data exchange by electromagnetic induction will be described with reference to Fig. 10 (see Patent Document 1). The semiconductor device 301 includes a coil antenna portion 302 and a semiconductor circuit portion 303. The terminal 304 of the semiconductor circuit portion 303 is electrically connected to one end 305 of the coiled antenna portion 302. The terminal 306 of the semiconductor circuit portion 303 is electrically connected to the other end 307 of the coiled antenna portion 302.

當包括線圈狀天線部的讀寫器接近半導體裝置301時，則產生來自讀寫器所包括的線圈狀天線部的交流磁場。交流磁場貫穿半導體裝置301內的線圈狀天線部302，並因電磁感應而在半導體裝置301內的線圈狀天線部302中的端子之間(一端305和另一端307之間)產生電動勢。因電磁感應而產生的電動勢使半導體裝置301內的半導體電路部303工作。When the reader/writer including the coil antenna portion approaches the semiconductor device 301, an alternating magnetic field from the coil antenna portion included in the reader/writer is generated. The AC magnetic field penetrates the coil antenna portion 302 in the semiconductor device 301, and an electromotive force is generated between the terminals (between the one end 305 and the other end 307) in the coil antenna portion 302 in the semiconductor device 301 by electromagnetic induction. The electromotive force generated by the electromagnetic induction causes the semiconductor circuit portion 303 in the semiconductor device 301 to operate.

[專利文件1]日本特開平第11－11058號公報[Patent Document 1] Japanese Patent Laid-Open No. 11-11058

如上所述，藉由天線將電源供應到利用電磁感應方式進行資料交換的半導體裝置，因此難以穩定地供應電源。因而，需要儘量抑制耗電量。As described above, the power is supplied to the semiconductor device for data exchange by the electromagnetic induction by the antenna, and thus it is difficult to stably supply the power. Therefore, it is necessary to suppress power consumption as much as possible.

當在線圈狀天線部內形成有佔有大面積的導電層時，會受到電磁感應的影響並且電流還流過所述導電層。換言之，當在線圈狀天線部內形成有佔有大面積的導電層時，難以穩定地供應電源。When a conductive layer occupying a large area is formed in the coiled antenna portion, it is affected by electromagnetic induction and current also flows through the conductive layer. In other words, when a conductive layer occupying a large area is formed in the coil-shaped antenna portion, it is difficult to stably supply the power source.

因此，本發明的目的在於提供一種藉由有效地配置線圈狀天線部和佔有大面積的導電層來防止電磁感應影響到所述導電層並實現電源的穩定化的半導體裝置。Accordingly, it is an object of the present invention to provide a semiconductor device which prevents electromagnetic induction from affecting the conductive layer and stabilizing the power supply by efficiently arranging the coil antenna portion and the conductive layer occupying a large area.

本發明的特徵在於，在使用在具備天線的一個半導體裝置中佔有大面積的導電層作為一對電極中的一個電極的元件(例如，記憶元件、發光元件、感測器元件等)中，使天線和佔有大面積的導電層至少部分重疊。The present invention is characterized in that an element (for example, a memory element, a light-emitting element, a sensor element, or the like) that occupies a large-area conductive layer as one of a pair of electrodes in a semiconductor device including an antenna is used The antenna and the conductive layer occupying a large area at least partially overlap.

本說明書所揭示的發明的結構如下：一種半導體裝置，其在具有絕緣表面的基板上至少包括多個積體電路、以旋渦形狀(稱為在一個平面內的旋渦形狀或線圈形狀)為主要結構的天線、第一電極、第二電極、以及形成在所述第一電極和所述第二電極之間的包含有機化合物的層，其中所述天線至少與所述多個積體電路中的一個電連接，所述第一電極或所述第二電極至少與所述多個積體電路中的一個電連接，所述天線與所述第二電極重疊。The structure of the invention disclosed in the present specification is as follows: a semiconductor device including at least a plurality of integrated circuits on a substrate having an insulating surface, and having a vortex shape (referred to as a vortex shape or a coil shape in one plane) as a main structure Antenna, a first electrode, a second electrode, and a layer comprising an organic compound formed between the first electrode and the second electrode, wherein the antenna is at least one of the plurality of integrated circuits Electrically connected, the first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits, and the antenna overlaps with the second electrode.

另外，天線也可以配置為還與電晶體重疊的形式。本發明的其他結構如下：一種半導體裝置，其在具有絕緣表面的基板上至少包括多個積體電路、電晶體、以旋渦形狀(稱為在一個平面內的旋渦形狀或線圈形狀)為主要結構的天線、第一電極、第二電極、以及形成在所述第一電極和所述第二電極之間的包含有機化合物的層，其中所述天線至少與所述多個積體電路中的一個電連接，所述第一電極或所述第二電極至少與所述多個積體電路中的一個電連接，所述電晶體與所述第一電極電連接，所述天線與所述第二電極及所述電晶體重疊。此外，在除了第二電極以外積體電路的電晶體也與天線重疊的情況下，所述積體電路的一部分還配置在被天線包圍的區域外側。In addition, the antenna can also be configured in a form that also overlaps the transistor. Other structures of the present invention are as follows: a semiconductor device including at least a plurality of integrated circuits, transistors, and a vortex shape (referred to as a vortex shape or a coil shape in one plane) as a main structure on a substrate having an insulating surface Antenna, a first electrode, a second electrode, and a layer comprising an organic compound formed between the first electrode and the second electrode, wherein the antenna is at least one of the plurality of integrated circuits Electrically connecting, the first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits, the transistor is electrically connected to the first electrode, and the antenna and the second The electrode and the transistor overlap. Further, in the case where the transistor of the integrated circuit other than the second electrode overlaps with the antenna, a part of the integrated circuit is also disposed outside the region surrounded by the antenna.

此外，記憶元件、發光元件、感測器元件等由第一電極、第二電極、以及形成在這些電極之間的包含有機化合物的層組成。較佳的，這些元件被配置成電極之一或兩者的面積相當大，且元件的至少一部分與天線重疊。Further, the memory element, the light-emitting element, the sensor element, and the like are composed of a first electrode, a second electrode, and a layer containing an organic compound formed between the electrodes. Preferably, these elements are configured such that the area of one or both of the electrodes is relatively large and at least a portion of the elements overlap the antenna.

使用了有機材料的記憶元件的優點如下：即使別人為偽造而拆開，偽造也是非常不容易的，這是因為接觸大氣等的有機材料容易改變其性質，並難以認出其使用的材料。The advantage of the memory element using the organic material is as follows: even if others are disassembled for forgery, forgery is very difficult, because the organic material that contacts the atmosphere or the like easily changes its properties, and it is difficult to recognize the material used.

另外，當使用不可逆相變的有機材料或無機材料作為記憶元件的包含有機化合物的層，以防止資訊被竄改或者不正當地使用時，對記憶體進行寫入的次數為一次。Further, when an irreversible phase change organic material or inorganic material is used as a layer containing an organic compound of a memory element to prevent information from being tampered with or improperly used, the number of times of writing the memory is once.

另外，當使用可逆相變的有機材料(例如，紅菲繞啉(簡稱為BPhen))或無機材料作為記憶元件的包含有機化合物的層時，可對記憶體改寫資料的次數為多次，以實現反覆使用。另外，也可以使用讀/寫器對使用了有機材料的記憶元件進行寫入和讀取。In addition, when a reversible phase change organic material (for example, phenanthroline (abbreviated as BPhen)) or an inorganic material is used as a layer containing an organic compound of a memory element, the number of times the memory can be rewritten is plural times, Achieve repeated use. In addition, it is also possible to use a reader/writer to write and read a memory element using an organic material.

另外，在上述各結構中，所述天線由供電部及具有線狀或帶狀的多個天線導體組成，該天線導體設置為從供電部周圍朝著供電部具有旋渦形狀的形式。另外，天線導體也可以為橢圓形或圓形。Further, in each of the above configurations, the antenna is composed of a power supply portion and a plurality of antenna conductors having a line shape or a strip shape, and the antenna conductor is provided in a form having a spiral shape from the periphery of the power supply portion toward the power supply portion. In addition, the antenna conductor may also be elliptical or circular.

另外，在上述各結構中，所述積體電路是例如寫入電路、讀出電路、感應放大器、輸出電路、緩衝器等。Further, in each of the above configurations, the integrated circuit is, for example, a write circuit, a read circuit, a sense amplifier, an output circuit, a buffer, or the like.

如上所述的這些手段並不是簡單的設計事項，而是配置記憶體、天線或佈線並製造包括採用了其配置的記憶電路的半導體裝置，使它進行寫入或讀出工作，並且在發明人們進行深入的研究之後，所發明的事項。These means as described above are not simple design matters, but are to configure a memory, an antenna or a wiring and to manufacture a semiconductor device including a memory circuit using the configuration thereof, to perform writing or reading work, and inventors After intensive research, the invented matter.

根據本發明，可以將佔有大面積的導電層配置在與天線重疊的區域，因此與在與天線重疊的區域什麽也不配置的情況相比，可以有效地利用空間。因此，可以實現半導體裝置的小型化。According to the present invention, it is possible to arrange the conductive layer occupying a large area in a region overlapping the antenna, and therefore it is possible to effectively utilize the space as compared with the case where the area overlapping the antenna is not disposed. Therefore, miniaturization of the semiconductor device can be achieved.

另外，藉由層疊記憶電路部和線圈狀天線部，可以防止電流流過記憶電路部所包括的佔有大面積的導電層，並可以謀求低耗電量。Further, by stacking the memory circuit portion and the coil antenna portion, it is possible to prevent current from flowing through the conductive layer occupying a large area included in the memory circuit portion, and it is possible to achieve low power consumption.

以下參照附圖對本發明的實施例模式詳細進行說明。注意，本發明不局限於以下說明，在不脫離本發明宗旨和範圍的條件下可以對其方式和詳細情況進行各種變更，這對於本領域技術人員來說也是容易理解的。因此，本發明並不被限定在以下所示的實施例模式的記載內容而被解釋。在以下所述本發明的結構中，在不同的附圖之間對同一部分使用同一標號。Embodiment modes of the present invention will be described in detail below with reference to the accompanying drawings. It is to be noted that the present invention is not limited to the following description, and various changes in the form and details may be made without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the description of the embodiment modes shown below. In the structures of the present invention described below, the same reference numerals are used for the same parts between the different drawings.

實施例模式1Embodiment mode 1

本發明的半導體裝置具備半導體電路部11、記憶電路部12、線圈狀天線部13。記憶電路部12具備多個記憶元件。多個記憶元件中的每一個具有在一對電極之間夾有包含有機化合物的層的結構。多個記憶元件所包括的一對電極之一或兩者被多個記憶元件共同使用。因此多個記憶元件所包括的一對電極之一或兩者成為佔有大面積的導電層。因此，在本發明中，將記憶電路部12和線圈狀天線部13配置為彼此重疊的形式，以防止因電磁感應而使電流流過記憶電路部12所包括的佔有大面積的導電層。A semiconductor device of the present invention includes a semiconductor circuit portion 11, a memory circuit portion 12, and a coil antenna portion 13. The memory circuit unit 12 is provided with a plurality of memory elements. Each of the plurality of memory elements has a structure in which a layer containing an organic compound is sandwiched between a pair of electrodes. One or both of the pair of electrodes included in the plurality of memory elements are used in common by the plurality of memory elements. Therefore, one or both of the pair of electrodes included in the plurality of memory elements become a conductive layer occupying a large area. Therefore, in the present invention, the memory circuit portion 12 and the coiled antenna portion 13 are arranged to overlap each other to prevent a current from flowing through the conductive layer occupying a large area included in the memory circuit portion 12 due to electromagnetic induction.

以下說明本發明的半導體裝置的上表面結構。以下說明半導體裝置和具備半導體電路部、記憶電路部、線圈狀天線部且記憶電路部和線圈狀天線部不重疊的半導體裝置(參照圖1C)進行比較。此外，圖1C不是本發明而是比較例。圖1C所示的半導體裝置具備半導體電路部1201、記憶電路部1202、以及天線部1203。此外，半導體電路部1201的第一端子電連接到線圈狀天線部1203的一端，半導體電路部1201的第二端子電連接到線圈狀天線部1203的另一端。另外，半導體電路部1201和記憶電路部1202電連接。The upper surface structure of the semiconductor device of the present invention will be described below. Hereinafter, a semiconductor device and a semiconductor device including a semiconductor circuit portion, a memory circuit portion, and a coil antenna portion, and the memory circuit portion and the coil antenna portion are not overlapped (see FIG. 1C) will be described. Further, Fig. 1C is not the present invention but a comparative example. The semiconductor device shown in FIG. 1C includes a semiconductor circuit portion 1201, a memory circuit portion 1202, and an antenna portion 1203. Further, the first terminal of the semiconductor circuit portion 1201 is electrically connected to one end of the coiled antenna portion 1203, and the second terminal of the semiconductor circuit portion 1201 is electrically connected to the other end of the coiled antenna portion 1203. Further, the semiconductor circuit portion 1201 and the memory circuit portion 1202 are electrically connected.

在記憶電路部12佔有與圖1C的結構相同的面積，且記憶電路部12和線圈狀天線部13配置為重疊的情況下(參照圖1A)，可以增加半導體電路部11的佔有面積。若可增加半導體電路部11的佔有面積，則可提供更多個元件，因此可以提供高性能電路。此外，圖1A所示的線圈狀天線部13是其匝數超過5匝的例子，但是並不局限於此。只要其匝數為2匝以上，即可。此外，半導體電路部11的第一端子電連接到線圈狀天線部13的一端，半導體電路部11的第二端子電連接到線圈狀天線部13的另一端。另外，半導體電路部11和記憶電路部12電連接。When the memory circuit unit 12 occupies the same area as the configuration of FIG. 1C and the memory circuit unit 12 and the coil antenna unit 13 are disposed to overlap each other (see FIG. 1A), the area occupied by the semiconductor circuit unit 11 can be increased. If the area occupied by the semiconductor circuit portion 11 can be increased, more components can be provided, and thus a high-performance circuit can be provided. Further, the coiled antenna portion 13 shown in FIG. 1A is an example in which the number of turns exceeds 5 ,, but is not limited thereto. As long as the number of turns is 2 or more, it can be. Further, the first terminal of the semiconductor circuit portion 11 is electrically connected to one end of the coiled antenna portion 13, and the second terminal of the semiconductor circuit portion 11 is electrically connected to the other end of the coiled antenna portion 13. Further, the semiconductor circuit portion 11 and the memory circuit portion 12 are electrically connected.

在半導體電路部11佔有與圖1C的結構相同的面積，且將記憶電路部12和線圈狀天線部13配置為重疊的情況下(參照圖1B)，可以增加記憶電路部12的佔有面積。若可增加記憶電路部12的佔有面積，則可提供更多個元件，因此可以提供大記憶容量的電路。在圖1B中，半導體電路部11的第一端子電連接到線圈狀天線部13的一端，半導體電路部11的第二端子電連接到線圈狀天線部13的另一端。另外，半導體電路部11和記憶電路部12電連接。When the semiconductor circuit portion 11 occupies the same area as the configuration of FIG. 1C and the memory circuit portion 12 and the coil antenna portion 13 are disposed to overlap each other (see FIG. 1B), the occupied area of the memory circuit portion 12 can be increased. If the area occupied by the memory circuit portion 12 can be increased, more components can be provided, and thus a circuit having a large memory capacity can be provided. In FIG. 1B, the first terminal of the semiconductor circuit portion 11 is electrically connected to one end of the coiled antenna portion 13, and the second terminal of the semiconductor circuit portion 11 is electrically connected to the other end of the coiled antenna portion 13. Further, the semiconductor circuit portion 11 and the memory circuit portion 12 are electrically connected.

接著，說明具有上述結構的半導體裝置的截面結構(參照圖2)。圖2所示的截面結構是表示沿著圖1A的半導體裝置的上表面結構中的A－B線的截面結構的圖。Next, a cross-sectional structure of the semiconductor device having the above configuration (see FIG. 2) will be described. The cross-sectional structure shown in FIG. 2 is a view showing a cross-sectional structure along the line A-B in the upper surface structure of the semiconductor device of FIG. 1A.

本發明的半導體裝置在具有絕緣表面的基板100上具備用作底座的絕緣層101、設置在絕緣層101上的薄膜電晶體102至105、覆蓋薄膜電晶體102至105的絕緣層106、以及藉由形成在絕緣層106中的開口部連接到薄膜電晶體102至105的源極或汲極的佈線107至114。The semiconductor device of the present invention includes an insulating layer 101 serving as a chassis, thin film transistors 102 to 105 disposed on the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 to 105, and borrowing on the substrate 100 having an insulating surface. The wirings 107 to 114 connected to the source or the drain of the thin film transistors 102 to 105 are connected by openings formed in the insulating layer 106.

本發明的半導體裝置還具備覆蓋佈線107至114的絕緣層115、藉由形成在絕緣層115中的開口部連接到佈線112和114的導電層116和117、覆蓋導電層116和117的絕緣層118、藉由形成在絕緣層118中的開口部連接到導電層116和117的包含有機化合物的層119和120、以及連接到包含有機化合物的層119和120的導電層121。另外，還具備覆蓋導電層121的絕緣層123、形成在絕緣層123上的導電層124至128、覆蓋導電層124至128的絕緣層129。The semiconductor device of the present invention further includes an insulating layer 115 covering the wirings 107 to 114, conductive layers 116 and 117 connected to the wirings 112 and 114 by openings formed in the insulating layer 115, and insulating layers covering the conductive layers 116 and 117. 118, an organic compound-containing layer 119 and 120 connected to the conductive layers 116 and 117, and a conductive layer 121 connected to the organic compound-containing layers 119 and 120, by an opening formed in the insulating layer 118. In addition, an insulating layer 123 covering the conductive layer 121, conductive layers 124 to 128 formed on the insulating layer 123, and an insulating layer 129 covering the conductive layers 124 to 128 are further provided.

在上述截面結構中，包括薄膜電晶體102和103的部分相當於半導體電路部11。另外，由導電層116、包含有機化合物的層119、以及導電層121組成的疊層體相當於記憶元件130。另外，由導電層117、包含有機化合物的層120、以及導電層121組成的疊層體相當於記憶元件131。包括記憶元件130和131的電路相當於記憶電路部12。另外，導電層124至128相當於線圈狀天線部13。In the above cross-sectional structure, the portion including the thin film transistors 102 and 103 corresponds to the semiconductor circuit portion 11. Further, a laminate composed of the conductive layer 116, the layer 119 containing an organic compound, and the conductive layer 121 corresponds to the memory element 130. Further, a laminate composed of the conductive layer 117, the layer 120 containing the organic compound, and the conductive layer 121 corresponds to the memory element 131. The circuit including the memory elements 130 and 131 is equivalent to the memory circuit portion 12. Further, the conductive layers 124 to 128 correspond to the coil antenna portion 13.

像上述結構那樣，藉由將記憶電路部12所包括的佔有大面積的導電層121和線圈狀天線部13所包括的導電層124至128配置為重疊的形式，可以防止因為電磁感應而使電流流過導電層121。另外，藉由層疊配置記憶電路部12和線圈狀天線部13，可以實現小型化。By arranging the conductive layers 124 to 128 included in the large-area conductive layer 121 and the coil-shaped antenna portion 13 included in the memory circuit portion 12 in an overlapping manner, it is possible to prevent current from being induced by electromagnetic induction. Flow through the conductive layer 121. Further, by arranging the memory circuit unit 12 and the coil antenna portion 13 in a stacked manner, it is possible to achieve downsizing.

接著，說明與上述結構不相同的半導體裝置的截面結構(參照圖3)。半導體裝置在具有絕緣表面的基板100上具備用作底座的絕緣層101、設置在絕緣層101上的薄膜電晶體102和103、覆蓋薄膜電晶體102和103的絕緣層106、以及藉由形成在絕緣層106中的開口部連接到薄膜電晶體102和103的源極或汲極的佈線107至110。Next, a cross-sectional structure of a semiconductor device which is different from the above configuration will be described (see FIG. 3). The semiconductor device includes an insulating layer 101 serving as a base, thin film transistors 102 and 103 disposed on the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 and 103, and formed on the substrate 100 having an insulating surface. The openings in the insulating layer 106 are connected to the wirings 107 to 110 of the source or drain of the thin film transistors 102 and 103.

另外，半導體裝置還具備覆蓋佈線107至110的絕緣層115、藉由形成在絕緣層115中的開口部連接到佈線110的導電層145、覆蓋導電層145的絕緣層118、藉由形成在絕緣層118中的開口部連接到導電層145的包含有機化合物的層147至150、以及連接到包含有機化合物的層147至150的導電層146。另外，還具備覆蓋導電層146的絕緣層123、形成在絕緣層123上的導電層124至128、覆蓋導電層124至128的絕緣層129。由導電層145、包含有機化合物的層147至150中的任何一個、以及導電層146組成的疊層體相當於記憶元件141至144。In addition, the semiconductor device further includes an insulating layer 115 covering the wirings 107 to 110, a conductive layer 145 connected to the wiring 110 by an opening formed in the insulating layer 115, and an insulating layer 118 covering the conductive layer 145, which are formed in the insulating layer. The opening portion in the layer 118 is connected to the organic compound-containing layers 147 to 150 of the conductive layer 145, and the conductive layer 146 connected to the organic compound-containing layers 147 to 150. In addition, an insulating layer 123 covering the conductive layer 146, conductive layers 124 to 128 formed on the insulating layer 123, and an insulating layer 129 covering the conductive layers 124 to 128 are further provided. The laminate composed of the conductive layer 145, any one of the layers 147 to 150 containing the organic compound, and the conductive layer 146 corresponds to the memory elements 141 to 144.

像上述結構那樣，藉由將記憶電路部12所包括的佔有大面積的導電層145及146和線圈狀天線部13所包括的導電層124至128配置為重疊的形式，可以防止因為電磁感應而使電流流過導電層121。另外，藉由層疊記憶電路部12和線圈狀天線部13，可以實現小型化。As described above, by arranging the conductive layers 145 and 146 which are included in the memory circuit portion 12 and the conductive layers 124 to 128 included in the coil-like antenna portion 13 to be overlapped, it is possible to prevent electromagnetic induction. Current is caused to flow through the conductive layer 121. Further, by stacking the memory circuit unit 12 and the coil antenna portion 13, it is possible to achieve downsizing.

實施例模式2Embodiment mode 2

在本實施例模式中，參照附圖詳細說明具備上述實施例模式1所示的記憶裝置的半導體裝置的一個例子。圖8A是本實施例模式的半導體裝置的俯視圖，而圖8B是沿著圖8A中的X－Y線的截面圖。In the present embodiment mode, an example of a semiconductor device including the memory device shown in the first embodiment will be described in detail with reference to the drawings. Fig. 8A is a plan view of the semiconductor device of the present embodiment mode, and Fig. 8B is a cross-sectional view taken along line X-Y of Fig. 8A.

如圖8A所示，在基板400上形成有作為具備記憶元件的記憶裝置的記憶元件部404、積體電路部421、天線431。圖8A及8B表示進行中的製造過程，和在能夠耐受製造條件的基板400上形成了記憶元件部、電路部、以及天線的狀態。用於記憶裝置的材料及製造處理可以是公知的。As shown in FIG. 8A, a memory element portion 404, an integrated circuit portion 421, and an antenna 431 as memory devices including memory elements are formed on the substrate 400. 8A and 8B show a manufacturing process in progress, and a state in which a memory element portion, a circuit portion, and an antenna are formed on a substrate 400 capable of withstanding manufacturing conditions. Materials and manufacturing processes for memory devices are well known.

在基板400上隔著剝離層452和絕緣層453在記憶元件部404中和積體電路部421中分別形成有電晶體441和442。使用50nm至200nm厚的鎢膜作為剝離層452，並使用氧化矽膜作為絕緣層453。但是，剝離層不局限於鎢膜，也可以使用Mo膜或非晶矽膜等。在電晶體441和442上形成有絕緣層451、454及455，並在絕緣層455上形成有由第一導電層457d、有機化合物層458及第二導電層459的疊層組成的記憶元件443。由用作分隔壁的絕緣層460b將有機化合物層458分別分隔開。第一導電層457d連接到電晶體441的佈線層，並且記憶元件443電連接到電晶體441。On the substrate 400, transistors 441 and 442 are formed in the memory element portion 404 and the integrated circuit portion 421 via the peeling layer 452 and the insulating layer 453, respectively. A tungsten film of 50 nm to 200 nm thick is used as the peeling layer 452, and a hafnium oxide film is used as the insulating layer 453. However, the release layer is not limited to the tungsten film, and a Mo film, an amorphous germanium film, or the like may be used. Insulating layers 451, 454, and 455 are formed on the transistors 441 and 442, and a memory element 443 composed of a laminate of the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 is formed on the insulating layer 455. . The organic compound layer 458 is separated by an insulating layer 460b serving as a partition wall, respectively. The first conductive layer 457d is connected to the wiring layer of the transistor 441, and the memory element 443 is electrically connected to the transistor 441.

在絕緣層455中形成開口(也稱為接觸孔)，以分別連接第一導電層457d和電晶體441、導電層457c和佈線層456a、導電層457e和佈線層456b。由於增大開口可以增加導電層之間的接觸面積從而得到更低的電阻，因此在本實施例模式中，以連接第一導電層457d和電晶體441的開口最小，其次是連接導電層457c和佈線層456a的開口，最大的是連接導電層457e和佈線層456b的開口的順序來增大開口。在本實施例模式中，將連接第一導電層457d和電晶體441的開口、連接導電層457c和佈線層456a的開口、連接導電層457e和佈線層456b的開口分別設定為5μm×5μm、50μm×50μm、500μm×500μm。Openings (also referred to as contact holes) are formed in the insulating layer 455 to connect the first conductive layer 457d and the transistor 441, the conductive layer 457c and the wiring layer 456a, the conductive layer 457e, and the wiring layer 456b, respectively. Since increasing the opening can increase the contact area between the conductive layers to obtain a lower electric resistance, in the embodiment mode, the opening for connecting the first conductive layer 457d and the transistor 441 is the smallest, followed by the connection of the conductive layer 457c and The opening of the wiring layer 456a, the largest is the order in which the openings of the conductive layer 457e and the wiring layer 456b are connected to increase the opening. In the present embodiment mode, the opening connecting the first conductive layer 457d and the transistor 441, the opening connecting the conductive layer 457c and the wiring layer 456a, the opening connecting the conductive layer 457e and the wiring layer 456b are set to 5 μm × 5 μm, 50 μm, respectively. ×50 μm, 500 μm × 500 μm.

在圖8B所示的半導體裝置中，第二導電層459與佈線層456a和導電層457c相層疊並與它們電連接。第二導電層459的電極面積比第一導電層457d的大，在本發明中，將所述第二導電層459和天線431配置為重疊的形式。In the semiconductor device shown in FIG. 8B, the second conductive layer 459 is laminated with and electrically connected to the wiring layer 456a and the conductive layer 457c. The electrode area of the second conductive layer 459 is larger than that of the first conductive layer 457d. In the present invention, the second conductive layer 459 and the antenna 431 are disposed in an overlapping form.

在絕緣層455上形成有絕緣層461。在絕緣層461上分別層疊有導電層457a和天線431a、導電層457b和天線431b、導電層457e和天線431c、以及導電層457f和天線431d。導電層457e形成為經由形成在絕緣層461中的到達佈線層462的開口與佈線層462接觸。另外，佈線層462形成為經由形成在絕緣層455中的到達佈線層456b的開口與佈線層456b接觸。此外，在本說明書中，所述天線和形成在天線下方的佈線層之間的連接部分被稱為天線的供電部。這裏，使用佈線層462和佈線層456b將天線與記憶元件部404以及積體電路部421電連接起來，但是不局限於這種連接，只要採用天線431c和佈線層456b電連接的結構即可。An insulating layer 461 is formed on the insulating layer 455. A conductive layer 457a and an antenna 431a, a conductive layer 457b and an antenna 431b, a conductive layer 457e and an antenna 431c, and a conductive layer 457f and an antenna 431d are laminated on the insulating layer 461, respectively. The conductive layer 457e is formed to be in contact with the wiring layer 462 via an opening reaching the wiring layer 462 formed in the insulating layer 461. In addition, the wiring layer 462 is formed in contact with the wiring layer 456b via an opening reaching the wiring layer 456b formed in the insulating layer 455. Further, in the present specification, a connecting portion between the antenna and a wiring layer formed under the antenna is referred to as a power supply portion of the antenna. Here, the antenna is electrically connected to the memory element portion 404 and the integrated circuit portion 421 by using the wiring layer 462 and the wiring layer 456b. However, the connection is not limited to this, and the antenna 431c and the wiring layer 456b may be electrically connected.

形成在天線431a、天線431b、天線431c、以及天線431d之下的導電層457a、導電層457b、導電層457e、導電層457f還作用以提高絕緣層455和天線431a、天線431b、天線431c、以及天線431d之間的緊密性。在本實施例模式中，分別將聚醯亞胺膜用於絕緣層455及絕緣層461、鈦膜用於導電層457a、457b、457e、457f、以及將鋁膜用於天線431a、431b、431c、431d。The conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f formed under the antenna 431a, the antenna 431b, the antenna 431c, and the antenna 431d also function to improve the insulating layer 455 and the antenna 431a, the antenna 431b, the antenna 431c, and The tightness between the antennas 431d. In this embodiment mode, a polyimide film is used for the insulating layer 455 and the insulating layer 461, a titanium film is used for the conductive layers 457a, 457b, 457e, 457f, and an aluminum film is used for the antennas 431a, 431b, 431c, respectively. 431d.

在積體電路部421中部分地形成有絕緣層460c，並且電晶體442也具有不被絕緣層460c覆蓋或被絕緣層460c覆蓋的區域。An insulating layer 460c is partially formed in the integrated circuit portion 421, and the transistor 442 also has a region not covered by the insulating layer 460c or covered by the insulating layer 460c.

圖9A和9B是關於本實施例模式的半導體裝置的電路的方塊圖。圖9A的半導體裝置的方塊圖包括RF輸入部401、邏輯電路部402、外部輸入部403、記憶元件部404、調整電路部405、二極體406、電阻器407。此外，如圖8A所示的積體電路部421相當於圖9A的RF輸入部401、邏輯電路部402、外部輸入部403、調整電路部405、二極體406、或電阻器407。9A and 9B are block diagrams showing circuits of a semiconductor device of the present embodiment mode. The block diagram of the semiconductor device of FIG. 9A includes an RF input unit 401, a logic circuit unit 402, an external input unit 403, a memory element unit 404, an adjustment circuit unit 405, a diode 406, and a resistor 407. Further, the integrated circuit portion 421 shown in FIG. 8A corresponds to the RF input unit 401, the logic circuit unit 402, the external input unit 403, the adjustment circuit unit 405, the diode 406, or the resistor 407 of FIG. 9A.

從外部輸入端子輸入的電壓及信號輸入到記憶元件部404，資料(資訊)寫入到記憶元件部404。在RF輸入部401中利用天線接收交流信號並將信號及電壓輸入到邏輯電路部402。信號藉由邏輯電路部402成為控制信號，藉由將控制信號輸入到記憶元件部404來從記憶元件部404再次讀出所寫入的資料。The voltage and signal input from the external input terminal are input to the memory element portion 404, and the data (information) is written to the memory element portion 404. The RF input unit 401 receives an AC signal by an antenna and inputs the signal and voltage to the logic circuit unit 402. The signal is converted into a control signal by the logic circuit unit 402, and the written information is read again from the memory element unit 404 by inputting a control signal to the memory element unit 404.

圖9B是調整電路部405的結構與圖9A的半導體裝置不相同的例子。調整電路部405由電阻器組成，而調整電路部415由開關組成。圖9B的方塊圖包括RF輸入部411、邏輯電路部412、外部輸入部413、記憶元件部414、調整電路部415、二極體416、電阻器417。此外，如圖8A所示的積體電路部421相當於圖9B的RF輸入部411、邏輯電路部412、外部輸入部413、調整電路部415、二極體416、或電阻器417。FIG. 9B shows an example in which the configuration of the adjustment circuit portion 405 is different from that of the semiconductor device of FIG. 9A. The adjustment circuit portion 405 is composed of a resistor, and the adjustment circuit portion 415 is composed of a switch. The block diagram of FIG. 9B includes an RF input unit 411, a logic circuit unit 412, an external input unit 413, a memory element unit 414, an adjustment circuit unit 415, a diode 416, and a resistor 417. Further, the integrated circuit portion 421 shown in FIG. 8A corresponds to the RF input portion 411, the logic circuit portion 412, the external input portion 413, the adjustment circuit portion 415, the diode 416, or the resistor 417 of FIG. 9B.

另外，電阻器407和417是升壓電路，並當成調整電路部。調整電路部405是為了在將資料寫入到記憶元件部404時，不使不需要的控制信號從邏輯電路部402輸入到記憶元件部404而進行調整的。與此同樣，電阻器407也是為了在將資料寫入到記憶元件部404時，不使信號從邏輯電路部402輸入到記憶元件部404而進行調整的。在將資料寫入到記憶元件部404時，由二極體406遮斷來自外部輸入部403的信號，而當從記憶元件部404讀出資料時，將記憶元件部404的VDDH固定在從RF輸入部401施加的VDD並使其穩定。這裏，參照圖9A的方塊圖進行說明，但是圖9B的情況與圖9A相同。In addition, the resistors 407 and 417 are booster circuits and serve as adjustment circuit sections. The adjustment circuit unit 405 is configured to prevent an unnecessary control signal from being input from the logic circuit unit 402 to the memory element unit 404 when data is written to the memory element unit 404. Similarly, the resistor 407 is also adapted to input a signal from the logic circuit unit 402 to the memory element unit 404 when data is written to the memory element unit 404. When the data is written to the memory element unit 404, the signal from the external input unit 403 is blocked by the diode 406, and when the data is read from the memory element unit 404, the VDDH of the memory element unit 404 is fixed at the RF. The VDD applied to the input portion 401 is stabilized. Here, description will be made with reference to the block diagram of Fig. 9A, but the case of Fig. 9B is the same as Fig. 9A.

另外，電連接到RF輸入部401和411的天線設置為與具備記憶元件部的記憶裝置重疊的形式。另外，可以與記憶裝置的電極的整個面重疊，或者，可以與記憶裝置的電極的一部分重疊。若採用天線部與記憶裝置重疊的結構，可以減少因天線進行通訊時，信號所包含的噪音等、或因電磁感應而產生的電動勢的變動等影響所導致的半導體裝置的工作不良，從而提高可靠性。另外，也可以實現半導體裝置的低耗電化。再者，也可以使半導體裝置小型化。Further, the antenna electrically connected to the RF input portions 401 and 411 is provided in a form overlapping with the memory device having the memory element portion. Alternatively, it may overlap the entire surface of the electrode of the memory device or may overlap with a portion of the electrode of the memory device. By adopting a configuration in which the antenna unit and the memory device are overlapped, it is possible to reduce the malfunction of the semiconductor device due to noise or the like included in the signal when the antenna is communicated, or the fluctuation of the electromotive force due to electromagnetic induction, thereby improving reliability. Sex. In addition, it is also possible to achieve low power consumption of the semiconductor device. Furthermore, the semiconductor device can also be miniaturized.

本實施例模式所示的具備第一導電層457d、有機化合物層458、以及第二導電層459的記憶元件443具有良好的緊密性，因此在形成在作為第一基板(玻璃基板)的基板400上之後，不會因在被轉印到第二基板上的處理中所施加的壓力而在介面產生膜剝離等的不良。因此，可以在以良好形狀剝離記憶元件之後將它轉印到紙或塑膠基板上，來製造重量輕且具有撓性的記憶裝置或重量輕且具有撓性的半導體裝置。The memory element 443 having the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 shown in this embodiment mode has good tightness, and thus is formed on the substrate 400 as the first substrate (glass substrate). After the above, there is no problem such as film peeling or the like on the interface due to the pressure applied in the process of being transferred onto the second substrate. Therefore, it is possible to transfer a memory element to a paper or plastic substrate after peeling it in a good shape to manufacture a lightweight and flexible memory device or a lightweight and flexible semiconductor device.

由於具備在本實施例模式中被製造的記憶元件的記憶裝置具有良好緊密性，所以可以在良好狀態下進行剝離處理及轉印處理。因此，可以自由地被轉印在各種基板上，因而，可選擇的基板材料的範圍很廣。另外，也可以選擇廉價的材料作為基板，並不僅可以根據用途提供各種功能，而且還可以以低成本製造記憶裝置和半導體裝置。Since the memory device having the memory element manufactured in the present embodiment mode has good tightness, the peeling process and the transfer process can be performed in a good state. Therefore, it can be freely transferred onto various substrates, and thus, a wide range of substrate materials can be selected. In addition, an inexpensive material can be selected as the substrate, and not only various functions can be provided depending on the use, but also a memory device and a semiconductor device can be manufactured at low cost.

根據本發明，可以製造具備可在良好狀態下進行轉印處理的緊密性高的記憶元件的記憶裝置。因此，可以高成品率地製造更高可靠性的記憶裝置及具備該記憶裝置的半導體裝置，而不使裝置或處理複雜化。According to the present invention, it is possible to manufacture a memory device having a memory element which can be subjected to a transfer process in a good state. Therefore, a memory device having higher reliability and a semiconductor device having the memory device can be manufactured with high yield without complicating the device or the process.

以如下所述的實施例更詳細地說明具有上述結構的本發明。The invention having the above structure will be explained in more detail by way of the following examples.

實施例1Example 1

以下說明本發明的半導體裝置所包括的記憶電路部的結構(參照圖4及圖5)。The configuration of the memory circuit unit included in the semiconductor device of the present invention will be described below (see FIGS. 4 and 5).

記憶電路部具備包括多個位元線B1至Bm(m為自然數)、多個字線W1至Wn(n為自然數)、以及包括多個記憶胞201的記憶胞陣列202。另外，還具備控制多個位元線B1至Bm的解碼器203、控制多個字線W1至Wn的解碼器204、選擇器205、以及讀出/寫入電路206。The memory circuit portion is provided with a memory cell array 202 including a plurality of bit lines B1 to Bm (m is a natural number), a plurality of word lines W1 to Wn (n is a natural number), and a plurality of memory cells 201. Further, a decoder 203 that controls the plurality of bit lines B1 to Bm, a decoder 204 that controls the plurality of word lines W1 to Wn, a selector 205, and a read/write circuit 206 are provided.

作為記憶胞陣列202的結構，可以舉出主動矩陣型和被動矩陣型。在記憶胞陣列202為主動矩陣型的情況下，記憶胞201包括電晶體215和記憶元件207(參照圖4)。電晶體215的閘極電連接到字線Wb(1≦b≦n)，電晶體215的源極和汲極之一電連接到位元線Ba(1≦a≦m)，而電晶體215的源極或汲極的另一電連接到記憶元件207所包括的一對電極之一。As the structure of the memory cell array 202, an active matrix type and a passive matrix type can be cited. In the case where the memory cell array 202 is of an active matrix type, the memory cell 201 includes a transistor 215 and a memory element 207 (refer to FIG. 4). The gate of the transistor 215 is electrically connected to the word line Wb (1≦b≦n), and one of the source and the drain of the transistor 215 is electrically connected to the bit line Ba (1≦a≦m), and the transistor 215 The other source or drain is electrically coupled to one of a pair of electrodes included in memory element 207.

在記憶胞陣列202為被動矩陣型的情況下，記憶胞201包括設置在位元線Ba和字線Wb的交叉位置上的記憶元件207(參照圖5)。In the case where the memory cell array 202 is of a passive matrix type, the memory cell 201 includes a memory element 207 (refer to FIG. 5) disposed at the intersection of the bit line Ba and the word line Wb.

接著，說明當將資料寫入到記憶電路部時的動作。Next, an operation when data is written to the memory circuit unit will be described.

以下說明藉由電作用將資料寫入到記憶電路部的情況。首先，由解碼器203、解碼器204、選擇器205選擇記憶胞201。接著，利用讀出/寫入電路206將資料寫入到被選出的記憶胞201。具體地說，藉由利用讀出/寫入電路206將預定的電壓施加到被選出的記憶胞201所包括的記憶元件，資料被寫入。若施加預定的電壓，則記憶元件的電阻值變化。作為記憶元件的電阻值變化，可以舉出電阻值上升的情況或電阻值降低的情況，兩者都可應用於資料寫入。電阻值上升的現象是利用藉由將預定的電壓施加到記憶元件上而使一對電極之間的包含有機化合物的層高電阻化的現象。相反，電阻值降低的現象是利用藉由將預定的電壓施加到記憶元件上而減少一對電極之間的距離的現象。像這樣，記憶電路部利用藉由電作用使記憶元件的電阻值變化的現象進行資料寫入。例如，若初始狀態的記憶元件為資料“0”，則將電作用施加到將要寫入資料“1”的記憶元件。The case where data is written to the memory circuit unit by electrical action will be described below. First, the memory cell 201 is selected by the decoder 203, the decoder 204, and the selector 205. Next, the data is written to the selected memory cell 201 by the read/write circuit 206. Specifically, data is written by applying a predetermined voltage to the memory element included in the selected memory cell 201 by the read/write circuit 206. If a predetermined voltage is applied, the resistance value of the memory element changes. The change in the resistance value of the memory element may be a case where the resistance value increases or a resistance value decreases, and both of them can be applied to data writing. The phenomenon in which the resistance value rises is a phenomenon in which a layer containing an organic compound between a pair of electrodes is increased in resistance by applying a predetermined voltage to the memory element. Conversely, the phenomenon in which the resistance value is lowered is a phenomenon in which the distance between a pair of electrodes is reduced by applying a predetermined voltage to the memory element. In this manner, the memory circuit unit writes data using a phenomenon in which the resistance value of the memory element is changed by electrical action. For example, if the memory element in the initial state is the material "0", an electrical action is applied to the memory element to which the material "1" is to be written.

接著，說明利用光學作用寫入資料的情況。在這種情況下，從具有透光性的導電層一側使用光學照射裝置(例如，鐳射照射裝置)將光照射到包含有機化合物的層，以將資料寫入到照射了光的記憶元件。藉由光照射，記憶元件的電阻值變化。作為記憶元件的電阻值變化，可以舉出電阻值上升的情況或電阻值降低的情況，兩者都可應用於資料寫入。像這樣，記憶電路部利用藉由光學作用使記憶元件的電阻值變化的現象進行資料寫入。例如，若初始狀態的記憶元件為資料“0”，則將光學作用施加到將要寫入資料“1”的記憶元件。Next, a case where data is written by optical action will be described. In this case, an optical irradiation device (for example, a laser irradiation device) is used to irradiate light to a layer containing an organic compound from the side of the light-transmitting conductive layer to write data to the light-irradiated memory element. The resistance value of the memory element changes by light irradiation. The change in the resistance value of the memory element may be a case where the resistance value increases or a resistance value decreases, and both of them can be applied to data writing. In this manner, the memory circuit unit writes data by a phenomenon in which the resistance value of the memory element is changed by optical action. For example, if the memory element in the initial state is the material "0", an optical effect is applied to the memory element to which the material "1" is to be written.

接著，說明當從記憶電路部讀出資料時的動作。Next, an operation when data is read from the memory circuit unit will be described.

不管資料寫入的方法如何，資料讀出都是利用電作用而進行的。由解碼器203和204、選擇器205、讀出/寫入電路206讀出記憶元件的電阻值的差異，以進行資料讀出。Regardless of the way the data is written, data reading is performed using electrical action. The difference in resistance values of the memory elements is read by the decoders 203 and 204, the selector 205, and the read/write circuit 206 to perform data reading.

此外，也可以在記憶元件所包括的一對導電層之一與包含有機化合物的層之間設置具有整流性的元件。具有整流性的元件指的是電連接了閘極和汲極的電晶體、二極體等。藉由設置具有整流性的元件，可以限定電流流過的方向，因此可以提高資料讀出的正確性。Further, a rectifying element may be provided between one of a pair of conductive layers included in the memory element and a layer containing an organic compound. The rectifying element refers to a transistor, a diode, or the like electrically connected to the gate and the drain. By providing a rectifying element, the direction in which the current flows can be limited, so that the correctness of the data reading can be improved.

接著，說明用於記憶元件所包括的包含有機化合物的層的材料。Next, a material for a layer containing an organic compound included in the memory element will be described.

在藉由電作用將資料寫入到記憶元件的情況下，可以將低分子類材料、高分子類材料、單重態材料、三重態材料等用於包含有機化合物的層。另外，不僅可以使用只由有機化合物材料構成的包含有機化合物的層，而且還可以使用包含一部分無機化合物的材料。另外，作為包含有機化合物的層可以使用電洞注入層、電洞傳輸層、電洞阻擋層、發光層、電子傳輸層、電子注入層等，但可以採用單層結構，也可以層疊多個層。此外，可以使用以噴墨法為代表的液滴噴射法形成包含有機化合物的層。藉由使用液滴噴射法，可以提高材料的利用效率，並實現由製造步驟的簡化導致的製造時間的縮短、製造成本的降低。In the case where data is written to the memory element by electrical action, a low molecular material, a polymer material, a singlet material, a triplet material or the like can be used for the layer containing the organic compound. Further, not only a layer containing an organic compound composed only of an organic compound material but also a material containing a part of the inorganic compound may be used. Further, as the layer containing the organic compound, a hole injection layer, a hole transport layer, a hole barrier layer, a light-emitting layer, an electron transport layer, an electron injection layer, or the like may be used, but a single layer structure may be used, or a plurality of layers may be stacked. . Further, a layer containing an organic compound can be formed using a droplet discharge method typified by an inkjet method. By using the droplet discharge method, the utilization efficiency of the material can be improved, and the manufacturing time can be shortened and the manufacturing cost can be reduced by the simplification of the manufacturing steps.

另外，在藉由光學作用將資料寫入到記憶電路部的情況下，可以使用因光學作用而改變性質的材料作為包含有機化合物的層。例如，可以使用摻雜有因吸收光而產生酸的化合物(光酸產生劑)的共軛高分子。作為共軛高分子，可以使用聚乙炔類、聚亞苯基亞乙烯基類、聚噻吩類、聚苯胺類、聚亞苯基亞乙炔基類等。此外，作為光酸產生劑，可以使用芳基鋶鹽、芳基碘鹽、o－硝基苄基甲苯磺酸鹽、芳基磺酸p－硝基苄基酯、磺酰基苯乙酮類、Fe－芳烴絡合物PF6鹽等。Further, in the case where data is written to the memory circuit portion by optical action, a material which changes properties due to optical action can be used as a layer containing an organic compound. For example, a conjugated polymer doped with a compound (photoacid generator) which generates an acid by absorbing light can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenyleneethylene groups, and the like can be used. Further, as the photoacid generator, an arylsulfonium salt, an aryl iodide salt, an o-nitrobenzyl tosylate, an arylsulfonic acid p-nitrobenzyl ester, a sulfonylacetophenone, Fe-arene complex PF6 salt or the like.

另外，本發明的半導體裝置所具備的記憶裝置也可以是非揮發性記憶裝置，也可以增加資料。另外，本發明的半導體裝置所具備的記憶裝置也可以藉由來自外部的電作用改寫資料。Further, the memory device included in the semiconductor device of the present invention may be a non-volatile memory device, and data may be added. Further, the memory device included in the semiconductor device of the present invention can also rewrite data by an electric action from the outside.

在本實施中，天線的面積尺寸為大約9mm×11mm，天線的匝數為9匝，天線本身的線寬度為150μm，天線的佈線以10μm的間隔捲繞。與像這樣被捲繞為線圈形狀的天線重疊地配置記憶電路部中的一個電極，即，上部電極。該上部電極設置在包含有機化合物的層上，並用作多個記憶元件的公共電極。在構成具有1千位元的信息量的記憶電路的情況下，只要其上部電極的面積尺寸為大約1.5mm×3mm即可。此外，對上部電極的面積尺寸沒有特別的限制，也可以使其尺寸小於4.5mm2 。In the present embodiment, the area size of the antenna is about 9 mm × 11 mm, the number of turns of the antenna is 9 匝, the line width of the antenna itself is 150 μm, and the wiring of the antenna is wound at intervals of 10 μm. One of the memory circuit portions, that is, the upper electrode, is disposed to overlap the antenna wound in a coil shape as described above. The upper electrode is disposed on a layer containing an organic compound and serves as a common electrode of a plurality of memory elements. In the case of constituting a memory circuit having an information amount of one thousand bits, the area size of the upper electrode may be approximately 1.5 mm × 3 mm. Further, the area size of the upper electrode is not particularly limited, and the size thereof may be made smaller than 4.5 mm 2 .

與在重疊於天線的區域什麽也不配置的情況相比，藉由將天線和佔有大面積的導電層(上部電極：4.5mm2 )配置為重疊的形式，可以有效地利用空間。因此，可以實現半導體裝置的小型化。The space can be effectively utilized by arranging the antenna and the conductive layer occupying a large area (upper electrode: 4.5 mm 2 ) in an overlapping manner as compared with the case where nothing is disposed in the region overlapping the antenna. Therefore, miniaturization of the semiconductor device can be achieved.

另外，藉由層疊佔有大面積的上部電極和線圈狀天線部，可以防止電流流過記憶電路部所包括的上部電極，並可以謀求低耗電量。Further, by laminating the upper electrode and the coil antenna portion occupying a large area, it is possible to prevent current from flowing through the upper electrode included in the memory circuit portion, and it is possible to achieve low power consumption.

本實施例可以與實施例模式1或實施例模式2自由地組合。This embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

實施例2Example 2

以下說明本發明的半導體裝置所包括的半導體電路部的結構(參照圖6)。The structure of the semiconductor circuit portion included in the semiconductor device of the present invention will be described below (see FIG. 6).

半導體電路部具備類比電路551和數位電路552。類比電路551具備諧振電容器501、帶通濾波器502、包括整流電路和保持電容器的電源電路503、解調電路504、調制電路505等。數位電路552具備碼提取電路506、時鐘產生電路507、迴圈冗餘碼檢查電路508、控制電路509、記憶電路510等。The semiconductor circuit unit includes an analog circuit 551 and a digital circuit 552. The analog circuit 551 includes a resonance capacitor 501, a band pass filter 502, a power supply circuit 503 including a rectifier circuit and a holding capacitor, a demodulation circuit 504, a modulation circuit 505, and the like. The digital circuit 552 includes a code extraction circuit 506, a clock generation circuit 507, a loop redundancy code check circuit 508, a control circuit 509, a memory circuit 510, and the like.

以下說明當半導體裝置接收資料時的動作。從線圈狀天線輸入的無線信號(被調制的載波)從端子221a輸入到類比電路551。由帶通濾波器502取出被輸入的無線信號中的所希望的頻率成分，並輸入到電源電路503及解調電路504。藉由帶通濾波器502輸入的被調制的載波被電源電路503所包括的整流電路整流，並被電源電路503所包括的儲存電容器平滑化。這樣，電源電路503產生直流電壓。在電源電路503中產生的直流電壓被提供到各電路作為電源電壓。The following describes the action when the semiconductor device receives the data. The wireless signal (modulated carrier) input from the coil antenna is input from the terminal 221a to the analog circuit 551. The desired frequency component of the input wireless signal is taken out by the band pass filter 502, and is input to the power supply circuit 503 and the demodulation circuit 504. The modulated carrier input by the band pass filter 502 is rectified by a rectifying circuit included in the power supply circuit 503, and smoothed by a storage capacitor included in the power supply circuit 503. Thus, the power supply circuit 503 generates a DC voltage. The DC voltage generated in the power supply circuit 503 is supplied to each circuit as a power supply voltage.

另外，藉由帶通濾波器502輸入的被調制的載波被輸入到數位電路552內的時鐘產生電路507。在時鐘產生電路507中產生的時鐘被提供到各電路。藉由帶通濾波器502輸入的被調制的載波被解調電路504解調，被解調的信號輸入到數位電路552。使用解調電路504解調被調制的載波而獲得的解調信號輸入到碼提取電路506，信號所具有的碼被提取出來。碼提取電路506的輸出輸入到控制電路509，碼被提取出來。被提取出來的碼輸入到迴圈冗餘碼檢查電路508，進行用來識別發送錯誤的計算處理。這樣，迴圈冗餘碼檢查電路508將接收資料是否有錯誤輸出到控制電路509。Further, the modulated carrier input by the band pass filter 502 is input to the clock generating circuit 507 in the digital circuit 552. A clock generated in the clock generating circuit 507 is supplied to each circuit. The modulated carrier input by the band pass filter 502 is demodulated by the demodulation circuit 504, and the demodulated signal is input to the digital circuit 552. The demodulated signal obtained by demodulating the modulated carrier using the demodulation circuit 504 is input to the code extraction circuit 506, and the code having the signal is extracted. The output of the code extraction circuit 506 is input to the control circuit 509, and the code is extracted. The extracted code is input to the loop redundancy code check circuit 508, and calculation processing for identifying a transmission error is performed. Thus, the loop redundancy code check circuit 508 outputs an error to the received data to the control circuit 509.

接著，說明當半導體裝置發送資料時的動作。記憶電路510根據從控制電路509輸入的信號將被儲存的獨特識別字元(UID)輸出到控制電路509。迴圈冗餘碼檢查電路508計算對應於發送資料的CRC碼，並輸出到控制電路509。控制電路509對發送資料附加CRC碼。另外，控制電路509對發送資料附加有CRC碼的資料進行編碼。再者，控制電路509將被編碼的資訊變換成用來根據預定的調制方式調制載波的信號。控制電路509的輸出被輸入到類比電路551的調制電路505。調制電路505根據被輸入的信號對載波進行負載調制，並將它輸出到線圈狀天線部。Next, an operation when the semiconductor device transmits data will be described. The memory circuit 510 outputs the stored unique identification character (UID) to the control circuit 509 in accordance with a signal input from the control circuit 509. The loop redundancy code check circuit 508 calculates a CRC code corresponding to the transmitted data, and outputs it to the control circuit 509. The control circuit 509 adds a CRC code to the transmission material. Further, the control circuit 509 encodes the data to which the CRC code is attached to the transmission data. Furthermore, control circuit 509 converts the encoded information into a signal for modulating the carrier in accordance with a predetermined modulation scheme. The output of the control circuit 509 is input to the modulation circuit 505 of the analog circuit 551. The modulation circuit 505 performs load modulation on the carrier based on the input signal and outputs it to the coil antenna portion.

本實施例可以與實施例模式1、實施例模式2、或實施例1自由地組合。This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment 1.

實施例3Example 3

在本實施例中，說明本發明的半導體裝置的用途。本發明的半導體裝置可以設置在如下物品中來使用：例如紙幣、硬幣、有價證券、無記名債券、證書類(駕照或居住證等)、包裝用容器類(包裝紙或瓶子等)、記錄媒體如DVD(數位通用光碟)或錄影帶等、交通工具類如汽車或自行車等、個人物品如書包或眼鏡等、食品類、衣類、生活用品類、電子設備等。電子設備指的是液晶顯示裝置、EL(電致發光)顯示裝置、電視裝置、以及行動電話等。In the present embodiment, the use of the semiconductor device of the present invention will be described. The semiconductor device of the present invention can be used in articles such as banknotes, coins, securities, bearer bonds, certificates (drivers' licenses or residence permits, etc.), packaging containers (wrapping paper or bottles, etc.), recording media such as DVD (digital versatile disc) or video tape, vehicles such as cars or bicycles, personal items such as school bags or glasses, food, clothing, household goods, electronic equipment, etc. The electronic device refers to a liquid crystal display device, an EL (electroluminescence) display device, a television device, a mobile phone, and the like.

本發明的半導體裝置可以被貼在物品表面或者被嵌入到物品中來固定於物品上。例如，如果是書，就可以被嵌入到紙中；而如果是由有機樹脂構成的包裝，就可以被嵌入到該有機樹脂中。藉由將半導體裝置提供到紙幣、硬幣、有價證券類、無記名債券類、證書類等，可以防止偽造。另外，藉由將半導體裝置提供於包裝用容器類、記錄媒體、個人物品、食品類、衣類、生活用品類、電子設備等，可以實現產品檢查系統或租賃店中的系統等的效率化。另外，藉由將半導體裝置提供於交通工具類，可以防止偽造和偷竊。另外，藉由將半導體裝置嵌入到諸如動物等的活體中，以可以容易地識別各個活體，例如藉由將半導體裝置嵌入到諸如家畜等的活體中，可以容易管理出生年、性別、或種類等。像這樣，本發明的半導體裝置可以提供到任何物品(包括活體)來使用。The semiconductor device of the present invention can be attached to the surface of an article or embedded in an article to be attached to the article. For example, if it is a book, it can be embedded in paper; and if it is a package made of an organic resin, it can be embedded in the organic resin. Counterfeiting can be prevented by providing a semiconductor device to banknotes, coins, securities, unregistered bonds, certificates, and the like. In addition, by providing the semiconductor device in packaging containers, recording media, personal articles, foods, clothing, household goods, electronic equipment, and the like, it is possible to improve the efficiency of the system in the product inspection system or the rental store. In addition, by providing the semiconductor device to the vehicle, it is possible to prevent counterfeiting and theft. In addition, by embedding a semiconductor device in a living body such as an animal, it is possible to easily identify each living body, for example, by embedding a semiconductor device in a living body such as a domestic animal, etc., it is possible to easily manage the birth year, sex, or kind, and the like. . As such, the semiconductor device of the present invention can be provided to any article (including living bodies) for use.

接著，參照圖7說明使用了半導體裝置的系統的一個模式。在包括顯示部9521的終端9520上設置有天線及連接到該天線的讀/寫器。本發明的半導體裝置9531被設置在物品9532中，而本發明的半導體裝置9523被設置在物品9522中。當將終端9520的天線對準物品9532包括的半導體裝置9531時，和商品有關的資訊如物品9532的原材料和原產地、各生產處理的檢查結果、流通過程的記錄等以及商品的說明等顯示在顯示部9521。當將終端9520的天線對準物品9522包括的半導體裝置9523時，和商品有關的資訊如物品9522的原材料和原產地、各生產處理的檢查結果、流通過程的記錄等以及商品的說明等顯示在顯示部9521。Next, a mode of a system using a semiconductor device will be described with reference to FIG. An antenna and a reader/writer connected to the antenna are provided on the terminal 9520 including the display portion 9521. The semiconductor device 9531 of the present invention is disposed in the article 9532, and the semiconductor device 9523 of the present invention is disposed in the article 9522. When the antenna of the terminal 9520 is aligned with the semiconductor device 9531 included in the article 9532, information related to the product such as the raw material and origin of the article 9532, the inspection result of each production process, the recording of the circulation process, and the like, and the description of the product are displayed. The display unit 9521. When the antenna of the terminal 9520 is aligned with the semiconductor device 9523 included in the article 9522, information related to the product such as the raw material and origin of the article 9522, the inspection result of each production process, the recording of the circulation process, and the like, and the description of the product are displayed. The display unit 9521.

本實施例可以與實施例模式1、實施例模式2、實施例1、或實施例2自由地組合。This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment 1, or Embodiment 2.

301．．．半導體裝置301. . . Semiconductor device

302．．．線圈狀天線部302. . . Coil antenna

303．．．半導體電路部303. . . Semiconductor circuit department

304．．．端子304. . . Terminal

305．．．一端305. . . One end

306．．．端子306. . . Terminal

307．．．另一端307. . . another side

12．．．記憶電路部12. . . Memory circuit

13．．．線圈狀天線部13. . . Coil antenna

11．．．半導體電路部11. . . Semiconductor circuit department

1201．．．半導體電路部1201. . . Semiconductor circuit department

1202．．．記憶電路部1202. . . Memory circuit

1203．．．線圈狀天線部1203. . . Coil antenna

100．．．基板100. . . Substrate

101．．．絕緣層101. . . Insulation

102－105．．．薄膜電晶體102-105. . . Thin film transistor

106．．．絕緣層106. . . Insulation

107－114．．．佈線107-114. . . wiring

115．．．絕緣層115. . . Insulation

116、117．．．導電層116, 117. . . Conductive layer

118．．．絕緣層118. . . Insulation

119、120．．．包含有機化合物的層119, 120. . . Layer containing organic compounds

121．．．導電層121. . . Conductive layer

123．．．絕緣層123. . . Insulation

124－128．．．導電層124-128. . . Conductive layer

129．．．絕緣層129. . . Insulation

130．．．記憶元件130. . . Memory component

131．．．記憶元件131. . . Memory component

145．．．導電層145. . . Conductive layer

147－150．．．包含有機化合物的層147-150. . . Layer containing organic compounds

146．．．導電層146. . . Conductive layer

141－144．．．記憶元件141-144. . . Memory component

400．．．基板400. . . Substrate

404．．．記憶元件部404. . . Memory component department

421．．．積體電路部421. . . Integrated circuit

431．．．天線431. . . antenna

441、442．．．電晶體441, 442. . . Transistor

452．．．剝離層452. . . Peeling layer

453、451、454、455．．．絕緣層453, 451, 454, 455. . . Insulation

443．．．記憶元件443. . . Memory component

457d．．．第一導電層457d. . . First conductive layer

458．．．有機化合物層458. . . Organic compound layer

459．．．第二導電層459. . . Second conductive layer

460b．．．絕緣層460b. . . Insulation

456a．．．佈線層456a. . . Wiring layer

457e．．．導電層457e. . . Conductive layer

457c．．．導電層457c. . . Conductive layer

456b．．．佈線層456b. . . Wiring layer

461．．．絕緣層461. . . Insulation

457a．．．導電層457a. . . Conductive layer

431a．．．天線431a. . . antenna

457b．．．導電層457b. . . Conductive layer

431b、431c、431d．．．天線431b, 431c, 431d. . . antenna

457f．．．導電層457f. . . Conductive layer

462．．．佈線層462. . . Wiring layer

460c．．．絕緣層460c. . . Insulation

401．．．RF輸入部401. . . RF input

402．．．邏輯電路部402. . . Logic circuit

403．．．外部輸入部403. . . External input

405．．．調整電路部405. . . Adjustment circuit

406．．．二極體406. . . Dipole

407．．．電阻器407. . . Resistor

415．．．調整電路部415. . . Adjustment circuit

411．．．RF輸入部411. . . RF input

412．．．邏輯電路部412. . . Logic circuit

413．．．外部輸入部413. . . External input

414．．．記憶元件部414. . . Memory component department

416．．．二極體416. . . Dipole

417．．．電阻器417. . . Resistor

202．．．記憶胞陣列202. . . Memory cell array

201．．．記憶胞201. . . Memory cell

203、204．．．解碼器203, 204. . . decoder

205．．．選擇器205. . . Selector

206．．．讀出/寫入電路206. . . Read/write circuit

207．．．記憶元件207. . . Memory component

215．．．電晶體215. . . Transistor

501．．．諧振電容器501. . . Resonant capacitor

502．．．帶通濾波器502. . . Bandpass filter

503．．．電源供應電路503. . . Power supply circuit

504．．．解調電路504. . . Demodulation circuit

505．．．調制電路505. . . Modulation circuit

506．．．碼提取電路506. . . Code extraction circuit

507．．．時鐘產生電路507. . . Clock generation circuit

508．．．迴圈冗餘碼檢查電路508. . . Loop redundancy code check circuit

509．．．控制電路509. . . Control circuit

510．．．記憶電路510. . . Memory circuit

551．．．類比電路551. . . Analog circuit

552．．．數位電路552. . . Digital circuit

221a．．．端子221a. . . Terminal

9520．．．端子9520. . . Terminal

9521．．．顯示部9521. . . Display department

9522．．．物品9522. . . article

9523．．．半導體裝置9523. . . Semiconductor device

9531．．．半導體裝置9531. . . Semiconductor device

9532．．．物品9532. . . article

圖1A至1C分別是說明本發明的半導體裝置的結構的圖，說明本發明的半導體裝置的結構的圖，和說明比較例的圖；圖2是說明本發明的半導體裝置的結構的圖；圖3是說明本發明的半導體裝置的結構的圖；圖4是說明本發明的半導體裝置的結構的圖；圖5是說明本發明的半導體裝置的結構的圖；圖6是說明本發明的半導體裝置的結構的圖；圖7是說明本發明的半導體裝置的結構的圖；圖8A和8B分別說明本發明的半導體裝置的結構的截面圖；圖9A和9B分別說明本發明的半導體裝置的結構的電路圖；和圖10是說明半導體裝置的結構的圖。1A to 1C are views for explaining a configuration of a semiconductor device of the present invention, a view showing a configuration of a semiconductor device of the present invention, and a view for explaining a comparative example; and Fig. 2 is a view for explaining a configuration of a semiconductor device of the present invention; 3 is a view for explaining a configuration of a semiconductor device of the present invention; FIG. 4 is a view for explaining a configuration of a semiconductor device of the present invention; FIG. 5 is a view for explaining a configuration of a semiconductor device of the present invention; Figure 7 is a view for explaining the structure of a semiconductor device of the present invention; Figures 8A and 8B are respectively sectional views showing the structure of a semiconductor device of the present invention; and Figures 9A and 9B respectively show the structure of a semiconductor device of the present invention. FIG. 10 is a diagram illustrating the structure of a semiconductor device.

11．．．半導體電路部11. . . Semiconductor circuit department

12．．．記憶電路部12. . . Memory circuit

13．．．線圈狀天線部13. . . Coil antenna

100．．．基板100. . . Substrate

101．．．絕緣層101. . . Insulation

102－103．．．薄膜電晶體102-103. . . Thin film transistor

106．．．絕緣層106. . . Insulation

107－110．．．佈線107-110. . . wiring

115．．．絕緣層115. . . Insulation

118．．．絕緣層118. . . Insulation

123．．．絕緣層123. . . Insulation

124－128．．．導電層124-128. . . Conductive layer

129．．．絕緣層129. . . Insulation

141－144．．．記憶元件141-144. . . Memory component

145．．．導電層145. . . Conductive layer

146．．．導電層146. . . Conductive layer

147－150．．．包含有機化合物的層147-150. . . Layer containing organic compounds

Claims (21)

一種半導體裝置，包含：一積體電路；具有旋渦形狀為主要結構的天線；和一元件，在具有絕緣表面的基板上，其中該元件包含第一電極、第二電極、以及夾在該第一電極和該第二電極之間的包含有機化合物的層，其中該天線電連接到該積體電路，其中該第一電極或該第二電極電連接到該積體電路，和其中該天線與該第二電極重疊。A semiconductor device comprising: an integrated circuit; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes the first electrode, the second electrode, and the first a layer comprising an organic compound between the electrode and the second electrode, wherein the antenna is electrically connected to the integrated circuit, wherein the first electrode or the second electrode is electrically connected to the integrated circuit, and wherein the antenna and the antenna The second electrodes overlap. 如申請專利範圍第1項的半導體裝置，其中該元件是記憶元件。The semiconductor device of claim 1, wherein the component is a memory component. 如申請專利範圍第1項的半導體裝置，其中該天線由供電部及多個線狀或帶狀的天線導體形成，且該天線導體被設置成從該供電部周圍向著該供電部的旋渦形狀。The semiconductor device according to claim 1, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion. 如申請專利範圍第1項的半導體裝置，其中該天線由供電部及多個線狀或帶狀的天線導體形成，且該天線導體為橢圓形或圓形。A semiconductor device according to claim 1, wherein the antenna is formed by a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is elliptical or circular. 如申請專利範圍第1項的半導體裝置，其中該具有絕緣表面的基板是玻璃、塑膠、或紙。The semiconductor device of claim 1, wherein the substrate having an insulating surface is glass, plastic, or paper. 一種半導體裝置，包含：一積體電路；一電晶體；具有旋渦形狀為主要結構的天線；和一元件，在具有絕緣表面的基板上，其中該元件包含第一電極、第二電極、以及夾在該第一電極和該第二電極之間的包含有機化合物的層，其中該天線電連接到該積體電路，其中該第一電極或該第二電極電連接到該積體電路，其中該電晶體電連接到該第一電極，和其中該天線與該第二電極及該電晶體重疊。A semiconductor device comprising: an integrated circuit; a transistor; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes the first electrode, the second electrode, and the clip a layer comprising an organic compound between the first electrode and the second electrode, wherein the antenna is electrically connected to the integrated circuit, wherein the first electrode or the second electrode is electrically connected to the integrated circuit, wherein A transistor is electrically coupled to the first electrode, and wherein the antenna overlaps the second electrode and the transistor. 如申請專利範圍第6項的半導體裝置，其中該元件是記憶元件。A semiconductor device according to claim 6, wherein the component is a memory component. 如申請專利範圍第6項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體被設置為從該供電部周圍向著該供電部的旋渦形狀。The semiconductor device according to claim 6, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion. 如申請專利範圍第6項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體為橢圓形或圓形。The semiconductor device of claim 6, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular. 如申請專利範圍第6項的半導體裝置，其中該電晶體是薄膜電晶體。The semiconductor device of claim 6, wherein the transistor is a thin film transistor. 如申請專利範圍第6項的半導體裝置，其中該具有絕緣表面的基板是玻璃、塑膠、或紙。The semiconductor device of claim 6, wherein the substrate having an insulating surface is glass, plastic, or paper. 一種半導體裝置，包含：一控制電路；具有旋渦形狀為主要結構的天線；和一元件，在具有絕緣表面的基板上，其中該元件包含第一電極、第二電極、以及夾在該第一電極和該第二電極之間的包含有機化合物的層，其中該第一電極或該第二電極電連接到該控制電路，和其中該天線與該第二電極重疊。A semiconductor device comprising: a control circuit; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes a first electrode, a second electrode, and a first electrode And a layer comprising an organic compound between the second electrode, wherein the first electrode or the second electrode is electrically connected to the control circuit, and wherein the antenna overlaps the second electrode. 如申請專利範圍第12項的半導體裝置，其中該元件是記憶元件。The semiconductor device of claim 12, wherein the component is a memory component. 如申請專利範圍第12項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體被設置為從該供電部周圍向著該供電部的旋渦形狀。The semiconductor device according to claim 12, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion. 如申請專利範圍第12項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體為橢圓形或圓形。The semiconductor device of claim 12, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular. 如申請專利範圍第12項的半導體裝置，其中該具有絕緣表面的基板是玻璃、塑膠、或紙。The semiconductor device of claim 12, wherein the substrate having an insulating surface is glass, plastic, or paper. 一種半導體裝置，包含：一類比電路；一數位電路；和具有以旋渦形狀為主要結構的天線，在具有絕緣表面的基板上，其中該數位電路包括包含第一電極、第二電極、以及夾在該第一電極和該第二電極之間的包含有機化合物的層的元件；其中該數位電路電連接到該類比電路，和其中該天線與該第二電極重疊。A semiconductor device comprising: an analog circuit; a digital circuit; and an antenna having a vortex shape as a main structure on a substrate having an insulating surface, wherein the digital circuit includes a first electrode, a second electrode, and a clip An element comprising a layer of an organic compound between the first electrode and the second electrode; wherein the digital circuit is electrically coupled to the analog circuit, and wherein the antenna overlaps the second electrode. 如申請專利範圍第17項的半導體裝置，其中該元件是記憶元件。The semiconductor device of claim 17, wherein the component is a memory component. 如申請專利範圍第17項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體被設置為從該供電部周圍向著該供電部的旋渦形狀。The semiconductor device according to claim 17, wherein the antenna is formed by a power supply unit and a plurality of linear or strip antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply unit toward the power supply unit. 如申請專利範圍第17項的半導體裝置，其中該天線由供電部及多個線狀或帶狀天線導體形成，且該天線導體為橢圓形或圓形。The semiconductor device of claim 17, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular. 如申請專利範圍第17項的半導體裝置，其中該具有絕緣表面的基板是玻璃、塑膠、或紙。The semiconductor device of claim 17, wherein the substrate having an insulating surface is glass, plastic, or paper.
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US9768210B2 (en) 2017-09-19
US9437777B2 (en) 2016-09-06

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