TWI411964B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI411964B
TWI411964B TW096103361A TW96103361A TWI411964B TW I411964 B TWI411964 B TW I411964B TW 096103361 A TW096103361 A TW 096103361A TW 96103361 A TW96103361 A TW 96103361A TW I411964 B TWI411964 B TW I411964B
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TW
Taiwan
Prior art keywords
antenna
semiconductor device
electrode
circuit
power supply
Prior art date
Application number
TW096103361A
Other languages
Chinese (zh)
Other versions
TW200802119A (en
Inventor
Tamae Takano
Nobuharu Ohsawa
Kiyoshi Kato
Original Assignee
Semiconductor Energy Lab
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Filing date
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Priority to JP2006033473 priority Critical
Application filed by Semiconductor Energy Lab filed Critical Semiconductor Energy Lab
Publication of TW200802119A publication Critical patent/TW200802119A/en
Application granted granted Critical
Publication of TWI411964B publication Critical patent/TWI411964B/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773Antenna details
    • G06K19/07777Antenna details the antenna being of the inductive type
    • G06K19/07784Antenna details the antenna being of the inductive type the inductive antenna consisting of a plurality of coils stacked on top of one another
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
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    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
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    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/28Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
    • H01L27/285Integrated circuits with a common active layer, e.g. cross point devices
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    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
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    • H01L51/00Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
    • H01L51/05Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture
    • H01L51/0575Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential- jump barrier or surface barrier multistep processes for their manufacture the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L51/0591Bi-stable switching devices
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    • H01L51/50Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes [OLED] or polymer light emitting devices [PLED];
    • H01L51/5012Electroluminescent [EL] layer
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    • H01L51/52Details of devices
    • H01L51/5203Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
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    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04Resonant antennas
    • H01Q9/16Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/26Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength
    • H01Q9/27Spiral antennas
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    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F5/00Coils
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    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/922Active solid-state devices, e.g. transistors, solid-state diodes with means to prevent inspection of or tampering with an integrated circuit, e.g. "smart card", anti-tamper

Abstract

When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

Description

Semiconductor device

The present invention relates to a semiconductor device that performs data exchange using wireless communication. More particularly, the present invention relates to a semiconductor device that performs data exchange using electromagnetic induction and wireless communication.

Further, in the present specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

In recent years, individual identification technology of semiconductor devices that use wireless communication for data exchange has attracted attention. Individual identification technology using semiconductor devices has begun to be applied to the production or management of individual articles, and has also begun to be applied to personal authentication. Such semiconductor devices are also referred to as RFID (Radio Frequency Identification) tags, IC (integrated circuit) tags, IC chips, RF tags, wireless tags, and electronic tags.

A semiconductor device that performs data exchange by electromagnetic induction will be described with reference to Fig. 10 (see Patent Document 1). The semiconductor device 301 includes a coil antenna portion 302 and a semiconductor circuit portion 303. The terminal 304 of the semiconductor circuit portion 303 is electrically connected to one end 305 of the coiled antenna portion 302. The terminal 306 of the semiconductor circuit portion 303 is electrically connected to the other end 307 of the coiled antenna portion 302.

When the reader/writer including the coil antenna portion approaches the semiconductor device 301, an alternating magnetic field from the coil antenna portion included in the reader/writer is generated. The AC magnetic field penetrates the coil antenna portion 302 in the semiconductor device 301, and an electromotive force is generated between the terminals (between the one end 305 and the other end 307) in the coil antenna portion 302 in the semiconductor device 301 by electromagnetic induction. The electromotive force generated by the electromagnetic induction causes the semiconductor circuit portion 303 in the semiconductor device 301 to operate.

[Patent Document 1] Japanese Patent Laid-Open No. 11-11058

As described above, the power is supplied to the semiconductor device for data exchange by the electromagnetic induction by the antenna, and thus it is difficult to stably supply the power. Therefore, it is necessary to suppress power consumption as much as possible.

When a conductive layer occupying a large area is formed in the coiled antenna portion, it is affected by electromagnetic induction and current also flows through the conductive layer. In other words, when a conductive layer occupying a large area is formed in the coil-shaped antenna portion, it is difficult to stably supply the power source.

Accordingly, it is an object of the present invention to provide a semiconductor device which prevents electromagnetic induction from affecting the conductive layer and stabilizing the power supply by efficiently arranging the coil antenna portion and the conductive layer occupying a large area.

The present invention is characterized in that an element (for example, a memory element, a light-emitting element, a sensor element, or the like) that occupies a large-area conductive layer as one of a pair of electrodes in a semiconductor device including an antenna is used The antenna and the conductive layer occupying a large area at least partially overlap.

The structure of the invention disclosed in the present specification is as follows: a semiconductor device including at least a plurality of integrated circuits on a substrate having an insulating surface, and having a vortex shape (referred to as a vortex shape or a coil shape in one plane) as a main structure Antenna, a first electrode, a second electrode, and a layer comprising an organic compound formed between the first electrode and the second electrode, wherein the antenna is at least one of the plurality of integrated circuits Electrically connected, the first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits, and the antenna overlaps with the second electrode.

In addition, the antenna can also be configured in a form that also overlaps the transistor. Other structures of the present invention are as follows: a semiconductor device including at least a plurality of integrated circuits, transistors, and a vortex shape (referred to as a vortex shape or a coil shape in one plane) as a main structure on a substrate having an insulating surface Antenna, a first electrode, a second electrode, and a layer comprising an organic compound formed between the first electrode and the second electrode, wherein the antenna is at least one of the plurality of integrated circuits Electrically connecting, the first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits, the transistor is electrically connected to the first electrode, and the antenna and the second The electrode and the transistor overlap. Further, in the case where the transistor of the integrated circuit other than the second electrode overlaps with the antenna, a part of the integrated circuit is also disposed outside the region surrounded by the antenna.

Further, the memory element, the light-emitting element, the sensor element, and the like are composed of a first electrode, a second electrode, and a layer containing an organic compound formed between the electrodes. Preferably, these elements are configured such that the area of one or both of the electrodes is relatively large and at least a portion of the elements overlap the antenna.

The advantage of the memory element using the organic material is as follows: even if others are disassembled for forgery, forgery is very difficult, because the organic material that contacts the atmosphere or the like easily changes its properties, and it is difficult to recognize the material used.

Further, when an irreversible phase change organic material or inorganic material is used as a layer containing an organic compound of a memory element to prevent information from being tampered with or improperly used, the number of times of writing the memory is once.

In addition, when a reversible phase change organic material (for example, phenanthroline (abbreviated as BPhen)) or an inorganic material is used as a layer containing an organic compound of a memory element, the number of times the memory can be rewritten is plural times, Achieve repeated use. In addition, it is also possible to use a reader/writer to write and read a memory element using an organic material.

Further, in each of the above configurations, the antenna is composed of a power supply portion and a plurality of antenna conductors having a line shape or a strip shape, and the antenna conductor is provided in a form having a spiral shape from the periphery of the power supply portion toward the power supply portion. In addition, the antenna conductor may also be elliptical or circular.

Further, in each of the above configurations, the integrated circuit is, for example, a write circuit, a read circuit, a sense amplifier, an output circuit, a buffer, or the like.

These means as described above are not simple design matters, but are to configure a memory, an antenna or a wiring and to manufacture a semiconductor device including a memory circuit using the configuration thereof, to perform writing or reading work, and inventors After intensive research, the invented matter.

According to the present invention, it is possible to arrange the conductive layer occupying a large area in a region overlapping the antenna, and therefore it is possible to effectively utilize the space as compared with the case where the area overlapping the antenna is not disposed. Therefore, miniaturization of the semiconductor device can be achieved.

Further, by stacking the memory circuit portion and the coil antenna portion, it is possible to prevent current from flowing through the conductive layer occupying a large area included in the memory circuit portion, and it is possible to achieve low power consumption.

Embodiment modes of the present invention will be described in detail below with reference to the accompanying drawings. It is to be noted that the present invention is not limited to the following description, and various changes in the form and details may be made without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the description of the embodiment modes shown below. In the structures of the present invention described below, the same reference numerals are used for the same parts between the different drawings.

Embodiment mode 1

A semiconductor device of the present invention includes a semiconductor circuit portion 11, a memory circuit portion 12, and a coil antenna portion 13. The memory circuit unit 12 is provided with a plurality of memory elements. Each of the plurality of memory elements has a structure in which a layer containing an organic compound is sandwiched between a pair of electrodes. One or both of the pair of electrodes included in the plurality of memory elements are used in common by the plurality of memory elements. Therefore, one or both of the pair of electrodes included in the plurality of memory elements become a conductive layer occupying a large area. Therefore, in the present invention, the memory circuit portion 12 and the coiled antenna portion 13 are arranged to overlap each other to prevent a current from flowing through the conductive layer occupying a large area included in the memory circuit portion 12 due to electromagnetic induction.

The upper surface structure of the semiconductor device of the present invention will be described below. Hereinafter, a semiconductor device and a semiconductor device including a semiconductor circuit portion, a memory circuit portion, and a coil antenna portion, and the memory circuit portion and the coil antenna portion are not overlapped (see FIG. 1C) will be described. Further, Fig. 1C is not the present invention but a comparative example. The semiconductor device shown in FIG. 1C includes a semiconductor circuit portion 1201, a memory circuit portion 1202, and an antenna portion 1203. Further, the first terminal of the semiconductor circuit portion 1201 is electrically connected to one end of the coiled antenna portion 1203, and the second terminal of the semiconductor circuit portion 1201 is electrically connected to the other end of the coiled antenna portion 1203. Further, the semiconductor circuit portion 1201 and the memory circuit portion 1202 are electrically connected.

When the memory circuit unit 12 occupies the same area as the configuration of FIG. 1C and the memory circuit unit 12 and the coil antenna unit 13 are disposed to overlap each other (see FIG. 1A), the area occupied by the semiconductor circuit unit 11 can be increased. If the area occupied by the semiconductor circuit portion 11 can be increased, more components can be provided, and thus a high-performance circuit can be provided. Further, the coiled antenna portion 13 shown in FIG. 1A is an example in which the number of turns exceeds 5 ,, but is not limited thereto. As long as the number of turns is 2 or more, it can be. Further, the first terminal of the semiconductor circuit portion 11 is electrically connected to one end of the coiled antenna portion 13, and the second terminal of the semiconductor circuit portion 11 is electrically connected to the other end of the coiled antenna portion 13. Further, the semiconductor circuit portion 11 and the memory circuit portion 12 are electrically connected.

When the semiconductor circuit portion 11 occupies the same area as the configuration of FIG. 1C and the memory circuit portion 12 and the coil antenna portion 13 are disposed to overlap each other (see FIG. 1B), the occupied area of the memory circuit portion 12 can be increased. If the area occupied by the memory circuit portion 12 can be increased, more components can be provided, and thus a circuit having a large memory capacity can be provided. In FIG. 1B, the first terminal of the semiconductor circuit portion 11 is electrically connected to one end of the coiled antenna portion 13, and the second terminal of the semiconductor circuit portion 11 is electrically connected to the other end of the coiled antenna portion 13. Further, the semiconductor circuit portion 11 and the memory circuit portion 12 are electrically connected.

Next, a cross-sectional structure of the semiconductor device having the above configuration (see FIG. 2) will be described. The cross-sectional structure shown in FIG. 2 is a view showing a cross-sectional structure along the line A-B in the upper surface structure of the semiconductor device of FIG. 1A.

The semiconductor device of the present invention includes an insulating layer 101 serving as a chassis, thin film transistors 102 to 105 disposed on the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 to 105, and borrowing on the substrate 100 having an insulating surface. The wirings 107 to 114 connected to the source or the drain of the thin film transistors 102 to 105 are connected by openings formed in the insulating layer 106.

The semiconductor device of the present invention further includes an insulating layer 115 covering the wirings 107 to 114, conductive layers 116 and 117 connected to the wirings 112 and 114 by openings formed in the insulating layer 115, and insulating layers covering the conductive layers 116 and 117. 118, an organic compound-containing layer 119 and 120 connected to the conductive layers 116 and 117, and a conductive layer 121 connected to the organic compound-containing layers 119 and 120, by an opening formed in the insulating layer 118. In addition, an insulating layer 123 covering the conductive layer 121, conductive layers 124 to 128 formed on the insulating layer 123, and an insulating layer 129 covering the conductive layers 124 to 128 are further provided.

In the above cross-sectional structure, the portion including the thin film transistors 102 and 103 corresponds to the semiconductor circuit portion 11. Further, a laminate composed of the conductive layer 116, the layer 119 containing an organic compound, and the conductive layer 121 corresponds to the memory element 130. Further, a laminate composed of the conductive layer 117, the layer 120 containing the organic compound, and the conductive layer 121 corresponds to the memory element 131. The circuit including the memory elements 130 and 131 is equivalent to the memory circuit portion 12. Further, the conductive layers 124 to 128 correspond to the coil antenna portion 13.

By arranging the conductive layers 124 to 128 included in the large-area conductive layer 121 and the coil-shaped antenna portion 13 included in the memory circuit portion 12 in an overlapping manner, it is possible to prevent current from being induced by electromagnetic induction. Flow through the conductive layer 121. Further, by arranging the memory circuit unit 12 and the coil antenna portion 13 in a stacked manner, it is possible to achieve downsizing.

Next, a cross-sectional structure of a semiconductor device which is different from the above configuration will be described (see FIG. 3). The semiconductor device includes an insulating layer 101 serving as a base, thin film transistors 102 and 103 disposed on the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 and 103, and formed on the substrate 100 having an insulating surface. The openings in the insulating layer 106 are connected to the wirings 107 to 110 of the source or drain of the thin film transistors 102 and 103.

In addition, the semiconductor device further includes an insulating layer 115 covering the wirings 107 to 110, a conductive layer 145 connected to the wiring 110 by an opening formed in the insulating layer 115, and an insulating layer 118 covering the conductive layer 145, which are formed in the insulating layer. The opening portion in the layer 118 is connected to the organic compound-containing layers 147 to 150 of the conductive layer 145, and the conductive layer 146 connected to the organic compound-containing layers 147 to 150. In addition, an insulating layer 123 covering the conductive layer 146, conductive layers 124 to 128 formed on the insulating layer 123, and an insulating layer 129 covering the conductive layers 124 to 128 are further provided. The laminate composed of the conductive layer 145, any one of the layers 147 to 150 containing the organic compound, and the conductive layer 146 corresponds to the memory elements 141 to 144.

As described above, by arranging the conductive layers 145 and 146 which are included in the memory circuit portion 12 and the conductive layers 124 to 128 included in the coil-like antenna portion 13 to be overlapped, it is possible to prevent electromagnetic induction. Current is caused to flow through the conductive layer 121. Further, by stacking the memory circuit unit 12 and the coil antenna portion 13, it is possible to achieve downsizing.

Embodiment mode 2

In the present embodiment mode, an example of a semiconductor device including the memory device shown in the first embodiment will be described in detail with reference to the drawings. Fig. 8A is a plan view of the semiconductor device of the present embodiment mode, and Fig. 8B is a cross-sectional view taken along line X-Y of Fig. 8A.

As shown in FIG. 8A, a memory element portion 404, an integrated circuit portion 421, and an antenna 431 as memory devices including memory elements are formed on the substrate 400. 8A and 8B show a manufacturing process in progress, and a state in which a memory element portion, a circuit portion, and an antenna are formed on a substrate 400 capable of withstanding manufacturing conditions. Materials and manufacturing processes for memory devices are well known.

On the substrate 400, transistors 441 and 442 are formed in the memory element portion 404 and the integrated circuit portion 421 via the peeling layer 452 and the insulating layer 453, respectively. A tungsten film of 50 nm to 200 nm thick is used as the peeling layer 452, and a hafnium oxide film is used as the insulating layer 453. However, the release layer is not limited to the tungsten film, and a Mo film, an amorphous germanium film, or the like may be used. Insulating layers 451, 454, and 455 are formed on the transistors 441 and 442, and a memory element 443 composed of a laminate of the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 is formed on the insulating layer 455. . The organic compound layer 458 is separated by an insulating layer 460b serving as a partition wall, respectively. The first conductive layer 457d is connected to the wiring layer of the transistor 441, and the memory element 443 is electrically connected to the transistor 441.

Openings (also referred to as contact holes) are formed in the insulating layer 455 to connect the first conductive layer 457d and the transistor 441, the conductive layer 457c and the wiring layer 456a, the conductive layer 457e, and the wiring layer 456b, respectively. Since increasing the opening can increase the contact area between the conductive layers to obtain a lower electric resistance, in the embodiment mode, the opening for connecting the first conductive layer 457d and the transistor 441 is the smallest, followed by the connection of the conductive layer 457c and The opening of the wiring layer 456a, the largest is the order in which the openings of the conductive layer 457e and the wiring layer 456b are connected to increase the opening. In the present embodiment mode, the opening connecting the first conductive layer 457d and the transistor 441, the opening connecting the conductive layer 457c and the wiring layer 456a, the opening connecting the conductive layer 457e and the wiring layer 456b are set to 5 μm × 5 μm, 50 μm, respectively. ×50 μm, 500 μm × 500 μm.

In the semiconductor device shown in FIG. 8B, the second conductive layer 459 is laminated with and electrically connected to the wiring layer 456a and the conductive layer 457c. The electrode area of the second conductive layer 459 is larger than that of the first conductive layer 457d. In the present invention, the second conductive layer 459 and the antenna 431 are disposed in an overlapping form.

An insulating layer 461 is formed on the insulating layer 455. A conductive layer 457a and an antenna 431a, a conductive layer 457b and an antenna 431b, a conductive layer 457e and an antenna 431c, and a conductive layer 457f and an antenna 431d are laminated on the insulating layer 461, respectively. The conductive layer 457e is formed to be in contact with the wiring layer 462 via an opening reaching the wiring layer 462 formed in the insulating layer 461. In addition, the wiring layer 462 is formed in contact with the wiring layer 456b via an opening reaching the wiring layer 456b formed in the insulating layer 455. Further, in the present specification, a connecting portion between the antenna and a wiring layer formed under the antenna is referred to as a power supply portion of the antenna. Here, the antenna is electrically connected to the memory element portion 404 and the integrated circuit portion 421 by using the wiring layer 462 and the wiring layer 456b. However, the connection is not limited to this, and the antenna 431c and the wiring layer 456b may be electrically connected.

The conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f formed under the antenna 431a, the antenna 431b, the antenna 431c, and the antenna 431d also function to improve the insulating layer 455 and the antenna 431a, the antenna 431b, the antenna 431c, and The tightness between the antennas 431d. In this embodiment mode, a polyimide film is used for the insulating layer 455 and the insulating layer 461, a titanium film is used for the conductive layers 457a, 457b, 457e, 457f, and an aluminum film is used for the antennas 431a, 431b, 431c, respectively. 431d.

An insulating layer 460c is partially formed in the integrated circuit portion 421, and the transistor 442 also has a region not covered by the insulating layer 460c or covered by the insulating layer 460c.

9A and 9B are block diagrams showing circuits of a semiconductor device of the present embodiment mode. The block diagram of the semiconductor device of FIG. 9A includes an RF input unit 401, a logic circuit unit 402, an external input unit 403, a memory element unit 404, an adjustment circuit unit 405, a diode 406, and a resistor 407. Further, the integrated circuit portion 421 shown in FIG. 8A corresponds to the RF input unit 401, the logic circuit unit 402, the external input unit 403, the adjustment circuit unit 405, the diode 406, or the resistor 407 of FIG. 9A.

The voltage and signal input from the external input terminal are input to the memory element portion 404, and the data (information) is written to the memory element portion 404. The RF input unit 401 receives an AC signal by an antenna and inputs the signal and voltage to the logic circuit unit 402. The signal is converted into a control signal by the logic circuit unit 402, and the written information is read again from the memory element unit 404 by inputting a control signal to the memory element unit 404.

FIG. 9B shows an example in which the configuration of the adjustment circuit portion 405 is different from that of the semiconductor device of FIG. 9A. The adjustment circuit portion 405 is composed of a resistor, and the adjustment circuit portion 415 is composed of a switch. The block diagram of FIG. 9B includes an RF input unit 411, a logic circuit unit 412, an external input unit 413, a memory element unit 414, an adjustment circuit unit 415, a diode 416, and a resistor 417. Further, the integrated circuit portion 421 shown in FIG. 8A corresponds to the RF input portion 411, the logic circuit portion 412, the external input portion 413, the adjustment circuit portion 415, the diode 416, or the resistor 417 of FIG. 9B.

In addition, the resistors 407 and 417 are booster circuits and serve as adjustment circuit sections. The adjustment circuit unit 405 is configured to prevent an unnecessary control signal from being input from the logic circuit unit 402 to the memory element unit 404 when data is written to the memory element unit 404. Similarly, the resistor 407 is also adapted to input a signal from the logic circuit unit 402 to the memory element unit 404 when data is written to the memory element unit 404. When the data is written to the memory element unit 404, the signal from the external input unit 403 is blocked by the diode 406, and when the data is read from the memory element unit 404, the VDDH of the memory element unit 404 is fixed at the RF. The VDD applied to the input portion 401 is stabilized. Here, description will be made with reference to the block diagram of Fig. 9A, but the case of Fig. 9B is the same as Fig. 9A.

Further, the antenna electrically connected to the RF input portions 401 and 411 is provided in a form overlapping with the memory device having the memory element portion. Alternatively, it may overlap the entire surface of the electrode of the memory device or may overlap with a portion of the electrode of the memory device. By adopting a configuration in which the antenna unit and the memory device are overlapped, it is possible to reduce the malfunction of the semiconductor device due to noise or the like included in the signal when the antenna is communicated, or the fluctuation of the electromotive force due to electromagnetic induction, thereby improving reliability. Sex. In addition, it is also possible to achieve low power consumption of the semiconductor device. Furthermore, the semiconductor device can also be miniaturized.

The memory element 443 having the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 shown in this embodiment mode has good tightness, and thus is formed on the substrate 400 as the first substrate (glass substrate). After the above, there is no problem such as film peeling or the like on the interface due to the pressure applied in the process of being transferred onto the second substrate. Therefore, it is possible to transfer a memory element to a paper or plastic substrate after peeling it in a good shape to manufacture a lightweight and flexible memory device or a lightweight and flexible semiconductor device.

Since the memory device having the memory element manufactured in the present embodiment mode has good tightness, the peeling process and the transfer process can be performed in a good state. Therefore, it can be freely transferred onto various substrates, and thus, a wide range of substrate materials can be selected. In addition, an inexpensive material can be selected as the substrate, and not only various functions can be provided depending on the use, but also a memory device and a semiconductor device can be manufactured at low cost.

According to the present invention, it is possible to manufacture a memory device having a memory element which can be subjected to a transfer process in a good state. Therefore, a memory device having higher reliability and a semiconductor device having the memory device can be manufactured with high yield without complicating the device or the process.

The invention having the above structure will be explained in more detail by way of the following examples.

Example 1

The configuration of the memory circuit unit included in the semiconductor device of the present invention will be described below (see FIGS. 4 and 5).

The memory circuit portion is provided with a memory cell array 202 including a plurality of bit lines B1 to Bm (m is a natural number), a plurality of word lines W1 to Wn (n is a natural number), and a plurality of memory cells 201. Further, a decoder 203 that controls the plurality of bit lines B1 to Bm, a decoder 204 that controls the plurality of word lines W1 to Wn, a selector 205, and a read/write circuit 206 are provided.

As the structure of the memory cell array 202, an active matrix type and a passive matrix type can be cited. In the case where the memory cell array 202 is of an active matrix type, the memory cell 201 includes a transistor 215 and a memory element 207 (refer to FIG. 4). The gate of the transistor 215 is electrically connected to the word line Wb (1≦b≦n), and one of the source and the drain of the transistor 215 is electrically connected to the bit line Ba (1≦a≦m), and the transistor 215 The other source or drain is electrically coupled to one of a pair of electrodes included in memory element 207.

In the case where the memory cell array 202 is of a passive matrix type, the memory cell 201 includes a memory element 207 (refer to FIG. 5) disposed at the intersection of the bit line Ba and the word line Wb.

Next, an operation when data is written to the memory circuit unit will be described.

The case where data is written to the memory circuit unit by electrical action will be described below. First, the memory cell 201 is selected by the decoder 203, the decoder 204, and the selector 205. Next, the data is written to the selected memory cell 201 by the read/write circuit 206. Specifically, data is written by applying a predetermined voltage to the memory element included in the selected memory cell 201 by the read/write circuit 206. If a predetermined voltage is applied, the resistance value of the memory element changes. The change in the resistance value of the memory element may be a case where the resistance value increases or a resistance value decreases, and both of them can be applied to data writing. The phenomenon in which the resistance value rises is a phenomenon in which a layer containing an organic compound between a pair of electrodes is increased in resistance by applying a predetermined voltage to the memory element. Conversely, the phenomenon in which the resistance value is lowered is a phenomenon in which the distance between a pair of electrodes is reduced by applying a predetermined voltage to the memory element. In this manner, the memory circuit unit writes data using a phenomenon in which the resistance value of the memory element is changed by electrical action. For example, if the memory element in the initial state is the material "0", an electrical action is applied to the memory element to which the material "1" is to be written.

Next, a case where data is written by optical action will be described. In this case, an optical irradiation device (for example, a laser irradiation device) is used to irradiate light to a layer containing an organic compound from the side of the light-transmitting conductive layer to write data to the light-irradiated memory element. The resistance value of the memory element changes by light irradiation. The change in the resistance value of the memory element may be a case where the resistance value increases or a resistance value decreases, and both of them can be applied to data writing. In this manner, the memory circuit unit writes data by a phenomenon in which the resistance value of the memory element is changed by optical action. For example, if the memory element in the initial state is the material "0", an optical effect is applied to the memory element to which the material "1" is to be written.

Next, an operation when data is read from the memory circuit unit will be described.

Regardless of the way the data is written, data reading is performed using electrical action. The difference in resistance values of the memory elements is read by the decoders 203 and 204, the selector 205, and the read/write circuit 206 to perform data reading.

Further, a rectifying element may be provided between one of a pair of conductive layers included in the memory element and a layer containing an organic compound. The rectifying element refers to a transistor, a diode, or the like electrically connected to the gate and the drain. By providing a rectifying element, the direction in which the current flows can be limited, so that the correctness of the data reading can be improved.

Next, a material for a layer containing an organic compound included in the memory element will be described.

In the case where data is written to the memory element by electrical action, a low molecular material, a polymer material, a singlet material, a triplet material or the like can be used for the layer containing the organic compound. Further, not only a layer containing an organic compound composed only of an organic compound material but also a material containing a part of the inorganic compound may be used. Further, as the layer containing the organic compound, a hole injection layer, a hole transport layer, a hole barrier layer, a light-emitting layer, an electron transport layer, an electron injection layer, or the like may be used, but a single layer structure may be used, or a plurality of layers may be stacked. . Further, a layer containing an organic compound can be formed using a droplet discharge method typified by an inkjet method. By using the droplet discharge method, the utilization efficiency of the material can be improved, and the manufacturing time can be shortened and the manufacturing cost can be reduced by the simplification of the manufacturing steps.

Further, in the case where data is written to the memory circuit portion by optical action, a material which changes properties due to optical action can be used as a layer containing an organic compound. For example, a conjugated polymer doped with a compound (photoacid generator) which generates an acid by absorbing light can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenyleneethylene groups, and the like can be used. Further, as the photoacid generator, an arylsulfonium salt, an aryl iodide salt, an o-nitrobenzyl tosylate, an arylsulfonic acid p-nitrobenzyl ester, a sulfonylacetophenone, Fe-arene complex PF6 salt or the like.

Further, the memory device included in the semiconductor device of the present invention may be a non-volatile memory device, and data may be added. Further, the memory device included in the semiconductor device of the present invention can also rewrite data by an electric action from the outside.

In the present embodiment, the area size of the antenna is about 9 mm × 11 mm, the number of turns of the antenna is 9 匝, the line width of the antenna itself is 150 μm, and the wiring of the antenna is wound at intervals of 10 μm. One of the memory circuit portions, that is, the upper electrode, is disposed to overlap the antenna wound in a coil shape as described above. The upper electrode is disposed on a layer containing an organic compound and serves as a common electrode of a plurality of memory elements. In the case of constituting a memory circuit having an information amount of one thousand bits, the area size of the upper electrode may be approximately 1.5 mm × 3 mm. Further, the area size of the upper electrode is not particularly limited, and the size thereof may be made smaller than 4.5 mm 2 .

The space can be effectively utilized by arranging the antenna and the conductive layer occupying a large area (upper electrode: 4.5 mm 2 ) in an overlapping manner as compared with the case where nothing is disposed in the region overlapping the antenna. Therefore, miniaturization of the semiconductor device can be achieved.

Further, by laminating the upper electrode and the coil antenna portion occupying a large area, it is possible to prevent current from flowing through the upper electrode included in the memory circuit portion, and it is possible to achieve low power consumption.

This embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

Example 2

The structure of the semiconductor circuit portion included in the semiconductor device of the present invention will be described below (see FIG. 6).

The semiconductor circuit unit includes an analog circuit 551 and a digital circuit 552. The analog circuit 551 includes a resonance capacitor 501, a band pass filter 502, a power supply circuit 503 including a rectifier circuit and a holding capacitor, a demodulation circuit 504, a modulation circuit 505, and the like. The digital circuit 552 includes a code extraction circuit 506, a clock generation circuit 507, a loop redundancy code check circuit 508, a control circuit 509, a memory circuit 510, and the like.

The following describes the action when the semiconductor device receives the data. The wireless signal (modulated carrier) input from the coil antenna is input from the terminal 221a to the analog circuit 551. The desired frequency component of the input wireless signal is taken out by the band pass filter 502, and is input to the power supply circuit 503 and the demodulation circuit 504. The modulated carrier input by the band pass filter 502 is rectified by a rectifying circuit included in the power supply circuit 503, and smoothed by a storage capacitor included in the power supply circuit 503. Thus, the power supply circuit 503 generates a DC voltage. The DC voltage generated in the power supply circuit 503 is supplied to each circuit as a power supply voltage.

Further, the modulated carrier input by the band pass filter 502 is input to the clock generating circuit 507 in the digital circuit 552. A clock generated in the clock generating circuit 507 is supplied to each circuit. The modulated carrier input by the band pass filter 502 is demodulated by the demodulation circuit 504, and the demodulated signal is input to the digital circuit 552. The demodulated signal obtained by demodulating the modulated carrier using the demodulation circuit 504 is input to the code extraction circuit 506, and the code having the signal is extracted. The output of the code extraction circuit 506 is input to the control circuit 509, and the code is extracted. The extracted code is input to the loop redundancy code check circuit 508, and calculation processing for identifying a transmission error is performed. Thus, the loop redundancy code check circuit 508 outputs an error to the received data to the control circuit 509.

Next, an operation when the semiconductor device transmits data will be described. The memory circuit 510 outputs the stored unique identification character (UID) to the control circuit 509 in accordance with a signal input from the control circuit 509. The loop redundancy code check circuit 508 calculates a CRC code corresponding to the transmitted data, and outputs it to the control circuit 509. The control circuit 509 adds a CRC code to the transmission material. Further, the control circuit 509 encodes the data to which the CRC code is attached to the transmission data. Furthermore, control circuit 509 converts the encoded information into a signal for modulating the carrier in accordance with a predetermined modulation scheme. The output of the control circuit 509 is input to the modulation circuit 505 of the analog circuit 551. The modulation circuit 505 performs load modulation on the carrier based on the input signal and outputs it to the coil antenna portion.

This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment 1.

Example 3

In the present embodiment, the use of the semiconductor device of the present invention will be described. The semiconductor device of the present invention can be used in articles such as banknotes, coins, securities, bearer bonds, certificates (drivers' licenses or residence permits, etc.), packaging containers (wrapping paper or bottles, etc.), recording media such as DVD (digital versatile disc) or video tape, vehicles such as cars or bicycles, personal items such as school bags or glasses, food, clothing, household goods, electronic equipment, etc. The electronic device refers to a liquid crystal display device, an EL (electroluminescence) display device, a television device, a mobile phone, and the like.

The semiconductor device of the present invention can be attached to the surface of an article or embedded in an article to be attached to the article. For example, if it is a book, it can be embedded in paper; and if it is a package made of an organic resin, it can be embedded in the organic resin. Counterfeiting can be prevented by providing a semiconductor device to banknotes, coins, securities, unregistered bonds, certificates, and the like. In addition, by providing the semiconductor device in packaging containers, recording media, personal articles, foods, clothing, household goods, electronic equipment, and the like, it is possible to improve the efficiency of the system in the product inspection system or the rental store. In addition, by providing the semiconductor device to the vehicle, it is possible to prevent counterfeiting and theft. In addition, by embedding a semiconductor device in a living body such as an animal, it is possible to easily identify each living body, for example, by embedding a semiconductor device in a living body such as a domestic animal, etc., it is possible to easily manage the birth year, sex, or kind, and the like. . As such, the semiconductor device of the present invention can be provided to any article (including living bodies) for use.

Next, a mode of a system using a semiconductor device will be described with reference to FIG. An antenna and a reader/writer connected to the antenna are provided on the terminal 9520 including the display portion 9521. The semiconductor device 9531 of the present invention is disposed in the article 9532, and the semiconductor device 9523 of the present invention is disposed in the article 9522. When the antenna of the terminal 9520 is aligned with the semiconductor device 9531 included in the article 9532, information related to the product such as the raw material and origin of the article 9532, the inspection result of each production process, the recording of the circulation process, and the like, and the description of the product are displayed. The display unit 9521. When the antenna of the terminal 9520 is aligned with the semiconductor device 9523 included in the article 9522, information related to the product such as the raw material and origin of the article 9522, the inspection result of each production process, the recording of the circulation process, and the like, and the description of the product are displayed. The display unit 9521.

This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment 1, or Embodiment 2.

301. . . Semiconductor device

302. . . Coil antenna

303. . . Semiconductor circuit department

304. . . Terminal

305. . . One end

306. . . Terminal

307. . . another side

12. . . Memory circuit

13. . . Coil antenna

11. . . Semiconductor circuit department

1201. . . Semiconductor circuit department

1202. . . Memory circuit

1203. . . Coil antenna

100. . . Substrate

101. . . Insulation

102-105. . . Thin film transistor

106. . . Insulation

107-114. . . wiring

115. . . Insulation

116, 117. . . Conductive layer

118. . . Insulation

119, 120. . . Layer containing organic compounds

121. . . Conductive layer

123. . . Insulation

124-128. . . Conductive layer

129. . . Insulation

130. . . Memory component

131. . . Memory component

145. . . Conductive layer

147-150. . . Layer containing organic compounds

146. . . Conductive layer

141-144. . . Memory component

400. . . Substrate

404. . . Memory component department

421. . . Integrated circuit

431. . . antenna

441, 442. . . Transistor

452. . . Peeling layer

453, 451, 454, 455. . . Insulation

443. . . Memory component

457d. . . First conductive layer

458. . . Organic compound layer

459. . . Second conductive layer

460b. . . Insulation

456a. . . Wiring layer

457e. . . Conductive layer

457c. . . Conductive layer

456b. . . Wiring layer

461. . . Insulation

457a. . . Conductive layer

431a. . . antenna

457b. . . Conductive layer

431b, 431c, 431d. . . antenna

457f. . . Conductive layer

462. . . Wiring layer

460c. . . Insulation

401. . . RF input

402. . . Logic circuit

403. . . External input

405. . . Adjustment circuit

406. . . Dipole

407. . . Resistor

415. . . Adjustment circuit

411. . . RF input

412. . . Logic circuit

413. . . External input

414. . . Memory component department

416. . . Dipole

417. . . Resistor

202. . . Memory cell array

201. . . Memory cell

203, 204. . . decoder

205. . . Selector

206. . . Read/write circuit

207. . . Memory component

215. . . Transistor

501. . . Resonant capacitor

502. . . Bandpass filter

503. . . Power supply circuit

504. . . Demodulation circuit

505. . . Modulation circuit

506. . . Code extraction circuit

507. . . Clock generation circuit

508. . . Loop redundancy code check circuit

509. . . Control circuit

510. . . Memory circuit

551. . . Analog circuit

552. . . Digital circuit

221a. . . Terminal

9520. . . Terminal

9521. . . Display department

9522. . . article

9523. . . Semiconductor device

9531. . . Semiconductor device

9532. . . article

1A to 1C are views for explaining a configuration of a semiconductor device of the present invention, a view showing a configuration of a semiconductor device of the present invention, and a view for explaining a comparative example; and Fig. 2 is a view for explaining a configuration of a semiconductor device of the present invention; 3 is a view for explaining a configuration of a semiconductor device of the present invention; FIG. 4 is a view for explaining a configuration of a semiconductor device of the present invention; FIG. 5 is a view for explaining a configuration of a semiconductor device of the present invention; Figure 7 is a view for explaining the structure of a semiconductor device of the present invention; Figures 8A and 8B are respectively sectional views showing the structure of a semiconductor device of the present invention; and Figures 9A and 9B respectively show the structure of a semiconductor device of the present invention. FIG. 10 is a diagram illustrating the structure of a semiconductor device.

11. . . Semiconductor circuit department

12. . . Memory circuit

13. . . Coil antenna

100. . . Substrate

101. . . Insulation

102-103. . . Thin film transistor

106. . . Insulation

107-110. . . wiring

115. . . Insulation

118. . . Insulation

123. . . Insulation

124-128. . . Conductive layer

129. . . Insulation

141-144. . . Memory component

145. . . Conductive layer

146. . . Conductive layer

147-150. . . Layer containing organic compounds

Claims (21)

  1. A semiconductor device comprising: an integrated circuit; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes the first electrode, the second electrode, and the first a layer comprising an organic compound between the electrode and the second electrode, wherein the antenna is electrically connected to the integrated circuit, wherein the first electrode or the second electrode is electrically connected to the integrated circuit, and wherein the antenna and the antenna The second electrodes overlap.
  2. The semiconductor device of claim 1, wherein the component is a memory component.
  3. The semiconductor device according to claim 1, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion.
  4. A semiconductor device according to claim 1, wherein the antenna is formed by a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is elliptical or circular.
  5. The semiconductor device of claim 1, wherein the substrate having an insulating surface is glass, plastic, or paper.
  6. A semiconductor device comprising: an integrated circuit; a transistor; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes the first electrode, the second electrode, and the clip a layer comprising an organic compound between the first electrode and the second electrode, wherein the antenna is electrically connected to the integrated circuit, wherein the first electrode or the second electrode is electrically connected to the integrated circuit, wherein A transistor is electrically coupled to the first electrode, and wherein the antenna overlaps the second electrode and the transistor.
  7. A semiconductor device according to claim 6, wherein the component is a memory component.
  8. The semiconductor device according to claim 6, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion.
  9. The semiconductor device of claim 6, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular.
  10. The semiconductor device of claim 6, wherein the transistor is a thin film transistor.
  11. The semiconductor device of claim 6, wherein the substrate having an insulating surface is glass, plastic, or paper.
  12. A semiconductor device comprising: a control circuit; an antenna having a vortex shape as a main structure; and an element on the substrate having an insulating surface, wherein the element includes a first electrode, a second electrode, and a first electrode And a layer comprising an organic compound between the second electrode, wherein the first electrode or the second electrode is electrically connected to the control circuit, and wherein the antenna overlaps the second electrode.
  13. The semiconductor device of claim 12, wherein the component is a memory component.
  14. The semiconductor device according to claim 12, wherein the antenna is formed of a power supply portion and a plurality of linear or strip-shaped antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply portion toward the power supply portion.
  15. The semiconductor device of claim 12, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular.
  16. The semiconductor device of claim 12, wherein the substrate having an insulating surface is glass, plastic, or paper.
  17. A semiconductor device comprising: an analog circuit; a digital circuit; and an antenna having a vortex shape as a main structure on a substrate having an insulating surface, wherein the digital circuit includes a first electrode, a second electrode, and a clip An element comprising a layer of an organic compound between the first electrode and the second electrode; wherein the digital circuit is electrically coupled to the analog circuit, and wherein the antenna overlaps the second electrode.
  18. The semiconductor device of claim 17, wherein the component is a memory component.
  19. The semiconductor device according to claim 17, wherein the antenna is formed by a power supply unit and a plurality of linear or strip antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power supply unit toward the power supply unit.
  20. The semiconductor device of claim 17, wherein the antenna is formed by a power supply portion and a plurality of linear or strip antenna conductors, and the antenna conductor is elliptical or circular.
  21. The semiconductor device of claim 17, wherein the substrate having an insulating surface is glass, plastic, or paper.
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US20140291800A1 (en) 2014-10-02
JP5483764B2 (en) 2014-05-07
US8772917B2 (en) 2014-07-08
US20160364641A1 (en) 2016-12-15
US9437777B2 (en) 2016-09-06
US20070187820A1 (en) 2007-08-16
KR20070081449A (en) 2007-08-16
JP2012253370A (en) 2012-12-20
TW200802119A (en) 2008-01-01
CN101017833A (en) 2007-08-15
US9768210B2 (en) 2017-09-19

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