JP2007241997A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which prevents an influence of electromagnetic induction to a conductive layer and stabilizes a power source by devising the layout of a coil-like antenna part and a conductive layer, large in occupancy area. <P>SOLUTION: The current is prevented from flowing through the conductive layer, large in occupancy area in a storage circuit part, and power consumption is saved by arranging the storage circuit part and the coil-like antenna part by laminating them. In addition, a space can be efficiently used by arranging the storage circuit part and the coil-like antenna part by laminating them. Consequently, miniaturization of the semiconductor device is attained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that performs data communication by wireless communication. In particular, the present invention relates to a semiconductor device that performs data communication by wireless communication using an electromagnetic induction method.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, individual identification technology using a semiconductor device that communicates data by wireless communication has attracted attention. Individual identification technology using semiconductor devices has begun to be used for production and management of individual objects, and has also begun to be applied to personal authentication. Such a semiconductor device is also referred to as an RFID (Radio Frequency Identification) tag, an IC (Integrated Circuit) tag, an IC chip, an RF tag, a wireless tag, or an electronic tag.

  A semiconductor device that performs data communication by an electromagnetic induction method (see Patent Document 1) will be described with reference to FIG. The semiconductor device 301 includes a coiled antenna portion 302 and a semiconductor circuit portion 303. A terminal 304 of the semiconductor circuit unit 303 is electrically connected to one end 305 of the coiled antenna unit 302. A terminal 306 of the semiconductor circuit unit 303 is electrically connected to the other end 307 of the coiled antenna unit 302.

When a reader / writer including a coiled antenna unit is brought close to the semiconductor device 301, an alternating magnetic field is generated from the coiled antenna unit included in the reader / writer. The AC magnetic field penetrates the coiled antenna unit 302 in the semiconductor device 301, and an electromotive force is generated between the terminals of the coiled antenna unit 302 in the semiconductor device 301 (between one end 305 and the other end 307) by electromagnetic induction. To do. The semiconductor circuit portion 303 in the semiconductor device 301 operates by an electromotive force generated by electromagnetic induction.
JP-A-11-11058

A semiconductor device that communicates data by an electromagnetic induction system is supplied with power using an antenna as described above, and thus it is difficult to stably supply power. Therefore, it is necessary to suppress power consumption as much as possible.

  If there is a conductive layer with a large occupation area inside the coiled antenna portion, current may flow through the conductive layer due to the influence of electromagnetic induction. That is, if a conductive layer having a large occupation area is provided inside the coiled antenna portion, it is difficult to stably supply power.

  Accordingly, the present invention provides a semiconductor device that prevents the influence of electromagnetic induction on the conductive layer and stabilizes the power supply by devising the arrangement of the coiled antenna portion and the conductive layer having a large occupied area. The issue is to provide

The present invention relates to an antenna (such as a memory element, a light emitting element, and a sensor element) that uses a conductive layer having a large occupied area as one of a pair of electrodes with respect to one semiconductor device having an antenna. The conductive layer is at least partially overlapped.

The structure of the invention disclosed in this specification includes an antenna mainly including at least a plurality of integrated circuits and a spiral shape (called a spiral shape or a coil shape in one plane) over a substrate having an insulating surface. A first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode, wherein the antenna is at least one of the plurality of integrated circuits. The first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits, and the antenna overlaps the second electrode. This is a featured semiconductor device.

The antenna may be arranged so as to overlap with the transistor. Another structure of the present invention is that a substrate having an insulating surface has at least a plurality of integrated circuits, a transistor, and a spiral shape (a spiral shape in one plane). An antenna having a main structure), a first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode. The antenna is electrically connected to at least one of the plurality of integrated circuits, and the first electrode or the second electrode is electrically connected to at least one of the plurality of integrated circuits. The transistor is electrically connected to the first electrode, and the antenna overlaps with the second electrode and the transistor. Note that in the case where not only the second electrode but also the transistor of the integrated circuit overlaps with the antenna, a part of the integrated circuit is also disposed outside the region surrounded by the antenna.

Note that the first electrode, the second electrode, and the layer containing an organic compound between these electrodes constitute a memory element, a light-emitting element, a sensor element, or the like. These elements are preferably arranged so that one or both electrode areas are relatively large and at least partly overlap with the antenna.

Above all, the advantage of memory elements using organic materials is that when others try to forge them and decompose them, the organic materials exposed to the atmosphere are easily altered, making it difficult to identify the material being used. Can be difficult.

  In addition, in order to prevent falsification and unauthorized use of information, when a layer containing an organic compound of a memory element is made of an organic material or an inorganic material that does not reversibly change, writing into the memory is performed once.

In addition, when the layer containing the organic compound of the memory element is made an organic material that reversibly changes phase (for example, bathophenanthroline (abbreviation: BPhen)) or an inorganic material for repeated use, data stored in the memory Rewriting is possible multiple times. Further, the reader / writer may be capable of both writing to and reading from the memory element using an organic material.

Further, in each of the above-described configurations, the antenna includes a power feeding unit and a plurality of linear or strip antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the power feeding unit toward the power feeding unit. It is one. The antenna conductor may be elliptical or circular.

In each of the above configurations, the integrated circuit is, for example, a writing circuit, a reading circuit, a sense amplifier, an output circuit, a buffer, or the like.

These means described above are not merely design matters, but a memory, an antenna, and wiring are arranged, a semiconductor device including a memory circuit using the arrangement is manufactured, a writing operation and a reading operation are performed, and the inventors have made a deep study. This is an invented matter.

According to the present invention, since a conductive layer having a large occupation area can be disposed in a region overlapping with the antenna, space can be used more effectively than in the case where nothing is disposed in a region overlapping with the antenna. Therefore, it is possible to reduce the size of the semiconductor device.

  In addition, by arranging the memory circuit portion and the coiled antenna portion in a stacked manner, it is possible to prevent a current from flowing through a conductive layer having a large occupied area included in the memory circuit portion, thereby reducing power consumption. Can be planned.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.
(Embodiment 1)

  The semiconductor device of the present invention includes a semiconductor circuit unit 11, a memory circuit unit 12, and a coiled antenna unit 13. The memory circuit unit 12 includes a plurality of memory elements. Each of the plurality of memory elements has a structure in which a layer containing an organic compound is sandwiched between a pair of electrodes. One or both of the pair of electrodes included in the plurality of memory elements are used in common by the plurality of memory elements. Therefore, one of the pair of electrodes included in the plurality of memory elements becomes a conductive layer having a large occupied area. Therefore, in the present invention, the memory circuit unit 12 and the coiled antenna unit 13 are overlapped with each other in order to prevent a current from flowing into the conductive layer included in the memory circuit unit 12 due to the influence of electromagnetic induction. To place.

  The top structure of the semiconductor device of the present invention will be described. In the following description, a semiconductor circuit portion, a memory circuit portion, and a coiled antenna portion are included, and the description is made in comparison with a semiconductor device (see FIG. 1C) in which the memory circuit portion and the coiled antenna portion do not overlap. To do. FIG. 1C is a comparative example and is not the present invention. A semiconductor device illustrated in FIG. 1C includes a semiconductor circuit portion 1201, a memory circuit portion 1202, and an antenna portion 1203. Note that the first terminal of the semiconductor circuit portion 1201 is electrically connected to one end of the coiled antenna portion 1203, and the second terminal of the semiconductor circuit portion 1201 is the other end of the coiled antenna portion 1203. It is electrically connected to the end of the. In addition, the semiconductor circuit portion 1201 and the memory circuit portion 1202 are electrically connected.

  In the case where the memory circuit portion 12 occupies the same area as the configuration in FIG. 1C and the memory circuit portion 12 and the coiled antenna portion 13 overlap with each other (see FIG. 1A). The area occupied by the semiconductor circuit unit 11 can be increased. If the area occupied by the semiconductor circuit portion 11 can be increased, a plurality of elements can be provided, so that a highly functional circuit can be provided. In addition, although the coil-shaped antenna part 13 shown to FIG. 1 (A) showed the example in which a winding number exceeds five turns, it is not specifically limited, What is necessary is just two or more turns. Note that the first terminal of the semiconductor circuit unit 11 is electrically connected to one end of the coiled antenna unit 13, and the second terminal of the semiconductor circuit unit 11 is the other end of the coiled antenna unit 13. It is electrically connected to the end of the. Further, the semiconductor circuit unit 11 and the memory circuit unit 12 are electrically connected.

  In the case where the semiconductor circuit portion 11 has the same area as the configuration in FIG. 1C and is arranged so that the memory circuit portion 12 and the coiled antenna portion 13 overlap (see FIG. 1B). The area occupied by the memory circuit unit 12 can be increased. If the area occupied by the memory circuit portion 12 can be increased, a plurality of elements can be provided, so that a circuit having a large memory capacity can be provided. Also in FIG. 1B, the first terminal of the semiconductor circuit unit 11 is electrically connected to one end of the coiled antenna unit 13, and the second terminal of the semiconductor circuit unit 11 is coiled. The other end of the antenna unit 13 is electrically connected. Further, the semiconductor circuit unit 11 and the memory circuit unit 12 are electrically connected.

  Next, a cross-sectional structure of the semiconductor device having the above structure will be described (see FIG. 2). The cross-sectional structure illustrated in FIG. 2 is a diagram illustrating a cross-sectional structure from point A to point B of the top surface structure of the semiconductor device in FIG.

  The semiconductor device of the present invention includes a base insulating layer 101 over a substrate 100 having an insulating surface, thin film transistors 102 to 105 provided over the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 to 105, and insulation. Wirings 107 to 114 are connected to the sources or drains of the thin film transistors 102 to 105 through openings provided in the layer 106.

  Further, the insulating layer 115 covering the wirings 107 to 114, the conductive layers 116 and 117 connected to the wirings 112 and 114 through the openings provided in the insulating layer 115, and the insulating layer covering the conductive layers 116 and 117 118, layers 119 and 120 including an organic compound connected to the conductive layers 116 and 117, and a conductive layer 121 connected to the layers 119 and 120 including the organic compound through an opening provided in the insulating layer 118. Have In addition, the semiconductor device includes an insulating layer 123 that covers the conductive layer 121, conductive layers 124 to 128 provided over the insulating layer 123, and an insulating layer 129 that covers the conductive layers 124 to 128.

  In the cross-sectional structure, the portion including the thin film transistors 102 and 103 corresponds to the semiconductor circuit portion 11. A stacked body of the conductive layer 116, the layer 119 containing an organic compound, and the conductive layer 121 corresponds to the memory element 130. A stacked body of the conductive layer 117, the layer 120 containing an organic compound, and the conductive layer 121 corresponds to the memory element 131. A circuit including the memory elements 130 and 131 corresponds to the memory circuit unit 12. The conductive layers 124 to 128 correspond to the coiled antenna unit 13.

  As in the above structure, the conductive layer 121 included in the memory circuit unit 12 having a large occupied area and the conductive layers 124 to 128 included in the coiled antenna unit 13 are arranged so as to be conductive due to the influence of electromagnetic induction. It is possible to prevent current from flowing through the layer 121. Further, the memory circuit portion 12 and the coiled antenna portion 13 are stacked and arranged, so that downsizing can be realized.

  Next, a cross-sectional structure of a semiconductor device having a structure different from the above is described (see FIG. 3). The semiconductor device includes a substrate 100 having an insulating surface, a base insulating layer 101, thin film transistors 102 and 103 provided over the insulating layer 101, an insulating layer 106 covering the thin film transistors 102 and 103, and an insulating layer 106. Wirings 107 to 110 connected to the sources or drains of the thin film transistors 102 and 103 are provided through the provided openings.

  Further, the insulating layer 115 covering the wirings 107 to 110, the conductive layer 145 connected to the wiring 110 through the opening provided in the insulating layer 115, the insulating layer 118 covering the conductive layer 145, and the insulating layer 118 The layers 147 to 150 including an organic compound connected to the conductive layer 145 and the conductive layers 146 connected to the layers 147 to 150 including the organic compound are provided through an opening provided in the conductive layer 145. In addition, the insulating layer 123 covering the conductive layer 146, conductive layers 124 to 128 provided over the insulating layer 123, and the insulating layer 129 covering the conductive layers 124 to 128 are provided. A stacked body of the conductive layer 145, any one of the layers 147 to 150 containing an organic compound, and the conductive layer 146 corresponds to the memory elements 141 to 144.

  As in the above-described structure, the conductive layers 145 and 146 included in the memory circuit portion 12 having a large occupied area and the conductive layers 124 to 128 included in the coiled antenna portion 13 are arranged so as to be affected by electromagnetic induction. Thus, current can be prevented from flowing through the conductive layer 121. Further, the memory circuit portion 12 and the coiled antenna portion 13 are stacked and arranged, so that downsizing can be realized.

(Embodiment 2)
In this embodiment, an example of a semiconductor device including the memory device described in Embodiment 1 will be described with reference to more detailed drawings. A top view of the semiconductor device of this embodiment is illustrated in FIG. 8A, and a cross-sectional view taken along line XY in FIG. 8A is illustrated in FIG. 8B.

As shown in FIG. 8A, a memory element portion 404 which is a memory device having a memory element, an integrated circuit portion 421, and an antenna 431 are formed over a substrate 400. 8A and 8B show a state in which a memory element portion, a circuit portion, and an antenna are formed over a substrate 400 that can withstand the manufacturing conditions in the middle of the manufacturing process. Known materials and manufacturing steps may be used for the memory device.

  A transistor 441 is provided in the memory element portion 404 and a transistor 442 is provided in the integrated circuit portion 421 with a separation layer 452 and an insulating layer 453 provided over a substrate 400. A 50 nm to 200 nm tungsten film is used as the separation layer 452, and a silicon oxide film is used as the insulating layer 453. However, the peeling layer is not limited to the tungsten film, and a Mo film, an amorphous silicon film, or the like may be used. An insulating layer 451, an insulating layer 454, and an insulating layer 455 are formed over the transistors 441 and 442. From the stack of the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 over the insulating layer 455. A memory element 443 is formed. The organic compound layers 458 are individually separated by an insulating layer 460b functioning as a partition wall. The first conductive layer 457 d is connected to the wiring layer of the transistor 441, and the memory element 443 is electrically connected to the transistor 441.

  An opening (also referred to as a contact hole) is formed in the insulating layer 455 so that the first conductive layer 457d and the transistor 441, the conductive layer 457c and the wiring layer 456a, and the conductive layer 457e and the wiring layer 456b are connected to each other. When the opening is increased and the contact area between the conductive layers is increased, the resistance becomes lower. Therefore, in this embodiment, the opening where the first conductive layer 457d and the transistor 441 are connected is the smallest, and the next However, the openings are set in order so that the opening connecting the conductive layer 457c and the wiring layer 456a and the opening connecting the conductive layer 457e and the wiring layer 456b are the largest. In this embodiment, an opening connecting the first conductive layer 457d and the transistor 441 is 5 μm × 5 μm, an opening connecting the conductive layer 457c and the wiring layer 456a is 50 μm × 50 μm, and the conductive layer 457e and the wiring layer 456b are connected. The opening for connecting is set to 500 μm × 500 μm.

  In the semiconductor device in FIG. 8B, the second conductive layer 459 is stacked and electrically connected to the wiring layer 456a and the conductive layer 457c. The second conductive layer 459 has an electrode area larger than that of the first conductive layer 457d. In the present invention, the second conductive layer 459 is disposed so that the second conductive layer 459 and the antenna 431 overlap with each other.

An insulating layer 461 is formed over the insulating layer 455. Over the insulating layer 461, a conductive layer 457a and an antenna 431a, a conductive layer 457b and an antenna 431b, a conductive layer 457e and an antenna 431c, and a conductive layer 457f and an antenna 431d are stacked. The conductive layer 457 e is formed in contact with the wiring layer 462 through an opening reaching the wiring layer 462 formed in the insulating layer 461. The wiring layer 462 is formed in contact with the wiring layer 456b through an opening reaching the wiring layer 456b formed in the insulating layer 455. In this specification, a connection portion between the antenna and a wiring layer below the antenna is referred to as an antenna power feeding unit. Here, the antenna, the memory element portion 404, and the integrated circuit portion 421 are electrically connected using the wiring layer 462 and the wiring layer 456b. However, the connection is not particularly limited, and the antennas 431c and 456b are electrically connected. It is sufficient to make a structure that connects them.

The conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f below the antenna 431a, the antenna 431b, and the antennas 431c and 431d provide adhesion between the insulating layer 455 and the antenna 431a, the antenna 431b, the antenna 431c, and 431d. There is also an effect to improve. In this embodiment, polyimide films are used for the insulating layers 455 and 461, titanium films are used for the conductive layers 457a, 457b, conductive layers 457e, and 457f, and the antennas 431a, 431b, and 431c are used. , And 431d are aluminum films.

  In the integrated circuit portion 421, the insulating layer 460c is partially formed, and the transistor 442 includes a region not covered with the insulating layer 460c and a region covered with the insulating layer 460c.

  Here, FIG. 9 shows a block diagram of a circuit of the semiconductor device in this embodiment. The block diagram of the semiconductor device in FIG. 9A includes an RF input portion 401, a logic circuit portion 402, an external input portion 403, a memory element portion 404, an adjustment circuit portion 405, a diode 406, and a resistor 407. Note that the integrated circuit portion 421 illustrated in FIG. 8A corresponds to the RF input portion 401, the logic circuit portion 402, the external input portion 403, the adjustment circuit portion 405, the diode 406, or the resistor 407 in FIG. To do.

  The voltage and signal input from the external input terminal are input to the memory element portion 404, and data (information) is written to the memory element portion 404. In the RF input unit 401, an AC signal is received by an antenna and a signal and a voltage are input to the logic circuit unit 402. The signal becomes a control signal via the logic circuit portion 402, and the data written from the memory element portion 404 is read again when the control signal is input to the memory element portion 404.

  FIG. 9B illustrates an example in which the structure of the semiconductor device in FIG. 9A is different from that of the adjustment circuit portion 405. The adjustment circuit portion 405 includes a resistor, and the adjustment circuit portion 415 includes a switch. The block diagram in FIG. 9B includes an RF input portion 411, a logic circuit portion 412, an external input portion 413, a memory element portion 414, an adjustment circuit portion 415, a diode 416, and a resistor 417. Note that the integrated circuit portion 421 illustrated in FIG. 8A corresponds to the RF input portion 411, the logic circuit portion 412, the external input portion 413, the adjustment circuit portion 415, the diode 416, or the resistor 417 in FIG. 9B. To do.

The resistors 407 and 417 are pull-up circuits and function as an adjustment circuit unit. The adjustment circuit unit 405 performs adjustment so that unnecessary control signals are not input to the storage element unit 404 from the logic circuit unit 402 when data is written to the storage element unit 404. Similarly, the resistor 407 is also adjusted so that no signal is input from the logic circuit portion 402 to the memory element portion 404 when data is written to the memory element portion 404. When writing data to the storage element unit 404, the signal from the external input unit 403 is cut off by the diode 406, but when reading data from the storage element unit 404, VDDH of the storage element unit 404 is set from the RF input unit 401. Fix to the applied VDD and stabilize. Although described based on the block diagram of FIG. 9A, the same applies to FIG. 9B.

  Further, the antenna electrically connected to the RF input portions 401 and 411 is provided so as to overlap with the memory device having the memory element portion. Further, the entire surface of the electrodes of the memory device may be overlapped, or a part of the electrodes may be overlapped. When the antenna unit and the storage device overlap each other, it is possible to reduce the malfunction of the semiconductor device due to the influence of noise or the like on the signal when the antenna communicates or fluctuation of electromotive force generated by electromagnetic induction. This is possible and improves reliability. Further, power saving of the semiconductor device can be realized. In addition, the semiconductor device can be reduced in size.

  Since the memory element 443 including the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 described in this embodiment has high adhesion, the substrate 400 which is a first substrate (glass substrate) is used. Defects such as film peeling do not occur at the layer interface due to the force applied in the process of being transferred to the second substrate after being formed. Therefore, after the memory element is peeled in a favorable shape, the memory element is transferred onto paper or a plastic substrate, so that a lightweight and flexible memory device or a lightweight and flexible semiconductor device can be manufactured.

  Since the memory device including the memory element manufactured in this embodiment has favorable adhesion, the peeling process and the transfer process can be performed in a favorable state. Therefore, since it can be freely transferred onto various substrates, the range of selectivity of the substrate material is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a memory device and a semiconductor device can be manufactured at low cost.

  According to the present invention, a memory device having a memory element with good adhesion that can perform a transfer process in a favorable state can be manufactured. Therefore, a highly reliable memory device and a semiconductor device including the memory device can be manufactured with high yield without complicating the device and the process.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  A structure of a memory circuit portion included in the semiconductor device of the present invention will be described (see FIGS. 4 and 5).

  The memory circuit portion includes a memory cell array 202 including a plurality of bit lines B1 to Bm (m is a natural number), a plurality of word lines W1 to Wn (n is a natural number), and a plurality of memory cells 201. In addition, it includes a decoder 203 that controls a plurality of bit lines B1 to Bm, a decoder 204 that controls a plurality of word lines W1 to Wn, a selector 205, and a read / write circuit 206.

  The configuration of the memory cell array 202 includes an active matrix type and a passive matrix type. When the memory cell array 202 is an active matrix type, the memory cell 201 includes a transistor 215 and a memory element 207 (see FIG. 4). The gate of the transistor 215 is electrically connected to the word line Wb (1 ≦ b ≦ n), and one of the source and the drain of the transistor 215 is electrically connected to the bit line Ba (1 ≦ a ≦ m). The other of the source and the drain is electrically connected to one of a pair of electrodes included in the memory element 207.

  When the memory cell array 202 is a passive matrix type, the memory cell 201 includes a memory element 207 provided at a location where the bit line Ba and the word line Wb intersect (see FIG. 5).

  Next, an operation when data is written to the memory circuit portion is described.

  First, the case where data is written to the memory circuit portion by an electrical action will be described. First, the memory cell 201 is selected by the decoder 203, the decoder 204, and the selector 205. Next, data is written into the selected memory cell 201 by the read / write circuit 206. Specifically, data is written by applying a predetermined voltage to the memory element included in the selected memory cell 201 by the read / write circuit 206. When a predetermined voltage is applied, the resistance value of the memory element changes. The resistance value of the memory element may change depending on whether the resistance value is large or the resistance value is small. Either of these phenomena may be used for data writing. The phenomenon in which the resistance value increases is a phenomenon in which a predetermined voltage is applied to the memory element to increase the resistance of the layer containing the organic compound between the pair of electrodes. The phenomenon that the resistance value decreases is a phenomenon in which a predetermined voltage is applied to the memory element to shorten the distance between the pair of electrodes. In this manner, the memory circuit portion writes data by utilizing the change in resistance value of the memory element due to electrical action. For example, if the memory element in the initial state is “0” data, an electrical action is applied to the memory element to which data “1” is written.

  Next, a case where data is written by optical action will be described. In this case, light is applied to the layer containing the organic compound from the light-transmitting conductive layer side by an optical irradiation device (for example, a laser irradiation device). Then, data is written into the memory element irradiated with light. When the light is irradiated, the resistance value of the memory element changes. The change in the resistance value of the memory element includes a case where the resistance value increases and a case where the resistance value decreases. Either of these phenomena may be used for data writing. As described above, the memory circuit portion writes data by utilizing the change in the resistance value of the memory element due to an optical action. For example, when the storage element in the initial state is “0” data, an optical action is applied to the storage element to which data “1” is written.

  Next, an operation when data is read from the memory circuit portion is described.

  Data reading is performed by electrical action regardless of the data writing method. Data is read by reading the difference in resistance value of the memory element by the decoders 203 and 204, the selector 205, and the read / write circuit 206.

  Note that an element having a rectifying property may be provided between one of the pair of conductive layers included in the memory element and the layer including the organic compound. The element having a rectifying property is a transistor, a diode, or the like in which a gate and a drain are electrically connected to each other. When a rectifying element is provided, the direction of current flow can be limited, so that the accuracy of data reading can be improved.

  Next, materials used for the layer containing an organic compound included in the memory element will be described.

  In the case where data is written to the memory element by an electric action, a low molecular material, a high molecular material, a singlet material, a triplet material, or the like is preferably used for the layer containing an organic compound. For the layer containing an organic compound, a material containing not only an organic compound material but also an inorganic compound may be used. The layer containing an organic compound may be a hole injection layer, a hole transport layer, a hole blocking layer, a light emitting layer, an electron transport layer, an electron injection layer, or the like, but may be used as a single layer, A plurality of layers may be stacked. Note that the layer containing an organic compound is preferably formed by a droplet discharge method typified by an inkjet method. By using the droplet discharge method, it is possible to improve the utilization efficiency of materials, shorten the manufacturing time by simplifying the manufacturing process, and reduce manufacturing costs.

  In the case where data is written to the memory circuit portion by an optical action, a material whose properties are changed by an optical action may be used for the layer containing an organic compound. For example, a conjugated polymer doped with a compound that generates acid by absorbing light (a photoacid generator) may be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylene, or the like may be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF6 salts and the like may be used.

  Further, the memory device included in the semiconductor device of the present invention may be non-volatile and may allow additional data writing. In addition, the memory device included in the semiconductor device of the present invention may be capable of rewriting data by an external electric action.

In this embodiment, the antenna area size is about 9 mm × 11 mm, the number of turns of the antenna is 9, the line width of the antenna itself is 150 μm, and the antenna wiring is wound at an interval of 10 μm. Thus, one electrode of the memory circuit portion, that is, the upper electrode is arranged so as to overlap with the antenna wound in a coil shape. The upper electrode is provided above the layer containing an organic compound and serves as an electrode common to a plurality of memory elements. When a memory circuit having an information amount of 1 kilobit is configured, the area size of the upper electrode may be about 1.5 mm × 3 mm. The area size of the upper electrode is not particularly limited and can be smaller than 4.5 mm ² .

By arranging the antenna and the conductive layer (upper electrode: 4.5 mm ² ) having a large occupation area so as to overlap each other, a space can be used more effectively than when nothing is arranged in a region overlapping with the antenna. Therefore, it is possible to reduce the size of the semiconductor device.

  Further, by stacking and arranging the upper electrode having a large occupied area and the coiled antenna portion, it is possible to prevent a current from flowing to the upper electrode included in the memory circuit portion and to save power. be able to.

  This embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

A structure of a semiconductor circuit portion included in the semiconductor device of the present invention will be described (see FIG. 6).

  The semiconductor circuit portion includes an analog circuit 551 and a digital circuit 552. The analog circuit 551 includes a resonance capacitor 501, a band filter 502, a power supply circuit 503 including a rectifier circuit and a storage capacitor, a demodulation circuit 504, a modulation circuit 505, and the like. The digital circuit 552 includes a code extraction circuit 506, a clock generation circuit 507, a cyclic redundancy check circuit 508, a control circuit 509, a storage circuit 510, and the like.

  An operation when the semiconductor device receives data will be described. A radio signal (modulated carrier wave) input from the coiled antenna is input to the analog circuit 551 from the terminal 221a. A desired frequency component is extracted from the input radio signal by the band filter 502 and input to the power supply circuit 503 and the demodulation circuit 504. The modulated carrier wave input through the band-pass filter 502 is rectified by a rectifier circuit included in the power supply circuit 503 and further smoothed by a storage capacitor included in the power supply circuit 503. Thus, the power supply circuit 503 generates a DC voltage. The DC voltage generated in the power supply circuit 503 is supplied to each circuit as a power supply voltage.

  The modulated carrier wave input through the band filter 502 is input to the clock generation circuit 507 in the digital circuit 552. The clock generated by the clock generation circuit 507 is supplied to each circuit. The modulated carrier wave input through the band filter 502 is demodulated by the demodulation circuit 504, and the demodulated signal is input to the digital circuit 552. A signal obtained by demodulating the modulated carrier wave by the demodulation circuit 504 is input to the code extraction circuit 506, and a code included in the signal is extracted. The output of the code extraction circuit 506 is input to the control circuit 509, and the code is extracted. The extracted code is input to the cyclic redundancy check circuit 508, and arithmetic processing for identifying a transmission error is performed. In this way, the cyclic redundancy check circuit 508 outputs to the control circuit 509 whether there is an error in the received data.

  Next, an operation when the semiconductor device transmits data will be described. The storage circuit 510 outputs the stored unique identifier (UID) to the control circuit 509 in response to a signal input from the control circuit 509. The cyclic redundancy check circuit 508 calculates a CRC code corresponding to the transmission data and outputs it to the control circuit 509. The control circuit 509 adds a CRC code to the transmission data. In addition, the control circuit 509 encodes data in which a CRC code is added to transmission data. Further, the control circuit 509 converts the encoded information into a signal for modulating the carrier wave in accordance with a predetermined modulation method. The output of the control circuit 509 is input to the modulation circuit 505 of the analog circuit 551. The modulation circuit 505 load-modulates the carrier wave in accordance with the input signal and outputs it to the coiled antenna unit.

  This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment 1.

In this embodiment, an application of the semiconductor device of the present invention will be described. The semiconductor device of the present invention includes, for example, banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc.), packaging containers (wrapping paper, bottles, etc.), DVD (Digital Versatile Disc). It can be used in recording media such as video tapes, vehicles such as cars and bicycles, personal items such as bags and glasses, foods, clothing, daily necessities, electronic devices and the like. Electronic devices refer to liquid crystal display devices, EL (electroluminescence) display devices, television devices, mobile phones, and the like.

  The semiconductor device of the present invention can be fixed to an article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing semiconductor devices for banknotes, coins, securities, bearer bonds, certificates, and the like. Further, by providing semiconductor devices in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. Further, forgery or theft can be prevented by providing a semiconductor device in the vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a semiconductor device in a living creature such as livestock, it becomes possible to easily identify the year of birth, sex, type, or the like. As described above, the semiconductor device of the present invention can be provided and used for any article (including a living thing).

  Next, one mode of a system using a semiconductor device is described with reference to FIGS. A terminal 9520 including the display portion 9521 is provided with an antenna and a reader / writer connected to the antenna. The article 9532 is provided with the semiconductor device 9531 of the present invention, and the article 9522 is provided with the semiconductor device 9523 of the present invention. When the antenna of the terminal 9520 is held over the semiconductor device 9531 included in the article 9532, information on the product such as the raw material and the place of origin of the article 9532, the inspection result for each production process, the history of the distribution process, and the description of the product is displayed on the display portion 9521. The When the antenna of the terminal 9520 is held over the semiconductor device 9523 included in the article 9522, information on the product such as the raw material and the place of origin of the article 9522, the inspection result for each production process, the history of the distribution process, and the description of the product is displayed on the display portion 9521. The

  This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 1, or Example 2.

FIG. 5A illustrates a structure of a semiconductor device of the present invention. FIG. 5B illustrates a structure of a semiconductor device of the invention. (C) The figure explaining a comparative example. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. FIG. 14 is a cross-sectional view illustrating a structure of a semiconductor device of the invention. FIG. 10 is a circuit diagram illustrating a structure of a semiconductor device of the invention. 6A and 6B illustrate a structure of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Semiconductor circuit part 12 Memory circuit part 13 Coiled antenna part 100 Substrate 101 Insulating layers 102-105 Thin film transistor 106 Insulating layers 107-114 Wiring 115 Insulating layer 116 Conductive layer 117 Conductive layer 118 Insulating layer 119 Layer 120 containing an organic compound Organic Layer 121 containing a compound Conductive layer 123 Insulating layer 124-128 Conductive layer 129 Insulating layer 130 Memory element 131 Memory element 141-144 Memory element 145 Conductive layer 146 Conductive layer 147-149 Layer 150 containing an organic compound Layer 201 containing an organic compound Memory cell 202 Memory cell array 203 Decoder 204 Decoder 205 Selector 206 Read / write circuit 207 Memory element 210 Organic compound layer 215 Transistor 221a Terminal 301 Semiconductor device 302 Coiled antenna section 303 Conductor circuit section 304 Terminal 305 One end 306 Terminal 307 Other end 400 Substrate 401 RF input section 402 Logic circuit section 403 External input section 404 Storage element section 405 Adjustment circuit section 406 Diode 407 Resistor 411 RF input section 412 Logic circuit section 413 External input section 414 Memory element portion 415 Adjustment circuit portion 416 Diode 417 Resistor 421 Integrated circuit portion 431 Antenna 431a Antenna 431b Antenna 431c Antenna 431d Antenna 441 Transistor 442 Transistor 443 Memory element 451 Insulating layer 452 Separating layer 453 Insulating layer 454 Insulating layer 455 Insulating layer 456a Wiring Layer 456b wiring layer 457a conductive layer 457b conductive layer 457c conductive layer 457d first conductive layer 457e conductive layer 457f conductive layer 458 organic compound layer 459 second conductive 460a Insulating layer 460b Insulating layer 460c Insulating layer 461 Insulating layer 462 Wiring layer 501 Resonant capacitance 502 Filter 503 Power supply circuit 504 Demodulating circuit 505 Modulating circuit 506 Extracting circuit 507 Generating circuit 508 Cyclic redundancy checking circuit 509 Control circuit 510 Storage circuit 551 Analog circuit 552 Digital circuit 1201 Semiconductor circuit portion 1202 Memory circuit portion 1203 Antenna portion 9520 Terminal 9521 Display portion 9522 Article 9523 Semiconductor device 9531 Semiconductor device 9532 Article

Claims (9)

On a substrate having an insulating surface, an integrated circuit, an antenna mainly having a spiral shape, and an element,
The element includes a first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode,
The antenna is electrically connected to the integrated circuit;
The first electrode or the second electrode is electrically connected to the integrated circuit;
The semiconductor device is characterized in that the antenna overlaps with the second electrode. On a substrate having an insulating surface, an integrated circuit, a transistor, an antenna mainly having a spiral shape, and an element,
The element includes a first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode,
The antenna is electrically connected to the integrated circuit;
The first electrode or the second electrode is electrically connected to the integrated circuit;
The transistor is electrically connected to the first electrode;
The semiconductor device is characterized in that the antenna overlaps with the second electrode and the transistor. 3. The semiconductor device according to claim 2, wherein the transistor is a thin film transistor. On a substrate having an insulating surface, a control circuit, an antenna mainly having a spiral shape, and an element,
The element includes a first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode,
The first electrode or the second electrode is electrically connected to the control circuit;
The semiconductor device is characterized in that the antenna overlaps with the second electrode. On a substrate having an insulating surface, an analog circuit, a digital circuit, and an antenna mainly having a spiral shape are provided.
The digital circuit includes an element having a first electrode, a second electrode, and a layer containing an organic compound between the first electrode and the second electrode,
The digital circuit is electrically connected to the analog circuit;
The semiconductor device is characterized in that the antenna overlaps with the second electrode. 6. The semiconductor device according to claim 1, wherein the element is a memory element. 7. The antenna according to claim 1, wherein the antenna includes a feeding portion and a plurality of linear or strip antenna conductors, and the antenna conductor is provided in a spiral shape from the periphery of the feeding portion toward the feeding portion. A semiconductor device. 7. The semiconductor device according to claim 1, wherein the antenna includes a feeding portion and a plurality of linear or strip antenna conductors, and the antenna conductors are elliptical or circular. 9. The semiconductor device according to claim 1, wherein the substrate having an insulating surface is glass, plastic, or paper.

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