JP2001101368A - Integrated semiconductor device - Google Patents
Integrated semiconductor deviceInfo
- Publication number
- JP2001101368A JP2001101368A JP28116699A JP28116699A JP2001101368A JP 2001101368 A JP2001101368 A JP 2001101368A JP 28116699 A JP28116699 A JP 28116699A JP 28116699 A JP28116699 A JP 28116699A JP 2001101368 A JP2001101368 A JP 2001101368A
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- Japan
- Prior art keywords
- semiconductor device
- integrated semiconductor
- insulating layer
- memory
- conductor layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、集積半導体装置に
関し、特に、非接触型メモリ装置として用いられる集積
半導体装置に関する。The present invention relates to an integrated semiconductor device, and more particularly, to an integrated semiconductor device used as a non-contact type memory device.
【０００２】[0002]
【従来の技術】一般に、非接触型のＩＣメモリ装置とし
て、外部から電磁波のエネルギーを受けて、装置内部の
半導体素子を駆動させて、これによって、半導体素子に
記録された情報を電波によって外部に送り、専用の受信
機で読み出すようにしたＩＣメモリ装置が知られてい
る。そして、この種のＩＣメモリ装置では、専用の送信
機を用いて装置内部の半導体素子に記録された情報を変
更して書き換えることができる。2. Description of the Related Art In general, as a non-contact type IC memory device, a semiconductor element inside the device is driven by receiving electromagnetic wave energy from the outside, whereby information recorded in the semiconductor element is transmitted to the outside by radio waves. 2. Description of the Related Art There is known an IC memory device in which data is sent and read by a dedicated receiver. In this type of IC memory device, information recorded in a semiconductor element inside the device can be changed and rewritten using a dedicated transmitter.
【０００３】従来の非接触型ＩＣメモリ装置は、外部コ
イル又はコンデンサからなるアンテナ装置と集積半導体
装置とを備えており、集積半導体装置には電源部及び半
導体素子からなるメモリ部が備えられている。そして、
この非接触型ＩＣメモリ装置では、アンテナ装置と集積
半導体装置とはワイヤーボンディング等の手法を用いて
電気的に接続されている。A conventional non-contact type IC memory device includes an antenna device including an external coil or a capacitor and an integrated semiconductor device. The integrated semiconductor device includes a power supply unit and a memory unit including a semiconductor element. . And
In this non-contact type IC memory device, the antenna device and the integrated semiconductor device are electrically connected by using a method such as wire bonding.
【０００４】上記の非接触型ＩＣメモリでは、アンテナ
装置で外部からの電磁波のエネルギーを受け、電源部
（インターフェース回路）で半導体素子駆動電圧に変換
し、これによって、メモリ部を駆動するようにしてい
る。In the above-mentioned non-contact type IC memory, an antenna device receives energy of an external electromagnetic wave and converts it into a semiconductor element driving voltage by a power supply unit (interface circuit), thereby driving the memory unit. I have.
【０００５】具体的には、図３に示すように、従来の非
接触型ＩＣメモリ装置は集積半導体装置２０を備えてお
り、集積半導体装置２０の内部にはメモリ部（メモリロ
ジック回路）及びインターフェース回路（ともに図示せ
ず）を備えられている。そして、インターフェース回路
から外部接続端子２０ａ及び２０ｂが装置外部に引き出
されている。つまり、集積半導体装置２０には外部接続
端子２０ａ及び２０ｂが備えられている。これら外部接
続端子２０ａ及び２０ｂにはコイル２１がワイヤーボン
ディング等の手法で接続され、コイル２１に並列にコン
デンサ２２が接続されて、コイル２１及び２２によっ
て、アンテナ装置が構成されている。このように、従来
の非接触型ＩＣメモリ装置２０では、メモリロジック回
路及びインターフェース回路を備える集積半導体装置２
０とアンテナ装置とを電気的に接続している。More specifically, as shown in FIG. 3, a conventional non-contact type IC memory device includes an integrated semiconductor device 20, and a memory section (memory logic circuit) and an interface are provided inside the integrated semiconductor device 20. A circuit (both not shown) is provided. The external connection terminals 20a and 20b are led out of the device from the interface circuit. That is, the integrated semiconductor device 20 includes the external connection terminals 20a and 20b. A coil 21 is connected to these external connection terminals 20a and 20b by a method such as wire bonding, and a capacitor 22 is connected in parallel with the coil 21. The coil 21 and 22 constitute an antenna device. As described above, in the conventional non-contact type IC memory device 20, the integrated semiconductor device 2 including the memory logic circuit and the interface circuit is provided.
0 and the antenna device are electrically connected.
【０００６】[0006]
【発明が解決しようとする課題】前述のように、従来の
非接触型ＩＣメモリ装置では、アンテナ装置と集積半導
体装置とを別に設けてワイヤーボンディング等の手法を
用いてこれら装置を電気的に接続している。つまり、従
来の非接触型ＩＣメモリ装置では、アンテナ装置が集積
半導体装置の外部に形成して、アンテナ装置と集積半導
体装置とを電気的に接続しており、このため、装置間の
接続部が劣化しやすく、耐環境性等の信頼性が劣るとい
う問題点がある。As described above, in a conventional non-contact type IC memory device, an antenna device and an integrated semiconductor device are separately provided, and these devices are electrically connected using a technique such as wire bonding. are doing. That is, in the conventional non-contact type IC memory device, the antenna device is formed outside the integrated semiconductor device, and the antenna device and the integrated semiconductor device are electrically connected to each other. There is a problem that it is easily deteriorated and its reliability such as environmental resistance is inferior.
【０００７】さらに、従来の非接触型ＩＣメモリ装置で
は、ワイヤーボンディング等の手法を用いてアンテナ装
置と集積半導体装置とを接続している関係上、部品点数
が多くなるばかりでなく製造工数が多くなり、その結
果、コストアップとなってしまうという問題点がある。Further, in the conventional non-contact type IC memory device, not only the number of parts is increased but also the number of manufacturing steps is increased due to the connection between the antenna device and the integrated semiconductor device using a method such as wire bonding. As a result, there is a problem that the cost is increased.
【０００８】本発明の目的は低コストで製造可能でかつ
高品質の非接触型ＩＣメモリ装置として用いられる集積
半導体装置を提供することにある。An object of the present invention is to provide an integrated semiconductor device which can be manufactured at low cost and is used as a high quality non-contact type IC memory device.
【０００９】[0009]
【課題を解決するための手段】本発明によれば、基板上
に形成され情報を記録するメモリ部を有し、該メモリ部
が非接触でアクセスされる集積半導体装置において、前
記基板上には電気容量素子及びコイル素子を備えるアン
テナ部が形成されており、該アンテナ部を介して前記メ
モリが非接触でアクセスされるようにしたことを特徴と
する集積半導体装置が得られる。According to the present invention, there is provided an integrated semiconductor device having a memory section formed on a substrate and recording information, wherein the memory section is accessed in a non-contact manner. An integrated semiconductor device is obtained in which an antenna unit including a capacitance element and a coil element is formed, and the memory is accessed in a non-contact manner via the antenna unit.
【００１０】この場合、前記基板上に前記メモリ部が形
成され、前記電気容量素子は前記メモリ部の上方に形成
され、前記電気容量素子と前記メモリ部との間には第１
の絶縁層が配置されており、前記電気容量素子はスルー
ホールを介して前記メモリ部に結合されている。なお、
前記第１の絶縁層は絶縁樹脂層、ケイ素酸素化合物絶縁
層、ケイ素窒素化合物絶縁層、及びケイ素酸素窒素化合
物絶縁層のいずれか一つであり、前記第１の絶縁層は前
記電気容量素子側の面が平坦化処理されている。In this case, the memory section is formed on the substrate, the capacitance element is formed above the memory section, and a first capacitance is provided between the capacitance element and the memory section.
And the electric capacitance element is coupled to the memory unit through a through hole. In addition,
The first insulating layer is any one of an insulating resin layer, a silicon-oxygen compound insulating layer, a silicon-nitrogen compound insulating layer, and a silicon-oxygen-nitrogen compound insulating layer, and the first insulating layer is provided on the side of the capacitance element. Has been flattened.
【００１１】例えば、前記電気容量素子はそれぞれ電極
層として用いられる第１及び第２の導体層を備えてお
り、前記コイル素子は前記第１及び前記第２の導体層間
に配設され前記第１及び前記第２の導体層に電気的に接
続された平面コイルである。そして、前記第１及び前記
第２の導体層の少なくとも一つは電気伝導性を有する強
磁性体で形成されている。For example, the capacitance element includes first and second conductor layers each used as an electrode layer, and the coil element is disposed between the first and second conductor layers and the first and second conductor layers are disposed between the first and second conductor layers. And a planar coil electrically connected to the second conductor layer. At least one of the first and second conductor layers is formed of a ferromagnetic material having electrical conductivity.
【００１２】加えて、前記コイル素子と前記第１及び前
記第２の導体層との間には第２の絶縁層が配置されてお
り、前記コイル素子の巻き始め端及び巻き終り端はスル
ーホールを介してそれぞれ前記第１及び前記第２の導体
層に電気的に接続されており、前記基板を除いて他の部
分を絶縁保護層で封止するようにすることが望ましい。In addition, a second insulating layer is disposed between the coil element and the first and second conductor layers, and a winding start end and a winding end end of the coil element are formed through holes. It is preferable that the semiconductor device is electrically connected to the first and second conductor layers via a via hole, respectively, and that other portions except the substrate are sealed with an insulating protective layer.
【００１３】[0013]
【発明の実施の形態】以下に本発明について図面を参照
して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【００１４】まず、図１を参照して、通常の手法を用い
て、シリコン基板１上に複数のＭＯＳトランジスタ素子
２を形成する。その後、シリコン基板１上には電気絶縁
層３を形成し、電気絶縁層３上に導体層４を形成する。
この際、電気絶縁層３として、例えば、ＳｉＯ2 薄膜が
用いられ、導体層４として。例えば、アルミ薄膜が用い
られる。First, referring to FIG. 1, a plurality of MOS transistor elements 2 are formed on a silicon substrate 1 by using an ordinary method. After that, the electric insulating layer 3 is formed on the silicon substrate 1, and the conductor layer 4 is formed on the electric insulating layer 3.
At this time, for example, a SiO 2 thin film is used as the electric insulating layer 3 and the conductive layer 4 is used. For example, an aluminum thin film is used.
【００１５】導体層４上には電気絶縁層５（例えば、Ｓ
ｉＯ2 薄膜）が形成され、電気絶縁層５の予め定められ
た複数の位置において導体層４に達するスルーホールが
形成される。この際、電気絶縁層５には、電気絶縁樹脂
を用いて平坦化処理が施され、これによって、凹凸が平
坦化される。電気絶縁樹脂としては、例えば、ポリイミ
ド樹脂が用いられ、ポリイミド樹脂をスピンコート法に
よって電気絶縁層５に塗布して凹凸を平坦化する。その
後、電気絶縁層５上の所定のエリアには導体層６が形成
され、電気絶縁層５に形成されたスルーホールを用いて
導体層６は導体層４と電気的に接続される。この際、導
体層６として、例えば、強磁性を備えるＦｅＳｉ合金薄
膜が用いられる。なお、電気絶縁層５を平坦化処理する
際、ＳｉＯ2 膜を形成した後、ＣＭＰと呼ばれる高精度
薄膜研磨法を用いて平坦化処理を行うようにしてもよ
い。加えて、電気絶縁層３及び５は集合的に第１の絶縁
層と呼ばれ、第１の絶縁層は絶縁樹脂、ケイ素酸素化合
物、ケイ素窒素化合物、及びケイ素酸素窒素化合物のい
ずれか一つで形成するようにしてもよく、第１の絶縁層
の上面は平坦化処理される。On the conductor layer 4, an electric insulating layer 5 (for example, S
An iO 2 thin film is formed, and through holes reaching the conductor layer 4 are formed at a plurality of predetermined positions of the electric insulating layer 5. At this time, the electric insulating layer 5 is subjected to a flattening process using an electric insulating resin, whereby the unevenness is flattened. As the electric insulating resin, for example, a polyimide resin is used, and the unevenness is flattened by applying the polyimide resin to the electric insulating layer 5 by a spin coating method. Thereafter, a conductor layer 6 is formed in a predetermined area on the electric insulation layer 5, and the conductor layer 6 is electrically connected to the conductor layer 4 by using a through hole formed in the electric insulation layer 5. At this time, for example, an FeSi alloy thin film having ferromagnetism is used as the conductor layer 6. When the electrical insulating layer 5 is flattened, after the SiO 2 film is formed, the flattening process may be performed by using a high-precision thin film polishing method called CMP. In addition, the electrically insulating layers 3 and 5 are collectively called a first insulating layer, and the first insulating layer is made of one of an insulating resin, a silicon oxygen compound, a silicon nitrogen compound, and a silicon oxygen nitrogen compound. The upper surface of the first insulating layer may be planarized.
【００１６】さらに、導体層６上には電気絶縁層７（例
えば、ＳｉＯ2 薄膜）が形成され、電気絶縁層７の予め
定められた複数の位置において導体層６に達するスルー
ホールが形成される。その後、電気絶縁層７上には導体
層８が形成され、電気絶縁層７に形成されたスルーホー
ルを用いて導体層８は導体層６と電気的に接続される。
導体層８として、例えば、アルミ薄膜が用いられ、導体
層８は、電気絶縁層７上に渦巻き状に形成されており、
これによって、導体層８は同一平面上で渦巻きを描く形
状の平面コイルとして用いられる。Further, an electric insulating layer 7 (for example, a SiO 2 thin film) is formed on the conductive layer 6, and through holes reaching the conductive layer 6 are formed at a plurality of predetermined positions of the electric insulating layer 7. . After that, a conductor layer 8 is formed on the electric insulation layer 7, and the conductor layer 8 is electrically connected to the conductor layer 6 using through holes formed in the electric insulation layer 7.
As the conductor layer 8, for example, an aluminum thin film is used, and the conductor layer 8 is formed in a spiral shape on the electric insulating layer 7.
Thus, the conductor layer 8 is used as a planar coil having a shape that draws a spiral on the same plane.
【００１７】導体層８上には電気絶縁層９（例えば、Ｓ
ｉＯ2 薄膜）が形成され、電気絶縁層９の予め定められ
た複数の位置において導体層８に達するスルーホールが
形成される（電気絶縁層７及び９は集合的に第２の絶縁
層と呼ばれる）。その後、電気絶縁層９上には導体層１
０が形成され、この導体層１０は電気絶縁層５に形成さ
れたスルーホール及び電気絶縁層９に形成されたスルー
ホールを用いてそれぞれ導体層４及び導体層８と電気的
に接続される。この結果、平面コイル状の導体層８はそ
の両端部がスルーホールによって導体層６又は導体１０
に電気的接続されることになる。なお、導体層１０とし
て、例えば、強磁性を備えるＦｅＳｉ合金薄膜が用いら
れる。そして、最後に、導体層１０上にはシリコン基板
１を除いて全体を包み込むようにして電気絶縁層１１が
形成される。この電気絶縁層１１は湿度の進入を防止す
るとともにハンドリングの際に加わる機械的応力に対す
る保護層として用いられる。このため、電気絶縁保護層
１０には、例えば、ＳｉＮ薄膜が用いられる。On the conductor layer 8, an electric insulating layer 9 (for example, S
An iO 2 thin film is formed, and through holes reaching the conductor layer 8 are formed at a plurality of predetermined positions of the electric insulating layer 9. The electric insulating layers 7 and 9 are collectively called a second insulating layer. ). After that, the conductor layer 1 is formed on the electric insulating layer 9.
0 is formed, and the conductor layer 10 is electrically connected to the conductor layers 4 and 8 using the through holes formed in the electric insulation layer 5 and the through holes formed in the electric insulation layer 9, respectively. As a result, the conductor layer 8 in the form of a planar coil has the conductor layer 6 or the conductor 10
Will be electrically connected to the As the conductor layer 10, for example, an FeSi alloy thin film having ferromagnetism is used. Finally, an electric insulating layer 11 is formed on the conductor layer 10 so as to wrap the whole except for the silicon substrate 1. The electric insulating layer 11 is used as a protective layer for preventing the entry of humidity and for protecting against mechanical stress applied during handling. For this reason, for example, a SiN thin film is used for the electric insulation protection layer 10.
【００１８】上述の例では、導体層６及び導体層１０は
互いに対向する導体層面でコンデンサ（電気容量素子）
を形成しており、これによって、所望の電気容量値を得
ることができる。さらに、平面コイルを形成する導体層
８は、電気容量素子を形成する導体層６及び１０の間に
絶縁層７及び９を介して形成されていることがわかる。In the above-described example, the conductor layer 6 and the conductor layer 10 are provided with a capacitor (capacitance element) on the conductor layer surfaces facing each other.
Is formed, whereby a desired capacitance value can be obtained. Further, it can be seen that the conductor layer 8 forming the planar coil is formed between the conductor layers 6 and 10 forming the capacitance element with the insulating layers 7 and 9 interposed therebetween.
【００１９】このようにして、図１に示す集積半導体装
置では、その内部にコイル、コンデンサ、インタフェー
ス回路、及びメモリロジック回路が形成されることにな
る。Thus, in the integrated semiconductor device shown in FIG. 1, a coil, a capacitor, an interface circuit, and a memory logic circuit are formed therein.
【００２０】図２を参照して、図１に示すようにして構
成された集積半導体装置１２は非接触ＩＣメモリ装置と
して用いられ、その内部にコイル１３、コンデンサ１
４、インターフェース回路部１５、及びメモリ・ロジッ
ク回路部１６を備えており、コイル１３及びコンデンサ
１４によってアンテナ装置が構成されている。装置外部
から輻射される電磁波のエネルギー１７をアンテナ装置
で受けると、インターフェース回路部１５は電磁波エネ
ルギーを半導体素子の駆動電圧に変換して、半導体素子
（つまり、メモリロジック部）を駆動させる。さらに、
このインターフェース回路部１５は受信電波信号を記憶
情報書き換え信号に変換し、記憶情報を電波信号に変換
する。一方、メモリ・ロジック回路部１６は情報の記録
及び信号処理を行う。Referring to FIG. 2, integrated semiconductor device 12 constructed as shown in FIG. 1 is used as a non-contact IC memory device, and has coil 13 and capacitor 1 therein.
4, an interface circuit section 15, and a memory / logic circuit section 16. The coil 13 and the capacitor 14 constitute an antenna device. When the antenna device receives the energy 17 of the electromagnetic wave radiated from the outside of the device, the interface circuit unit 15 converts the electromagnetic wave energy into a driving voltage of the semiconductor device and drives the semiconductor device (that is, the memory logic unit). further,
The interface circuit unit 15 converts a received radio signal into a stored information rewriting signal, and converts the stored information into a radio signal. On the other hand, the memory / logic circuit section 16 performs recording of information and signal processing.
【００２１】図示の集積半導体装置１２ではその記録さ
れた情報を電波１８によって発信し、専用の送受信機１
９でこの電波を受けて記録情報を読み出す。一方、専用
の送受信機１９を用いて必要に応じてメモリ・ロジック
回路部１６に記録された記録情報を変更して書き換え
る。In the integrated semiconductor device 12 shown in the figure, the recorded information is transmitted by radio waves 18 and the dedicated transceiver 1 is used.
In step 9, the recording information is read out by receiving the radio wave. On the other hand, the recording information recorded in the memory / logic circuit section 16 is changed and rewritten as needed using the dedicated transceiver 19.
【００２２】前述の図３に示す従来例と比較すると、図
１及び図２に示す例では、コイルとコンデンサとからな
るアンテナ装置が装置内部に内蔵集積化されており、こ
の結果、装置寸法が極めて小さくなる。加えて、アンテ
ナ装置の接続が不要であるから、接続部が断線する等の
不具合が発生することがなく、耐環境性等の信頼性が向
上する。Compared to the conventional example shown in FIG. 3, in the examples shown in FIGS. 1 and 2, the antenna device composed of a coil and a capacitor is integrated inside the device, and as a result, the size of the device is reduced. Extremely small. In addition, since there is no need to connect the antenna device, problems such as disconnection of the connection portion do not occur, and reliability such as environmental resistance is improved.
【００２３】また、図示の例では、コンデンサが形成さ
れる絶縁層を平坦化処理しているので、高精度に所望の
電気容量を得ることができる。加えて、内部コンデンサ
と内部コイルとの接続部が少なく、内部コイルの所望の
インダクタンスを少ない巻き回数で得ることができ、そ
の結果、コイル部の抵抗分を低減し送受信アンテナの効
率を向上できる。In the illustrated example, the insulating layer on which the capacitor is formed is planarized, so that a desired electric capacitance can be obtained with high precision. In addition, the number of connection portions between the internal capacitor and the internal coil is small, and a desired inductance of the internal coil can be obtained with a small number of turns. As a result, the resistance of the coil portion can be reduced and the efficiency of the transmitting / receiving antenna can be improved.
【００２４】さらに、図示の例では、腐食し易い金属部
が全く外部に露出することがなく、その結果、耐腐食パ
ッケージ等による保護が不要となり、従来例と比較して
飛躍的に品質を高めることができる。Further, in the example shown in the figure, the easily corroded metal portion is not exposed to the outside at all, and as a result, protection by a corrosion-resistant package or the like becomes unnecessary, and the quality is dramatically improved as compared with the conventional example. be able to.
【００２５】なお、図示の例における構成材料は、単な
る一例であり、例えば、導体膜の材質の一例としてアル
ミを示したが、必要に応じて、不純物を含むシリコン、
銅、金、鉄、あるいは種々の合金などを用いてもよい。It should be noted that the constituent material in the illustrated example is merely an example. For example, aluminum is shown as an example of the material of the conductor film.
Copper, gold, iron, or various alloys may be used.
【００２６】[0026]
【発明の効果】以上説明したように、本発明では、非接
触型ＩＣメモリ装置として用いられる集積半導体装置を
小型で低コストにしかも高精度にできるばかりでなく、
品質を極めて高くできるという効果がある。As described above, according to the present invention, not only can an integrated semiconductor device used as a non-contact type IC memory device be made small, low-cost and high-precision,
There is an effect that the quality can be extremely high.
【図１】本発明による集積半導体装置の一例を模式的に
示す断面図である。FIG. 1 is a cross-sectional view schematically showing one example of an integrated semiconductor device according to the present invention.
【図２】図１に示す集積半導体装置の電気回路要素を模
式的に示す図である。FIG. 2 is a diagram schematically showing electric circuit elements of the integrated semiconductor device shown in FIG.
【図３】従来の非接触ＩＣメモリ装置の電気回路要素を
模式的に示す図である。FIG. 3 is a diagram schematically showing electric circuit elements of a conventional non-contact IC memory device.
１ シリコン基板 ２ ＭＯＳトランジスタ ３，５，７，９ 電気絶縁層 ４，６，８，１０ 導体層 １１ 電気絶縁保護層 １２，２０ 集積半導体装置 １３，２１ コイル １４，２２ 電気容量素子（コンデンサ） １５ インターフェース回路部 １６ メモリ・ロジック回路部 １７ 電磁波エネルギー １８ 記憶情報電波信号 １９ 記憶情報読み書き用送受信機 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 MOS transistor 3,5,7,9 Electrical insulating layer 4,6,8,10 Conductive layer 11 Electrical insulating protective layer 12,20 Integrated semiconductor device 13,21 Coil 14,22 Electric capacitance element (capacitor) 15 Interface circuit section 16 Memory / logic circuit section 17 Electromagnetic wave energy 18 Stored information radio signal 19 Stored information read / write transceiver
Claims (8)
部を有し、該メモリ部が非接触でアクセスされる集積半
導体装置において、前記基板上には電気容量素子及びコ
イル素子を備えるアンテナ部が形成されており、該アン
テナ部を介して前記メモリが非接触でアクセスされるよ
うにしたことを特徴とする集積半導体装置。1. An integrated semiconductor device having a memory portion formed on a substrate for recording information, wherein the memory portion is accessed in a non-contact manner, wherein the antenna portion includes a capacitance element and a coil element on the substrate. Wherein the memory is accessed in a non-contact manner via the antenna section.
おいて、前記基板上に前記メモリ部が形成され、前記電
気容量素子は前記メモリ部の上方に形成されていること
を特徴とする集積半導体装置。2. The integrated semiconductor device according to claim 1, wherein said memory portion is formed on said substrate, and said capacitance element is formed above said memory portion. apparatus.
おいて、前記電気容量素子と前記メモリ部との間には第
１の絶縁層が配置されており、前記電気容量素子はスル
ーホールを介して前記メモリ部に結合されていることを
特徴とする集積半導体装置。3. The integrated semiconductor device according to claim 2, wherein a first insulating layer is disposed between said electric capacitance element and said memory section, and said electric capacitance element is provided through a through hole. An integrated semiconductor device, wherein the integrated semiconductor device is coupled to the memory unit.
おいて、前記第１の絶縁層は絶縁樹脂層、ケイ素酸素化
合物絶縁層、ケイ素窒素化合物絶縁層、及びケイ素酸素
窒素化合物絶縁層のいずれか一つであり、前記第１の絶
縁層は前記電気容量素子側の面が平坦化処理されている
ことを特徴とする集積半導体装置。4. The integrated semiconductor device according to claim 3, wherein the first insulating layer is any one of an insulating resin layer, a silicon-oxygen compound insulating layer, a silicon-nitrogen compound insulating layer, and a silicon-oxygen-nitrogen compound insulating layer. An integrated semiconductor device, wherein a surface of the first insulating layer on a side of the capacitance element is subjected to flattening treatment.
れた集積半導体装置において、前記電気容量素子はそれ
ぞれ電極層として用いられる第１及び第２の導体層を備
えており、前記コイル素子は前記第１及び前記第２の導
体層間に配設され前記第１及び前記第２の導体層に電気
的に接続された平面コイルであることを特徴とする集積
半導体装置。5. The integrated semiconductor device according to claim 1, wherein the capacitance element includes first and second conductor layers each used as an electrode layer, and the coil includes: An integrated semiconductor device, wherein the element is a planar coil disposed between the first and second conductor layers and electrically connected to the first and second conductor layers.
おいて、前記第１及び前記第２の導体層の少なくとも一
つは電気伝導性を有する強磁性体で形成されていること
を特徴とする集積半導体装置。6. The integrated semiconductor device according to claim 5, wherein at least one of said first and second conductor layers is formed of a ferromagnetic material having electrical conductivity. Integrated semiconductor device.
おいて、前記コイル素子と前記第１及び前記第２の導体
層との間には第２の絶縁層が配置されており、前記コイ
ル素子の巻き始め端及び巻き終り端はスルーホールを介
してそれぞれ前記第１及び前記第２の導体層に電気的に
接続されていることを特徴とする集積半導体装置。7. The integrated semiconductor device according to claim 5, wherein a second insulating layer is disposed between the coil element and the first and second conductor layers, and Wherein the winding start end and the winding end end are electrically connected to the first and second conductor layers via through holes, respectively.
れた集積半導体装置において、前記基板を除いて他の部
分が絶縁保護層で封止されていることを特徴とする集積
半導体装置。8. The integrated semiconductor device according to claim 1, wherein other parts except for the substrate are sealed with an insulating protective layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28116699A JP2001101368A (en) | 1999-10-01 | 1999-10-01 | Integrated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28116699A JP2001101368A (en) | 1999-10-01 | 1999-10-01 | Integrated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001101368A true JP2001101368A (en) | 2001-04-13 |
Family
ID=17635280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28116699A Withdrawn JP2001101368A (en) | 1999-10-01 | 1999-10-01 | Integrated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001101368A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007288175A (en) * | 2006-03-21 | 2007-11-01 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
| JP2007294910A (en) * | 2006-03-31 | 2007-11-08 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
| JP2007294911A (en) * | 2006-03-31 | 2007-11-08 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
| US7956352B2 (en) * | 2005-03-25 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Memory element comprising an organic compound and an insulator |
| US20120193694A1 (en) * | 2005-03-08 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Wireless chip and electronic appliance having the same |
| US8288197B2 (en) | 2005-04-27 | 2012-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device including a memory device comprising an insulator mixture region in a conductive layer |
| US8421061B2 (en) | 2006-03-10 | 2013-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Memory element and semiconductor device including the memory element |
| US8772917B2 (en) | 2006-02-10 | 2014-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having an antenna |
| KR101440928B1 (en) * | 2006-03-21 | 2014-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Nonvolatile semiconductor memory device |
-
1999
- 1999-10-01 JP JP28116699A patent/JP2001101368A/en not_active Withdrawn
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120193694A1 (en) * | 2005-03-08 | 2012-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Wireless chip and electronic appliance having the same |
| US8455954B2 (en) * | 2005-03-08 | 2013-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Wireless chip and electronic appliance having the same |
| US8399881B2 (en) | 2005-03-25 | 2013-03-19 | Semiconductor Energy Laboratory Co., Ltd. | Memory element, memory device, and semiconductor device |
| US7956352B2 (en) * | 2005-03-25 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Memory element comprising an organic compound and an insulator |
| US8288197B2 (en) | 2005-04-27 | 2012-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device including a memory device comprising an insulator mixture region in a conductive layer |
| US8772917B2 (en) | 2006-02-10 | 2014-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having an antenna |
| US9437777B2 (en) | 2006-02-10 | 2016-09-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with antenna and light-emitting element |
| US9768210B2 (en) | 2006-02-10 | 2017-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having antenna and sensor elements |
| US8421061B2 (en) | 2006-03-10 | 2013-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Memory element and semiconductor device including the memory element |
| JP2007288175A (en) * | 2006-03-21 | 2007-11-01 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
| KR101440928B1 (en) * | 2006-03-21 | 2014-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Nonvolatile semiconductor memory device |
| JP2007294911A (en) * | 2006-03-31 | 2007-11-08 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
| JP2007294910A (en) * | 2006-03-31 | 2007-11-08 | Semiconductor Energy Lab Co Ltd | Nonvolatile semiconductor memory device |
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