JP2007288175A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device excellent in writing characteristics and charge retention characteristics. <P>SOLUTION: A first insulation layer, a floating gate, a second insulation layer, and a control gate are provided on a semiconductor substrate where a channel forming region is formed between a pair of impurity regions. The floating gate has an at least two layer structure, and a first layer touching the first insulation layer is preferably smaller than the band gap of the semiconductor substrate. For example, the band gap of a semiconductor layer forming the floating gate and the band gap in the channel forming region of the semiconductor substrate has a difference of 0.1 eV or above, and the former is preferably smaller. Energy level on the bottom of conduction band of the floating gate is set lower than the energy level on the bottom of conduction band in the channel forming region of the semiconductor substrate, in order to enhance carrier injection properties thus enhancing the charge retention characteristics. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a nonvolatile semiconductor memory device which can be electrically written, read and erased, and a manufacturing method thereof. In particular, the present invention relates to a structure of a floating gate in the nonvolatile semiconductor memory device.

The market for nonvolatile memories that can electrically rewrite data and store data even when the power is turned off is expanding. The nonvolatile memory has a structure similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and is characterized in that a region capable of accumulating charges for a long period is provided on the channel formation region. This charge storage region is formed on an insulating layer and is also called a floating gate because it is isolated from the surroundings. Since the floating gate is surrounded by an insulator and is electrically insulated from the surroundings, the floating gate has a characteristic of continuing to hold the charge when the charge is injected into the floating gate. On the floating gate, a gate electrode called a control gate is further provided via an insulating layer. The control gate is distinguished from the floating gate because a predetermined voltage is applied when data is written or read.

A so-called floating gate type nonvolatile memory having such a structure has a mechanism for storing data by electrically controlling charge injection into the floating gate and discharge of the charge from the floating gate. Specifically, charge injection into the floating gate and charge discharge from the floating gate are performed by applying a high voltage between the semiconductor layer in which the channel formation region is formed and the control gate. At this time, it is said that Fowler-Nordheim type (FN type) tunnel current (NAND type) or thermal electrons (NOR type) flow in the insulating layer on the channel formation region. Thus, the insulating layer is also called a tunnel insulating layer.

Floating gate type non-volatile memories are required to have characteristics capable of retaining the charge stored in the floating gate for more than 10 years in order to guarantee reliability. For this reason, the tunnel insulating layer is required to have high insulating properties so as to prevent charges from leaking while being formed with a thickness through which a tunnel current flows.

The floating gate formed on the tunnel insulating layer is formed of silicon, which is the same semiconductor material as the semiconductor in which the channel formation region is formed. For example, a method of forming a floating gate with polycrystalline silicon is widespread. For example, a method in which a polysilicon film is deposited to a thickness of 400 nm is known (see Patent Document 1).
JP 2000-58685 A (page 7, FIG. 7)

Since the floating gate of the nonvolatile memory is formed of polycrystalline silicon, the energy level at the bottom of the conduction band in the channel formation region of the semiconductor substrate is the same. Rather, if the thickness of the polycrystalline silicon of the floating gate is reduced, the energy level at the bottom of the conduction band becomes higher than that of the semiconductor forming the channel formation region. When such a state is formed, it becomes difficult for electrons to be injected from the semiconductor substrate to the floating gate, and it is necessary to increase the writing voltage. In order to lower the write voltage as much as possible, in a nonvolatile memory in which the floating gate is formed of polycrystalline silicon, an n-type impurity such as phosphorus or arsenic is added to the floating gate to shift the Fermi level to the conduction band side. There is a need.

Regarding the gate insulating layer provided between the floating gate and the semiconductor substrate, it is necessary to reduce the thickness of the gate insulating layer in order to inject charges into the floating gate at a low voltage. On the other hand, in order to stably hold charges for a long period of time, it is necessary to increase the film thickness in order to prevent leakage of charges and entry of impurities.

After all, the conventional nonvolatile memory requires a high write voltage. In addition, with respect to deterioration due to repeated rewriting of the charge retention characteristic, reliability is ensured by taking measures such as providing a redundant memory cell or devising a controller and performing error detection / error correction.

Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that is excellent in writing characteristics and charge retention characteristics.

The present invention provides a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed apart from each other, and a first insulating layer at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region , A non-volatile semiconductor memory device having a floating gate, a second insulating layer, and a control gate. In the present invention, the floating gate is formed of a plurality of layers using a semiconductor material. Alternatively, a barrier layer that improves the water resistance of the floating gate and prevents corrosion is provided in contact with the second insulating layer side of the floating gate formed of a specific semiconductor material. The semiconductor material for forming the floating gate can be selected from a plurality of types in relation to the semiconductor material for forming the channel formation region.

As a semiconductor material for forming the floating gate, a material that satisfies one or more of the following conditions can be selected. The band gap (also referred to as “band gap”) of the semiconductor material forming the floating gate is preferably smaller than the band gap of the channel formation region of the semiconductor substrate. For example, the band gap of the semiconductor material forming the floating gate and the band gap of the channel formation region of the semiconductor substrate have a difference of 0.1 eV or more, and the former is preferably smaller. The band gap of the second insulating layer provided in contact with the floating gate is preferably larger than the band gap of the semiconductor material forming the floating gate.

The semiconductor material is preferably formed of a material having an electron affinity higher than that of the material forming the semiconductor substrate. The semiconductor material preferably has a higher barrier energy to electrons in the floating gate formed by the first insulating layer than the barrier energy to electrons in the channel formation region of the semiconductor substrate formed by the first insulating layer.

As a semiconductor material for forming the floating gate, typically, germanium or a germanium compound is preferable.

The floating gate is applied to the nonvolatile semiconductor memory device according to the present invention for the purpose of accumulating electric charge, but if it has a similar function, that is, if it functions as a charge accumulation layer, germanium or It is not limited to a germanium compound, and can be replaced by an oxide or nitride of the germanium or germanium compound, or an oxide layer or nitride layer containing the germanium or germanium compound.

Further, it is preferable to apply a layer formed of silicon or a silicon compound as a layer in contact with the floating gate formed of germanium or a germanium compound. As the silicon compound, silicon nitride, silicon nitride oxide, silicon carbide, silicon germanium containing germanium at a concentration of less than 10 atomic%, or the like can be used.

In the case where the floating gate is formed on the semiconductor substrate through the first insulating layer functioning as the tunnel insulating layer, the floating gate is formed from a semiconductor material containing at least germanium, thereby forming the floating gate from the channel formation region of the semiconductor substrate. It is possible to easily inject charges into the floating gate and improve the charge retention characteristics of the floating gate. Further, by providing a semiconductor material or a barrier layer that prevents corrosion by improving the water resistance of the floating gate in contact with the floating gate, deterioration of the floating gate can be suppressed.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

FIG. 1 is a cross-sectional view for explaining a main configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. 1 particularly shows the main part of the nonvolatile memory element. This nonvolatile memory element is manufactured using a semiconductor substrate 10. As the semiconductor substrate 10, it is preferable to use a single crystal silicon substrate (silicon wafer). An SOI (Si-On-Insulator) substrate can also be used. As an SOI substrate, oxygen ions are implanted into a mirror-polished wafer and then annealed at a high temperature to form an oxide film layer at a certain depth from the surface, and the so-called defect formed in the surface layer is eliminated. A SIMOX (Separation by Implanted Oxygen) substrate may be used.

When the semiconductor substrate 10 is n-type, a p-well 12 into which p-type impurities are implanted is formed. For example, boron is used as the p-type impurity, and is added at a concentration of about 5 × 10 ¹⁵ atoms / cm ^{3 to} 1 × 10 ¹⁶ atoms / cm ³ . By forming the p-well 12, an n-channel transistor can be formed in this region. Further, the p-type impurity added to the p-well 12 also has an effect of controlling the threshold voltage of the transistor. A channel formation region 14 to be formed in the semiconductor substrate 10 is formed in a region substantially coincident with a gate 26 described later, and is located between a pair of impurity regions 18 formed in the semiconductor substrate 10. It is.

The pair of impurity regions 18 functions as a source and a drain in the nonvolatile memory element. The pair of impurity regions 18 is formed by adding phosphorus or arsenic, which is an n-type impurity, at a concentration of about 1 × 10 ¹⁹ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ .

A spacer 28 is formed on the side wall of the gate 26, and has an effect of preventing leakage current (for example, current flowing between the floating gate electrode 20 and the control gate electrode 24) at the end thereof. In addition, the low concentration impurity regions 18 c can be formed at both ends of the gate 26 in the channel length direction by using the spacer 28. This low concentration impurity region 18c functions as a low concentration drain (LDD). Although the low-concentration impurity region 18c is not an essential structure, by providing this region, the electric field at the drain end can be relaxed and deterioration due to repeated writing and erasing can be suppressed.

A first insulating layer 16, a floating gate electrode 20, a second insulating layer 22, and a control gate electrode 24 are formed on the semiconductor substrate 10. In this specification, from the floating gate electrode 20 to the control gate electrode 24. The stacked structure may be referred to as the gate 26.

The first insulating layer 16 can be formed of silicon oxide or a stacked structure of silicon oxide and silicon nitride. The first insulating layer 16 may be formed by oxidizing the surface of the semiconductor substrate 10 by thermal oxidation, but is preferably formed by solid phase oxidation or solid phase nitridation by plasma treatment. This is because the insulating layer formed by oxidizing or nitriding the surface of the semiconductor substrate 10 by plasma treatment is dense and has high withstand voltage and excellent reliability. Since the first insulating layer 16 is used as a tunnel insulating layer for injecting charges into the floating gate electrode 20, it is preferable that the first insulating layer 16 is strong as described above. The first insulating layer 16 is preferably formed to a thickness of 1 nm to 20 nm, preferably 3 nm to 6 nm. For example, when the gate length is 600 nm, the first insulating layer 16 can be formed to a thickness of 3 nm to 6 nm.

As solid-phase oxidation treatment or solid-phase nitridation treatment by plasma treatment, the electron density is 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less when excited by microwaves (typically 2.45 GHz), and It is preferable to use plasma having an electron temperature of 0.5 eV to 1.5 eV. This is because in the solid phase oxidation treatment or solid phase nitridation treatment, a dense insulating film is formed at a temperature of 500 ° C. or lower and a practical reaction rate is obtained.

When the surface of the semiconductor substrate 10 is oxidized by this plasma treatment, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas (He, Ne, Ar, Kr, Xe) are used in an oxygen atmosphere. Or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). In the case of performing nitridation by plasma treatment, nitrogen and hydrogen are used in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere). Plasma treatment is performed in a rare gas atmosphere or in a rare gas atmosphere with NH ₃ . As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used.

FIG. 15 shows a configuration example of an apparatus for performing plasma processing. This plasma processing apparatus includes a support base 80 for arranging the semiconductor substrate 10, a gas supply unit 76 for introducing gas, an exhaust port 78 connected to a vacuum pump for exhausting gas, an antenna 72, a dielectric A plate 74 and a microwave supply unit 84 for supplying microwaves for plasma generation are provided. In addition, the temperature of the semiconductor substrate 10 can be controlled by providing the temperature control unit 82 on the support base 80.

Hereinafter, the plasma treatment will be described. Note that plasma treatment includes oxidation treatment, nitridation treatment, oxynitridation treatment, hydrogenation treatment, and surface modification treatment for a semiconductor substrate, an insulating layer, and a conductive layer. For these processes, a gas supplied from the gas supply unit 76 may be selected according to the purpose.

The oxidation treatment or nitridation treatment may be performed as follows. First, the processing chamber is evacuated, and a plasma processing gas containing oxygen or nitrogen is introduced from the gas supply unit 76. The semiconductor substrate 10 is heated to 100 ° C. to 550 ° C. by the room temperature or the temperature controller 82. The distance between the semiconductor substrate 10 and the dielectric plate 74 is about 20 mm to 80 mm (preferably 20 mm to 60 mm). Next, a microwave is supplied from the microwave supply unit 84 to the antenna 72. Then, plasma 86 is generated by introducing microwaves from the antenna 72 through the dielectric plate 74 into the processing chamber. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. The surface of the semiconductor substrate can be oxidized or nitrided by oxygen radicals (which may include OH radicals) and / or nitrogen radicals (which may include NH radicals) generated by this high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals or nitrogen radicals can be efficiently generated by the excited species of the rare gas. In this method, active radicals excited by plasma can be effectively used to nitride an oxidized, nitrided, oxynitrided or oxidized layer by a solid phase reaction at a low temperature of 500 ° C. or lower.

In FIG. 1, an example of a suitable first insulating layer 16 formed by plasma treatment is that a silicon oxide layer 16a is formed with a thickness of 3 nm or more and 6 nm or less on the surface of the semiconductor substrate 10 by plasma treatment in an oxidizing atmosphere. Thereafter, the silicon nitride layer 16b is formed by nitriding the surface of the silicon oxide layer in a nitrogen atmosphere. As a representative example of the first insulating layer 16, a dense oxide film without distortion can be formed by oxidizing the surface of the semiconductor substrate 10 by plasma treatment. Further, when the oxide film is nitrided by plasma treatment and oxygen in the surface layer portion is replaced with nitrogen to form a nitride layer, the oxide film can be further densified. Thereby, an insulating layer having a high withstand voltage can be formed.

The floating gate electrode 20 is formed on the first insulating layer 16. The floating gate electrode 20 is formed of a first floating gate electrode 20a and a second floating gate electrode 20b. Of course, the present invention is not limited to this two-layer structure, and a plurality of layers may be stacked. However, the first floating gate electrode 20a formed in contact with the first insulating layer 16 is preferably formed of a semiconductor material, and a material that satisfies one or more of the following conditions can be selected.

The band gap of the semiconductor material forming the first floating gate electrode 20a is preferably smaller than the band gap of the semiconductor substrate 10 (channel formation region in this example). For example, the band gap of the semiconductor material forming the first floating gate electrode 20a and the band gap in the channel formation region 14 of the semiconductor substrate 10 have a difference of 0.1 eV or more, and the former is preferably smaller. . By lowering the energy level of the bottom of the conduction band of the floating gate electrode 20 from the energy level of the bottom of the conduction band of the channel formation region 14 of the semiconductor substrate 10, the carrier (electron) injection property is improved, and the charge retention characteristics. It is for improving.

The semiconductor material forming the first floating gate electrode 20a is preferably a material having a higher electron affinity than the material forming the semiconductor substrate 10. By lowering the energy level of the bottom of the conduction band of the first floating gate electrode 20a from the energy level of the bottom of the conduction band of the channel formation region 14 in the semiconductor substrate 10, the carrier (electron) injection property is improved, This is to improve the charge retention characteristics. In the case of semiconductors, electron affinity is the energy difference from the bottom of the conduction band to vacuum.

The semiconductor material forming the first floating gate electrode 20 a is formed by the first insulating layer 16 against the barrier energy against electrons in the channel formation region 14 of the semiconductor substrate 10 formed by the first insulating layer 16. It is preferable that the barrier energy for electrons of the first floating gate electrode 20a is high. This is to make it easier to inject charges (electrons) from the channel formation region 14 of the semiconductor substrate 10 into the first floating gate electrode 20a and to prevent the charge from disappearing from the first floating gate electrode 20a.

Typically, germanium or a germanium compound can be selected as satisfying such conditions. A typical example of the germanium compound is silicon germanium. In this case, it is preferable that germanium is contained at 10 atomic% or more with respect to silicon. This is because if the concentration of germanium is less than 10 atomic%, the effect as a constituent element is reduced, and the band gap is not effectively reduced.

Of course, other materials can be applied as long as the floating gate electrode 20 is formed as long as the same effect is exhibited. For example, a ternary semiconductor material containing germanium can be used. The semiconductor material may be hydrogenated. Further, as a function of a charge storage layer of a nonvolatile memory element, an oxide or nitride of the germanium or germanium compound, or an oxide or nitride layer containing the germanium or germanium compound can be used. .

A layer formed of silicon or a silicon compound is preferably used for the second floating gate electrode 20b provided on the second insulating layer 22 side in contact with the first floating gate electrode 20a. As the silicon compound, silicon nitride, silicon nitride oxide, silicon carbide, silicon germanium containing germanium at a concentration of less than 10 atomic%, or the like can be used. Thus, by forming the second floating gate electrode 20b with a material having a larger band gap than the first floating gate electrode 20a, the charge accumulated in the floating gate leaks to the second insulating layer 22 side. Can be prevented.

In any case, the above-described second layer of silicon or silicon compound is provided on the upper layer side of the first layer formed of germanium or germanium compound, thereby providing water resistance and chemical resistance in the manufacturing process. It can be used as the intended barrier layer. Thereby, the handling of the substrate in the photolithography process, the etching process, and the cleaning process becomes easy, and the productivity can be improved. That is, the floating gate can be easily processed.

The second insulating layer 22 is made of silicon oxide, silicon oxynitride (SiOxNy, (x> y)), silicon nitride (SiNx), silicon nitride oxide (SiNxOy, (x> y)), aluminum oxide (AlxOy), or the like. One layer or a plurality of layers are formed by a low pressure CVD method, a plasma CVD method, or the like. The thickness of the second insulating layer 22 is 1 nm to 20 nm, preferably 5 nm to 10 nm. For example, a silicon nitride layer 22a having a thickness of 3 nm and a silicon oxide layer 22b having a thickness of 5 nm can be used. Further, plasma treatment is performed on the second floating gate electrode 20b to form a nitride film (for example, silicon nitride when silicon is used as the second floating gate electrode 20b) by nitriding the surface of the floating gate electrode 20 May be. In any case, the first insulating layer 16 and the second insulating layer 22 are either a nitride film or a nitrided layer on one or both sides in contact with the floating gate electrode 20, so that the floating gate electrode 20 Oxidation can be prevented.

The control gate electrode 24 is a metal selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), chromium (Cr), niobium (Nb), or the like, or contains these metals as a main component. It is preferable to form with an alloy material or a compound material. Alternatively, polycrystalline silicon to which an impurity element such as phosphorus is added can be used. Further, the control gate electrode 24 may be formed by a laminated structure of one or more metal nitride layers 24a and the metal layer 24b. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride layer 24a, the adhesion of the metal layer 24b can be improved and peeling can be prevented. Further, since the metal nitride such as tantalum nitride has a high work function, the thickness of the first insulating layer 16 can be increased by a synergistic effect with the second insulating layer 22.

An operation mechanism of the nonvolatile memory element shown in FIG. 1 will be described with reference to a band diagram. In the band diagram shown below, the same elements as those in FIG.

FIG. 2 shows a state in which the channel formation region 14, the first insulating layer 16, the floating gate electrode 20, the second insulating layer 22, and the control gate electrode 24 of the semiconductor substrate 10 are stacked. FIG. 2 shows a case where no voltage is applied to the control gate electrode 24 and the Fermi level Ef of the channel formation region 14 of the semiconductor substrate 10 is equal to the Fermi level Efm of the control gate electrode 24.

The semiconductor substrate 10 and the first floating gate electrode 20a are formed of different materials with the first insulating layer 16 interposed therebetween. The band gap Eg1 (energy difference between the lower end Ec of the conduction band and the upper end Ev of the valence band) of the channel formation region 14 of the semiconductor substrate 10 is different from the band gap Eg2 of the first floating gate electrode 20a. Are combined to be smaller. For example, silicon (1.12 eV) can be combined as the channel formation region 14 of the semiconductor substrate 10, and germanium (0.72 eV) or silicon germanium (0.73 eV to 1.0 eV) can be combined as the first floating gate electrode 20a. The first insulating layer 16 is represented by a silicon oxide layer 16a (about 8 eV) and a silicon nitride layer 16b (about 5 eV) obtained by nitriding the silicon oxide by plasma treatment. The second insulating layer 22 also shows a state in which the silicon nitride layer 22a and the silicon oxide layer 22b are stacked from the floating gate electrode 20 side. When polycrystalline silicon is used as the second floating gate electrode 20b, the band gap is larger than that of the first floating gate electrode 20a. This difference in band gap serves as a barrier against carriers injected into the first floating gate electrode 20a through the first insulating layer 16. Thereby, the injected carriers can be prevented from leaking to the second insulating layer 22 side and trapped at the interface.

If the vacuum level is 0 eV, the energy level of the conduction band of silicon is −4.05 eV, and the energy level of the conduction band of germanium is −4.1 eV. The energy level of the conduction band of silicon oxide is -0.9 eV. Accordingly, the combination of the channel formation region 14 of the semiconductor substrate 10 and the first floating gate electrode 20a, barrier energy (Be1) against electrons in the channel formation region 14 of the semiconductor substrate 10 formed by the first insulating layer 16 is achieved. ), The barrier energy (Be2) for electrons of the first floating gate electrode 20a formed by the first insulating layer 16 can be increased. That is, the energy barrier against electrons, that is, the first barrier Be1 and the second barrier Be2 have different values, and can have a relationship of Be2> Be1.

In such a situation, the silicon band gap Eg1 as the channel formation region 14 of the semiconductor substrate 10 and the germanium band gap Eg2 as the first floating gate electrode 20a satisfy the relationship Eg1> Eg2. Further, when the electron affinity is taken into consideration as described above, an energy difference ΔE between the energy level at the bottom of the conduction band of the channel formation region 14 of the semiconductor substrate 10 and the floating gate electrode 20 is generated. As will be described later, this energy difference ΔE acts in the direction of accelerating the electrons when they are injected from the channel formation region 14 of the semiconductor substrate 10 into the floating gate electrode 20, and thus contributes to lowering the write voltage. .

For comparison, FIG. 16 shows a band diagram in the case where the channel formation region of the semiconductor substrate and the floating gate electrode are formed of the same semiconductor material. This band diagram shows a state in which the semiconductor substrate 01, the first insulating layer 02, the floating gate electrode 03, the second insulating layer 04, and the control gate electrode 05 are sequentially stacked.

It is inherently preferable that the thickness of the floating gate electrode 03 is at most the same as or thinner than the channel length. This is to form a fine pattern at a submicron level. This is because if the film thickness is increased, a fine pattern cannot be formed with respect to the gate length. However, if the floating gate electrode 03 becomes thinner, the band gap becomes larger as a result if it is formed of the same silicon semiconductor as the channel formation region of the semiconductor substrate 01. That is, the energy level of the bottom of the conduction band of the floating gate electrode 03 is higher than the energy level of the bottom of the conduction band in the channel formation region of the semiconductor substrate 01.

FIG. 16 shows this state. The band gap of the channel formation region in the semiconductor substrate 01 is indicated by Eg1, and the band gap of the floating gate electrode 03 is indicated by Eg2. When silicon is thinned, the band gap is said to increase from 1.12 eV in bulk to about 1.4 eV. As a result, an energy difference of ΔE is generated between the semiconductor substrate 01 and the floating gate electrode 03 in a direction that makes it difficult to inject electrons. In such a situation, a high voltage is required to inject electrons from the semiconductor substrate 01 into the floating gate electrode 03. That is, in order to lower the write voltage, it is necessary to dope the floating gate electrode 03 with high concentration of phosphorus or arsenic as an n-type impurity. This is a defect in the conventional nonvolatile memory.

However, as shown in FIG. 2, when germanium is used as the floating gate electrode 20, the band gap is as small as 0.72 eV than silicon. Even if the band gap of germanium is increased by thinning, it is at most about 1 eV, so that a state smaller than the band gap in the channel formation region 14 of the semiconductor substrate 10 is maintained. As a result, the self-bias generated by the energy difference at the lower end of the conduction band with respect to the electrons injected from the channel forming region 14 works in a direction that facilitates injection of electrons into the floating gate electrode 20. When phosphorus or arsenic, which are n-type impurities, is added to germanium, the action can be further increased.

As a result, when germanium or a germanium compound is used as the floating gate electrode 20, the film thickness can be reduced and a finer structure can be formed. In particular, when the channel length of the nonvolatile memory element is 100 nm or less, preferably 20 nm or more and 50 nm or less, germanium or a germanium compound, or a floating gate electrode to which an n-type impurity is added can be reduced in thickness, This is preferable for ultra-high integration.

Further, when an n-type impurity is added at a high concentration to the floating gate electrode, the breakdown voltage tends to be lowered between the floating gate electrode and the channel formation region, and it is not preferable to make the concentration too high. As a result, conductive germanium or a germanium compound in which n-type or p-type impurities are not intentionally added or n-type impurities are added at a concentration of 1 × 10 ^{18 to} 2 × 10 ²⁰ cm ⁻³ is preferable. . Therefore, carbon (C), nitrogen (N), and oxygen (O), which are impurities that are easily insulated, in the floating gate electrode formed of germanium or a germanium compound are all 5 × 10 ¹⁹ cm ⁻³ or less, Preferably it is 2 * 10 < ¹⁹ > cm <^-3> or less.

By the way, in order to inject electrons into the floating gate electrode 20, there are a method using thermal electrons and a method using FN tunnel current. When thermoelectrons are used, a positive voltage is applied to the control gate electrode 24, and a high voltage is applied to the drain to generate thermoelectrons. Thereby, thermoelectrons can be injected into the floating gate electrode 20. When using the FN type tunnel current, a positive voltage is applied to the control gate electrode 24 and injected from the channel formation region 14 of the semiconductor substrate 10 into the floating gate electrode 20 by the FN type tunnel current.

FIG. 6A shows an applied voltage when injecting into the floating gate electrode 20 by the FN type tunnel current. The p-well 12 of the semiconductor substrate 10 is grounded, a positive high voltage (10V to 20V) is applied to the control gate electrode 24, and the source region 18a and the drain region 18b are set to 0V. The band diagram at this time is as shown in FIG. Electrons in the channel formation region 14 of the semiconductor substrate 10 are injected into the first insulating layer 16 by a high electric field, and an FN tunnel current flows. As described with reference to FIG. 2, the relationship between the band gap Eg1 of the channel formation region 14 in the semiconductor substrate 10 and the band gap Eg2 of the floating gate electrode 20 is Eg1> Eg2. This difference acts as a self-bias so that electrons injected from the channel formation region 14 are accelerated toward the floating gate electrode 20. Thereby, the electron injection property can be improved.

The energy level of the bottom of the conduction band of the floating gate electrode 20 is at a level lower by ΔE in terms of electronic energy than the energy level of the bottom of the conduction band of the channel formation region of the semiconductor substrate 10. Therefore, when electrons are injected into the floating gate electrode 20, an internal electric field caused by this energy difference acts. This is realized by the combination of the channel forming region 14 of the semiconductor substrate 10 and the floating gate electrode 20 as described above. That is, it becomes easier to inject electrons from the channel formation region 14 of the semiconductor substrate 10 into the floating gate electrode 20, and the write characteristics in the nonvolatile memory element can be improved. This effect is the same when electrons are injected into the floating gate electrode 20 using thermoelectrons.

While electrons are held in the floating gate electrode 20, the threshold voltage of the nonvolatile memory element shifts in the positive direction. This state can be a state in which data “0” is written. FIG. 4 shows a band diagram in the charge holding state. The electrons of the floating gate electrode 20 are in an energetic state by being sandwiched between the first insulating layer 16 and the second insulating layer 22. Although the potential is increased by carriers (electrons) accumulated in the first floating gate electrode 20a, electrons are not emitted from the first floating gate electrode 20a unless energy exceeding the barrier energy is applied to the electrons. More specifically, it can be said that the carrier of the first floating gate electrode 20a is energeticly confined between the first insulating layer 16 and the second floating gate electrode 20b. In this state, it is possible to prevent the injected carriers from leaking to the second insulating layer 22 side and being trapped at the interface. That is, in the erase operation, it is possible to prevent the carriers injected into the floating gate region from remaining and causing an erase failure. However, since the second floating gate electrode 20b also has the ability to accumulate carriers as a floating gate, the first floating gate electrode 20a can be supplemented to function as a floating gate. That is, the carriers accumulated in the floating gate 20 can be held even in a reliability test by being kept at a constant temperature of 150 ° C.

In this case, electrons are not emitted from the floating gate electrode 20 unless energy exceeding the barrier energy is applied to the electrons. In addition, the energy level of the bottom of the conduction band of the floating gate electrode 20 is at a level lower by ΔE in terms of electron energy than the energy level of the bottom of the conduction band of the channel formation region 14 of the semiconductor substrate 10. Energy barriers are formed. This barrier can prevent electrons from flowing out to the semiconductor substrate 10 due to the tunnel current.

In order to detect the state in which the data “0” is written, the circuit may determine that the transistor is not turned on when the intermediate potential Vread is applied to the control gate electrode 24. The intermediate potential is an intermediate potential between the threshold voltage Vth1 for data “1” and the threshold voltage Vth2 for data “0” (in this case, Vth1 <Vread <Vth2). Alternatively, as shown in FIG. 6B, whether or not the nonvolatile memory element becomes conductive when a bias is applied between the source region 18a and the drain region 18b so that the control gate electrode 24 is set to 0V or an intermediate potential Vread. Can be judged.

FIG. 7A shows a state in which charges are released from the floating gate electrode 20 and data is erased from the nonvolatile memory element. In this case, the control gate electrode 24 is grounded, a negative bias is applied to the p-well 12 of the semiconductor substrate 10, and an FN type tunnel current between the channel formation region 14 of the semiconductor substrate 10 and the floating gate electrode 20 is applied. It is done by flowing. Alternatively, as shown in FIG. 7B, a negative bias is applied to the control gate electrode 24, and a positive high voltage is applied to the source region 18a, thereby generating an FN type tunnel current. Electrons may be extracted to the 18a side.

FIG. 5 shows a band diagram in this erased state. In the erase operation, since the first insulating layer 16 can be formed thin, electrons of the floating gate electrode 20 can be emitted to the semiconductor substrate 10 side by the FN type tunnel current. Further, by injecting holes from the channel formation region 14 of the semiconductor substrate 10 into the floating gate electrode 20, a substantial erasing operation can be performed. Moreover, holes are more easily injected from the channel formation region 14 of the semiconductor substrate 10, and a substantial erase operation can be performed by injecting the holes into the floating gate electrode 20.

By forming the floating gate electrode 20 from germanium or a germanium compound, the thickness of the first insulating layer 16 can be reduced. Thereby, it becomes easy to inject electrons into the floating gate electrode 20 through the first insulating layer 16 by a tunnel current, and a low voltage operation becomes possible. Furthermore, it becomes possible to store electric charges at a low energy level, and a significant effect can be obtained that electric charges can be stored in a stable state.

As shown in FIGS. 2 and 3, the nonvolatile memory device according to the present invention is configured such that self bias is generated between the channel formation region 14 of the semiconductor substrate 10 and the floating gate electrode 20 as Eg1> Eg2. . This relationship is extremely important, and acts to facilitate injection when carriers are injected from the channel formation region 14 of the semiconductor substrate into the floating gate electrode. That is, the writing voltage can be lowered. Conversely, it is difficult to release carriers from the floating gate electrode. This acts to improve the storage retention characteristics of the nonvolatile memory element. In addition, by doping the germanium layer as the floating gate electrode with an n-type impurity, the energy level at the bottom of the conduction band can be further lowered, and the self-bias acts to make it easier to inject carriers into the floating gate electrode. Can be made. That is, the write voltage can be lowered and the memory retention characteristics of the nonvolatile memory element can be improved.

As described above, the nonvolatile memory element according to the present invention can easily inject charges from the semiconductor substrate to the floating gate electrode, and can prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved.

Various nonvolatile semiconductor memory devices can be obtained using such a nonvolatile memory element. FIG. 8 shows an example of an equivalent circuit of a nonvolatile memory cell array. The memory cell MS01 that stores 1-bit information includes a selection transistor S01 and a nonvolatile memory element M01. The selection transistor S01 is inserted in series between the bit line BL0 and the nonvolatile memory element M01, and the gate is connected to the word line WL1. The gate of the nonvolatile memory element M01 is connected to the word line WL11. When writing data to the nonvolatile memory element M01, if the word line WL1 and the bit line BL0 are set to the H level, the BL1 is set to the L level, and a high voltage is applied to the word line WL11, charges are accumulated in the floating gate as described above. Is done. When erasing data, the word line WL1 and the bit line BL0 are set to H level, and a negative high voltage is applied to the word line WL11.

FIG. 9 shows a NOR-type equivalent circuit in which a nonvolatile memory element is directly connected to a bit line. In this memory cell array, word lines WL (WL1 to WL3) and bit lines BL (BL0 to BL2) are arranged so as to intersect with each other, and nonvolatile memory elements (M0 to M23) are arranged at each intersection. In the NOR type, the drain of each nonvolatile memory element is connected to the bit line BL. The sources of the nonvolatile memory elements are commonly connected to the source line SL.

The NOR type operation is, for example, as follows. In data writing, the source line SL is set to 0 V, a high voltage is applied to the word line WL selected for data writing, and a potential corresponding to data “0” and “1” is applied to the bit line BL. For example, H level and L level potentials are applied to the bit line BL for “0” and “1”, respectively. In order to write “0” data, in the nonvolatile memory element to which H level is given, hot electrons are generated in the vicinity of the drain, and this is injected into the floating gate. In the case of “1” data, such electron injection does not occur.

In a memory cell to which “0” data is given, hot electrons are generated in the vicinity of the drain due to a strong lateral electric field between the drain and the source, and this is injected into the floating gate. As a result, the state where electrons are injected into the floating gate and the threshold voltage becomes high is “0”. In the case of “1” data, hot electrons are not generated, electrons are not injected into the floating gate, and a low threshold voltage state, that is, an erased state is maintained.

When erasing data, a positive voltage of about 10 V is applied to the source line SL, and the bit line BL is left floating. Then, a negative high voltage is applied to the word line WL (a negative high voltage is applied to the control gate), and electrons are extracted from the floating gate. As a result, the data “1” is erased.

For data reading, the source line SL is set to 0V and the bit line BL is set to about 0.8V, and the selected word line WL is set to an intermediate value between the threshold values of data “0” and “1”. A voltage is applied, and the presence / absence of current draw in the nonvolatile memory element is determined by a sense amplifier connected to the bit line BL.

FIG. 10 shows an equivalent circuit of the NAND memory cell array. A NAND cell NS1 in which a plurality of nonvolatile memory elements are connected in series is connected to the bit line BL. A plurality of NAND cells gather to constitute a block BLK. The block BLK1 shown in FIG. 10 has 32 word lines (word lines WL0 to WL31). The nonvolatile memory elements located in the same row of the block BLK1 are commonly connected to word lines corresponding to this row.

The write operation is executed after the NAND cell NS1 is in the erased state, that is, the threshold values of the nonvolatile memory elements (M0 to M31) of the NAND cell NS1 are in a negative voltage state. Writing is performed in order from the nonvolatile memory element M0 on the source line SL side. An example of writing to the memory element M0 is as follows.

Writing is executed after the NAND cell is in the erased state, that is, the threshold value of each memory cell of the NAND cell is in a negative voltage state. In FIG. 11A, when “0” is written, for example, Vcc (power supply voltage) is applied to the selection gate line SG2 to turn on the selection transistor S2 and to set the bit line BL0 to 0 V (ground voltage). The selection gate line SG1 is set to 0V, and the selection transistor S1 is turned off. Next, the word line WL0 of the nonvolatile memory element M0 is set to the high voltage Vpgm (about 20V), and the other word lines are set to the intermediate voltage Vpass (about 10V). Since the voltage of the bit line BL0 is 0V, the potential of the channel formation region of the selected nonvolatile memory element M0 is 0V. Since the potential difference between the word line WL0 and the channel formation region is large, electrons are injected into the floating gate of the nonvolatile memory element M0 by the FN tunnel current as described above. As a result, the threshold voltage of the nonvolatile memory element M0 becomes positive (a state in which “0” is written).

On the other hand, when "1" is written, the bit line BL is set to Vcc (power supply voltage), for example, as shown in FIG. Since the voltage of the selection gate line SG2 is Vcc, the selection transistor S2 is cut off when Vcc minus Vth (Vcc−Vth) with respect to the threshold voltage Vth of the selection transistor S2. Accordingly, the channel formation region of the nonvolatile memory element M0 is in a floating state. Next, when the high voltage Vpgm (20 V) is applied to the word line WL0 and the intermediate voltage Vpass (10 V) is applied to the other word lines, the capacitive coupling between each word line and the channel formation region causes the channel formation region. The voltage rises from Vcc-Vth and becomes about 8V, for example. Since the voltage of the channel formation region is boosted to a high voltage, the potential difference between the word line WL0 and the channel formation region is small unlike the case of writing “0”. Therefore, electron injection due to the FN tunnel current does not occur in the floating gate of the nonvolatile memory element M0. Therefore, the threshold value of the nonvolatile memory element M0 is maintained in a negative state (a state in which “1” is written).

When performing the erase operation, as shown in FIG. 12A, all the word lines in the selected block are set to 0 V, and a negative high voltage (Vers) is applied to the p-well. The bit line BL and the source line SL are in a floating state. Thereby, electrons in the floating gate are emitted to the semiconductor substrate by the tunnel current in all the memory cells of the block. As a result, the threshold voltages of these memory cells shift in the negative direction.

In the reading operation shown in FIG. 12B, the word line WL0 of the nonvolatile memory element M0 selected for reading is set to the voltage Vr (for example, 0 V), and the word lines WL1 to WL31 and the selection gate lines of the unselected memory cells. SG1 and SG2 are read intermediate voltages Vread that are slightly higher than the power supply voltage. That is, as shown in FIG. 13, the memory elements other than the selected memory element function as transfer transistors. Thus, it is detected whether or not a current flows through the nonvolatile memory element M0 selected for reading. That is, when the data stored in the nonvolatile memory element M0 is “0”, the nonvolatile memory element M0 is off, and the bit line BL is not discharged. On the other hand, in the case of “1”, since the nonvolatile memory element M0 is turned on, the bit line BL is discharged.

FIG. 14 shows an example of a circuit block diagram of a nonvolatile semiconductor memory device. In the nonvolatile semiconductor memory device, the memory cell array 52 and the peripheral circuit 54 are formed on the same substrate. The memory cell array 52 has a configuration as shown in FIG. 8, FIG. 9, and FIG. The configuration of the peripheral circuit 54 is as follows.

A row decoder 62 for selecting a word line and a column decoder 64 for selecting a bit line are provided around the memory cell array 52. The address is sent to the control circuit 58 via the address buffer 56, and the internal row address signal and the internal column address signal are transferred to the row decoder 62 and the column decoder 64, respectively.

For writing and erasing data, a potential obtained by boosting the power supply potential is used. Therefore, a booster circuit 60 controlled by the control circuit 58 according to the operation mode is provided. The output of the booster circuit 60 is supplied to the word line WL and the bit line BL via the row decoder 62 and the column decoder 64. The sense amplifier 66 receives the data output from the column decoder 64. Data read by the sense amplifier 66 is held in the data buffer 68, and the data is randomly accessed under the control of the control circuit 58 and output via the data input / output buffer 70. The write data is temporarily held in the data buffer 68 via the data input / output buffer 70 and transferred to the column decoder 64 under the control of the control circuit 58.

Next, the above-described nonvolatile semiconductor memory device will be described in detail with reference to examples. In the structure of the present invention described below, reference numerals indicating the same elements are used in common in different drawings, and repetitive description in that case may be omitted.

In this embodiment, an example of a nonvolatile semiconductor memory device will be described with reference to the drawings. In the following description, in a nonvolatile semiconductor memory device, a non-volatile memory element that forms a memory unit, and an element such as a transistor that forms a logic unit that is provided on the same substrate as the memory unit and controls the memory unit. Are shown simultaneously.

First, an equivalent circuit of a memory portion in the nonvolatile semiconductor memory device is shown in FIG.

In the memory portion shown in this embodiment, a plurality of memory cells each including a selection transistor and a nonvolatile memory element are provided. In FIG. 8, one memory cell is formed by the select transistor S01 and the nonvolatile memory element M01. Similarly, the selection transistor S02 and the nonvolatile memory element M02, the selection transistor S03 and the nonvolatile memory element M03, the selection transistor S11 and the nonvolatile memory element M11, the selection transistor S12 and the nonvolatile memory element M12, and the selection transistor S13 and the nonvolatile transistor A memory cell is formed by the volatile memory element M13.

The gate electrode of the selection transistor S01 is connected to the word line WL1, one of the source and the drain is connected to the bit line BL0, and the other is connected to the source or the drain of the nonvolatile memory element M01. The gate electrode of the nonvolatile memory element M01 is connected to the word line WL11, one of the source and the drain is connected to the source or the drain of the selection transistor S01, and the other is connected to the source line SL0.

Note that since the selection transistor provided in the memory portion has a higher driving voltage than the transistor provided in the logic portion, the gate insulating film of the transistor provided in the memory portion and the transistor provided in the logic portion are formed with different thicknesses. It is preferable. For example, it is preferable to provide a transistor with a thin gate insulating film when the driving voltage is small and it is desired to reduce variation in threshold voltage. When the driving voltage is large and the withstand voltage performance of the gate insulating film is required, the gate insulating film is It is preferable to provide a thick transistor.

Therefore, in this embodiment, an insulating layer having a small film thickness is formed for a transistor in the logic portion where the driving voltage is small and the variation in threshold voltage is small, and the withstand voltage performance of the gate insulating film is required because the driving voltage is large. A case where an insulating layer having a large film thickness is formed for a transistor in a memory portion will be described below with reference to the drawings. Note that in FIGS. 17 to 20, between AB and CD are transistors provided in the logic portion, between EF are nonvolatile memory elements provided in the memory portion, and between GH are A transistor provided in the memory portion is shown. In this embodiment, a transistor provided between A and B is a p-channel type, a transistor provided between C and D, a transistor provided between GH is an n channel type, and a carrier of a nonvolatile memory element provided between EF However, the nonvolatile semiconductor device of the present invention is not limited to this.

First, regions 104, 106, 108, and 110 in which elements are separated are formed on the substrate 100, and first insulating layers 112, 114, 116, and 118 are formed on the surfaces of the regions 104, 106, 108, and 110, respectively. Then, charge storage layers 120 and 123 functioning as floating gates are stacked in the nonvolatile memory element to be completed later so as to cover the first insulating layers 112, 114, 116, and 118 (FIG. 17A). reference). The regions 104, 106, 108, and 110 provided in the substrate 100 are separated by an insulating layer 102 (also referred to as a field oxide film). In this example, a single crystal silicon substrate having n-type conductivity is used as the substrate 100, and a p-well 107 is provided in the regions 106, 108, and 110 of the substrate 100.

The substrate 100 can be used without any particular limitation as long as it is a semiconductor substrate. For example, an n-type or p-type single crystal silicon substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by Implanted) An SOI (Silicon on Insulator) substrate manufactured by an Oxygen method or the like can be used.

For the regions 104, 106, 108, and 110 where the elements are isolated, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used as appropriate.

The p well formed in the regions 106, 108, and 110 of the substrate 100 can be formed by selectively introducing an impurity element having p-type conductivity into the substrate 100. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

Note that in this embodiment, since a semiconductor substrate having n-type conductivity is used as the substrate 100, no impurity element is introduced into the region 104, but by introducing an impurity element exhibiting n-type conductivity. An n-well may be formed in the region 104. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 104 to form an n-well, and the impurity element is introduced into the regions 106, 108, and 110. There may be no configuration.

The first insulating layers 112, 114, 116, and 118 can be formed using a silicon oxide film by performing heat treatment to oxidize the surfaces of the regions 104, 106, 108, and 110 provided in the substrate 100. In addition, after a silicon oxide film is formed by a thermal oxidation method, a surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. Can be formed with a structure.

In addition, the first insulating layers 112, 114, 116, and 118 may be formed by plasma treatment. For example, by performing oxidation treatment or nitridation treatment by high-density plasma treatment on the surfaces of the regions 104, 106, 108, and 110 provided in the substrate 100, silicon oxide (as the first insulating layers 112, 114, 116, and 118) A SiOx) film or a silicon nitride (SiNx) film can be formed. In addition, after the surface of the regions 104, 106, 108, and 110 is oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 104, 106, 108, and 110, and a (silicon oxynitride film) is formed over the silicon oxide film, so that the first insulating layers 112, 114, 116, Reference numeral 118 denotes a film in which a silicon oxide film and a silicon oxynitride film are stacked. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 104, 106, 108, and 110 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

In this example, the first insulating layers 112, 114, 116, and 118 are formed with a thickness of 1 nm to 10 nm, preferably 1 nm to 5 nm. For example, an oxidation treatment is performed on the regions 104, 106, 108, and 110 by heat treatment to form a silicon oxide film having a thickness of about 5 nm on the surface of the regions 104, 106, 108, and 110, and then a nitridation treatment is performed by high-density plasma treatment. A silicon oxynitride film having a thickness of about 2 nm is formed on the surface of the silicon film. At this time, it is preferable that the nitriding treatment by the heat treatment and the high-density plasma treatment is continuously performed without being exposed to the atmosphere. By continuously performing the heat treatment and the high-density plasma treatment, contamination can be prevented and production efficiency can be improved.

Note that when an object to be processed (the substrate 100 in this example) is oxidized by high-density plasma treatment, an atmosphere containing oxygen (eg, oxygen (O ₂ ) or dinitrogen monoxide (N ₂ O) and a rare gas is used. (Including at least one of He, Ne, Ar, Kr, and Xe) or in an atmosphere of oxygen or dinitrogen monoxide and hydrogen (H ₂ ) and a rare gas). On the other hand, when nitriding an object to be processed by high-density plasma treatment, in an atmosphere containing nitrogen (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe)) Plasma treatment is performed in an atmosphere, nitrogen, hydrogen, and a rare gas atmosphere, or NH ₃ and a rare gas atmosphere.

As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. When the high-density plasma treatment is performed in a rare gas atmosphere, the first insulating layers 112, 114, 116, and 118 are formed of at least one of rare gases (He, Ne, Ar, Kr, and Xe) used for the plasma treatment. In the case of using Ar, the first insulating layers 112, 114, 116, and 118 may contain Ar.

The high-density plasma treatment is performed in an atmosphere of the above gas at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and an electron temperature of plasma of 1.5 eV or less. More specifically, the electron density is 1 × 10 ¹¹ cm ^{−3 to} 1 × 10 ¹³ cm ⁻³ and the plasma electron temperature is 0.5 eV to 1.5 eV. Since the electron density of the plasma is high and the electron temperature in the vicinity of the object to be processed (the substrate 100 in this example) formed on the substrate 100 is low, damage to the object to be processed can be prevented. . In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1.5 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. As a frequency for forming plasma, a high frequency such as a microwave (eg, 2.45 GHz) can be used.

In this embodiment, when an object to be processed is oxidized by high-density plasma treatment, a mixed gas of oxygen (O ₂ ), hydrogen (H ₂ ), and argon (Ar) is introduced. The mixed gas used here may be introduced with oxygen at 0.1 sccm to 100 sccm, hydrogen at 0.1 sccm to 100 sccm, and argon at 100 sccm to 5000 sccm. Note that the mixed gas is preferably introduced at a ratio of oxygen: hydrogen: argon = 1: 1: 100. For example, oxygen may be introduced at 5 sccm, hydrogen at 5 sccm, and argon at 500 sccm.

In addition, when performing nitriding treatment by high-density plasma treatment, a mixed gas of nitrogen (N ₂ ) and argon (Ar) is introduced. The mixed gas used here may be introduced at 20 sccm to 2000 sccm for nitrogen and 100 sccm to 10000 sccm for argon. For example, nitrogen may be introduced at 200 sccm and argon at 1000 sccm.

In this embodiment, in the substrate 100, the first insulating layer 116 formed over the region 108 provided in the memory portion functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating layer 116 is, the easier it is for the tunnel current to flow and the higher speed operation of the memory becomes possible. Further, as the thickness of the first insulating layer 116 is thinner, charges can be accumulated in a floating gate formed later at a lower voltage, so that power consumption of the nonvolatile semiconductor memory device can be reduced. . Therefore, the first insulating layers 112, 114, 116, and 118 are preferably formed thin.

The charge storage layers 120 and 123 are formed by a stacked structure of a film containing germanium such as germanium (Ge) or a silicon germanium alloy and a film containing silicon (Si). In this example, a plasma CVD method is performed in the atmosphere containing a germanium element (for example, GeH ₄ ) as the charge storage layer 120, so that a film containing germanium as a main component is 1 nm to 20 nm, preferably 1 nm to 10 nm. After forming the film, a plasma CVD method is performed in an atmosphere containing silicon element (for example, SiH ₄ ) as the charge storage layer 123, so that a film containing silicon as a main component is 1 nm to 50 nm, preferably 1 nm to 20 nm. By forming, a stacked structure of germanium and silicon is provided. In this manner, a single crystal silicon substrate is used as the substrate 100, and a film containing germanium having an energy gap smaller than that of silicon is formed on a certain region of the silicon substrate via a first insulating layer functioning as a tunnel oxide film. The second barrier formed by the first insulating layer for the charge in the charge storage layer is energy relative to the first barrier formed by the first insulating layer for the charge in a certain region of the silicon substrate. Become expensive. As a result, it is possible to easily inject charges from a region of the silicon substrate into the charge storage layer, and it is possible to prevent the charge from disappearing from the charge storage layer. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. In addition, in the substrate 100, a stacked structure including the charge storage layer 120 and the charge storage layer 123 formed over the region 108 provided in the memory portion functions as a floating gate in a nonvolatile memory element to be completed later. Alternatively, a film containing germanium and a silicon germanium alloy may be sequentially stacked.

Next, the first insulating layers 112, 114, and 118 and the charge storage layers 120 and 123 formed over the regions 104, 106, and 110 of the substrate 100 are selectively removed, and formed over the region 108. The stacked structure including the first insulating layer 116, the charge storage layer 120, and the charge storage layer 123 is left. In this example, in the substrate 100, the stacked structure including the first insulating layer 116, the charge storage layer 120, and the charge storage layer 123 in the region 108 provided in the memory portion is selectively covered with a resist, and the regions 104, 106, The stacked structure including the first insulating layers 112, 114, and 118, the charge storage layer 120, and the charge storage layer 123 formed over 110 is selectively removed by etching (see FIG. 17B).

Next, a resist 122 is formed so as to selectively cover a part of the stacked structure including the regions 104, 106, and 110 of the substrate 100 and the charge storage layer 120 and the charge storage layer 123 formed above the region 108. The charge storage layers 120 and 123 not covered with the resist 122 are selectively removed by etching, so that a part of the stacked structure including the charge storage layer 120 and the charge storage layer 123 remains, and the charge storage layer A stacked structure including 121 and a charge storage layer 125 functioning as a floating gate is formed (see FIG. 17C).

Next, an impurity region is formed in a specific region of the region 110 of the substrate 100. In this example, after removing the resist 122, a resist 124 is formed so as to selectively cover the regions 104, 106, and 108 and part of the region 110, and an impurity element is applied to the region 110 not covered with the resist 124. By introducing the impurity region 126, an impurity region 126 is formed (see FIG. 18A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is introduced into the region 110 as the impurity element.

Next, second insulation is performed so as to cover the stacked structure including the regions 104, 106, and 110 of the substrate 100, the first insulating layer 116 formed above the region 108, the charge storage layer 121, and the charge storage layer 125. The layer 128 is formed (see FIG. 18B).

The second insulating layer 128 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y> 0)), silicon nitride oxide (SiNxOy, (x> y>) using a CVD method, a sputtering method, or the like. 0)) or the like, and a single layer or a stacked layer. For example, when the second insulating layer 128 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 nm to 50 nm by a CVD method. In the case where the second insulating layer 128 is provided with a three-layer structure, a silicon oxynitride film is formed as the first insulating layer, a silicon nitride film is formed as the second insulating layer, A silicon oxynitride film is formed as the insulating layer. In addition, germanium oxide or nitride may be used for the second insulating layer 128.

Note that the second insulating layer 128 formed above the region 108 functions as a control insulating layer in a nonvolatile memory element to be completed later, and the second insulating layer 128 formed above the region 110 is used later. It functions as a gate insulating film in a completed transistor.

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the regions 108 and 110, and the second insulating layer 128 formed over the regions 104 and 106 is selectively formed. (See FIG. 18C).

Next, third insulating layers 132 and 134 are formed so as to cover the regions 104 and 106, respectively (see FIG. 19A).

The third insulating layers 132 and 134 are formed by any one of the methods described for forming the first insulating layers 112, 114, 116, and 118. For example, the third insulating layers 132 and 134 can be formed using a silicon oxide film by oxidizing the surfaces of the regions 104 and 106 provided in the substrate 100 by performing heat treatment. In addition, after a silicon oxide film is formed by a thermal oxidation method, a surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

In addition, as described above, the third insulating layers 132 and 134 may be formed by plasma treatment. For example, the surface of the regions 104 and 106 provided on the substrate 100 is subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, so that a silicon oxide (SiOx) film or silicon nitride (SiNx) is formed as the third insulating layers 132 and 134. ) It can be formed with a film. In addition, after performing oxidation treatment on the surfaces of the regions 104 and 106 by high-density plasma treatment, nitridation treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 104 and 106, a (silicon oxynitride film) is formed over the silicon oxide film, and the third insulating layers 132 and 134 are formed using the silicon oxide film and the oxynitride film. It becomes a film in which a silicon film is laminated. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 104 and 106 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

Note that when the third insulating layers 132 and 134 are formed by thermal oxidation or high-density plasma treatment, the surface of the second insulating layer 128 formed above the regions 108 and 110 of the substrate 100 is also oxidized. A film or an oxynitride film may be formed. In addition, the third insulating layers 132 and 134 formed in the regions 104 and 106 of the substrate 100 function as a gate insulating film in a transistor to be completed later.

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the regions 104 and 106 and the second insulating layer 128 formed above the regions 108 and 110 (FIG. 19). (See (B)). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

The conductive films 136 and 138 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

In this example, the conductive film 136 is formed using tantalum nitride, and the conductive film 138 is formed using tungsten over the stacked structure. In addition, a single layer or stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used as the conductive film 136, and a single layer or stacked film selected from tantalum, molybdenum, or titanium is used as the conductive film 138. Can be used.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left in portions above the regions 104, 106, 108, and 110, respectively. Conductive films 140, 142, 144, and 146 which function as gate electrodes are formed (see FIG. 19C). Note that the conductive film 144 formed over the region 108 provided in the memory portion in the substrate 100 functions as a control gate in a nonvolatile memory element to be completed later. In addition, the conductive films 140, 142, and 146 function as gate electrodes in transistors that are completed later.

Next, a resist 148 is selectively formed so as to cover the region 104, and an impurity region is formed by introducing an impurity element into the regions 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 20A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 20A, an impurity region 152 and a channel formation region 150 which form a source region or a drain region are formed in the region 106 by introducing an impurity element. In the region 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the region 110, an impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

In addition, the low-concentration impurity region 158 formed in the region 108 is formed by the impurity element introduced in FIG. 20A penetrating through a stacked structure including the charge accumulation layer 121 and the charge accumulation layer 125 which function as a floating gate. Is done. Accordingly, in the region 108, a channel formation region 154 is formed in a region overlapping with both of the stacked structure including the conductive film 144, the charge storage layer 121, and the charge storage layer 125, and the stacked structure including the charge storage layer 121 and the charge storage layer 125. A low-concentration impurity region 158 is formed in a region that does not overlap with the conductive film 144, and a high-concentration impurity region 156 is formed in a region that does not overlap with both the stacked structure including the charge storage layer 121 and the charge storage layer 125 and the conductive film 144. Is done.

Next, a resist 166 is selectively formed so as to cover the regions 106, 108, and 110, and impurity regions are formed by introducing an impurity element into the region 104 using the resist 166 and the conductive film 140 as a mask (FIG. 20). (See (B)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the regions 106, 108, and 110 in FIG. 20A is introduced. As a result, an impurity region 170 for forming a source region or a drain region and a channel formation region 168 are formed in the region 104.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the regions 104, 106, A conductive film 174 that is electrically connected to the impurity regions 170, 152, 156, and 162 formed in the regions 108 and 110 is formed (see FIG. 20C).

The insulating layer 172 is formed by CVD, sputtering, or the like using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)). An insulating layer having oxygen or nitrogen such as a film, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin A single layer or a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

The conductive film 174 is formed by a CVD method, a sputtering method, or the like by aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper ( Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 174 has, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. Adopt it. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the conductive film 174 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor substrate to the floating gate electrode, and it is possible to prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a nonvolatile semiconductor memory device different from that in Embodiment 1 will be described with reference to drawings. In addition, when referring to the same thing as the said Example, it shows using the same code | symbol and abbreviate | omits description. In FIGS. 21 to 23, between AB and CD are transistors provided in the logic portion, between EF are nonvolatile memory elements provided in the memory portion, and between GH are A transistor provided in the memory portion is shown. In this embodiment, a transistor provided between A and B is a p-channel type, a transistor provided between C and D, a transistor provided between GH is an n channel type, and a carrier of a nonvolatile memory element provided between EF However, the nonvolatile semiconductor device of the present invention is not limited to this.

First, up to FIG. 17C, after the formation, the resist 122 is removed, and the regions 104, 106, 110, the first insulating layer 116 formed above the region 108, and the charge accumulation functioning as a floating gate are formed. A second insulating layer 128 is formed so as to cover the stacked structure including the layer 121 and the charge storage layer 125 (see FIG. 21A).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the regions 108 and 110, and the second insulating layer 128 formed over the regions 104 and 106 is selectively formed. (See FIG. 21B).

Next, third insulating layers 132 and 134 are formed so as to cover the regions 104 and 106, respectively (see FIG. 21C).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the regions 104 and 106 and the second insulating layer 128 formed above the regions 108 and 110 (FIG. 22). (See (A)). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left in portions above the regions 104, 106, 108, and 110, respectively. Conductive films 140, 142, 144, and 146 that function as gate electrodes are formed (see FIG. 22B). Note that the conductive film 140 includes conductive films 182 a and 184 a provided by being stacked using the remaining conductive films 136 and 138. In this embodiment, the width of the conductive film 182a formed below in the conductive film 140 (width with respect to a direction substantially parallel to the direction in which carriers flow in the channel formation region (the direction connecting the source region and the drain region)). The width is larger than the width of the conductive film 184a. Similarly, the conductive film 142 is formed by sequentially stacking a conductive film 182b and a width 184b smaller than the conductive film 182b, and the conductive film 144 is formed by sequentially stacking a conductive film 182c and a width 184c smaller than the conductive film 182c. In the conductive film 146, the conductive film 182d and the conductive film 182d having a smaller width than the conductive film 182d are sequentially stacked.

Next, a resist 148 is selectively formed so as to cover the region 104, and an impurity region is formed by introducing an impurity element into the regions 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 22C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 22C, a high concentration impurity region 152 for forming a source region or a drain region, a low concentration impurity region 186 for forming an LDD region, and a channel formation region 150 are formed in the region 106 by introducing an impurity element. Is done. In the region 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the region 110, a high-concentration impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

The low-concentration impurity region 186 formed in the region 106 is formed when the impurity element introduced in FIG. 22C penetrates the conductive film 182b. Accordingly, in the region 106, a channel formation region 150 is formed in a region overlapping with both the conductive film 182b and the conductive film 184b, and a low-concentration impurity region 186 is formed in a region overlapping with the conductive film 182b and not overlapping with the conductive film 184b. A high concentration impurity region 152 is formed in a region that does not overlap with both the film 182b and the conductive film 184b.

The low concentration impurity region 158 formed in the region 108 is formed when the impurity element introduced in FIG. 22C penetrates the stacked structure including the charge accumulation layer 121 and the charge accumulation layer 125. Accordingly, in the region 108, the channel formation region 154 is formed in a region overlapping with both of the stacked structure including the conductive film 182 c and the charge storage layer 121 and the charge storage layer 125, and the stacked structure including the charge storage layer 121 and the charge storage layer 125. A low-concentration impurity region 158 is formed in a region that does not overlap with the conductive film 182c, and a high-concentration impurity region 156 is formed in a region that does not overlap with both the stacked structure including the charge storage layer 121 and the charge storage layer 125 and the conductive film 182c. Is done. Note that in the case where the conductive film 182c is formed thin, the region 108 overlaps with both the stacked structure including the conductive film 182c, the charge storage layer 121, and the charge storage layer 125 and does not overlap with the conductive film 184c. In some cases, a low-concentration impurity region having a concentration equal to or lower than that of the concentration impurity region 158 may be formed.

The low-concentration impurity region 164 formed in the region 110 is formed by the impurity element introduced in FIG. 22C penetrating through the conductive film 182d. Accordingly, in the region 110, a channel formation region 160 is formed in a region overlapping with both the conductive film 182d and the conductive film 184d, and a low-concentration impurity region 164 is formed in a region overlapping with the conductive film 182d and not overlapping with the conductive film 184d. A high concentration impurity region 162 is formed in a region that does not overlap with both the film 182d and the conductive film 184d.

Next, a resist 166 is selectively formed so as to cover the regions 106, 108, and 110, and an impurity region is formed by introducing an impurity element into the region 104 using the resist 166 and the conductive film 140 as a mask (FIG. 23). (See (A)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the regions 106, 108, and 110 in FIG. 22C is introduced. As a result, a high concentration impurity region 170 that forms a source region or a drain region, a low concentration impurity region 188 that forms an LDD region, and a channel formation region 168 are formed in the region 104.

The low-concentration impurity region 188 formed in the region 104 is formed by the impurity element introduced in FIG. 22C penetrating through the conductive film 182a. Accordingly, in the region 104, a channel formation region 168 is formed in a region overlapping with both the conductive film 182a and the conductive film 184a, and a low concentration impurity region 188 is formed in a region overlapping with the conductive film 182a and not overlapping with the conductive film 184a. A high concentration impurity region 170 is formed in a region that does not overlap with both the film 182a and the conductive film 184a.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the regions 104, 106, A conductive film 174 that is electrically connected to the impurity regions 170, 152, 156, and 162 formed in the regions 108 and 110 is formed (see FIG. 23B).

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor substrate to the floating gate electrode, and it is possible to prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a nonvolatile semiconductor memory device different from that in Embodiment 1 or 2 will be described with reference to drawings. In addition, when referring to the same thing as the said Example 1 or 2, it shows using the same code | symbol and abbreviate | omits description. Note that in FIGS. 27 to 29, between AB and CD are transistors provided in the logic portion, between EF are nonvolatile memory elements provided in the memory portion, and between GH are A transistor provided in the memory portion is shown. In this embodiment, a transistor provided between A and B is a p-channel type, a transistor provided between C and D, a transistor provided between GH is an n channel type, and a carrier of a nonvolatile memory element provided between EF However, the nonvolatile semiconductor device of the present invention is not limited to this.

First, after the formation up to FIG. 17C of the first embodiment, an impurity region 190 is formed by introducing an impurity element into the region 108 using the resist 122 as a mask (see FIG. 27A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is introduced into the region 108 as the impurity element.

Next, the second insulating layer 128 is formed so as to cover the stacked structure including the regions 104, 106, 110, the first insulating layer 116 formed above the region 108, the charge storage layer 121, and the charge storage layer 125. It is formed (see FIG. 27B).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the regions 108 and 110, and the second insulating layer 128 formed over the regions 104 and 106 is selectively formed. (See FIG. 27C).

Next, third insulating layers 132 and 134 are formed so as to cover the regions 104 and 106, respectively (see FIG. 28A).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the regions 104 and 106 and the second insulating layer 128 formed above the regions 108 and 110 (FIG. 28). (See (B)). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left in portions above the regions 104, 106, 108, and 110, respectively. Conductive films 140, 142, 144, and 146 that function as gate electrodes are formed (see FIG. 28C).

Note that in this embodiment, the conductive film 144 formed over the region 108 includes a charge storage layer 121 and a charge storage layer 125 including a width of a stacked structure (at least with respect to a direction substantially parallel to a direction in which carriers flow through a channel). Is also formed to be large.

Next, a resist 148 is selectively formed so as to cover the region 104, and an impurity region is formed by introducing an impurity element into the regions 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 29A). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 29A, a high concentration impurity region 152 and a channel formation region 150 which form a source region or a drain region are formed in the region 106 by introducing an impurity element. In the region 108, an impurity region 156 that forms a source region or a drain region, a low-concentration impurity region 158 that forms an LDD region, and a channel formation region 154 are formed. In the region 110, a high-concentration impurity region 162 that forms a source region or a drain region and a channel formation region 160 are formed.

Next, a resist 166 is selectively formed so as to cover the regions 106, 108, and 110, and impurity regions are formed by introducing an impurity element into the region 104 using the resist 166 and the conductive film 140 as a mask (FIG. 29). (See (B)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the regions 106, 108, and 110 in FIG. 29A is introduced. As a result, a high concentration impurity region 170 for forming a source region or a drain region and a channel formation region 168 are formed in the region 104.

Next, an insulating layer 172 is formed so as to cover the second insulating layer 128, the third insulating layers 132 and 134, and the conductive films 140, 142, 144, and 146, and the regions 104, 106, A conductive film 174 that is electrically connected to the impurity regions 170, 152, 156, and 162 formed in the regions 108 and 110 is formed (see FIG. 29C).

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor substrate to the floating gate electrode, and it is possible to prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

This example can be implemented in combination with any of the other embodiments or examples shown in this specification.

In this embodiment, a method for manufacturing a nonvolatile semiconductor memory device, which is different from those of Embodiments 1 to 3, will be described with reference to drawings. In addition, when the same thing as what was shown in either of the said Example 1 thru | or 3 is pointed out, it uses the same code | symbol and abbreviate | omits description. Note that in FIGS. 24 to 26, between AB and CD are transistors provided in the logic portion, between EF are nonvolatile memory elements provided in the memory portion, and between GH are A transistor provided in the memory portion is shown. In this embodiment, a transistor provided between A and B is a p-channel type, a transistor provided between C and D, a transistor provided between GH is an n channel type, and a carrier of a nonvolatile memory element provided between EF However, the nonvolatile semiconductor device of the present invention is not limited to this.

First, after forming similarly to FIG. 17B, a resist is formed so as to selectively cover the regions 104, 106, and 108 and part of the region 110 as shown in FIG. An impurity region 126 is formed by introducing an impurity element into the region 110 not covered with the resist. Then, the resist is removed, and the regions 104, 106, 110, and the second insulating layer 116 formed above the region 108, the charge storage layer 120, and the stacked structure including the charge storage layer 123 are covered. The insulating layer 128 is formed (see FIG. 24A).

Next, a resist 130 is selectively formed so as to cover the second insulating layer 128 formed over the regions 108 and 110, and the second insulating layer 128 formed over the regions 104 and 106 is selectively formed. (See FIG. 24B).

Next, third insulating layers 132 and 134 are formed so as to cover the regions 104 and 106, respectively (see FIG. 24C).

Next, a conductive film is formed so as to cover the third insulating layers 132 and 134 formed above the regions 104 and 106 and the second insulating layer 128 formed above the regions 108 and 110 (FIG. 25). (See (A)). In this example, the conductive film 136 and the conductive film 138 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

Next, the conductive films 136 and 138 provided in a stacked manner are selectively etched and removed, so that the conductive films 136 and 138 are left in portions above the regions 104, 106, 108, and 110, respectively. Conductive films 140, 142, 144, and 146 functioning as gate electrodes are formed (see FIG. 25B). In this embodiment, the surfaces of the regions 104, 106, 108, and 110 that do not overlap with the conductive films 140, 142, 144, and 146 are exposed.

Specifically, in the region 104, a portion of the third insulating layer 132 formed below the conductive film 140 that does not overlap with the conductive film 140 is selectively removed, so that the conductive film 140 and the third insulating layer are removed. It is formed so that the end portions of 132 substantially coincide. Further, in the region 106, a portion of the third insulating layer 134 formed below the conductive film 142 that does not overlap with the conductive film 142 is selectively removed, so that edges of the conductive film 142 and the third insulating layer 134 are removed. The parts are formed so as to roughly match. In the region 108, the second insulating layer 128 formed below the conductive film 144, the stacked structure including the charge storage layer 120 and the charge storage layer 123, and the first insulating layer 116 overlaps with the conductive film 144. A portion not to be formed is selectively removed, and the conductive film 144 and the second insulating layer 128, the charge storage layer 121, the charge storage layer 125, and the stacked layer structure including the charge storage layer 125 and the end portion of the first insulating layer 116 are substantially matched. To do. Further, in the region 110, a portion of the second insulating layer 128 formed below the conductive film 146 that does not overlap with the conductive film 146 is selectively removed, so that end portions of the conductive film 146 and the second insulating layer 128 are removed. Are substantially matched.

In this case, a portion of the insulating layer that does not overlap with the formation of the conductive films 140, 142, 144, and 146 may be removed, or the resist remaining after the formation of the conductive films 140, 142, 144, and 146 or the conductive film may be removed. 140, 142, 144, and 146 may be used as a mask to remove portions of the insulating layer that do not overlap.

Next, a resist 148 is selectively formed so as to cover the region 104, and an impurity region is formed by introducing an impurity element into the regions 106, 108, and 110 using the resist 148 and the conductive films 142, 144, and 146 as masks. (See FIG. 25C). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, phosphorus (P) is used as the impurity element.

In FIG. 25C, an impurity element 152 and a channel formation region 150 which form a source region or a drain region are formed in the region 106 by introducing an impurity element. In the region 108, an impurity region 156 and a channel formation region 154 which form a source region or a drain region are formed. In the region 110, a high-concentration impurity region 162 that forms a source region or a drain region, a low-concentration impurity region 164 that forms an LDD region, and a channel formation region 160 are formed.

Next, a resist 166 is selectively formed so as to cover the regions 106, 108, and 110, and an impurity element is formed by introducing an impurity element into the region 104 using the resist 166 and the conductive film 140 as a mask (FIG. 26). (See (A)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, an impurity element (for example, boron (B)) having a conductivity type different from that of the impurity element introduced into the regions 106, 108, and 110 in FIG. 25C is introduced. As a result, an impurity region 170 for forming a source region or a drain region and a channel formation region 168 are formed in the region 104.

Note that in this embodiment, the impurity element is introduced in the state where the regions 104, 106, 108, and 110 that do not overlap with the conductive films 140, 142, 144, and 146 are exposed in FIG. 25C or FIG. It is carried out. Therefore, the channel formation regions 168, 150, 154, and 160 formed in the regions 104, 106, 108, and 110 can be formed in a self-aligned manner with the conductive films 140, 142, 144, and 146, respectively.

Next, an insulating layer 192 is formed so as to cover the exposed regions 104, 106, 108, and 110 and the conductive films 140, 142, 144, and 146 (see FIG. 26B).

The insulating layer 192 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)) by CVD or sputtering. The insulating layer having oxygen or nitrogen such as DLC (diamond-like carbon) or the like can be used to form a single layer or a stacked structure.

Next, an insulating layer 172 is formed so as to cover the insulating layer 192, and electrically connected to the impurity regions 170, 152, 156, and 162 formed in the regions 104, 106, 108, and 110 on the insulating layer 172, respectively. A conductive film 174 to be formed is formed (see FIG. 26C).

As the insulating layer 172, any of the materials described in Embodiment 1 can be used. For example, the insulating layer 192 includes oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), or silicon nitride oxide (SiNxOy, (x> y)). An insulating layer containing an inorganic material can be used, and the insulating layer 172 can be formed using an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic. Needless to say, both the insulating layer 192 and the insulating layer 172 may be formed using an insulating layer containing an inorganic material.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor substrate to the floating gate electrode, and it is possible to prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

Note that this example can be implemented in combination with any of the other embodiments and examples shown in this specification.

In this embodiment, a method for manufacturing a nonvolatile semiconductor memory device, which is different from the above embodiment, will be described with reference to drawings. 36, 38 and 39 are top views, FIGS. 30 to 35 are cross-sectional views taken along lines A-B and EF in FIGS. 36, 38 and 39, and FIG. Sectional drawing between CD in 38 and 39 is shown. A line between A and B shows a transistor and a non-volatile memory element provided in the memory part, a line between CD and a non-volatile memory element provided in the memory part, and a line between E and F a transistor provided in the logic part. Show. In this embodiment, the transistor provided in the region 212 of the substrate 200 between E and F is a p-channel type, the transistor provided in the region 213 is an n-channel type, and the region 214 of the substrate 200 between A and B is used. The case where the transistor provided in the transistor is an n-channel type and the carrier of the nonvolatile memory element is moved by electrons will be described; however, the nonvolatile semiconductor device of the present invention is not limited to this.

First, an insulating layer is formed over the substrate 200. In this example, single crystal silicon having n-type conductivity is used as the substrate 200, and the insulating layer 202 and the insulating layer 204 are formed over the substrate 200 (see FIG. 30A). For example, silicon oxide (SiOx) is formed as the insulating layer 202 by performing heat treatment on the substrate 200, and silicon nitride (SiNx) is formed over the insulating layer 202 by a CVD method.

The substrate 200 is not particularly limited as long as it is a semiconductor substrate. For example, an n-type or p-type single crystal silicon substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by Implanted) An SOI (Silicon on Insulator) substrate manufactured by an Oxygen method or the like can be used.

The insulating layer 204 may be provided by nitriding the insulating layer 202 by high-density plasma treatment after the insulating layer 202 is formed. Note that the insulating layer provided over the substrate 200 may be a single layer or a stacked structure including three or more layers.

Next, a pattern of a resist 206 is selectively formed over the insulating layer 204, and selective etching is performed using the resist 206 as a mask, whereby a recess 208 is selectively formed in the substrate 200 (FIG. 30B). )reference). Etching of the substrate 200 and the insulating layers 202 and 204 can be performed by dry etching using plasma.

Next, after removing the pattern of the resist 206, an insulating layer 210 is formed so as to fill the recess 208 formed in the substrate 200 (see FIG. 30C).

The insulating layer 210 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y> 0)), silicon nitride oxide (SiNxOy, (x> y> 0)) by a CVD method, a sputtering method, or the like. It is formed using an insulating material such as. In this example, as the insulating layer 210, a silicon oxide film is formed using TEOS (tetraethylorthosilicate) gas by an atmospheric pressure CVD method or a low pressure CVD method.

Next, the surface of the substrate 200 is exposed by performing a grinding process, a polishing process, or a CMP (Chemical Mechanical Polishing) process. In this example, by exposing the surface of the substrate 200, regions 212, 213, and 214 are provided between the insulating layers 211 formed in the recesses 208 of the substrate 200. The insulating layer 211 is obtained by removing the insulating layer 210 formed on the surface of the substrate 200 by grinding, polishing, or CMP. Subsequently, an impurity element having p-type conductivity is selectively introduced to form p-wells 215 in the regions 213 and 214 of the substrate 200 (FIGS. 31A, 36A, and 36B). ), FIG. 37 (A)).

As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. In this example, boron (B) is introduced into the regions 213 and 214 as an impurity element.

In this embodiment, since a semiconductor substrate having n-type conductivity is used as the substrate 200, no impurity element is introduced into the region 212. However, by introducing an impurity element exhibiting n-type conductivity, the region 212 is not introduced. An n-well may be formed in the region 212. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used.

On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 212 to form an n-well, and no impurity element is introduced into the regions 213 and 214. It is good.

Next, first insulating layers 216, 218, and 220 are formed over the regions 212, 213, and 214 provided in the substrate 200. Then, charge storage layers 222 and 227 that function as floating gates are stacked in the nonvolatile memory element to be completed later so as to cover the first insulating layers 216, 218, and 220 (see FIG. 31B).

The first insulating layers 216, 218, and 220 can be formed of a silicon oxide film by performing heat treatment to oxidize the surfaces of the regions 212, 213, and 214 provided in the substrate 200. In addition, after a silicon oxide film is formed by a thermal oxidation method, a surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. Can be formed with a structure.

In addition, as described above, the first insulating layers 216, 218, and 220 may be formed by plasma treatment. For example, when oxidation or nitridation is performed on the surfaces of the regions 212, 213, and 214 provided in the substrate 200 by high-density plasma treatment, a silicon oxide (SiOx) film or a first insulating layer 216, 218, or 220 is used. A silicon nitride (SiNx) film is formed. In addition, after performing oxidation treatment on the surfaces of the regions 212, 213, and 214 by high-density plasma treatment, nitridation treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 212, 213, and 214, a (silicon oxynitride film) is formed over the silicon oxide film, and the first insulating layers 216, 218, and 220 are formed of silicon oxide. A film and a silicon oxynitride film are stacked. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 212, 213, and 214 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

In this embodiment, the first insulating layer 220 formed over the region 214 provided in the memory portion in the substrate 200 functions as a tunnel oxide film in a nonvolatile memory element completed later. Therefore, the thinner the first insulating layer 220 is, the more easily the tunnel current flows, and the memory can operate at high speed. In addition, the thinner the first insulating layer 220 is, the more charge can be accumulated in the stacked structure including the charge accumulation layer 222 and the charge accumulation layer 227 that function as floating gates. The power consumption of the semiconductor memory device can be reduced. Therefore, the first insulating layer 220 is preferably formed thin.

The charge storage layers 222 and 227 are formed by a stacked structure of a film containing germanium such as germanium (Ge) or a silicon germanium alloy and a film containing silicon (Si). In this example, a plasma CVD method is performed as the charge storage layer 222 in an atmosphere containing a germanium element (for example, GeH ₄ ), so that a film containing germanium as a main component is 1 nm to 20 nm, preferably 1 nm to 10 nm. Then, a plasma CVD method is performed in an atmosphere containing silicon element (for example, SiH ₄ ) as the charge storage layer 227, so that a film containing silicon as a main component is 1 nm to 50 nm, preferably 1 nm to 20 nm. By forming, a stacked structure of germanium and silicon is provided. In this manner, a single crystal silicon substrate is used as the substrate 200, and a film containing germanium having an energy gap smaller than that of silicon is formed on a certain region of the silicon substrate via a first insulating layer functioning as a tunnel oxide film. The second barrier formed by the first insulating layer for the charge in the charge storage layer is energy relative to the first barrier formed by the first insulating layer for the charge in a certain region of the silicon substrate. Become expensive. As a result, it is possible to easily inject charges from a region of the silicon substrate into the charge storage layer, and it is possible to prevent the charge from disappearing from the charge storage layer. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. In addition, a stacked structure including the charge storage layer 222 and the charge storage layer 227 formed over the region 214 provided in the memory portion in the substrate 200 functions as a floating gate in a nonvolatile memory element to be completed later.

Next, a resist 223 is formed over the stacked structure including the charge storage layer 222 and the charge storage layer 227, and the stacked structure including the charge storage layer 222 and the charge storage layer 227 with the resist 223 as a mask, and the first insulating layer 216, 218, 220 are selectively removed. In this example, a resist 223 is formed so as to cover a part of the region 214 in the substrate 200, a stacked structure including the charge storage layer 222 and the charge storage layer 227 not covered with the resist 223, and the first insulating layer 216. 218, 220 are left, so that a stacked structure including a part of the first insulating layer 220 provided in the region 214, the charge storage layer 222, and the charge storage layer 227 remains, and the first insulating layer 224, A stacked structure including the charge storage layer 226 and the charge storage layer 229 is employed (see FIG. 31C). Specifically, a stacked structure including the first insulating layer 220, the charge storage layer 222, and the charge storage layer 227 provided in a region where the nonvolatile memory element is to be formed later is left in the region 214. In addition, a part of the surfaces of the regions 212 and 213 and the region 214 of the substrate 200 is exposed.

Next, a second insulating layer 228 is formed so as to cover the stacked structure including the regions 212, 213, and 214, the charge storage layer 226, and the charge storage layer 229 of the substrate 200 (see FIG. 32A).

The second insulating layer 228 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiOxNy, (x> y> 0)), silicon nitride oxide (SiNxOy, (x> y>) using a CVD method, a sputtering method, or the like. 0)) or the like, and a single layer or a stacked layer. For example, in the case where the second insulating layer 228 is provided as a single layer, a silicon oxynitride film or a silicon nitride oxide film is formed with a thickness of 5 nm to 50 nm by a CVD method. In the case where the second insulating layer 228 is provided in a three-layer structure, a silicon oxynitride film is formed as the first insulating layer, a silicon nitride film is formed as the second insulating layer, and the third insulating layer 228 is formed. A silicon oxynitride film is formed as the insulating layer.

Note that the second insulating layer 228 formed over the stacked structure including the charge storage layer 226 and the charge storage layer 229 in the region 214 of the substrate 200 functions as a control insulating layer in a nonvolatile memory element to be completed later. The second insulating layer formed in the exposed region 214 of the part functions as a gate insulating film in a transistor to be completed later.

Next, a resist 230 is selectively formed so as to cover the second insulating layer 228 formed in the region 214 of the substrate 200, and the second insulating layer 228 formed in the regions 212 and 213 of the substrate 200 is selected. (See FIG. 32B).

Next, third insulating layers 232 and 234 are formed over the surfaces of the regions 212 and 213 of the substrate 200, respectively (see FIG. 32C).

The third insulating layers 232 and 234 are formed using any one of the methods described for forming the first insulating layers 216, 218, and 220. For example, the third insulating layers 232 and 234 can be formed using silicon oxide films by oxidizing the surfaces of the regions 212 and 213 provided in the substrate 200 by performing heat treatment. In addition, after a silicon oxide film is formed by a thermal oxidation method, a surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

In addition, as described above, the third insulating layers 232 and 234 may be formed by plasma treatment. For example, the surface of the regions 212 and 213 provided in the substrate 200 is subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, whereby a silicon oxide (SiOx) film or silicon nitride (SiNx) is formed as the third insulating layers 232 and 234. ) It can be formed with a film. Alternatively, the surface of the regions 212 and 213 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 212 and 213, a (silicon oxynitride film) is formed over the silicon oxide film, and the third insulating layers 232 and 234 are formed of a silicon oxide film and an oxynitride film. It becomes a film in which a silicon film is laminated. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 212 and 213 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

Note that when the third insulating layers 232 and 234 are formed by thermal oxidation or high-density plasma treatment, an oxide film or a surface of the second insulating layer 228 formed over the region 214 of the substrate 200 is also formed. An oxynitride film may be formed. In addition, the third insulating layers 232 and 234 formed in the regions 212 and 213 of the substrate 200 function as a gate insulating film in a transistor to be completed later.

Next, a conductive film is formed so as to cover the third insulating layers 232 and 234 formed above the regions 212 and 213 provided on the substrate 200 and the second insulating layer 228 formed above the region 214. (See FIG. 33A). In this example, a conductive film 236 and a conductive film 238 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

The conductive films 236 and 238 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

In this example, the conductive film 236 is formed using tantalum nitride, and the conductive film 238 is formed using tungsten in a stacked structure. In addition, the conductive film 236 is a single layer or stacked film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride, and the conductive film 238 is selected from tungsten, tantalum, molybdenum, or titanium. A single layer or a laminated film can be used.

Next, the conductive films 236 and 238 provided by stacking are selectively etched and removed, so that the conductive films 236 and 238 are left in portions above the regions 212, 213, and 214 of the substrate 200. Conductive films 240, 242, 244, and 246 that function as gate electrodes are formed (see FIGS. 33B and 37B). In this example, in the substrate 200, the surfaces of the regions 212, 213, and 214 that do not overlap with the conductive films 240, 242, 244, and 246 are exposed. Note that the conductive film 246 functions as a control gate in a nonvolatile memory element to be completed later. The conductive films 240, 242, and 244 function as gate electrodes in transistors that are completed later.

Specifically, in the region 212 of the substrate 200, a portion of the third insulating layer 232 formed below the conductive film 240 that does not overlap with the conductive film 240 is selectively removed, so that the conductive film 240 and the third conductive layer 240 are removed. The insulating layer 232 is formed so that the end portions thereof substantially coincide with each other. Further, in the region 213 of the substrate 200, a portion of the third insulating layer 234 formed below the conductive film 242 that does not overlap with the conductive film 242 is selectively removed, so that the conductive film 242 and the third insulating layer are removed. It forms so that the edge part of 234 may correspond substantially. Further, in the region 214 of the substrate 200, a portion of the second insulating layer 228 formed below the conductive film 244 that does not overlap with the conductive film 244 is selectively removed, so that the conductive film 244 and the second insulating layer 228 are removed. Are formed so that their end portions substantially coincide. In addition, in the region 214 of the substrate 200, a stacked structure including the second insulating layer 228, the charge storage layer 226, and the charge storage layer 229 formed below the conductive film 246, and the conductive film of the first insulating layer 224. A portion that does not overlap with the conductive layer 246 is selectively removed, and the stacked structure including the conductive film 246, the second insulating layer 228, the charge storage layer 226, and the charge storage layer 229 and the end portion of the first insulating layer 224 substantially coincide with each other. To form.

In this case, a portion of the insulating layer that does not overlap with the formation of the conductive films 240, 242, 244, and 246 may be removed, or the resist remaining after the formation of the conductive films 240, 242, 244, and 246 or the conductive film may be removed. The portions of the insulating layer that do not overlap may be removed using 240, 242, 244, and 246 as masks.

Next, an impurity element is selectively introduced into the regions 212, 213, and 214 of the substrate 200 (see FIG. 33C). In this example, a low-concentration impurity element imparting n-type conductivity is selectively introduced into the regions 213 and 214 using the conductive films 242, 244 and 246 as masks, and p-type is imparted to the regions 212 using the conductive film 240 as a mask. A low-concentration impurity element is selectively introduced. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

Next, an insulating layer 254 (also referred to as a sidewall) in contact with the side surfaces of the conductive films 240 242 244 246 is formed. Specifically, a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin is formed in a single layer or stacked layers by a plasma CVD method, a sputtering method, or the like. Form. Then, the insulating layer can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 240 242 244 246. Note that the insulating layer 254 is used as a doping mask when an LDD (Lightly Doped Drain) region is formed. In this example, the insulating layer 254 is formed so as to be in contact with the side surfaces of the insulating layer and the charge storage layer formed below the conductive films 240, 242, 244, and 246.

Subsequently, an impurity element functioning as a source region or a drain region is formed by introducing an impurity element into the regions 212, 213, and 214 of the substrate 200 using the insulating layer 254 and the conductive films 240, 242, 244, and 246 as masks. (See FIGS. 34A, 38A, and 38B). In this example, a high concentration n-type impurity element is introduced into the regions 213 and 214 of the substrate 200 using the insulating layer 254 and the conductive films 242, 244 and 246 as masks, and the insulating layer 254 and the conductive film 240 are introduced into the region 212. As a mask, an impurity element imparting a high concentration of p-type is introduced.

As a result, an impurity region 258 that forms a source region or a drain region, a low-concentration impurity region 260 that forms an LDD region, and a channel formation region 256 are formed in the region 212 of the substrate 200. In the region 213 of the substrate 200, an impurity region 264 that forms a source region or a drain region, a low-concentration impurity region 266 that forms an LDD region, and a channel formation region 262 are formed. In the region 214 of the substrate 200, impurity regions 270 that form source or drain regions, low-concentration impurity regions 272 and 276 that form LDD regions, and channel formation regions 268 and 274 are formed.

Note that in this embodiment, the impurity element is introduced in a state where the regions 212, 213, and 214 of the substrate 200 that do not overlap with the conductive films 240, 242, 244, and 246 are exposed. Accordingly, the channel formation regions 256, 262, 268, and 274 formed in the regions 212, 213, and 214 of the substrate 200 can be formed in a self-alignment manner with the conductive films 240, 242, 244, and 246, respectively.

Next, an insulating layer 277 is formed so as to cover an insulating layer, a conductive film, or the like provided over the regions 212, 213, and 214 of the substrate 200, and an opening 278 is formed in the insulating layer 277 (FIG. 34B )reference).

The insulating layer 277 is formed by silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy, (x> y)), silicon nitride oxide (SiNxOy, (x> y)) by CVD or sputtering. An insulating layer having oxygen or nitrogen such as a film, a film containing carbon such as DLC (diamond-like carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin A single layer or a stacked structure can be provided. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

Next, a conductive film 280 is formed in the opening 278 by a CVD method, and conductive films 282a to 282d are selectively formed over the insulating layer 277 so as to be electrically connected to the conductive film 280 (FIG. 35). 39 (A), (B), and FIG. 37 (C)).

The conductive films 280, 282a to 282d are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) by CVD or sputtering. ), Copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements as main components An alloy material or a compound material to be formed is a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive films 280, 282a to 282d include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride (TiN) film, and a barrier film. It is good to adopt the laminated structure of. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive films 280 and 282a to 282d because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made. In this example, the conductive films 280 and 282a to 282d can be formed by selectively growing tungsten (W) by a CVD method.

Through the above steps, a p-type transistor formed in the region 212 of the substrate 200, an n-type transistor formed in the region 213, and an n-type transistor and a nonvolatile memory element formed in the region 214 are provided. A non-volatile semiconductor memory device can be obtained.

In the nonvolatile semiconductor memory device of this embodiment, power consumption can be reduced by changing the thickness of the gate insulating layer in the transistor in accordance with the circuit configuration. In addition, the operation of the nonvolatile semiconductor memory device can be stabilized. Specifically, by reducing the thickness of the gate insulating layer of a transistor included in the logic portion, variation in threshold voltage can be reduced and driving with a low voltage is possible. By increasing the thickness of the gate insulating layer of the selection transistor in the memory portion, the operation stability is improved even when a higher voltage is applied than in the logic portion in the writing and erasing operations for the nonvolatile memory element. Can do. In the nonvolatile memory element, it is possible to easily inject charges from the semiconductor substrate to the floating gate electrode, and it is possible to prevent the charge from disappearing from the floating gate electrode. That is, when operating as a memory, high-efficiency writing can be performed at a low voltage, and charge retention characteristics can be improved. According to the present embodiment, it is possible to manufacture a nonvolatile semiconductor memory device having such excellent effects in a continuous process.

Note that this example can be implemented in combination with any of the other embodiments and examples shown in this specification.

In this embodiment, an application example of a semiconductor device including the above-described nonvolatile semiconductor memory device of the present invention and capable of inputting and outputting data without contact will be described with reference to the drawings. A semiconductor device in which data can be input / output without contact is also referred to as an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, or a wireless chip depending on the application.

The semiconductor device 800 has a function of exchanging data without contact, and controls a high frequency circuit 810, a power supply circuit 820, a reset circuit 830, a clock generation circuit 840, a data demodulation circuit 850, a data modulation circuit 860, and other circuits. A control circuit 870, a memory circuit 880, and an antenna 890 are provided (FIG. 40A). The high frequency circuit 810 receives a signal from the antenna 890. The high frequency circuit 810 is a circuit that outputs a signal received from the data modulation circuit 860 to the antenna 890. The power supply circuit 820 is a circuit that generates a power supply potential from a reception signal, the reset circuit 830 is a circuit that generates a reset signal, and the clock generation circuit 840 generates various clock signals based on the reception signal input from the antenna 890. The data demodulating circuit 850 is a circuit that demodulates the received signal and outputs the demodulated signal to the control circuit 870. The data modulation circuit 860 is a circuit that modulates the signal received from the control circuit 870. As the control circuit 870, for example, a code extraction circuit 910, a code determination circuit 920, a CRC determination circuit 930, and an output unit circuit 940 are provided. The code extraction circuit 910 is a circuit that extracts a plurality of codes included in the instruction sent to the control circuit 870, and the code determination circuit 920 compares the extracted code with a code corresponding to a reference. The CRC determination circuit 930 is a circuit that detects the presence or absence of a transmission error or the like based on the determined code.

Next, an example of operation of the above-described semiconductor device will be described. First, a radio signal is received by the antenna 890. The wireless signal is sent to the power supply circuit 820 via the high frequency circuit 810, and a high power supply potential (hereinafter referred to as VDD) is generated. VDD is supplied to each circuit included in the semiconductor device 800. The signal sent to the data demodulation circuit 850 via the high frequency circuit 810 is demodulated (hereinafter, demodulated signal). Further, a signal and a demodulated signal that have passed through the reset circuit 830 and the clock generation circuit 840 via the high frequency circuit 810 are sent to the control circuit 870. The signal sent to the control circuit 870 is analyzed by the code extraction circuit 910, the code determination circuit 920, the CRC determination circuit 930, and the like. Then, information on the semiconductor device stored in the memory circuit 880 is output in accordance with the analyzed signal. The output semiconductor device information is encoded through the output unit circuit 940. Further, the encoded information of the semiconductor device 800 passes through the data modulation circuit 860 and is transmitted on the radio signal by the antenna 890. Note that a low power supply potential (hereinafter referred to as VSS) is common in the plurality of circuits included in the semiconductor device 800, and VSS can be GND. Further, the nonvolatile semiconductor memory device of the present invention can be applied to the memory circuit 880. In the nonvolatile semiconductor memory device of the present invention, since the driving voltage can be lowered, it is possible to extend the distance in which data can be communicated without contact.

As described above, by transmitting a signal from the reader / writer to the semiconductor device 800 and receiving the signal transmitted from the semiconductor device 800 by the reader / writer, the data of the semiconductor device can be read.

Further, the semiconductor device 800 may be of a type in which the power supply voltage is supplied to each circuit by an electromagnetic wave without mounting the power source (battery), or each circuit is mounted by the electromagnetic wave and the power source (battery). It is good also as a type which supplies a power supply voltage to.

Next, an example of a usage pattern of a semiconductor device capable of inputting and outputting data without contact will be described. A reader / writer 3200 is provided on the side surface of the portable terminal including the display portion 3210, and a semiconductor device 3230 is provided on the side surface of the article 3220 (FIG. 40B). When the reader / writer 3200 is held over the semiconductor device 3230 included in the product 3220, information about the product such as the description of the product, such as the raw material and origin of the product, the inspection result for each production process and the history of the distribution process, is displayed on the display unit 3210. Is done. Further, when the product 3260 is conveyed by the belt conveyor, the product 3260 can be inspected using the reader / writer 3240 and the semiconductor device 3250 provided in the product 3260 (FIG. 40C). In this manner, by using a semiconductor device in the system, information can be easily acquired, and high functionality and high added value are realized.

In addition, the nonvolatile semiconductor memory device of the present invention can be used for electronic devices in various fields equipped with a memory. For example, as an electronic device to which the nonvolatile semiconductor memory device of the present invention is applied, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, an audio playback device (car audio, audio component, etc.), a computer, a game Reproducing a recording medium such as a device, a portable information terminal (mobile computer, cellular phone, portable game machine or electronic book), an image reproducing apparatus (specifically, a DVD (digital versatile disc)) provided with a recording medium, And a device provided with a display capable of displaying an image). Specific examples of these electronic devices are shown in FIGS.

41A and 41B show a digital camera. FIG. 41B is a diagram showing the back side of FIG. This digital camera includes a housing 2111, a display portion 2112, a lens 2113, operation keys 2114, a shutter 2115, and the like. In addition, a removable nonvolatile memory 2116 is provided, and data captured by the digital camera is stored in the nonvolatile memory 2116. A nonvolatile semiconductor memory device formed using the present invention can be applied to the nonvolatile memory 2116.

FIG. 41C illustrates a mobile phone, which is a typical example of a mobile terminal. This mobile phone includes a housing 2121, a display portion 2122, operation keys 2123, and the like. In addition, the mobile phone includes a removable nonvolatile memory 2125, and data such as a phone number of the mobile phone, video, music data, and the like can be stored in the nonvolatile memory 2125 and played back. A nonvolatile semiconductor memory device formed using the present invention can be applied to the nonvolatile memory 2125.

FIG. 41D illustrates a digital player, which is a typical example of an audio device. A digital player shown in FIG. 41D includes a main body 2130, a display portion 2131, a memory portion 2132, an operation portion 2133, an earphone 2134, and the like. Note that headphones or wireless earphones can be used instead of the earphones 2134. As the memory portion 2132, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating the operation unit 2133 using a NAND type nonvolatile memory having a recording capacity of 20 to 200 gigabytes. Note that the display unit 2131 can reduce power consumption by displaying white characters on a black background. This is particularly effective in a portable audio device. Note that the nonvolatile semiconductor memory device provided in the memory portion 2132 may be removable.

FIG. 41E illustrates an electronic book (also referred to as electronic paper). This electronic book includes a main body 2141, a display portion 2142, operation keys 2143, and a nonvolatile memory portion 2144. Further, a modem may be incorporated in the main body 2141 or a configuration in which information can be transmitted and received wirelessly may be employed. As the nonvolatile memory portion 2144, a nonvolatile semiconductor memory device formed using the present invention can be used. For example, video and audio (music) can be recorded and reproduced by operating an operation key 2143 using a NAND nonvolatile memory having a recording capacity of 20 to 200 gigabytes. Note that the nonvolatile semiconductor memory device provided in the nonvolatile memory portion 2144 may be removable.

As described above, the applicable range of the nonvolatile semiconductor memory device of the present invention is so wide that it can be used for electronic devices in various fields as long as it has a memory.

1 is a cross-sectional view for explaining a main structure of a nonvolatile semiconductor memory device according to the present invention. The band figure of the non-volatile memory in the initial state (charge discharge state). The band diagram of the non-volatile memory in the writing state. The band figure of the non-volatile memory in a charge retention state. The band diagram of the non-volatile memory in the erased state. 4A and 4B illustrate writing and reading operations of a nonvolatile memory. 10A and 10B illustrate an erase operation of a nonvolatile memory. The figure which shows an example of the equivalent circuit of a non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NOR type non-volatile memory cell array. The figure which shows an example of the equivalent circuit of a NAND type non-volatile memory cell array. 4A and 4B illustrate a write operation of a NAND nonvolatile memory. The figure explaining erase and read-out operation of NAND type non-volatile memory. The figure which shows the change of the threshold voltage of a non-volatile memory in the case of "0" with which charge was accumulate | stored, and the case of "1" erase | eliminated. 1 is a diagram illustrating an example of a circuit block diagram of a nonvolatile semiconductor memory device. The figure explaining the structure of a plasma processing apparatus. The band figure of the conventional non-volatile memory. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. 8A and 8B illustrate an example of a method for manufacturing a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. 1 is a diagram showing an example of a cross section of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 6 shows an example of the top surface of a nonvolatile semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention. FIG. 11 shows an example of a usage pattern of a nonvolatile semiconductor memory device of the present invention.

Explanation of symbols

M0 Non-volatile memory element M01 Non-volatile memory element M02 Non-volatile memory element M03 Non-volatile memory element M11 Non-volatile memory element M12 Non-volatile memory element M13 Non-volatile memory element S1 Select transistor S2 Select transistor S01 Select transistor S02 Select transistor S03 Select transistor S11 Select transistor S12 Select transistor S13 Select transistor MS01 Memory cell WL Word line WL0 Word line WL1 Word line WL11 Word line BL Bit line BL0 Bit line SL Source line NS1 NAND cell 01 Semiconductor substrate 02 First insulating layer 03 Floating gate electrode 04 Second insulating layer 05 Control gate electrode 10 Semiconductor substrate 12 P well 14 Channel forming region 16 First insulating layer 16a Silicon oxide layer 16b Nitride Recon layer 18 Impurity region 18a Source region 18b Drain region 18c Low concentration impurity region 20 Floating gate electrode 20a First floating gate electrode 20b Second floating gate electrode 22 Second insulating layer 22a Silicon nitride layer 22b Silicon oxide layer 24 Control Gate electrode 24a Metal nitride layer 24b Metal layer 26 Gate 28 Spacer 52 Memory cell array 54 Peripheral circuit 56 Address buffer 58 Control circuit 60 Booster circuit 62 Row decoder 64 Column decoder 66 Sense amplifier 68 Data buffer 70 Data input / output buffer 72 Antenna 74 Dielectric Body plate 76 Gas supply unit 78 Exhaust port 80 Support base 82 Temperature control unit 84 Microwave supply unit 86 Plasma 100 Substrate 102 Insulating layer 104 Region 106 Region 107 P well 108 Region 110 Region 112 First Insulating layer 116 First insulating layer 120 Charge storage layer 121 Charge storage layer 122 Resist 123 Charge storage layer 124 Resist 125 Charge storage layer 126 Impurity region 128 Second insulating layer 130 Resist 132 Insulating layer 134 Insulating layer 136 Conductive film 138 Conductive film 140 conductive film 142 conductive film 144 conductive film 146 conductive film 148 resist 150 channel formation region 152 impurity region 154 channel formation region 156 impurity region 158 low concentration impurity region 160 channel formation region 162 impurity region 164 low concentration impurity region 166 resist 168 Channel formation region 170 Impurity region 172 Insulating layer 174 Conductive film 186 Low concentration impurity region 188 Low concentration impurity region 190 Impurity region 192 Insulating layer 194 Impurity region 200 Substrate 202 Insulating layer 204 Insulating layer 206 Resist 208 Recess 210 Insulating layer 211 Insulating layer 212 Region 213 Region 214 Region 215 P well 216 First insulating layer 220 First insulating layer 222 Charge storage layer 223 Resist 224 First insulating layer 226 Charge storage layer 227 Charge storage layer 228 Second insulating layer 229 Charge storage layer 230 Resist 232 Insulating layer 234 Insulating layer 236 Conductive film 238 Conductive film 240 Conductive film 242 Conductive film 244 Conductive film 246 Conductive film 254 Insulating layer 256 Channel formation region 258 Impurity region 260 Low concentration impurity Region 262 Channel formation region 264 Impurity region 266 Low concentration impurity region 268 Channel formation region 270 Impurity region 272 Low concentration impurity region 277 Insulating layer 278 Opening 280 Conductive film 182a Conductive film 182b Conductive film 182c Conductive film 182d Conductive film 184a Conductive film 184b Conductive film 184c Conductive film 184d Conductive film 282a Conductive film 800 Semiconductor device 810 High-frequency circuit 820 Power supply circuit 830 Reset circuit 840 Clock generation circuit 850 Data demodulation circuit 860 Data modulation circuit 870 Control circuit 880 Storage circuit 890 Antenna 910 Code extraction circuit 920 Code determination circuit 930 CRC determination circuit 940 Output unit circuit 2111 Case 2112 Display unit 2113 Lens 2114 Operation key 2115 Shutter 2116 Non-volatile memory 2121 Case 2122 Display unit 2123 Operation key 2125 Non-volatile memory 2130 Main body 2131 Display unit 2132 Memory unit 2133 Operation unit 2134 Earphone 2141 Main body 2142 Display unit 2143 Operation key 2144 Non-volatile memory unit 3200 Reader / writer 3210 Radical 113 3220 goods 3230 semiconductor device 3240 reader / writer 3250 semiconductor device 3260 items

Claims (14)

A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The floating gate is formed of at least a first layer and a second layer, a first layer in contact with the first insulating layer is formed of a semiconductor material, and a band gap of the semiconductor material is
A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device is smaller than a band gap in a channel formation region of the semiconductor substrate. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of a material having an electron affinity higher than that of silicon. A nonvolatile semiconductor memory device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The floating gate is formed of at least a first layer and a second layer,
The barrier energy for electrons in the first layer of the floating gate formed by the first insulating layer is higher than the barrier energy for electrons in the channel formation region of the semiconductor substrate formed by the first insulating layer. A non-volatile semiconductor memory device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of germanium or a germanium compound. Storage device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of germanium or a germanium compound and has a thickness of 1 nm to 20 nm. A non-volatile semiconductor memory device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The first insulating layer is formed by stacking a silicon oxide layer and a silicon nitride layer from the semiconductor substrate side,
The floating gate is formed of at least a first layer and a second layer, a first layer in contact with the first insulating layer is formed of a semiconductor material, and a band gap of the semiconductor material is the semiconductor substrate A non-volatile semiconductor memory device characterized by being smaller than the band gap in the channel formation region. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The first insulating layer is formed by stacking a silicon oxide layer and a silicon nitride layer from the semiconductor substrate side,
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of a material having an electron affinity higher than that of silicon. A nonvolatile semiconductor memory device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The first insulating layer is formed by stacking a silicon oxide layer and a silicon nitride layer from the semiconductor substrate side,
The floating gate is formed of at least a first layer and a second layer,
The barrier energy for electrons in the first layer of the floating gate formed by the first insulating layer is higher than the barrier energy for electrons in the channel formation region of the semiconductor substrate formed by the first insulating layer. A non-volatile semiconductor memory device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The first insulating layer is formed by stacking a silicon oxide layer and a silicon nitride layer from the semiconductor substrate side,
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of germanium or a germanium compound. Storage device. A pair of impurity regions formed apart from each other, a semiconductor substrate on which a channel formation region is formed, and
A first insulating layer, a floating gate, a second insulating layer, and a control gate at a position that is an upper layer portion of the semiconductor substrate and substantially overlaps the channel formation region;
The first insulating layer is formed by stacking a silicon oxide layer and a silicon nitride layer from the semiconductor substrate side,
The floating gate is formed of at least a first layer and a second layer, and the first layer in contact with the first insulating layer is formed of germanium or a germanium compound and has a thickness of 1 nm to 20 nm. A non-volatile semiconductor memory device. In claim 1 or 6,
A nonvolatile semiconductor memory device, wherein a difference between a band gap of a material forming a channel formation region in the semiconductor substrate and a band gap of a semiconductor material forming the floating gate is 0.1 eV or more. In any one of Claims 4, 5, 9, and 10,
The nonvolatile semiconductor memory device, wherein the germanium compound is germanium oxide or germanium nitride. In any one of Claims 1 thru | or 12,
The non-volatile semiconductor memory device, wherein the floating gate is in contact with the silicon nitride layer. In any one of Claims 1 thru | or 13,
The non-volatile semiconductor memory device, wherein the silicon oxide layer is obtained by oxidizing the semiconductor substrate by plasma treatment, and the silicon nitride layer is obtained by nitriding the silicon oxide layer by plasma treatment. .

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