TWI401007B - Method of fabricating circuit board structure having embedded semiconductor component - Google Patents

Method of fabricating circuit board structure having embedded semiconductor component Download PDF

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Publication number
TWI401007B
TWI401007B TW096100011A TW96100011A TWI401007B TW I401007 B TWI401007 B TW I401007B TW 096100011 A TW096100011 A TW 096100011A TW 96100011 A TW96100011 A TW 96100011A TW I401007 B TWI401007 B TW I401007B
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Taiwan
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passive component
circuit board
dielectric layer
board structure
circuit
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TW096100011A
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Chinese (zh)
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TW200830968A (en
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Jiang Wen Kung
Wen Sung Chang
Wei Hung Lin
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Unimicron Technology Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

嵌埋被動元件之電路板結構之製法Method for manufacturing circuit board structure with embedded passive components

本發明係有關於一種電路板結構之製法,尤指一種嵌埋被動元件之電路板結構之製法。The invention relates to a method for manufacturing a circuit board structure, in particular to a method for manufacturing a circuit board structure in which a passive component is embedded.

隨著電子產業的蓬勃發展,電子產品亦逐漸邁入多功能、高性能的研發方向。為滿足半導體封裝件高積集度(Integration)以及微型化(Miniaturization)的封裝需求,逐漸由單層板演變成多層板(Multi-layer Board),俾於有限的空間下,藉由層間連接技術(Interlayer Connection)以擴大承載板上可利用的電路面積,以因應高電子密度之積體電路(Integrated Circuit)的使用需求。同時,亦需於半導體封裝件中整合電阻器(Resistors)、電容器(Capacitors)及電感器(Inductors)等被動元件(Passive component),藉以相對提高或穩定電子產品的電性功能。With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, it has gradually evolved from a single-layer board to a multi-layer board, which is used in a limited space by inter-layer connection technology. (Interlayer Connection) to expand the available circuit area on the carrier board to meet the needs of the use of integrated circuits with high electron density. At the same time, passive components such as resistors, capacitors, and inductors are integrated into the semiconductor package to relatively enhance or stabilize the electrical function of the electronic product.

而一般習知技術係將該些被動元件安置於承載板上未被半導體晶片所使用之其餘線路佈局面積上;如第1圖所示,係於一印刷電路板或半導體元件之封裝基板的承載板1表面接置有複數被動元件12,然為避免該等被動元件12阻礙半導體元件11與多數焊墊間之電性連結,通常將該等被動元件12接置於該承載板1之邊緣位置未使用之區域面積上。惟將該被動元件12設置於承載板1表面,將限制線路佈局(Routability)之靈活性;同時考量必須佈設焊墊的位置,導致該等被動元件12佈設數量受到限制,而不利半導體裝置高度集積化之發展;甚者,該被動元件12佈設數量隨著半導體封裝件高性能之要求而相對地遽增,如採習知方法該承載板1表面必須同時容納多數半導體元件11以及大量被動元件12,迫使封裝件體積增大,亦不符合半導體封裝件輕薄短小之發展潮流。In the prior art, the passive components are disposed on the remaining circuit layout area of the carrier board that is not used by the semiconductor wafer; as shown in FIG. 1, the carrier is mounted on a printed circuit board or a package substrate of the semiconductor component. The surface of the board 1 is provided with a plurality of passive components 12. However, in order to prevent the passive components 12 from blocking the electrical connection between the semiconductor components 11 and the plurality of solder pads, the passive components 12 are usually placed at the edge of the carrier board 1. The area of the unused area. However, the passive component 12 is disposed on the surface of the carrier board 1 to limit the flexibility of the circuit layout. At the same time, the position of the soldering pad must be disposed, which limits the number of the passive components 12 to be disposed, and the semiconductor device is highly concentrated. In other words, the number of passive components 12 is relatively increased with the high performance requirements of the semiconductor package. As is known, the surface of the carrier 1 must accommodate a plurality of semiconductor components 11 and a large number of passive components 12 at the same time. Forcing the package to increase in volume and not conforming to the trend of thin and thin semiconductor packages.

而且,該些被動元件係分別接置至承載板上,不僅造成增加線路佈設(Routability)與製程之複雜性,更使得整體之封裝製程具有較大之複雜度,而不合乎成本效益。Moreover, the passive components are respectively connected to the carrier board, which not only increases the complexity of the circuit layout and the process, but also makes the overall packaging process more complicated and uneconomical.

為避免習知承載板表面之佈局限制問題並進一步滿足縮小承載板空間之需求,亦有於多層承載板層間安置膜狀被動元件,如美國專利第5,683,928及6,055,151號等揭示在多層承載板製程中於形成一新疊層前,先在一有機絕緣層表面以網印(Printing)及/或光阻蝕刻(Photoresist-etching)等方式形成電阻被動元件。In order to avoid the problem of the layout limitation of the surface of the carrier board and to further meet the requirements for reducing the space of the carrier board, a film-like passive component is also disposed between the layers of the multi-layer carrier board, as disclosed in U.S. Patent Nos. 5,683,928 and 6,055,151. Before forming a new laminate, the resistive passive component is formed by printing and/or photoresisting (Photoresist-etching) on the surface of an organic insulating layer.

利用形成於多層承載板間之膜狀被動元件,以避免習知承載板表面之佈設被動元件之問題,但此種方式較為繁瑣、複雜,且該嵌埋於承載板間之被動元件,需針對不同電路設計及需求進行更改,因此造成製造成本的大幅提升,此種被動元件之整合方式,將使得基板之整體結構及其所需製程具有較大之複雜度而不符合成本效益。The film-shaped passive component formed between the multi-layer carrier plates is used to avoid the problem of the passive components disposed on the surface of the carrier board. However, this method is cumbersome and complicated, and the passive component embedded in the carrier board needs to be targeted. Different circuit designs and requirements are changed, resulting in a significant increase in manufacturing costs. The integration of such passive components will make the overall structure of the substrate and its required process more complex and not cost effective.

請參閱第2圖,為此業界遂發展出於承載板中嵌埋被動元件之技術,其係於一以樹脂材質如環氧樹脂(Epoxy resin)、聚亞醯胺(Polyimide)樹脂、BT(Bismaleimide Trazine)樹脂、FR4樹脂等製成之承載板21形成有一開口210,於該開口210中容置有一被動元件22,該被動元件22具有一第一表面22a及第二表面22b,於該第一表面22a具有複數電極墊221,且於該被動元件22與開口之間的間隙中形成有黏著材料23,俾以將該被動元件22固定於該開口210中;又於該被動元件22之第一表面22a及承載板21之表面形成有一線路增層結構23,該線路增層結構23係包括介電層231、疊置於該介電層231上之線路層232,以及形成於該介電層231中之導電結構233,且該導電結構233電性連接置該被動元件22之電極墊221,又該線路增層結構23外表面形成複數電性連接墊234,並於該線路增層結構23外表面形成一防焊層24,且該防焊層24中形成複數開孔240以露出該等電性連接墊234。Referring to Figure 2, the industry has developed a technology for embedding passive components in a carrier board, which is made of a resin material such as epoxy resin, polyimide resin, BT ( The carrier plate 21 made of Bismaleimide Trazine resin, FR4 resin or the like is formed with an opening 210, and a passive component 22 is received in the opening 210. The passive component 22 has a first surface 22a and a second surface 22b. A surface 22a has a plurality of electrode pads 221, and an adhesive material 23 is formed in the gap between the passive component 22 and the opening to fix the passive component 22 in the opening 210; and in the passive component 22 A surface build-up structure 23 is formed on a surface of the surface 22a and the carrier plate 21. The circuit build-up structure 23 includes a dielectric layer 231, a circuit layer 232 stacked on the dielectric layer 231, and a dielectric layer formed thereon. The conductive structure 233 in the layer 231, and the conductive structure 233 is electrically connected to the electrode pad 221 of the passive component 22, and the outer surface of the circuit build-up structure 23 forms a plurality of electrical connection pads 234, and the circuit is added to the circuit. 23 an outer surface forming a solder resist layer 24, The solder resist layer 24 is formed a plurality of openings 240 to expose the conductive pads 234 of these.

然該承載板21於後續製程中,由於金屬材質之線路層與介電層及拒焊層之熱膨係數(Coefficient of thermal expansion,CTE)差異大,該嵌埋於開口中之被動元件,易因熱膨脹係數之差異而產生剝離現象。However, in the subsequent process, the carrier element 21 has a large difference in coefficient of thermal expansion (CTE) between the circuit layer of the metal material and the dielectric layer and the solder resist layer, and the passive component embedded in the opening is easy. Peeling occurs due to the difference in thermal expansion coefficient.

因此,如何提供一種嵌埋被動元件之製法,以避免習知技術中嵌埋被動元件之結合性,藉以提高承載板與線路增層結構之可靠度,實已成為目前業界亟待克服之難題。Therefore, how to provide a method for embedding a passive component to avoid the combination of embedded passive components in the prior art, thereby improving the reliability of the carrier board and the line build-up structure, has become an urgent problem to be overcome in the industry.

鑑於以上所述習知技術之缺點,本發明主要目的係提供一種嵌埋被動元件之電路板結構之製法,得提供承載板與嵌埋其中之被動元件間之結合性。In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a method for fabricating a circuit board structure in which a passive component is embedded, and to provide a bond between the carrier board and the passive component embedded therein.

為達上揭目的及其他目的,本發明之嵌埋被動元件之電路板結構之製法,係包括:提供一承載板,該承載板中形成有至少一貫穿開口;於該承載板之開口中容置被動元件,該被動元件具有一第一表面及第二表面,其中該第一表面具有複數電極墊,該被動元件之表面係經一第一蝕刻液及第二蝕刻液進行粗化製程以形成一粗化表面;以及於該承載板及被動元件之第一表面上形成一介電層。For the purpose of achieving the above and other objects, the method for manufacturing a circuit board structure embedding a passive component of the present invention comprises: providing a carrier board having at least one through opening formed therein; and accommodating the opening of the carrier board a passive component having a first surface and a second surface, wherein the first surface has a plurality of electrode pads, and the surface of the passive component is subjected to a roughening process by a first etching solution and a second etching solution to form a roughened surface; and a dielectric layer formed on the first surface of the carrier and the passive component.

該承載板係為絕緣板、陶瓷板或具有線路之電路板;該介電層並形成於該被動元件與開口之間的間隙中,或以一黏著材料形成於該被動元件與開口之間的間隙中,俾將該被動元件固定於該開口中。The carrier board is an insulating board, a ceramic board or a circuit board having a line; the dielectric layer is formed in a gap between the passive component and the opening, or is formed by an adhesive material between the passive component and the opening. In the gap, the passive element is fixed in the opening.

該被動元件之表面係先以該第一蝕刻液進行蝕刻粗化,再以該第二蝕刻液粗化處理該第一表面之電極墊;或該被動元件係以該第二蝕刻液先於該第一表面之電極墊進行粗化處理,再以該第一蝕刻液蝕刻粗化該被動元件之表面;其中該第一蝕刻液係為氫氧化鈉(NaOH)、氫氧化鈣(Ca(OH)2)、高錳酸鉀(KMnO4)或氫氧化鉀(KOH)之鹼性溶液(Alkaline solution),而該第二蝕刻液係為氫氯酸(HCl)、硝酸(HNO3)、過氯酸(HClO4)、醋酸(CH3COOH)、草酸(H3PO4)或硫酸(H2SO4)之酸性溶液(Acid solution)。The surface of the passive component is first etched and roughened by the first etchant, and the electrode pad of the first surface is roughened by the second etchant; or the passive component is preceded by the second etchant The electrode pad of the first surface is roughened, and the surface of the passive component is roughened by the first etching solution; wherein the first etching liquid is sodium hydroxide (NaOH) or calcium hydroxide (Ca(OH) 2) an alkaline solution of potassium permanganate (KMnO4) or potassium hydroxide (KOH), and the second etching solution is hydrochloric acid (HCl), nitric acid (HNO3), perchloric acid ( Acid solution of HClO4), acetic acid (CH3COOH), oxalic acid (H3PO4) or sulfuric acid (H2SO4).

依上述之製法,復包括於該承載板表面及被動元件之第二表面形成另一介電層,並於該被動元件第一表面上之介電層表面形成一線路層,且該線路層係可透過形成於該介電層開孔中之導電結構以電性連接該被動元件之電極墊;又於該介電層及線路層表面形成線路增層結構,該線路增層結構係包括介電層、疊置於該介電層上之線路層,以及形成於該介電層中之導電結構,又該線路增層結構外表面形成複數電性連接墊,於該線路增層結構外表面覆蓋有一防焊層,且該防焊層中形成複數開孔以露出該等電性連接墊。According to the above method, another dielectric layer is formed on the surface of the carrier and the second surface of the passive component, and a circuit layer is formed on the surface of the dielectric layer on the first surface of the passive component, and the circuit layer is The electrode pad of the passive component is electrically connected through the conductive structure formed in the opening of the dielectric layer; and the circuit build-up structure is formed on the surface of the dielectric layer and the circuit layer, the circuit build-up structure includes a dielectric a layer, a circuit layer stacked on the dielectric layer, and a conductive structure formed in the dielectric layer, and the outer surface of the line build-up structure forms a plurality of electrical connection pads, and the outer surface of the line build-up structure is covered A solder mask is formed, and a plurality of openings are formed in the solder resist layer to expose the electrical connection pads.

因此本發明之嵌埋被動元件之電路板結構之製法係可在被動元件嵌埋於承載板開口中之前,於該被動元件之表面及其電極墊表面以第一及第二蝕刻液全面進行表面粗化製程,俾在後續將被動元件嵌埋於電路板結構中時,得使該被動元件之粗化表面與介電層之間得有較佳之結合性,以避免該被動元件嵌合在承載板開口中,因熱膨脹係數不同而在後續熱循環製程中產生脫層的情況。Therefore, the circuit board structure of the embedded passive component of the present invention can be completely surface-etched with the first and second etching liquids on the surface of the passive component and the surface of the electrode pad before the passive component is embedded in the opening of the carrier plate. The roughening process, in the subsequent embedding of the passive component in the circuit board structure, has a better combination between the roughened surface of the passive component and the dielectric layer to avoid the passive component being embedded in the carrier In the plate opening, delamination occurs in the subsequent thermal cycle process due to the difference in thermal expansion coefficient.

以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention.

請參閱第3A至3D圖,係為本發明嵌埋被動元件之電路板結構之製法的第一實施例剖面示意圖。Please refer to FIGS. 3A to 3D, which are cross-sectional views showing a first embodiment of a method for manufacturing a circuit board structure embedding a passive component according to the present invention.

如第3A圖所示,提供一承載板31,該承載板31中形成至少一貫穿之開口310;該承載板31係為絕緣板、陶瓷板或具有線路之電路板。As shown in FIG. 3A, a carrier plate 31 is provided, and at least one opening 310 is formed in the carrier plate 31; the carrier plate 31 is an insulating plate, a ceramic plate or a circuit board having a line.

如第3B圖所示,於該承載板31之開口310中容置該被動元件32,該被動元件32具有一相對之第一表面32a及第二表面32b,於該第一表面32a具有複數電極墊321,且該被動元件32之表面係以例如鹼性溶液(Alkaline solution)之第一蝕刻液粗化該被動元件32之非金屬表面,再以係如酸性溶液(Acid solution)之第二蝕刻液粗化該被動元件32之金屬表面,如電極墊321;或該被動元件32之表面先以第二蝕刻液粗化該被動元件32之金屬表面,再以第一蝕刻液粗化該被動元件32之非金屬表面;其中該鹼性溶液係如氫氧化鈉(NaOH)、氫氧化鈣(Ca(OH)2)、高錳酸鉀(KMnO4)或氫氧化鉀(KOH),而該酸性溶液係為氫氯酸(HCl)、硝酸(HNO3)、過氯酸(HClO4)、醋酸(CH3COOH)、草酸(H3PO4)或硫酸(H2SO4)。As shown in FIG. 3B, the passive component 32 is received in the opening 310 of the carrier plate 31. The passive component 32 has an opposite first surface 32a and a second surface 32b. The first surface 32a has a plurality of electrodes. Pad 321 , and the surface of the passive component 32 is roughened by a first etching solution such as an alkaline solution (Alkaline solution) to the non-metal surface of the passive component 32, and then etched by a second solution such as an acidic solution. Liquid roughening the metal surface of the passive component 32, such as the electrode pad 321; or the surface of the passive component 32 first roughens the metal surface of the passive component 32 with a second etchant, and then roughens the passive component with the first etchant a non-metallic surface of 32; wherein the alkaline solution is such as sodium hydroxide (NaOH), calcium hydroxide (Ca(OH)2), potassium permanganate (KMnO4) or potassium hydroxide (KOH), and the acidic solution It is hydrochloric acid (HCl), nitric acid (HNO3), perchloric acid (HClO4), acetic acid (CH3COOH), oxalic acid (H3PO4) or sulfuric acid (H2SO4).

如第3C圖所示,於該承載板31表面及被動元件32之第一表面32a形成一介電層33,且於該承載板31表面及被動元件32之第二表面32b形成另一介電層33’,該介電層33,33’並填充於該被動元件32與開口310之間的間隙中,以將該被動元件32固定於該開口310中,並於該介電層33中形成有複數開孔330以露出該被動元件32之電極墊321。As shown in FIG. 3C, a dielectric layer 33 is formed on the surface of the carrier 31 and the first surface 32a of the passive component 32, and another dielectric is formed on the surface of the carrier 31 and the second surface 32b of the passive component 32. The layer 33 ′, the dielectric layer 33 , 33 ′ is filled in the gap between the passive component 32 and the opening 310 to fix the passive component 32 in the opening 310 and formed in the dielectric layer 33 . A plurality of openings 330 are provided to expose the electrode pads 321 of the passive component 32.

如第3D圖所示,於該介電層33,33’表面形成有線路層34,34’,且該線路層34係可透過形成於該介電層開孔330中之導電結構341以電性連接該被動元件32之電極墊321。As shown in FIG. 3D, a wiring layer 34, 34' is formed on the surface of the dielectric layer 33, 33', and the wiring layer 34 is electrically conductive through the conductive structure 341 formed in the dielectric layer opening 330. The electrode pads 321 of the passive component 32 are connected.

如第3E圖所示,於該介電層33,33’及線路層34,34’表面形成線路增層結構35,35’,該線路增層結構35,35’係包括介電層351,351’、疊置於該介電層上之線路層352,352’,以及形成於該介電層351,351’中之導電結構353,353’,且該導電結構353,353’係可供線路層352,352’電性連接至該線路層34,34’,又該線路增層結構35,35’外表面形成複數電性連接墊354,354’,且於該線路增層結構35,35’外表面覆蓋有防焊層36,36’,該防焊層36,36’中形成複數開孔360,360’以露出該等電性連接墊354,354’。As shown in FIG. 3E, a line build-up structure 35, 35' is formed on the surface of the dielectric layers 33, 33' and the circuit layers 34, 34'. The line build-up structure 35, 35' includes a dielectric layer 351, 351'. a circuit layer 352, 352' stacked on the dielectric layer, and conductive structures 353, 353' formed in the dielectric layer 351, 351', and the conductive structures 353, 353' are electrically connected to the circuit layer 352, 352' to the line The layers 34, 34', and the outer surface of the line build-up structure 35, 35' form a plurality of electrical connection pads 354, 354', and the outer surface of the line build-up structure 35, 35' is covered with a solder resist layer 36, 36', A plurality of openings 360, 360' are formed in the solder resist layers 36, 36' to expose the electrically connected pads 354, 354'.

請參閱第4A及4B圖所示,係為本發明之嵌埋被動元件之電路板結構之製法第二實施例之剖面示意圖,與前一實施例之不同處在於被動元件係以一黏著材料固定於承載件開口中。4A and 4B are cross-sectional views showing a second embodiment of the method for manufacturing a circuit board structure embedding a passive component according to the present invention. The difference from the previous embodiment is that the passive component is fixed by an adhesive material. In the opening of the carrier.

如第4A圖所示,提供如前一實施例之承載板31及被動元件32,該被動元件32之表面及其電極墊321係經第一及第二蝕刻液全面粗化,且該被動元件32係容置於該承載板31之開口310中,並以一黏著材料37填入該被動元件32與該承載板開口310之間的間隙中,以將該被動元件32固定於該承載板開口310中。As shown in FIG. 4A, the carrier board 31 and the passive component 32 of the previous embodiment are provided, and the surface of the passive component 32 and the electrode pad 321 thereof are completely roughened by the first and second etching liquids, and the passive component is The 32 series is received in the opening 310 of the carrier plate 31, and is filled into the gap between the passive component 32 and the carrier opening 310 by an adhesive material 37 to fix the passive component 32 to the carrier opening. 310.

如第4B圖所示,於該承載板31表面及被動元件32之第一表面32a形成一介電層33,並於該承載板31表面及被動元件32之第二表面32b形成另一介電層33’;於該介電層33,33’表面形成一線路層34,34’,且該線路層34係可透過形成於該介電層中之導電結構341以電性連接該被動元件32之電極墊321;於該介電層33,33’及線路層34,34’上形成線路增層結構35,35’,且於該線路增層結構35,35’外表面覆蓋一防焊層36,36’,其中該防焊層36,36’中形成複數開孔360,360’以露出形成於該線路增層結構35,35’外表面之電性連接墊354,354’。As shown in FIG. 4B, a dielectric layer 33 is formed on the surface of the carrier 31 and the first surface 32a of the passive component 32, and another dielectric is formed on the surface of the carrier 31 and the second surface 32b of the passive component 32. a layer 33'; a circuit layer 34, 34' is formed on the surface of the dielectric layer 33, 33', and the circuit layer 34 is electrically connected to the passive component 32 through the conductive structure 341 formed in the dielectric layer. An electrode pad 321; a line build-up structure 35, 35' is formed on the dielectric layers 33, 33' and the circuit layers 34, 34', and a solder resist layer is covered on the outer surface of the line build-up structure 35, 35' 36, 36', wherein the solder resist layers 36, 36' are formed with a plurality of openings 360, 360' to expose electrical connection pads 354, 354' formed on the outer surface of the line build-up structure 35, 35'.

因此本發明之嵌埋被動元件之電路板結構之製法中係將被動元件之表面以第一蝕刻液進行粗化,再以第二蝕刻液對電極墊表面進行粗化製程,或先該電極墊表面先以第二蝕刻液進行粗化,再以第一蝕刻液對被動元件表面進行粗化,使該被動元件全面形成有粗化之表面,俾可供被動元件嵌埋於承載板開口中時,使該被動元件之粗化表面與介電層之間得有較佳之結合性,以避免該電路板結構與嵌合在承載板開口中之被動元件產生脫層的情況。Therefore, in the method for manufacturing the circuit board structure of the embedded passive component of the present invention, the surface of the passive component is roughened by the first etching solution, and the surface of the electrode pad is roughened by the second etching solution, or the electrode pad is first used. The surface is first roughened by the second etching solution, and the surface of the passive component is roughened by the first etching solution, so that the passive component is completely formed with a roughened surface, and the passive component is embedded in the opening of the carrier plate. The preferred combination of the roughened surface of the passive component and the dielectric layer is to avoid delamination of the circuit board structure from the passive components embedded in the opening of the carrier.

上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

1,21,31...承載板1,21,31. . . Carrier board

11...半導體元件11. . . Semiconductor component

12,22,32...被動元件12,22,32. . . Passive component

210,310...開口210,310. . . Opening

221,321...電極墊221,321. . . Electrode pad

22a,32a...第一表面22a, 32a. . . First surface

22b,32b...第二表面22b, 32b. . . Second surface

23,35,35’...線路增層結構23,35,35’. . . Line buildup structure

23,37...黏著材料23,37. . . Adhesive material

231,33,33’,351,351’...介電層231, 33, 33', 351, 351'. . . Dielectric layer

232,34,34’,352,352’...線路層232, 34, 34', 352, 352'. . . Circuit layer

233,341,353,353’...導電結構233,341,353,353’. . . Conductive structure

234,354,354’...電性連接墊234,354,354’. . . Electrical connection pad

24,36,36’...防焊層24,36,36’. . . Solder mask

240,330,360,360’...開孔240,330,360,360’. . . Opening

第1圖係為習知於半導體封裝件中增設被動元件之示意圖;第2圖係為習知嵌埋被動元件之承載件結構剖面示意圖;第3A至3E圖係為本發明之嵌埋被動元件之電路板結構之製法第一實施例之剖面示意圖;以及第4A及4B圖係為本發明之嵌埋被動元件之電路板結構之製法第二實施例之剖面示意圖。1 is a schematic view showing the addition of a passive component in a semiconductor package; FIG. 2 is a schematic cross-sectional view of a carrier structure of a conventional embedded passive component; and FIGS. 3A to 3E are embedded passive components of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 4A and FIG. 4B are cross-sectional views showing a second embodiment of a method for fabricating a circuit board structure embedding a passive component according to the present invention.

31...承載板31. . . Carrier board

310...開口310. . . Opening

32...被動元件32. . . Passive component

321...電極墊321. . . Electrode pad

32a...第一表面32a. . . First surface

32b...第二表面32b. . . Second surface

33,33’...介電層33,33’. . . Dielectric layer

330...開孔330. . . Opening

34,34’...線路層34,34’. . . Circuit layer

341...導電結構341. . . Conductive structure

Claims (15)

一種嵌埋被動元件之電路板結構之製法,係包括:提供一承載板,該承載板中形成有至少一貫穿開口;於該承載板之開口中容置被動元件,該被動元件具有一第一表面及第二表面,其中該第一表面具有複數電極墊,該被動元件之非金屬表面及電極墊表面係分別經第一蝕刻液及第二蝕刻液進行粗化製程以形成粗化表面,該第一蝕刻液係為鹼性溶液(Alkaline solution),而該第二蝕刻液係為酸性溶液(Acid solution);以及於該承載板及被動元件之第一表面上形成一介電層。 A method for manufacturing a circuit board structure embedding a passive component, comprising: providing a carrier board having at least one through opening formed therein; receiving a passive component in the opening of the carrier board, the passive component having a first a surface and a second surface, wherein the first surface has a plurality of electrode pads, and the non-metal surface and the electrode pad surface of the passive component are respectively subjected to a roughening process by the first etching solution and the second etching solution to form a roughened surface, The first etching liquid is an alkaline solution (Alkaline solution), and the second etching liquid is an acidic solution; and a dielectric layer is formed on the first surface of the carrier plate and the passive component. 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,復包括於該介電層形成有複數開孔以露出該被動元件之電極墊。 The method for fabricating a circuit board structure of an embedded passive component according to claim 1, wherein the dielectric layer is formed with a plurality of openings to expose the electrode pads of the passive component. 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,其中,該承載板係為絕緣板、陶瓷板及具有線路之電路板之其中一者。 The method of manufacturing a circuit board structure for embedding a passive component according to claim 1, wherein the carrier board is one of an insulating board, a ceramic board, and a circuit board having a line. 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,其中,該介電層並填充於該被動元件與該承載板開口之間的間隙中,以將該被動元件固定於該承載板開口中。 The method of fabricating a circuit board structure for embedding a passive component according to claim 1, wherein the dielectric layer is filled in a gap between the passive component and the opening of the carrier plate to fix the passive component to the The carrier plate is in the opening. 如申請專利範圍第1項之嵌埋被動元件之電路板結構 之製法,其中,該被動元件與該承載板開口之間的間隙中填充有黏著材料,以將該被動元件固定於該開口中。 Such as the circuit board structure of the embedded passive component of claim 1 The method of claim, wherein a gap between the passive component and the opening of the carrier plate is filled with an adhesive material to fix the passive component in the opening. 如申請專利範圍第4或5項之嵌埋被動元件之電路板結構之製法,復包括於該承載板及被動元件之第二表面上形成另一介電層。 The method for manufacturing a circuit board structure embedding a passive component according to claim 4 or 5, further comprising forming another dielectric layer on the second surface of the carrier plate and the passive component. 如申請專利範圍第6項之嵌埋被動元件之電路板結構之製法,復包括於該介電層上形成線路層,並於該介電層中形成有導電結構,以供該線路層電性連接至該被動元件之電極墊。 The method for manufacturing a circuit board structure of an embedded passive component according to claim 6 is characterized in that the circuit layer is formed on the dielectric layer, and a conductive structure is formed in the dielectric layer for electrical connection of the circuit layer. Connected to the electrode pads of the passive component. 如申請專利範圍第7項之嵌埋被動元件之電路板結構之製法,復包括於該介電層及線路層表面形成線路增層結構。 For example, the method for manufacturing a circuit board structure embedded in a passive component of claim 7 includes forming a line build-up structure on the surface of the dielectric layer and the circuit layer. 如申請專利範圍第8項之嵌埋被動元件之電路板結構之製法,其中,該線路增層結構外表面形成有複數電性連接墊。 The method for manufacturing a circuit board structure for embedding a passive component according to claim 8 is characterized in that the outer surface of the circuit build-up structure is formed with a plurality of electrical connection pads. 如申請專利範圍第9項之嵌埋被動元件之電路板結構之製法,其中,該線路增層結構外表面形成有一防焊層,且該防焊層中形成複數開孔以露出該電性連接墊。 The method for manufacturing a circuit board structure for embedding a passive component according to claim 9, wherein a surface of the circuit build-up structure is formed with a solder resist layer, and a plurality of openings are formed in the solder resist layer to expose the electrical connection. pad. 如申請專利範圍第8項之嵌埋被動元件之電路板結構之製法,其中,該線路增層結構係包括有介電層、疊置於該介電層上之線路層,以及形成於該介電層中之導電結構。 The method for fabricating a circuit board structure of an embedded passive component according to claim 8 , wherein the circuit build-up structure comprises a dielectric layer, a circuit layer stacked on the dielectric layer, and a dielectric layer formed on the dielectric layer. Conductive structure in the electrical layer. 如申請專利範圍第1項之嵌埋被動元件之電路板結構 之製法,其中,該被動元件之表面係先以該第一蝕刻液進行蝕刻粗化,再以該第二蝕刻液粗化處理該第一表面之電極墊。 Such as the circuit board structure of the embedded passive component of claim 1 The method of the method, wherein the surface of the passive component is first etched and roughened by the first etching solution, and the electrode pad of the first surface is roughened by the second etching solution. 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,其中,該被動元件係以該第二蝕刻液先於該第一表面之電極墊進行粗化處理,再以該第一蝕刻液蝕刻粗化該被動元件之表面。 The method for manufacturing a circuit board structure of an embedded passive component according to claim 1, wherein the passive component is roughened by the electrode pad of the first surface, and then the first The etchant etches the surface of the passive component. 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,其中,該第一蝕刻液係為氫氧化鈉(NaOH)、氫氧化鈣(Ca(OH)2)、高錳酸鉀(KMnO4)及氫氧化鉀(KOH)之其中一者。 The method for manufacturing a circuit board structure of an embedded passive component according to claim 1, wherein the first etching liquid is sodium hydroxide (NaOH), calcium hydroxide (Ca(OH)2), potassium permanganate. One of (KMnO4) and potassium hydroxide (KOH). 如申請專利範圍第1項之嵌埋被動元件之電路板結構之製法,其中,該第二蝕刻液係為氫氯酸(HCl)、硝酸(HNO3)、過氯酸(HClO4)、醋酸(CH3COOH)、草酸(H3PO4)及硫酸(H2SO4)之其中一者。The method for manufacturing a circuit board structure of an embedded passive component according to claim 1, wherein the second etching liquid is hydrochloric acid (HCl), nitric acid (HNO3), perchloric acid (HClO4), acetic acid (CH3COOH). ), one of oxalic acid (H3PO4) and sulfuric acid (H2SO4).
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