KR100888561B1 - Manufacturing method of active device embedded printed circuit board - Google Patents

Manufacturing method of active device embedded printed circuit board Download PDF

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KR100888561B1
KR100888561B1 KR1020070019413A KR20070019413A KR100888561B1 KR 100888561 B1 KR100888561 B1 KR 100888561B1 KR 1020070019413 A KR1020070019413 A KR 1020070019413A KR 20070019413 A KR20070019413 A KR 20070019413A KR 100888561 B1 KR100888561 B1 KR 100888561B1
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printed circuit
circuit board
active element
copper foil
present
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KR1020070019413A
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Korean (ko)
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KR20080079384A (en
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이민석
이한성
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대덕전자 주식회사
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

본 발명은 능동소자 내장형 인쇄회로기판과 이를 제조하는 방법을 제공한다. 본 발명에 따른 능동소자 내장형 인쇄회로기판은 금속재 내부에 형성한 공동에 칩이 실장되므로, 전자파 차폐효과와 함께 열방산 특성을 개선할 수 있다. 그 결과 본 발명에 따른 능동소자 내장형 인쇄회로기판은 열전도성이 우수한 칩 실장 패키지로 사용되거나 또는 다층 인쇄회로기판의 내층 코어로 이용될 수 있다.The present invention provides an active element embedded printed circuit board and a method of manufacturing the same. In the active element embedded printed circuit board according to the present invention, since the chip is mounted in a cavity formed inside the metal material, heat dissipation characteristics may be improved along with an electromagnetic shielding effect. As a result, an active element embedded printed circuit board according to the present invention may be used as a chip mounting package having excellent thermal conductivity or may be used as an inner layer core of a multilayer printed circuit board.

인쇄회로기판, 능동소자, 내장형 기판, 열방출. Printed circuit board, active element, embedded board, heat dissipation.

Description

능동소자 내장형 인쇄회로기판 제조 방법{MANUFACTURING METHOD OF ACTIVE DEVICE EMBEDDED PRINTED CIRCUIT BOARD}Manufacture method of active circuit embedded PCB {MANUFACTURING METHOD OF ACTIVE DEVICE EMBEDDED PRINTED CIRCUIT BOARD}

도1은 본 발명의 양호한 실시예에 따라 제작한 능동소자가 내장된 인쇄회로기판 구조를 나타낸 도면.1 is a view showing a printed circuit board structure in which an active element manufactured according to a preferred embodiment of the present invention is incorporated.

도2a 내지 도2f는 본 발명의 양호한 실시예에 따라 능동소자 내장형 인쇄회로기판을 제작하는 공정 순서를 나타낸 도면.2A to 2F show a process sequence for manufacturing an active element embedded printed circuit board according to a preferred embodiment of the present invention.

도3은 본 발명에 따라 제작된 능동소자 내장형 기판을 패키지 기판으로 제작한 실시예를 나타낸 도면.3 is a view showing an embodiment of manufacturing an active device embedded substrate manufactured according to the present invention as a package substrate.

도4a 내지 도4d는 본 발명의 양호한 실시예로서 제작된 능동소자 내장형 기판을 내층 코어로 이용하여 빌드업 다층 인쇄 회로 기판을 형성한 실시예를 나타낸 도면.4A to 4D show an embodiment in which a build-up multilayer printed circuit board is formed using an active element embedded substrate manufactured as a preferred embodiment of the present invention as an inner layer core.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>

100 : 능동소자, 즉 반도체 칩100: active element, that is, semiconductor chip

110 : 금속재110: metal material

120 : 접착제120: adhesive

130 : 절연층130: insulation layer

140 : 비아홀140: via hole

150 : 동박 회로150: copper foil circuit

170 : 솔더 레지스트170: solder resist

180 : 솔더 볼180: solder ball

본 발명은 능동소자 (active device)가 기판 내부에 내장된 인쇄회로기판에 관한 것으로, 특히 능동소자가 방출하는 주울 열(Joule heat)을 효율적으로 방산할 수 있는 내장형 인쇄회로기판 구조 및 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board in which an active device is embedded in a substrate, and more particularly, to a structure and a manufacturing method of an embedded printed circuit board capable of efficiently dissipating Joule heat emitted by the active device. It is about.

최근 들어 전자기기들의 휴대성 기능이 강조되는 경향에 따라 인쇄회로기판에 저항 또는 인덕터와 같은 수동소자(passive device)뿐 아니라 트랜지스터 칩과 같은 능동 소자를 기판에 내장하는 기술이 업계에 도입되고 있다. 이와 같이, 부품들을 기판에 내장하면 기판의 소형화가 가능하고 부품의 실장 밀도가 증대되는 동시에 회로의 고주파 특성이 향상되는 효과가 있다.Recently, as the portability of electronic devices is emphasized, technologies for embedding active devices such as transistor chips as well as passive devices such as resistors or inductors in printed circuit boards have been introduced to the industry. As such, when the components are embedded in the substrate, the substrate can be miniaturized, the mounting density of the components can be increased, and the high frequency characteristics of the circuit can be improved.

현재 일반적으로 업계에 알려진 능동소자 내장형 인쇄회로기판 제조 기술은 기판을 가공하여 공동(cavity)을 형성한 후, 마이크로 비아를 가공하고 동도금을 진행함으로써 반도체 칩을 기판과 연결하는 공법에 의존하고 있다. 그런데, 에폭시 레진 계열의 절연체에 형성된 공동에 내장된 능동소자들은 동작시에 방대한 양의 열을 방출하게 되고, 공동에 내장된 능동소자의 열발산은 주위 절연체의 열전도 특성이 양호하지 않으므로 열방산이 쉽지 않은 문제점이 있다.Currently, the active element embedded printed circuit board manufacturing technology generally known in the industry relies on a method of connecting a semiconductor chip to a substrate by processing a substrate to form a cavity, processing a micro via, and copper plating. However, active devices embedded in the cavities formed in the epoxy resin-based insulators emit a large amount of heat during operation, and heat dissipation of the active devices embedded in the cavities is not easy because heat conduction characteristics of the surrounding insulators are not good. There is a problem.

따라서, 본 발명의 목적은 열방출 특성을 개선한 능동소자 내장형 인쇄회로기판과 이를 제조하는 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide an active element embedded printed circuit board having improved heat dissipation characteristics and a method of manufacturing the same.

상기 목적을 달성하기 위하여, 능동 소자 내장형 인쇄회로기판을 제작하는 방법에 있어서 (a) 금속재에 상기 능동소자를 실장할 부위를 식각 제거하여 공동(cavity)을 형성하는 단계; (b) 상기 금속제 내에 식각 형성된 공동의 밑면에 접착제를 도포하고 상기 접착제 위에 상기 능동 소자를 실장 고정하는 단계; 및 (c) 상기 능동소자가 공동 내부에 실장된 금속재의 표면에 절연체를 형성하는 단계를 포함하는 능동소자 내장형 인쇄회로기판 제조 방법을 제공한다.In order to achieve the above object, a method of manufacturing an active element embedded printed circuit board comprising the steps of: (a) forming a cavity by etching away a portion to mount the active element on a metal material; (b) applying an adhesive to the underside of the cavity etched in the metal and mounting the active element over the adhesive; And (c) forming an insulator on the surface of the metal material in which the active device is mounted inside the cavity.

이하에서는, 첨부 도면 도1 내지 도3을 참조하여 본 발명의 양호한 실시예를 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 능동소자 내장형 인쇄회로기판은 열방출 특성을 개선하기 위하여 금속재 내에 공동(cavity)을 식각 형성하여 칩을 실장하는 것을 특징으로 한다.An active element embedded printed circuit board according to the present invention is characterized by mounting a chip by etching a cavity in a metal material in order to improve heat dissipation characteristics.

도1은 본 발명의 양호한 실시예에 따라 능동소자가 내장된 인쇄회로기판 구조를 나타낸 단면 도면이다. 도1을 참조하면, 능동소자 칩(100)은 금속재(110) 내부에 형성한 공동(cavity)에 접착제(adhesive; 120)를 사이에 두고, 실장 되어 있으며, 칩 상부에는 절연층(130)이 형성되어, 절연층(130)에는 칩과의 연결을 위한 비아홀(140)과 동박 회로(150)가 형성되어 있다. 1 is a cross-sectional view showing a printed circuit board structure in which an active element is built according to a preferred embodiment of the present invention. Referring to FIG. 1, the active device chip 100 is mounted with an adhesive 120 interposed between a cavity formed in the metal material 110 and an insulating layer 130 on the chip. The via layer 140 and the copper foil circuit 150 for connecting to the chip are formed in the insulating layer 130.

이와 같이, 칩(100)이 금속재(110) 공동 내부에 실장되므로, EMI 등 전자장 차폐 효과가 개선되며 열전달 계수가 양호한 금속재(110) 층을 통해서 열방산 특성이 개선된다. 더욱이, 공동 속에 칩(100)이 내장되므로 절연층(130) 상부에 동박 회로(150)를 형성함으로써 기판 표면에 실장 밀도를 배가하는 효과가 있다.As such, since the chip 100 is mounted in the cavity of the metal material 110, the electromagnetic shielding effect such as EMI is improved and heat dissipation characteristics are improved through the metal material 110 having a good heat transfer coefficient. Furthermore, since the chip 100 is embedded in the cavity, the copper foil circuit 150 is formed on the insulating layer 130 to double the mounting density on the surface of the substrate.

도2a 내지 도2f는 본 발명의 양호한 실시예에 따라 능동소자 내장형 인쇄 회로 기판을 제작하는 공정을 나타낸 도면이다. 도2a를 참조하면, 내장될 칩(100)보다 두꺼운 두께를 지닌 금속재(110)를 준비하여 공동(cavity; 105)을 식각하여 형성한다. 이때에, 본 발명에 따른 금속재(110)는 중량 동박(heavy Cu)을 사용할 수 있으며, 중량 동박이란 두께가 400㎛이상 되는 동박을 의미한다.2A to 2F illustrate a process of manufacturing an active element embedded printed circuit board according to a preferred embodiment of the present invention. Referring to FIG. 2A, a cavity 105 is etched by preparing a metal material 110 having a thickness thicker than that of the chip 100 to be embedded. At this time, the metal material 110 according to the present invention may use a heavy copper foil (heavy Cu), the weight copper foil means a copper foil having a thickness of 400㎛ or more.

도2b는 본 발명에 따라 금속재 내부에 공동을 형성한 모습을 본 발명에 따른 양호한 실시예로서, 도2b의 공동(105)은 사진 식각 공정을 진행해서 금속재(110)의 원하는 부위에 형성할 수 있다. 사진 식각 공정은 감광성 물질을 도포하고 주어진 패턴에 따라 노광한 후 감광성 물질을 선택적으로 식각 제거하여 마스크를 형성한 후 마스크가 노출한 부분을 식각하는 공정이다. 이어서, 도2c를 참조하면 식각 형성된 공동의 밑면에 접착제(adhesive; 120)를 발라 그 위에 칩(100)을 실장하게 된다. 본 발명에 따른 접착제의 양호한 실시예로서 에폭시 수지가 이용될 수 있다. 본 발명의 양호한 실시예로서 접착제(adhesive)는 디스펜싱(dispensing) 방법으로 공동의 밑면에 도포할 수 있다.Figure 2b is a preferred embodiment according to the present invention in the form of a cavity inside the metal material in accordance with the present invention, the cavity 105 of Figure 2b can be formed in a desired portion of the metal material 110 by performing a photolithography process have. The photolithography process is a process of applying a photosensitive material and exposing according to a given pattern, selectively etching away the photosensitive material to form a mask, and then etching the exposed portion of the mask. Next, referring to FIG. 2C, an adhesive 120 is applied to the bottom surface of the etched cavity to mount the chip 100 thereon. Epoxy resins may be used as preferred embodiments of the adhesive according to the invention. As a preferred embodiment of the present invention, an adhesive may be applied to the underside of the cavity by a dispensing method.

이어서, 도2d를 참조하면 디스펜싱 방식으로 공동(105)의 밑면에 준비된 접착제(120) 위에 칩(100)을 실장한다. 그리고나면, 도2e에서와 같이 절연체(130)를 칩(100) 위에 형성하게 되는데, 양호한 실시예로서 액상 절연체를 디스펜싱 처리하거나 또는 레진 필름 또는 동박이 도포된 레진(RCC)를 밀착 가압하여 절연층을 밀봉 형성할 수 있다.Subsequently, referring to FIG. 2D, the chip 100 is mounted on the prepared adhesive 120 on the bottom surface of the cavity 105 by a dispensing method. Then, as shown in FIG. 2E, an insulator 130 is formed on the chip 100. In a preferred embodiment, a liquid insulator is dispensed or a resin film or a copper foil coated resin (RCC) is pressed and insulated. The layer can be sealed formed.

이어서 도2f를 참조하면, 칩(100) 상부에 형성한 절연층(130)에 레이저 드릴 방식으로 비아홀(140)을 형성할 수 있으며, 도금을 진행하여 비아홀(140)을 충진하고, 기판 표면에 형성된 동박을 사진 식각 공정을 진행하여 동박 회로 (150)를 형성할 수 있다.Subsequently, referring to FIG. 2F, the via hole 140 may be formed in the insulating layer 130 formed on the chip 100 by laser drilling. The via hole 140 may be filled by plating to fill the substrate surface. The formed copper foil may be subjected to a photolithography process to form the copper foil circuit 150.

이와 같이 해서 제작된 본 발명에 따른 능동 소자 내장형 인쇄회로기판은 그 자체로서 패키지 기판으로 사용될 수도 있고, 혹은 빌드업 공법의 내층 코어 또는 작은 모듈로서 역할을 할 수 있다.The active element embedded printed circuit board according to the present invention manufactured as described above may be used as a package substrate by itself, or may serve as an inner layer core or a small module of a build-up method.

도3은 본 발명에 따라 제작된 능동소자 내장형 기판을 패키지 기판으로 제작하는 실시예를 나타낸 도면이다. 도3을 참조하면, 본 발명에 따라 능동소자가 내장된 인쇄회로기판 위에 솔더 레지스트(170)를 도포하고, 패드 위에는 솔더 볼(180)을 형성한다. 솔더 레지스트는 당업계에서 사용하는 대로 종래의 프린트 방식으로 도포할 수 있다. 3 is a view showing an embodiment of manufacturing an active device embedded substrate manufactured according to the present invention as a package substrate. Referring to FIG. 3, the solder resist 170 is coated on a printed circuit board in which an active element is embedded, and the solder ball 180 is formed on a pad. The solder resist can be applied by conventional printing methods as used in the art.

도4a 내지 도4d는 본 발명의 양호한 실시예로서 본 발명에 따라 제작된 능동소자 내장형 기판을 내층 코어로 이용하여 빌드업 다층 인쇄회로기판을 형성하는 실시예를 나타낸 도면이다. 도4a를 참조하면, 본 발명에 따라 중량 동박(110)의 공동(cavity) 내에 칩(100)이 실장된 내장형 인쇄회로기판의 상하 양면에 절연층과 동박을 적층하고 열압착 라미네이트(laminate)하여 내층 코어를 형성한다. 4A to 4D illustrate a preferred embodiment of the present invention in which a build-up multilayer printed circuit board is formed using an active element embedded substrate manufactured according to the present invention as an inner layer core. Referring to FIG. 4A, the insulating layer and the copper foil are laminated on the upper and lower surfaces of the embedded printed circuit board on which the chip 100 is mounted in a cavity of the heavy copper foil 110 according to the present invention, and laminated by thermocompression bonding. Form an inner layer core.

도4b는 본 발명의 양호한 실시예에 따라 능동소자가 내장된 내층 코어 단면을 나타낸 도면으로서, 양면에는 동박이 절연체 위에 도포되어 있다.Fig. 4B is a cross-sectional view showing an inner layer core in which an active element is built according to a preferred embodiment of the present invention, in which copper foil is coated on an insulator on both sides.

도4c를 참조하면, 절연층 위의 동박을 박리하고, 칩과의 접속이 필요한 부위 또는 상층/하층간에 관통홀이 필요한 부위에 대해 드릴링을 수행한다. 이어서, 동도금을 수행하여 비아 홀과 관통홀을 충진하도록에 동박을 표면에 형성하고, 동박 표면에 감광성 레지스트를 도포하고 주어진 회로 패턴을 사진, 현상 및 식각하여 동박 회로(150)를 형성하고, 비아 홀(140)과 관통홀(210)을 형성한다. 감광성 레지스트를 도포하고 주어진 패턴에 따라 노광하고, 형상한 후 동박을 마스크 패턴에 따라 식각하는 사진 공정은 당업계에서 늘 사용하는 종래 기술이므로 상세한 설명을 생략한다. 이어서, 내층 코어에 절연층에 동박이 도포되어 있는 외층 기판을 적층한 후 열압착 라미네이트(laminate)하고, 주어진 회로 패턴에 따라 위에서 설명한 사진 공정을 반복 진행하여 층간 비아 홀(250)과 동박 회로(260)을 패턴 형성한다. 도4d를 참조하면, 열방출을 위한 관통홀(220)과 통전을 위한 관통홀(210)이 형성된 모습이 도시되어 있다. Referring to FIG. 4C, the copper foil on the insulating layer is peeled off, and drilling is performed on a portion requiring a connection with a chip or a portion where a through hole is required between upper and lower layers. Subsequently, copper plating is performed to form copper foil on the surface to fill the via holes and through holes, and a photosensitive resist is applied to the copper foil surface, and a given circuit pattern is photographed, developed and etched to form the copper foil circuit 150, and The hole 140 and the through hole 210 are formed. After the photosensitive resist is applied, exposed according to a given pattern, and shaped, the photographic process of etching copper foil according to a mask pattern is a conventional technique that is always used in the art, and thus detailed description thereof will be omitted. Subsequently, after laminating an outer layer substrate on which the copper foil is coated on the insulating layer on the inner core, it is laminated by thermocompression bonding, and the above-described photo process is repeated according to a given circuit pattern to repeat the interlayer via hole 250 and the copper foil circuit ( 260 is patterned. Referring to FIG. 4D, a through-hole 220 for heat dissipation and a through-hole 210 for energization are formed.

전술한 내용은 후술할 발명의 특허 청구 범위를 보다 잘 이해할 수 있도록 본 발명의 특징과 기술적 장점을 다소 폭넓게 개설하였다. 본 발명의 특허 청구 범위를 구성하는 부가적인 특징과 장점들이 이하에서 상술 될 것이다. 개시된 본 발명의 개념과 특정 실시예는 본 발명과 유사 목적을 수행하기 위한 다른 구조의 설계나 수정의 기본으로서 즉시 사용될 수 있음이 당해 기술 분야의 숙련된 사람들에 의해 인식되어야 한다. The foregoing has outlined rather broadly the features and technical advantages of the present invention to better understand the claims of the invention which will be described later. Additional features and advantages that make up the claims of the present invention will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiments of the invention disclosed may be readily used as a basis for designing or modifying other structures for carrying out similar purposes to the invention.

또한, 본 발명에서 개시된 발명 개념과 실시예가 본 발명의 동일 목적을 수행하기 위하여 다른 구조로 수정하거나 설계하기 위한 기초로서 당해 기술 분야의 숙련된 사람들에 의해 사용되어 질 수 있을 것이다. 또한, 당해 기술 분야의 숙련된 사람에 의한 그와 같은 수정 또는 변경된 등가 구조는 특허 청구 범위에서 기술한 발명의 사상이나 범위를 벗어나지 않는 한도 내에서 다양한 진화, 치환 및 변경이 가능하다. In addition, the inventive concepts and embodiments disclosed herein may be used by those skilled in the art as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. In addition, such modifications or altered equivalent structures by those skilled in the art may be variously evolved, substituted and changed without departing from the spirit or scope of the invention described in the claims.

이상과 같이, 본 발명에 따른 능동소자 내장형 인쇄회로기판은 금속재에 형성한 공동에 칩이 실장되므로, 전자파 차폐 효과와 함께 열방산 특성을 개선할 수 있다. 그 결과 본 발명에 따른 능동소자 내장형 인쇄회로기판은 열전도성이 우수 한 칩 실장 패키지로 사용되거나 또는 다층 인쇄회로기판의 내층 코어로 이용될 수 있다.As described above, the active element embedded printed circuit board according to the present invention, since the chip is mounted in the cavity formed in the metal material, it is possible to improve the heat dissipation characteristics with the electromagnetic shielding effect. As a result, an active element embedded printed circuit board according to the present invention may be used as a chip mounting package having excellent thermal conductivity or may be used as an inner layer core of a multilayer printed circuit board.

Claims (6)

능동 소자 내장형 인쇄회로기판을 제작하는 방법에 있어서 In the method of manufacturing an active element embedded printed circuit board (a) 두께가 400 ㎛ 이상인 중량 동박(heavy copper)에 상기 능동소자를 실장할 부위를 식각 제거하여 공동(cavity)을 형성하는 단계;(a) forming a cavity by etching away a portion to mount the active element on a heavy copper foil having a thickness of 400 μm or more; (b) 상기 금속제 내에 식각 형성된 공동의 밑면에 에폭시 수지 접착제(adhesive)를 도포하고 상기 에폭시 수지 접착제 위에 상기 능동 소자를 실장 고정하는 단계; 및(b) applying an epoxy resin adhesive to the bottom of the cavity etched in the metal and mounting the active element over the epoxy resin adhesive; And (c) 상기 능동소자가 공동 내부에 실장된 금속재의 표면에 액상 절연체를 디스펜싱 처리하거나, 레진 필름 또는 동박이 도포된 레진(RCC)를 밀착 가압하여 절연층을 밀봉 형성하는 단계(c) sealing the insulating layer by dispensing a liquid insulator on the surface of the metal material mounted inside the cavity, or pressing the resin film or the copper foil-coated resin (RCC) in close contact with the active element; (d) 상기 절연층에 마이크로 비아홀 또는 관통홀들을 가공하고 동도금 및 사진 식각 공정을 통해 동박 회로를 형성하는 단계(d) processing micro via holes or through holes in the insulating layer and forming a copper foil circuit through copper plating and photolithography; 를 포함하되, 상기 관통홀들 중 일부는 상기 중량 동박을 관통하도록 하는 것을 특징으로 하는 능동소자 내장형 인쇄회로기판 제조 방법.To include, wherein some of the through-holes penetrate the heavy copper foil, characterized in that the active element embedded printed circuit board manufacturing method. 삭제delete 삭제delete 삭제delete 삭제delete 삭제delete
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