TWI384568B - Reticle inspection system and program - Google Patents

Description

Mask verification system and program

The present invention relates to a reticle verification system for performing reticle data verification for performing a desired exposure, and more particularly to a reticle verification system for verifying reticle data for flat panel display fabrication. .

The flat panel display (FPD) production reticle data defines a shooting frame on the panel layout data, and is cut as an exposure element (hereinafter also referred to as a repeating element), including the graphic material of the exposure element and the exposure position on the panel substrate. Coordinate information. When the reticle data is transferred onto the FPD panel substrate, the coordinate information of the exposure element disposed using the reticle data is transferred to the panel substrate of the FPD in the exposure device.

At this time, when there is an error in the graphic material of the exposure element or the coordinate information provided on the photomask, not only the photomask but also the panel substrate is wasted. In particular, when producing a mask material for a flat panel display, it is necessary to manually divide the exposure region, and it is easy to cause an error.

In order to prevent this, a method of simulating an exposure device based on mask image data and coordinate information and performing verification is considered. Among them, in the relationship between the exposure device and the simulation, for example, a technique for realizing cost optimization of the exposure device is included. Patent Document 1 provides a method of optimizing a measurement condition for optimizing measurement conditions by using a simulator, reducing time and labor in an exposure apparatus. but Yes, Patent Document 1 only discloses an invention that is intended to optimize measurement conditions.

In general, the size of the panel substrate for a flat panel display is much larger than the exposure range of the exposure device. Therefore, the reticle attached to the exposure apparatus is smaller than the panel substrate, and an element on the reticle that cuts a part of the panel substrate is disposed as an exposure element.

When the mask is exposed by the exposure device, the exposure elements on the mask are repeatedly placed and exposed to produce a panel substrate for a flat panel display.

Therefore, when the reticle is produced, the division of the display panel area and the cutting of the layout data are performed, and the exposure elements of the reticle are produced. On the other hand, when the display panel is produced, the panel substrate is produced by repeated exposure, so that the layout data is When the cut and exposure elements are repeatedly configured, errors are likely to occur.

Further, even when the layout data is not cut, it is necessary to divide the display panel area. Therefore, it is necessary to designate the repeated arrangement of the exposure elements. At this time, there are many cases where an instruction error that causes repeated arrangement occurs. Therefore, it is required to verify the verification unit of the exposure result in advance in the pre-production process.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2006-140204

An object of the present invention is to provide a mask verification system that can preliminarily verify an exposure result of an exposure element provided on a photomask.

Further, an object of the present invention is to provide a mask verification system capable of preliminarily verifying an exposure result of an exposure element by the operation of the analog exposure apparatus.

Further, an object of the present invention is to provide a mask verification program that is executed by a computer and is suitable for constructing the mask verification system.

According to the present invention, there is provided a reticle verification system, comprising: a storage unit for storing graphic data of an exposure element contained in a reticle for exposure of a flat panel display, and a coordinate representation of a grid dot, indicating on the display panel a coordinate information of an exposure position of the exposure element; a layout graphic element generation unit generates a layout graphic element on the display panel corresponding to the exposure element according to the graphic data and the coordinate information of the exposure element stored in the storage unit; The verification unit verifies the exposure element according to the positional relationship of the plurality of layout graphic elements on the display panel generated by the layout graphic element generation unit; and a display unit displays the result of the verification unit verification.

The layout graphic element generation unit generates a layout graphic element on the display panel corresponding to the exposure element according to the graphic data and the coordinate information of the exposure element stored in the storage unit. The detecting unit verifies the exposure element according to the positional relationship of the plurality of layout graphic elements on the display panel generated by the layout graphic element generating unit. The display unit displays the results of the verification unit verification.

Wherein, the display unit has at least a window for displaying the verification result, and the verification unit verifies the plurality of exposure elements by performing calculation processing between the grid grids corresponding to the plurality of layout pattern elements, and the display unit obtains the verification result of the verification unit. The graphic is displayed on the window.

Moreover, the data of the reticle contains an intermediate layer defining a transistor pattern, or an external database of defined transistor patterns used as an intermediate layer, and An unfolding unit having a table structure that expands according to the needs of the intermediate layer or the external database defining the transistor pattern according to the index structure.

Further, the verification unit has a difference extraction unit that performs logical OR processing of the two layout graphic elements, and performs any one of the layout graphic elements and the layout graphic elements in the graphic elements obtained by the logical OR result. The logical XOR processing or differential processing of the regions extracts the differences between the two layout graphic elements.

Further, the verification unit includes an overlap amount detecting unit that detects the overlap amount of the two layout pattern elements by performing logical AND processing of the two layout pattern elements.

And, the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value.

Further, the verification unit includes a component determination unit that performs logical OR processing after the overlap amount detecting unit detects that there is no overlap amount of the two layout graphic elements, and confirms that two layout graphic elements form a closed graphic. As a result, it is judged that the two layout graphic elements are continuous graphic elements.

Moreover, each exposure element includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit for verifying the grid grid on the display panel corresponding to the inner edge of the louver frame. Whether the end point of the layout graphic element of the graphic element exists within the range of the specified offset value.

And, a specified unit is included, which specifies an error layer containing an erroneous verification result. When the display unit displays the error graphic information on the window indicating the verification result, the error layer specified by the specified unit is displayed on the window in a layer unit. Error graphic information.

And, the display unit has a dialog box different from the window for displaying the verification result, the specifying unit specifies the error layer on the dialog box, the display unit displays the number of errors on the dialog box, and responds to the designation of the error layer by the designated unit, The wrong graphic information of this layer is displayed on the window.

Further, according to the present invention, there is provided a program (computer program product) which is a computer having the function of the photomask verification system according to any one of the above.

The computer executes the above program to have the function of the photomask verification system described in any of the above.

According to the reticle verification system of the present invention, it is possible to pre-verify the exposure result of the exposure element provided in the reticle.

Further, the exposure result of the exposure element can be verified in advance by the operation of the analog exposure device.

Moreover, the program according to the present invention is executed by a computer, so that the above-mentioned reticle data exposure verification system can be constructed.

Hereinafter, a mask verification system and a mask verification program according to an embodiment of the present invention will be described. Or a plurality of computers, and a mask verification program for constructing a mask verification system by execution of the above computer, which will be described later in detail. The above-mentioned computer functions as a reticle data creation system for producing reticle data by executing a reticle data creation program. In the drawings, the same parts are denoted by the same reference numerals.

1 is a view showing a relationship between a panel substrate for a flat panel display (FPD) and a photomask according to the embodiment, wherein (a) is a plan view and (b) is a side view.

In Fig. 1, 101 is a panel substrate, 102 is an exposure area of an exposure device (not shown) that ensures characteristics, 103 is an exposure area of the exposure device, 104 is a light source system mechanism, 105 is a light shielding system mechanism, and 106 is The mask, 107 is the exposure surface. Among them, glass, a plastic film, or the like can be used as the material of the panel substrate 101.

In recent years, flat panel displays have been enlarged in size such as liquid crystal displays and plasma displays, and the exposure apparatus cannot collectively expose the panel substrate 101 (see the plan view of Fig. 1(a)). Therefore, it is necessary to divide the exposure area in some form and perform repeated exposure. The positional relationship between the exposure device and the panel substrate 101 is the light source system mechanism 104, the light shielding system mechanism 105, the mask 106, the exposure surface 107, and the panel substrate 101 as seen from the light source side. Although not shown in FIG. 1, it is still A lens system mechanism is added thereto (see the side view of Fig. 1 (b)).

Further, the light shielding system mechanism 105 refers to a rectangular mechanical mechanism that can mechanically shield light from a light source.

2 is a view showing a panel on a panel substrate in an embodiment of the present invention. A diagram of the relationship between the layout data and the reticle layout material on the reticle.

In FIG. 2, the liquid crystal panel 201 has an example of a large panel layout material A1 as the panel layout material 211 on the panel substrate 210. In the case of the liquid crystal panel 201, the panel layout material A1 is divided to extract the data group corresponding shooting frame 213 having a repeating structure, and is placed on the mask 205 as the mask layout material 206.

Usually, in this case, the division of the exposure region is performed along with the cutting of the panel layout material A1. In the present embodiment, each element of the mask layout material corresponding to each divided element (panel layout element) of the panel layout material is referred to as an exposure element or a repeating element. The mask layout data consists of multiple exposure elements. Further, 212 is an exposure area in which characteristics are ensured.

The liquid crystal panel 202 indicates that there is a case where the pattern layout materials A2 and A3 are among the panel layout materials. In this case as well, the panel layout data A2 and A3 are divided into exposure areas along with the cutting of the panel layout data, and a data group having a repeating structure is usually produced in association with the imaging frame 213.

The liquid crystal panel 203 indicates a case where a plurality of small panel layout materials A4 and A5 as panel layout materials are arranged on a panel substrate. In this case, the plurality of panel layout data A4 and the plurality of panel layout materials A5 are generated corresponding to the respective shooting frames 213, and it is necessary to arrange the generated mask layout data 206 on the mask 205 to reduce the number of exposures. Therefore, in this case, generally, the division of the exposure area is required, but the panel layout data is not cut.

The liquid crystal panel 204 is a case where the medium panel layout material A2 and the small panel layout materials A4 and A5 are present on the panel substrate. In this case, the medium-sized panel layout data A2 is divided by the exposure area that is cut along with the panel layout data, and is generated corresponding to the imaging frame 213, and the small layout materials A4 and A5 are divided into exposure areas that are not cut off with the panel layout data, and The shooting frame 213 is correspondingly generated as the mask layout material 206.

Therefore, when the reticle is produced, the data group having the repetitive structure is extracted from the panel layout material 211 of the panel substrate 210, and the photographic frame 213 is placed on the reticle 205 to create the reticle layout data. At this time, the versatility is strong, and a large frame area is extracted.

In either case, it is important to confirm that there is no erroneous data by performing an exposure device simulation. This is because even if the panel layout data is not cut off, the division of the exposure area in which the arrangement is repeatedly performed is also necessary, and when the repeated arrangement is designated, an error is likely to occur. In addition, the frame data in the mask data is a graphic element in which the louver frame is set, and is referred to as an exposure element or a repeating element.

Before explaining the reticle verification system according to the embodiment of the present invention, first, the production sequence of the reticle data will be briefly described.

3 and FIG. 4 are views showing a general processing procedure when the mask data is created from the panel layout data, and FIG. 3 is a display unit 1 showing the mask verification system (when the mask is used, it functions as a mask manufacturing system) FIG. 4 is a flowchart showing a processing procedure of a CPU (not shown) constituting the mask manufacturing system.

3(a) shows the panel layout data 211 on the panel substrate 210, and FIG. 3(b) shows the setting of the imaging frame 213 on the panel substrate 210 and the arrangement of the imaging frame 213 on the mask 205, FIG. 3 ( c) shows the extraction by the panel layout material 211 on the panel substrate 210 (for example, cutting along the imaging frame 213), the generation of a correction pattern (not shown), and the louver frame (not shown). Processing at the time of production.

Further, Fig. 3(d) shows the coordinate information of the reticle output from the reticle design system. The coordinate information includes information on the width and height of the mask layout data (also referred to as an exposure element or a repeating element in the present embodiment) as the exposure element data, and information on the position of the repeated arrangement of the repeated elements. (Repeat configuration information).

The fabrication process of the mask data will be briefly described with reference to FIGS. 3 and 4. When the mask data is created, the CPU first reads the panel layout data 211 (step S401), and sets a plurality of frame 213 for the panel layout data 211 on the panel substrate 210. The imaging frame 213 is placed on the mask 205, and the mask layout data 206 is created (step S402).

Next, the segmentation of the exposure region is performed in accordance with the imaging frame 213. At this time, the wiring material is usually present immediately below the designated shooting frame 213, so it must be cut. This includes a case where a pattern (correction pattern) wider than the cut portion is generated in the data cutting portion (steps S403, S404) and a case where it is not generated (step S405).

When the correction pattern is not generated, the shooting frame 213 is superimposed and defined, and then the process proceeds to process step S406 (step S405). With this configuration, small exposure can be prevented by multiple exposure of the exposure data itself during exposure. The information was cut off by mistake.

When the correction pattern is generated, after the correction pattern is generated, the process proceeds to process step S406 (steps S403, S404). When the correction pattern is generated, the correction pattern itself is generally subjected to multiple exposures, with the result that false cuts caused by minute deviations are prevented.

In the processing step S402, in the division of the exposure region without the data cut, the processing for generating a predetermined wide frame (louver frame) surrounding the exposure region is directly performed (step S406).

In the louver frame generation processing of the processing step S406, the louver frame is generated with the specified width. The correction pattern is composed of a pattern wider than the wiring pattern, and the inner edge of the louver frame is configured corresponding to the outer edge of the correction pattern described above.

Thereby, it is possible to produce an exposure element (overlapping element) composed of the material of the exposure region and the louver frame. Further, coordinate information corresponding to the exposure element is created.

Finally, the mask layout data and the coordinate information corresponding to the layout data are output, and the processing is terminated (step S407). The layout data described above is the mask layout data and the panel layout data to which the data of the shooting frame 213 is added.

The reticle layout data is information for defining a graphic of the exposure element, and is a data file composed of a rectangular graphic, a formed graphic, a wide graphic defined on the center line, and an intermediate module constituting the graphic data.

As described above, the coordinate information is information for defining the exposure position of the exposure element included in the mask layout data, and is a description of the name, height, width, and repeated arrangement information (repetition times and information of the configuration coordinates) of the exposure element. Text file.

Moreover, the reticle data refers to information composed of the reticle layout information and coordinate information.

Fig. 5 is a view showing a structure of panel layout data formed on a panel substrate. The top module is called the top module 511, and there is one. Other modules are affiliated with the top level module 511. They are layout data lower modules 512~515, which can also be layered. The layout data of the module includes, for example, a thin film transistor, a configuration data 516 of each transistor of the liquid crystal driving portion, wiring information 517, and via configuration data 518 in the case of a liquid crystal panel.

These transistors, wirings, and vias have names (the configuration data is the database name, the wiring data is the wiring type name, and the through-hole data is the through-hole name), and its contents are stored in the database file (configuration module database, wiring type) The database and through-hole database 519 are confirmed by the same name as the database.

Moreover, since there are many applications of the transistor data, there are cases in which the database is managed independently of the panel layout data.

Fig. 6 is a view showing a structure of a mask material. Basically the same structure as the panel layout data. The top module 521 also has one. Under the top module 521, the plurality of repeating elements 522 and 523 exist as lower modules, and become the basic unit of the mask data.

As the material constituting the repeating element as the exposure element, first, the exposed object data includes the louver frame material 524, the correction pattern data 525, the cut data, the data 526 which is not the cut object, and the photographic frame material 527. In addition, including the width and height of the repeating elements 528, repeating elements The data 529, the lower module data 530, the configuration data 535, and the through hole data 536 laid out in the frame after the cutting are set.

The layout data of the module is the same as the panel layout data. For example, in the case of a liquid crystal panel, the configuration data 531 of each transistor including the thin film transistor or the liquid crystal driving portion, the wiring material 532, and the via information 533 are included. The configuration data 531, the wiring data 532, and the through-hole data 533 of these transistors have names, and the contents thereof are stored in the database file (configuration module database, wiring type database, through-hole database, alignment mark database) In 534, it is confirmed by being consistent with the database name.

In the case of a panel, it is also a data structure that is consistent with all database file names. Also, it is not used during exposure, but the frame data is also kept.

Moreover, there are many applications of the transistor data, and therefore there are cases in which the database is managed independently of the mask data.

Fig. 7 is a table showing an example of a physical layer, each data level, and a layer code of the mask layout data in the case of the metal layer and the second layer.

For example, when the metal layer (aluminum layer 1), the frame data is layer code 101, the louver frame data is layer code 102, the pattern data is layer code 104, the correction pattern is layer code 105, and the metal layer 2 (aluminum second layer) Layers) are also specified so that the layers are code independent and can be processed independently. These layer codes are common to each repeating element. That is, as long as the physical layer and the data level are the same, the layer code is common between the repeated elements.

The data of the reticle shown in Fig. 6 and Fig. 7 is finally output as a file, and the content thereof is a rectangular figure, a shape of a figure, and a width defined by a center line. The graphics, and the modules that concentrate the graphics data are composed of modules of the intermediate layer module or the database module. As a middle layer module or a database module, a transistor module is used.

The number of transistor modules is large, and when the data is expanded and held, the amount of data is large, so it is usually output in the form of an intermediate layer defined as a database module.

Among them, the graphic data is a rectangular shape (Rectangle) compared to the GDS format used as a de facto standard in the field related to the present embodiment, a rectangular shaped figure is a boundary (Boundary), and a wide graphic is defined as a path on the center line ( Path), the module that concentrates these graphic data is called a unit.

8 is a view showing a coordinate information output process performed by the mask manufacturing system executing a coordinate information output program, and shows numerical expressions and arrangement specifications (including alignment marks) of the repeating elements of the panel substrate and the photomask.

In FIG. 8, 801 is a panel substrate, 802 is a panel layout material, and 803 is an XY center coordinate of the panel substrate (in this example, coincident with the center coordinates of the four shot frames A) (0, 0), 804 is alignment The mark (the coordinate is a coordinate (X0, Y0) based on the center coordinate (0, 0) of the panel substrate 801).

805, 808, and 811 are photomasks, and 807 is an exposure area that ensures characteristics. Further, 806, 809, 810, 812, and 813 are repeating elements corresponding to the shooting frames A, B1, C1, B2, and C2, respectively.

In the example of FIG. 8, one repeating element 806 is formed on the reticle 805, two repeating elements 809, 810 are formed on the reticle 808, and two repeating elements 812, 813 are formed on the reticle 811.

The exposure data including the louver frame is used as the repeating elements 806, 809, 810, 812, and 813 are formed on the respective masks 805, 808, and 811. That is, the repeating element is constituted by exposure data composed of a louver frame, cut data, a correction pattern, and data that is not a cut object. This is the basis for shooting information.

In the present embodiment, even if there is no repetition, it is called a repeating element. The number of repetitions without repetition is 0. In the example of FIG. 8, the number of repeating elements 806 corresponding to the shooting frame A is 2 × 2 (= 4) (the number of repetitions 2 × 2-1) (thereby forming a repeated set 814 as a set of the repeating elements A) The number of repetitions of the repeating elements 809, 810, 812, and 813 corresponding to the shooting frames B1, C1, B2, and C2 is 0.

Each repeating feature has a name. Each of the repeating elements has a width (W) and a height (H) with respect to the coordinate center of each of the repeating elements themselves. Each of the repeating elements is arranged based on the center coordinates of the repeated set of the repeated elements. In the illustrated example, the center coordinate (0, 0) of the panel substrate 801 corresponds to this, and is disposed at a position based on the center coordinate (0, 0).

On the other hand, as the layout material of the reticle, each of the repeating elements is disposed at its center position with the center coordinate position of the reticle as a reference coordinate.

Regarding the alignment mark, the panel substrate 801 is placed at a position based on the center coordinate (0, 0) of the panel substrate 801, and the photomask is placed at a position based on the center coordinates of the mask. Alignment marks are stored and defined in the repository file.

9 is a view showing coordinate coordinate output processing performed by the mask manufacturing system executing the coordinate information output program, and shows an example of coordinate information output. As shown in FIG. 9, the output result when the three masks 805, 808, and 811 in which the repeating elements are arranged is generated by the panel layout material 802 on the panel substrate 801.

The following example is shown: as the exposure shooting information, the name of the repeating element, the number of repetitions, the arrangement position of the height and the width, and the same repeating element name are specified as the shooting information arrangement on the mask as the shooting information arrangement on the panel substrate. The width and height of the configuration location are provided to the user as coordinate information.

10 to 12 are views showing a method of dividing the exposure area, showing two division methods, and FIG. 11 is an example in which the correction pattern 1004 is generated when the panel layout data 1003 of FIG. 10 is divided and cut, and FIG. 12 is a division diagram 10. An example in which the panel layout data 1003 is cut and no correction pattern is generated.

In other words, when the correction pattern 1004 is generated, in FIG. 10 and FIG. 11, the material (for example, wiring material) 1003 is cut immediately below the imaging frame 1002, and the correction patterns 1004 and 1004 which are elongated by the predetermined length Δ are continuously generated at the cutting portion. At this time, the correction pattern 1004 may be configured to be wider than the cut portion by a predetermined length from a position closer to the inside of the predetermined length than the cut portion. In this way, the correction pattern 1004 is formed on the portion 1007 where the double exposure is performed.

The louver frame 1005 having a predetermined width is formed such that the outer position of the correction pattern 1004 and the inner position of the louver frame 1005 have a predetermined amount of deviation, and are overlapped by a predetermined amount, thereby producing exposure element data having a correction pattern. The inner edge 1006 of the louver frame 1005 is a portion that is elongated by a predetermined Δ than the imaging frame 1002. The inner edge of the louver frame 1005 becomes the outer edge of the exposed area.

Therefore, when the correction pattern 1004 is generated and cut, the cutting of the material 1003 is performed directly below the shooting frame 1002, and the correction pattern 1004 becomes a double exposure region in which both exposure elements are exposed, and the panel formed by the adjacent exposure elements The layout data ensures the connection by the correction pattern 1004.

On the other hand, when the correction pattern is not generated and the cutting is performed, the layout data is superimposed. When overlapping, as shown in FIG. 12, the cutting is performed by a portion that is elongated by a predetermined length Δ than the imaging frame 1002. In the adjacent imaging frame 1001, the mask is also formed by cutting at a portion elongated by a predetermined length Δ. In this way, the overlapping portion 1008 is formed on the portion 1007 where the double exposure is performed.

The louver frame 1005 having a predetermined width is formed such that the outer position of the overlapping portion 1008 and the inner position of the louver frame 1005 have a predetermined amount of deviation and overlap by a predetermined amount. In this way, the exposure element data having the overlapping portion 1008 is created. The inner edge 1006 of the louver frame 1005 is a portion that is extended by Δ from the imaging frame 1002. The inner edge of the louver frame 1005 becomes the outer edge of the exposed area.

FIG. 13 is a view showing an exposure element cut in the imaging frame 1002 having the oblique line portion 1301, and is an example of an exposure element in which the correction pattern 1004 is formed.

In FIG. 13, when the imaging frame 1002 having the oblique line portion 1301 can be set, it is effective to easily extract the repetitive structure.

The correction patterns 1004 and 1004 are set to predetermined correction values in the inner direction and the outer direction along the longitudinal direction of the cut wiring data 1003. Further, predetermined correction values are set on both sides in the width direction of the clamp wiring data 1003. The width of the louver frame 1005 can be in the horizontal direction Wh and vertical Directly specified in Wv.

The correction pattern 1004 corresponding to the level cut end is a rectangle, and the correction pattern 1004 corresponding to the hatched portion 1301 is a parallelogram.

As shown in FIG. 13, when the louver frame 1005 having the inner edge 1006 including the oblique line portion 1301, the data cutting portion requires double exposure of the correction patterns 1004, 1004.

Above, Figures 1 to 13 illustrate how to make mask layout data and coordinate information. In the present embodiment, the verification of the panel layout data synthesized by the mask layout data and the coordinate information thus produced is performed, and as a result, the mask data exposure verification is performed.

FIG. 14 is a block diagram showing the structure of a reticle verification system according to the present embodiment, and is an example of a program executed by a computer and the above computer. The mask verification system according to the present embodiment includes a central processing unit (CPU), a plurality of program groups running on the CPU, a storage unit for storing program groups and data, an input device including a keyboard and a mouse, and a display device. .

When the outline of the reticle verification system according to the present embodiment is described, the reticle verification system according to the present embodiment functions as an exposure device simulator, so that the reticle layout data displayed on the reticle window is displayed on the panel based on the coordinate information. On the substrate window. The graphics calculation process is performed and verified, and if a function of displaying an error graphic is added, a mask verification system is constructed. Among them, the window displaying the error pattern is, for example, a panel substrate window.

As a program structure, it is divided into the following three stages: as the initial setting, the reading of the mask layout data and coordinate information, and the creation of the internal table; the calculation processing between the grids of graphics and graphics and the verification where they are accompanied Rational; verification of the display of the resulting graph. These program functions can be performed by operating the commands displayed on the menu window.

As the display window of the graphic, at least the panel substrate window for displaying the verification result graphic is required, and the input portion and the calculation portion do not necessarily require the graphic display function, but it is convenient to have the graphic display function from the viewpoint of operation confirmation.

In Fig. 14, the mask verification system has a display unit 1 composed of a liquid crystal display panel or the like, an operation unit 16 composed of a keyboard 2 or a mouse 3, a central processing unit (CPU) 7, and a magnetic disk device and a semiconductor memory. A storage unit 8 composed of a body or the like.

At least three windows can be displayed on the display unit 1 : a panel substrate window 9 for operating panel layout data on the panel substrate 12 , a mask window 10 for operating the mask layout material on the mask 13 , and an operation of the operation portion 16 Menu window 11. The shooting frame set on the panel substrate window 9 is operated between the windows as an operation of setting the shooting frame on the reticle window 10.

The verification result of the mask data is displayed on the display unit 1, and may be displayed on any one of the panel substrate window 9, the mask window 10, and the menu window 11. Further, when the verification result of the mask data is displayed, the above-described windows 9 to 11 can be removed, and only the verification result is displayed in the area where the respective windows 9 to 11 exist.

The operation of the mask and the verification operation are selected by the operation unit 16 to select the command displayed on the function table window 11, and the operation unit 16 has the function of the command, and the operation unit 16 performs the setting of the imaging frame on the panel substrate window 9, and the panel substrate. 9 and movement between the reticle window 10, and the reticle window Various operations such as setting of the corresponding shooting frame on the 10th.

The storage unit 8 includes a program storage unit 4 that stores a mask data generation program executed by the CPU 7 and a mask verification program, and a data file storage unit 5 that stores data files such as input/output data and intermediate data during processing; and file storage. The part 6 stores a reference file such as a rule file and a database file.

As a configuration of the above-mentioned program, the program for mask production is composed of a shooting frame setting program, a repeating structure verification program, a minimum interval verification program between louvers, a data cutting program, a correction pattern generation program, and a louver frame generation. Program, coordinate information list output program, input and output programs for various data.

The functions of the shooting frame setting, the repeating structure verification, the minimum interval verification between the louver frames, the data cutting, the correction pattern generation, the louver frame generation, and the coordinate information list output are all performed by the operation unit 16 selecting a command displayed on the function table window.

Further, the program for verifying the mask data includes a program for inputting the processing unit, a program for the verification processing unit for the graphic calculation processing, and a program for the verification result display unit.

As a file configuration, the file configuration for the mask production is composed of a file layout file file as an input file, a mask layout data file as an output file, and a coordinate information list file, and a database file as a reference file. And rules file. Further, the panel layout data file, the mask layout data file, and the coordinate information list file as the data files are stored in the material file storage unit 5. The database file and the rule file as the reference files are stored in the reference file storage unit 6.

Further, the file configuration for mask verification is composed of a database as a reference file in addition to the mask layout data and the coordinate information file as the input file, the mask data file as the output file, and the coordinate information list file. File and rule files.

In this way, a reticle design system that performs the reticle layout or a reticle data verification system that performs verification of the reticle data is constructed.

The display unit 1, the operation unit 16, and the storage unit 8 constitute a display unit, an operation unit, and a storage unit, respectively.

When the display unit, the operation unit, and the storage unit function as a mask manufacturing system, the following functions can be achieved.

For example, the display unit may display at least: a panel substrate window displaying panel layout data of the panel substrate, a mask window displaying the mask layout data, and a function table window displaying commands of the operation unit.

The operating unit selects the command displayed on the menu window and enters it. In this way, the shooting frame set on the panel layout data of the panel substrate can be subjected to operations such as designating repeated arrangement.

The storage unit can function as a primary storage device and an external storage device. The storage unit can store conditions for cutting the panel layout data, conditions for including the width of the correction pattern, and the minimum distance between the louver frames. And, the generation condition set by the operation unit can be stored in the storage unit.

Further, the CPU 17 constitutes a reticle data generating unit, a repeating verification unit, and a louver frame interval verifying unit in the reticle producing system. The mask data generating unit cuts out the panel layout data corresponding to the shooting frame set on the panel substrate window by using the operation unit, as part of the panel layout data. Extracting, when the part of the panel layout data includes the cutting data, forming a correction pattern at the end of the cutting data, and forming the panel layout by forming the inner edge and the louver frame corresponding to the outer edge of the correction pattern The exposure element data corresponding to the data is generated on the reticle window. Further, the reticle data generating unit may generate the above-described exposure element data to satisfy the above-described generation condition.

The reticle data generating unit has the following unit: cutting out the panel layout data corresponding to the shooting frame set on the panel substrate window by the operating unit, and extracting the panel layout data as part of the panel layout data; the partial panel layout data includes the cut When the data is broken, a correction pattern generating unit that forms a correction pattern at an end portion of the cutting data; and a louver frame generating unit that forms an inner edge and a louver frame corresponding to an outer edge of the correction pattern. The exposure element data corresponding to the partial panel layout data described above may be generated on the reticle window.

Moreover, the duplicate verification unit can compare whether the panel layout data corresponding to the comparison shooting frame and the area designated by the repeated arrangement are consistent.

Moreover, when the louver frame interval verification unit has a plurality of the louver frames, it is possible to verify whether the louver frames are separated by a predetermined minimum interval or more.

On the other hand, when the display unit, the operation unit, and the storage unit function as a mask verification system, the following functions can be achieved.

For example, the display unit can display the results of the verification unit verification. And, the display unit may have at least a window displaying the verification result. And, the display unit can display the graphic obtained by the verification result of the verification unit to the above window.

Further, when the display unit displays the error graphic information on the window displaying the verification result, the verification result graphic information of the error layer specified by the specifying unit may be displayed on the window in a layer unit. Moreover, the display unit has a dialog box different from the window for displaying the verification result, displays the number of errors on the dialog box, and responds to the designation of the error layer by the designated unit, and displays the verification result graphic information of the layer on the window.

The operating unit can function as a designated unit. The specified unit can specify the error layer contained in the incorrect verification result. And, the specifying unit can specify an error layer on a dialog box different from the window.

The storage unit can store: graphic data of the exposure element contained in the exposure cover of the flat panel display; coordinate information represented by the coordinates of the grid lattice point, and coordinate information indicating the exposure position of the exposure element on the display panel.

Further, the CPU 7 functions as a layout graphic element generation unit, a verification unit, and an expansion unit.

The layout graphic element generating unit may generate a layout graphic element on the display panel corresponding to the exposure element according to the graphic data and the coordinate information of the exposure element stored in the storage unit.

The verification unit can verify the exposure element according to the positional relationship of the plurality of layout graphic elements on the display panel generated by the layout graphic element generation unit. Moreover, the graphic data of the exposure element is defined by at least three types of line data, rectangular data, and polygonal data describing each vertex, and the verification unit can perform the grid grid corresponding to the layout graphic elements. The calculation process between the verifications verifies the above multiple exposure elements.

The verification unit may have a difference extraction unit that performs two layout diagrams After the logical OR processing of the shape element, logical XOR processing or difference processing of the pattern element obtainable by the result of the above-described one of the layout pattern elements and the logical OR is performed, thereby extracting the difference between the two layout pattern elements.

The verification unit may have an overlap amount detecting unit that detects the overlap amount of the two layout pattern elements by performing logical AND processing of the two layout pattern elements.

The verification unit may have a deviation verification unit that verifies whether the amount of overlap detected by the overlap amount detection unit satisfies the indicated deviation value.

The verification unit may have an element determination unit that performs logical OR processing after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements, and determines that the result is that when the two layout pattern elements form a closed pattern. The two layout graphic elements are continuous graphic elements.

Moreover, the data of the reticle may be constituted by an intermediate layer defining a transistor pattern or an external database having a defined transistor pattern as an intermediate layer. In this case, the expansion unit may have an intermediate portion defining the above transistor pattern. The layer or external database constructs a table structure that is expanded as needed through the indicator.

And each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit may have an end point verification unit that verifies the grid grid on the display panel corresponding to the inner edge of the louver frame. Whether or not the end point of the layout graphic element of the above graphic element exists within the range of the specified offset value.

Moreover, the program stored in the storage unit can use a computer having a display unit, an operation unit, a storage unit, and a CPU as a mask having the above functions. Verify that the system is working.

Fig. 15 is a flowchart showing the processing of the reticle verification system according to the embodiment of the present invention.

In Fig. 15, the input mask layout data is a data in the form of a representation in the so-called GDS format, which is a form expressed by a complex grid lattice point as a point whose coordinate value is known, and is a form allowing the intermediate layer to be constructed. data of. The reticle data file contains graphic data of exposure elements contained in the reticle for exposure of the flat panel display.

Usually, a transistor layer is used as the intermediate layer. Depending on the situation, there is also a case where the transistor layer is installed independently as an external database and a mask layout data file. However, even if it is installed independently, it is actually equivalent to the middle layer.

The coordinate information describing the repeated arrangement position of the repeated elements described in the mask layout data file is usually a text file. The coordinate information includes information indicating an exposure position of an exposure element on the display panel, which is represented by a grid lattice point coordinate.

The processing is composed of the following three stages: an input processing stage (step S151), an input processing program stored in the execution program storage unit 4, a verification processing stage (steps S152 and S153), a verification processing program for executing the graphic calculation processing, and graphics and The calculation processing between the grid grid points of the graphic; and the display phase (step S154), executing the verification result display program, and displaying the verification result.

In the input processing stage (step S151), the CPU 7 performs an input of reading the mask layout data file and the coordinate information file from the material file storage unit 5. The processing creates an exposure element data structure on the panel substrate based on the arrangement information of the repeated elements based on the coordinate information.

Here, it is produced in such a manner that a table structure (see Table Structure 1 of FIG. 17 below) which can be easily picked up by another repeating element connected to one repeating element space is formed. Further, when the reticle data has the intermediate layer, the amount of data is reduced, and the reticle data is produced in such a manner that the intermediate layer is easily picked up to the lowermost table structure (the following table structure 2).

After that, the CPU 7 proceeds to the verification processing of the calculation processing of the graphics (steps S152, S153). Calculations include logical calculations and differential calculations. As will be detailed later, the items to be verified are divided into a large aspect: verification of the double exposure area, verification of the connection exposure 1, verification of the connection exposure 2, and verification of the non-exposed area.

The logical calculations required to perform these verifications are AND, OR, and XOR. A differential calculation can also be used instead of XOR. This logical processing or differential processing is all computational processing between grid grid points. These calculation processing results are stored as graphic data. The CPU 7 performs processing of the processing of step S153 on all the layers (step S153).

Finally, the CPU 7 performs a display process of displaying the result of the calculation process on the display unit 1 (step S154). The object to be verified is the verification of the double exposure area, the verification of the connection exposure 1, the verification of the connection exposure 2, and the verification of the non-exposure area, and therefore, in accordance with the judgment reference (parameter) set by the operation unit 16, it is represented in the form of graphic data. One of the corresponding verifications. This graphic material is information indicating an error.

It is important that the calculation processing of the logic processing or the differential processing is performed in layer units, and the created exposure error data is also stored in the data unit in the layer unit. In the file storage unit 5. This is because the exposure is performed in layer units, so verification must be performed in layer units. Further, since the display unit 1 also changes to a layer unit when displayed, the access time is faster when the error data is stored in the layer unit.

Further, when the CPU 7 displays the processing result on the display unit 1, the error data may be displayed only when the determination criterion of the error data is set, and when only the determination criterion of the error data is not set, only the processing is displayed. result. Further, when the CPU 7 displays the processing result on the display unit 1, the graphic is not necessarily displayed, and the error content may be displayed by a character or the like, or only the processing result may be displayed when the determination as to whether or not the error is not made.

FIG. 16 is an explanatory view for explaining the relationship between the mask layout material 162 on the mask 13, the repeating element 163 in the mask layout data 162, the coordinate information, and the panel layout data 161 on the panel substrate 12.

Further, FIG. 17 is a table structure 1 showing the repeating elements 163 which may be multiple exposure, connection exposure 1, and connection exposure 2 in the repeating element 163 shown in FIG. 16, and is stored in the material file storage unit 5 of the storage unit 8.

The above table contains the address, instance name, duplicate feature name, double exposure or connection exposure 1 or the number of indicators connected to exposure 2 and indicator information.

The address is an address indicating the order of the duplicate element data to be arranged, the instance name is a unique name of the duplicate element to be placed, and the duplicate element name is the database name of the duplicate element described in the mask data. Also, an instance is a graphical element of a centralized unit consisting of a single or complex graphical element (eg, unit, device, etc.).

Each of the repeating elements 163 included in the mask layout data 162 disposed on the reticle 13 is exposed to a predetermined position on the panel substrate 12 according to the coordinate information. Light, forming corresponding panel layout elements on the panel substrate. As shown in the repeating element A1_1, in the case of repeating the repeated elements 163 of exposure, a predetermined number of exposures are performed at the position determined by the coordinate information. In this way, panel layout data composed of a plurality of panel layout elements is formed on the panel substrate 12.

The logical processing or the differential processing between the repeating elements 163 disposed on the panel substrate 12 is the main processing, and therefore it is preferable to easily pick up the adjacent repeating elements 163 from a given repeating element 163.

Among them, the data of the width W and the height H of the repeating element 163 in the mask layout material 162 is utilized. The width W and the height H indicate the smallest area beyond which the data does not exist. In the table structure 1, the width W and the height H of each of the repeating elements 163 maintain the index to the adjacent repeating element 163. The above indicator is an address indicator, and the address of the relevant duplicate element 163 is given as an indicator.

The adjacent ones include the following three modes: at least one overlap of the wide W direction area and the high H direction area; connection; the grid grid spacing is adjacent to each other. Since the width W and height H of the outer contour shape are adjacent, whether the actual exposure data is adjacent when they are adjacent is another problem, but as long as the width W and the height H are not adjacent, the actual exposure data are not adjacent. In short, a table structure that is easy to search for suspicious places is created, and a structure in which not all objects are used as verification objects is used. Thereby shortening the processing time.

18 is a view showing a structure of a material on a panel substrate produced by mask layout data and coordinate information, and FIG. 19 is a view showing a table structure 2 corresponding to the material structure of FIG. 18, showing a table structure in which a hierarchical structure is maintained. .

In Fig. 18, the only repeating elements 182, 188 are disposed in the lower layer of the top-level module located at the top of the hierarchical structure. The configured repeating elements 182, 188 are, for example, a transistor layer.

The lower layer of the arranged repeating elements 182 is arranged side by side: a series layer structure composed of a pattern data 183, a transistor (TR1) 184, and a pattern data 185, and a series layer structure composed of a transistor (TR2) 186 and a pattern data 187.

The lower layer of the arranged repeating elements 188 is arranged side by side: a series layer structure composed of a pattern data 189, a transistor (TR1) 190, and a pattern data 191, and a series layer structure composed of a transistor (TR2) 192 and a pattern material 193.

Moreover, in FIG. 19, the above table has an address, an instance name, a duplicate element name or a database name, an indicator to a graphic data, an intermediate layer module instance name, an intermediate layer module database name, and an intermediate layer module. Indicators for the group database.

The repeating element exists in the case of having an intermediate layer, and in many cases, it is a transistor layer. When the crystal layer is unfolded, the amount of data is large. Therefore, in the present embodiment, the intermediate layer is not developed in advance, and in the state of the intermediate layer, the data is held as a database by the index structure, and dynamic processing is performed as needed. .

The use of an intermediate layer that exhibits the same lower position even in two different intermediate layers does not make it a common method. This is because even if the crystals appearing in the repeating elements of importance appear in other repeating elements, they can be completely expanded only in the important elements. In Figure 19 is the following example: electro-crystal The bodies TR1 and TR2 appear in different repeating elements, but the forms are registered independently.

20 and 21 are diagrams for explaining logical processing or differential processing and verification processing of graphics, showing graphics logic processing or graphics difference processing for single-sided exposure area detection. Here, the one-sided exposure refers to a case where an adjacent element is compared with an element having only one side of the repeated element exposure in the adjacent portion.

For example, in FIG. 20, when the repeating element A of the reticle and the repeating element B of the reticle are placed on a designated coordinate on the panel substrate, the panel layout elements corresponding to the repeating element A and the repeating element B are overlapped as the area A', B' is disposed on the panel substrate.

When the area A' is a region on the panel substrate corresponding to the repeating element A, a portion of the region B' on the panel substrate corresponding to the repeating element B is projected in this region. That is, the region A' is a region on the panel substrate, and corresponds to the region of the repeating element A and the logical portion of the overlapping portion 2001, and a part of the panel layout element B' corresponding to the repeating element B is projected therein.

Similarly, the region B' is a region on the panel substrate, corresponding to the region of the repeating element B and the logical portion of the overlapping portion 2001, and a part of the panel layout element A' corresponding to the repeating element A is projected therein.

Therefore, as shown in FIG. 21, when the panel layout elements of the panel layout element A and the area A' on the panel substrate corresponding to the repeating element A are XORed, the presence is present on one side and not on the other side. Area (unilateral exposure area) 2101 data.

This is usually an overlap specified error. This error is a frame frame designation error when the mask data is created, or a louver frame designation error when the mask material is created, or a designation coordinate error. Usually, the exposure data of the overlapping parts must be completely overlapped by both.

In addition, the performance of taking the XOR difference is the same. In this case, the difference (A-A') is taken. When the result is positive, the data existing in the repeating element A and not in the repeating element B is superimposed. When the result is negative, the opposite is present in the repeating element A. The data of the repeating element B overlaps.

In this case it is the latter. If the same information is to be obtained from the XOR result, the XOR result and the repeated elements A, XOR results, and the AND of the repeating element B are taken. When the result of the former is logic 1, the present is present in the repeating element A and not in the repeating element B. The data overlaps, and when the latter result is logic 1, the data existing in the repeating element B does not overlap with the repeating element A.

The difference result has a flag, and the amount of information is larger than that of a single logic process. If the XOR result is to obtain exactly the same information as the difference process, an additional AND process is required. In short, if it is logical processing, OR and XOR and AND, if it is differential processing, it is OR and differential processing, so as to obtain the full equivalent verification result as information.

22 to 24 are diagrams for explaining OR processing of single-sided exposure region detection using a grid lattice.

Both the logic processing and the differential processing are performed between the grid grids. Wherein, the definition of OR indicates that when the result is logic 1, the grid lattice is exposed, and when logic 0, the grid is not exposed.

In FIG. 22, on the panel substrate corresponding to the repeating element A The logical layout processing of the panel layout element A and the panel layout element B on the panel substrate corresponding to the repeating element B results in the overlapping state of the panel layout elements A and B of the overlapping elements A and B by the overlapping unit 2001. In Fig. 22, the center line 2201 of the overlapping portion 2001 is displayed on the grid.

Fig. 23 shows the grid points for display corresponding to Fig. 22, and the center line 2201 of the corresponding overlapping portion is described for easy understanding of the drawings. That is, the processing results of the exposure data L of the repeating element A, the exposure element R of the repeating element B, and their logical ORs are shown.

Fig. 24 is a table showing logical values for defining the logical sum (OR) of each grid grid point shown in Fig. 23. The logical value of ○ is 0, which is an unexposed grid grid point. The logical value of ● is 1, which is the grid point of the exposure grid. ● The enclosed area becomes the exposed area.

A diagram of the result of the logical OR processing shown in FIG. 23 is displayed on the display unit 1. The display portion may be any one of the panel substrate window 9 and the mask window 10. Further, the panel substrate window 9, the mask window 10, and the function table window 11 may be removed, and the processing result of FIG. 23 may be displayed in all areas of the display unit 1. Further, it may be displayed by a character. In this case, it may be displayed in any one of the panel substrate window 9, the mask window 10, and the function table window 11, or these windows may be removed, and displayed in the entire area of the display unit 1 by text. process result.

25 and FIG. 26 are explanatory diagrams when the exclusive logic and (XOR) processing or the difference processing of FIG. 21 are performed using the grid lattice points.

In Fig. 25, the exposure data (panel layout element) of the repeating element A on the mask is L, and the exposure data of the area A' on the panel substrate (panel) The layout element is R, indicating the processing result of these logical XOR or difference.

Fig. 26 is a view showing the definition of the exclusive logic sum (XOR) of each grid point of the exposure data L, R shown in Fig. 25, and the (LR) difference processing of each grid grid point using the exposure data L, R. Logical value table.

The logical value of ○ is 0, indicating that there is an exposure data in both of the exposure data L and R, or a mesh in which no exposure data exists in both of the exposure data L and R. Further, the logical value of ● is 1, indicating that there is a grid of exposure data on one side of the exposure data L, R. Further, positive ● indicates that there is exposure data in the exposure data L, and negative ● indicates that exposure data exists in the exposure data R.

In this way, the grid points of the exposure that are only present in the one-sided area are detected. In the differential processing, the information on which side the exposed grid point is added by the positive and negative marks. Therefore, in the XOR, only the results can be judged to be different, and in the case of the difference, it is convenient to attach the information of the exposure data on one side in which region by the positive or negative flag.

As a result of performing XOR or differential processing, in the case of logic 1, the grid indicates that the exposure data exists only on one side of the graphic material, and in the case of logic 0, the grid indicating that the exposure data exists or does not exist on both sides .

27 and 28 are explanatory views showing the superposition of the most general panel layout elements.

FIG. 27 is a diagram showing the desired exposure data 2707 of the reticle with the unexposed grid grid dots 2704 and the exposed grid grid dots 2705.

Further, FIG. 28 is a view showing that the repeated elements of the divided mask are exposed based on the coordinate information, thereby reproducing the materials according to the obtained exposure data A and B. A diagram of the morphology of material 2707.

With respect to the divided area and the exposure data 2707 to be cut immediately below, the overlapping amount of the overlapping area 2703 is specified, and the mask layout data is created. Therefore, it is necessary to verify whether or not the restoration is correctly performed.

When the amount of overlap is specified by the operation unit 16 as the deviation value, it is stored in the storage unit 8, and the CPU 7 judges that it is not an error when it is within the range. In FIG. 27 and FIG. 28, the center line 2706 of the overlapping portion 2703 is described for the sake of easy understanding. In this example, the centerline 2706 is grid-based, but depending on the method of overlap, there are also cases where the grid is not based.

29 is a view showing a repeating element (panel layout element) A (L) disposed on a panel substrate, FIG. 30 is a view showing a repeating element B (R) disposed on a panel substrate, and FIG. 31 is a view showing a panel disposed on a panel; An explanatory diagram of the logical product (AND) of the repeating elements A and B on the substrate. 32 is a logical value table of AND of the repetition elements A and B arranged on the panel substrate, and shows the definition of AND for each grid lattice point.

In FIGS. 29 to 32, the arranged repeating elements A and B indicate the non-exposed area and the exposed area by the unexposed mesh grid point 2901 indicated by ○ and the exposed grid grid point 2902 indicated by ●.

Further, in FIG. 31, the arranged repeating elements A and B are overlapped by the overlapping unit 2703. This is the most common example of double exposure that produces overlap. When the detected overlapping portion 2703 is not a predetermined deviation value within the specified width plus or minus, it is not an error.

33 to 36 are diagrams showing an example of a double exposure region extracted by an AND process. And, by the unexposed grid lattice indicated by ○ The dots and the grid points of the exposure indicated by ● indicate the non-exposed area and the exposed area.

33 is an example in which the two overlapping elements A and B arranged on the panel substrate are arranged with the overlapping amount of the overlapping portion 2703, similarly to the example shown in FIGS. 29 to 32. By the AND processing of the arranged repeating elements A and B, the amount of overlap (deviation value) is a three-grid grid, and it is normally judged to be normal.

FIG. 34 shows an example in which the two overlapping elements A and B arranged on the panel substrate have only one grid grid shared by the overlapping unit 2703, and have not entered a predetermined width value of a predetermined width plus or minus, and are generally judged to be erroneous. In the present embodiment, as shown in FIG. 34, when the overlap region is a grid grid, it is referred to as connection exposure 1.

The example of Fig. 35 is a data arrangement in which two repeating elements A and B arranged on a panel substrate are spaced apart by one grid grid. In the present embodiment, this example is referred to as connection exposure 2, and it is generally determined to be an error. In this example, the area of the AND processing result is not extracted, but when a closed pattern is extracted by performing the OR processing, it can be judged that the type of the exposure 2 is connected.

The example of FIG. 36 is a data arrangement in which two repeating elements A and B arranged on a panel substrate are spaced apart from each other by two or more grids. In this example, the area of the AND processing result is not extracted, and the two repeating elements A, B disposed on the panel substrate are between the two grids, and there is one or more non-exposed area grid grid points 3601. It is detected by the extraction of the non-exposed area 3601 described below.

37 and 38 are explanatory views of the case where the mask material having the repeating element to which the correction pattern is added is double-exposed.

In FIG. 37, the first layer metal wiring 3702 and the second layer metal wiring 3703 in the panel layout data are cut by the set imaging frame 1002.

When the correction pattern is provided, as shown in FIG. 38, each end portion of the first layer metal wiring 3702 and the second layer metal wiring 3703 has a predetermined length wider than the first layer metal wiring 3702 and the second layer metal wiring 3703. The size is continuously formed integrally in the longitudinal direction thereof to form a correction pattern 1004 having a predetermined length.

The louver frame 1005 having a predetermined width is formed such that the inner edge 1006 overlaps the outer edge side of the correction pattern 1004 by a predetermined length (for example, one grid lattice).

A predetermined wide louver frame 1005 is formed such that the inner edge 1006 of the louver frame 1005 and the outer edge of the correction pattern 1004 are overlapped by a predetermined length (for example, a 1 grid).

Further, the louver frame 1005 and the correction pattern 1004 may not be overlapped, and the inner edge of the louver frame 1005 and the correction pattern 1004 may be formed in a connected manner.

Among them, the generated correction pattern 1004 becomes the area 1007, which is a double-exposed object.

Therefore, as shown in FIGS. 39 and 40, the result of the AND processing is also used to verify whether or not the correction pattern 1004 is correctly double-exposed.

That is, in FIG. 39, the repeating elements A and B arranged on the panel substrate are arranged to overlap the photographing frame areas 3903 and 3904 specified in the shooting frame 1002. In this way, the correction pattern 1004 of the repeating element A overlaps with the correction pattern 1004 of the repeating element B, and is double-exposed, and the metal wiring 3901 of the repeating element A and the metal wiring 3902 of the repeating element B are continuously formed on the panel substrate.

Fig. 40 is an explanatory diagram showing the form of a grid dot. In FIG. 40, the shot frame area 3903 overlapping the repeating element A and the shot frame area 3904 of the repeating element B are subjected to AND logic processing between the grid grid points of the repeating elements A and B, and a continuous area A is formed. ', B'. In addition, ● is a logic 1, indicating the grid point of the exposure, and ○ is a logic 0, indicating the grid point of the unexposed grid.

Also, Figure 38 illustrates dual exposure verification of the inner edge 1006 of the louver frame and the graphic material. That is, to what extent the verification pattern data (the correction pattern 1004 in the case of FIG. 38) enters into the inside of the louver frame 1005, and at this time, it is usually "1" as the connection exposure 1 (refer to FIG. 34), that is, one grid Sub-overlapping connections. In other words, in the normal case, the case where the deviation value of the overlap amount is one grid grid is normal.

However, at this time, the AND processing is applied, and the double exposure area is larger or smaller than the above-specified deviation value, which is an error.

Moreover, the double exposure verification of the inner edge edge 1006 of the louver frame of FIG. 38 and the graphic material is somewhat different in this verification. That is, only the mask layout data can be verified, so coordinate information is not required. However, as shown in FIG. 15, when a series of processing is performed, it is of course possible to perform verification processing on the result of the configuration based on the coordinate information.

FIG. 41 and FIG. 42 are explanatory diagrams for explaining the verification processing of the presence or absence of the non-exposed area, that is, whether or not all areas of the panel substrate are covered by the mask layout material 162.

As shown in FIG. 41, the repeating element 163 in the mask layout material 162 provided on the mask 13 is simulated on the panel substrate 12 based on the coordinate information. The exposure processing is performed, and the layout panel layout material 161 is formed analogly on the panel substrate 12.

When the repeating element 163 in the mask layout material 162 is placed on the panel substrate 12 based on the coordinate information, as shown in FIG. 42, the exposed object region included in the inner edge of the louver frame of the repeating element 163, and the exposure are taken The logical OR of the area of the panel substrate 12 corresponding to the object area. It is performed on all of the repeating elements 163. If there is a grid of lattices that becomes a logical zero on the panel substrate 12, the area is an area that is not an exposed object, and is an error.

Fig. 41 shows an example in which the repeating element R1 is absent, so that on the panel substrate 12, an area 4101 which is not covered by the mask material (the panel layout data is not formed) is generated, at which time the CPU 7 recognizes that it is an error.

The relationship between the logical processing of the mask material described above and the verification project is organized as follows.

For single-sided exposure verification, logic processing or differential processing takes the logical sum (A OR B) of A and B for graph A and graph B, and takes the exclusive logical sum of area A' of graph A and graph A with its result (A ' XOR A). Or take the difference between the area A' of the graph A and the graph A containing the result of the above logical sum. As the detection project, data existing only in the region including the pattern A and the region existing in the pattern B is detected (see FIGS. 20 to 26).

In double exposure verification (with connection exposure 1), logic processing or differential processing takes the logical product (A AND B) of A and B for graph A and graph B. As the detection project, the double exposure area detection is performed, and it is determined whether or not it is an error based on the set parameters. When it is determined to be an error, the determination result is output as an error report (see FIGS. 27 to 36, 39, and 40).

In the case where the exposure 2 is connected, the logical processing or the differential processing takes the logical product (A AND B) of A and B for the graph A and the graph B. When the result is logic 0 (no graphics), and the result of logical sum (A OR B) of A and B forms a pattern, as the detection project, the detection of the connection exposure 2 area is performed, and whether the error is determined according to the set parameter is When it is determined that the error is an error, the result of the determination is output as an error report (see FIGS. 39 and 40).

For non-exposure verification, logic processing or differential processing deploys all mask layout data on the panel substrate for logical AND (OR) processing. As the detection project, the grid grid points where the OR bit is not satisfied (the result of the OR processing is logic 0) are detected as non-exposure regions (see FIGS. 41 and 42).

43 and 44 are explanatory diagrams for explaining a graph of the verification result, FIG. 43 is a view showing a dialog box 431 displayed on the display unit 1, and FIG. 44 is a diagram showing a form of graph data displayed on the panel substrate window 12 of the display unit 1. The error shows the graph.

The setting of the verification condition or the like is set by the operation unit 16 operating the operation button in the dialog box 431. For example, the verification is all performed in the layer unit, so the operation unit 16 performs designation of the layer to be displayed in the dialog box 431, and then specifies the type of error to be displayed to indicate the retrieval.

Among them, the types of errors to be displayed include one-sided exposure, double exposure, connection exposure 1, connection exposure 2, and non-exposure. Each error type specifies the color of the display. In Fig. 44, ● indicates a grid lattice point (error grid lattice point) having any one of the above five errors, and ○ indicates a grid lattice point having no such error.

The CPU 7 displays the error to the user in accordance with the set conditions.

Next, the user operates the operation buttons in the display operation area 432 by the operation unit 16, and indicates the next, the front, the first, and the last of the error location. At this time, the instructed content is displayed on the error area displayed on the panel substrate window 12.

Usually, the wrong location displays a complex number. For example, if the next one is specified, the displayed resolution is shifted to the right from the upper left side. If there is no area on the right side, jump to the lower left side to display. And when the indication is enlarged or reduced, the center coordinates displayed at this time display enlarged or reduced chart data.

45 is a view showing a data structure of a detected error pattern. In the top module 451, the error data automatically generates the module names of the error modules 452, 454, 456, and 458, and performs chaining. The erroneous graphical data 453, 455, 457, 459 is chained directly below each of the error modules 452, 454, 456, 458. The instance names and database names of the error modules 452, 454, 456, and 458 are the same, so even error data of the same shape is not shared. This is because the errors are generated substantially independently on the panel substrate.

As described above, in the reticle verification system according to the embodiment of the present invention, the CPU 7 refers to the graphic data and the coordinate information of the exposure element stored in the material file storage unit 5 of the storage unit 8 to generate a display panel corresponding to the exposure element. The panel layout element (layout graphic element) on the upper panel displays the verification result based on the positional relationship of the plurality of panel layout elements to the display unit 1. Further, when it is determined whether or not it is an erroneous criterion, the positional relationship of the plurality of panel layout elements is determined to verify whether or not the exposure element is erroneous, and the verification result is displayed on the display unit 1. In the display unit 1, the panel base The above verification result is displayed in the panel window 9 or the mask window 10, or in a display area unrelated to these windows.

Therefore, the mask verification system according to the present embodiment inputs the arrangement information of the mask layout data and the exposure elements (repeating elements), simulates the operation of the exposure apparatus, and performs pattern calculation processing to simulate exposure processing and whether or not to pass the mask. Verification of appropriate panel layout data is formed on the panel substrate, in other words, whether the mask is properly verified.

That is, whether the reticle data produced is correct, the reticle data can be verified by the analog exposure device and the graphic calculation process. Especially in the manufacture of a flat panel display, the verification of the reticle data used can exert its power. According to the embodiment, whether the panel substrate material produced by the reticle layout data and the coordinate information is correctly exposed data can be verified.

Further, a verification function based on the motion simulation and the graphic calculation processing of the exposure device can be added, so that it can be verified before entering the manufacturing process.

As a result, in the manufacture of a flat panel display, there is a great effect in terms of the cost including the work time. In other words, by performing the mask verification system according to the embodiment of the present invention before manufacture, it is possible to prevent the occurrence of an unnecessary cost burden by confirming whether or not the mask is correct.

The reason for this is that the manufacturing cost of the mask, the manufacturing cost of the panel substrate, and the manufacturing time and the analysis time including the labor cost at the time of erroneous manufacturing are not required to be excessive. This effect is also the same in the case of a simple repeat configuration design requiring only region division. This is because there are many cases where the person specified in the designation error is repeated.

And, according to the present embodiment, a pass can be provided by having a display The computer of the unit 1, the operation unit 16, the CPU 7, and the storage unit 8 executes a mask verification program for constructing the mask verification system. A reticle verification method that achieves the above effects is also provided.

Further, in the above embodiment, the reticle verification system is constructed using one computer, and it is also possible to construct using a plurality of computers. In this case, each of the above programs can be appropriately divided according to the system configuration.

The present invention can be applied to a mask verification system that performs verification of various types of display manufacturing masks such as liquid crystal displays. Further, the present invention is also applicable to a program that functions as a mask verification system that performs verification of various types of display manufacturing masks.

1‧‧‧Display Department

2‧‧‧ keyboard

3‧‧‧ Mouse

4‧‧‧Program Storage

5‧‧‧Data Archives Storage Department

6‧‧‧Archives Storage Department

7‧‧‧CPU

8‧‧‧Storage Department

9‧‧‧ Panel substrate window

10‧‧‧mask window

11‧‧‧Menu window

12, 101, 210, 801‧‧‧ panel substrate

13, 205, 805, 808, 811 ‧ ‧ masks

16‧‧‧Operation Department

102, 212‧‧‧Exposure areas

103‧‧‧Exposureable area

104‧‧‧Light source system

105‧‧‧Lighting system

107‧‧‧Exposure surface

162‧‧‧Photomask layout information

163‧‧‧Exposure elements (repeated elements)

201~204‧‧‧LCD panel

206‧‧‧Photomask layout information

161, 211, 802, 1003‧‧‧ panel layout information

213, 1002‧‧‧ shooting frame

431‧‧‧Dialog Box

432‧‧‧Display operating area

804‧‧‧ alignment mark

806, 809, 810, 812, 813‧‧ ‧ repeating elements

1004‧‧‧correction pattern

1005‧‧‧ louver frame

1006‧‧‧ inner edge

1007‧‧‧Double exposure

1008, 2001, 2703‧‧‧ overlap

1301‧‧‧Slash Department

2101‧‧‧One-sided exposure area

2201, 2706‧‧‧ center line

2707‧‧‧Exposure data

2704, 2705, 2901, 2902‧‧‧ grid grid points

3601‧‧‧Unexposure area grid grid points

3702, 3703, 3901, 3902‧‧‧ metal wiring

3903, 3904‧‧‧ Frame area

1 is a view showing a relationship between a panel substrate for a flat panel display and a photomask according to an embodiment of the present invention; and FIG. 2 is a view showing panel layout data on a panel substrate and mask layout information on a photomask according to an embodiment of the present invention; FIG. 3 is a view showing the overall display content when the mask data is generated in the embodiment of the present invention; and FIG. 4 is a flowchart showing the overall processing when the mask data is generated in the embodiment of the present invention. FIG. 5 is a view showing a structure of panel layout data in an embodiment of the present invention; and FIG. 6 is a view showing a structure of a mask material in an embodiment of the present invention; 7 is a table showing mask data in the embodiment of the present invention; FIG. 8 is a view showing coordinate information output processing in the embodiment of the present invention; and FIG. 9 is a graph showing coordinate information output processing in the embodiment of the present invention. FIG. 10 is an explanatory view showing a method of dividing the exposure region in the embodiment of the present invention; FIG. 11 is an explanatory view showing a method of dividing the exposure region in the embodiment of the present invention; FIG. 13 is a view showing an exposure element in an embodiment of the present invention; FIG. 14 is a block diagram showing a mask verification system according to an embodiment of the present invention; 15 is a flowchart showing the processing of the mask verification system according to the embodiment of the present invention; FIG. 16 is a diagram showing the relationship between various materials in the embodiment of the present invention; and FIG. 17 is the data in the embodiment of the present invention. FIG. 18 is a view showing a material structure on a panel substrate in an embodiment of the present invention; and FIG. 19 is a view showing a data structure on a panel substrate in an embodiment of the present invention; FIG configuration corresponding to the table; FIG. 20 is a graph showing the various process embodiments of the present invention in FIG. 21 is an explanatory view showing various processes of the pattern in the embodiment of the present invention. FIG. 22 is an explanatory view showing an OR process of the one-side exposure area detection in the embodiment of the present invention; FIG. 24 is an explanatory view showing an OR process of single-side exposure region detection in the embodiment of the present invention; FIG. 25 is an explanatory view showing an OR process of the present invention. FIG. 26 is an explanatory diagram showing exclusive logic and processing or difference processing in the embodiment of the present invention; FIG. 27 is an explanatory diagram showing exposure data in the embodiment of the present invention. FIG. 28 is an explanatory view showing overlapping of exposure data in the embodiment of the present invention; FIG. 29 is a view showing a repeating element disposed on the panel substrate in the embodiment of the present invention; A diagram of a repeating element disposed on a panel substrate in an embodiment of the present invention; and FIG. 31 is a diagram showing a logic of a repeating element disposed on a panel substrate in an embodiment of the present invention; An illustration of the accumulation; FIG. 32 is a diagram showing the arrangement of the panel substrate in the embodiment of the present invention. FIG. 33 is a view showing an example of a double exposure region in the embodiment of the present invention; FIG. 34 is a view showing an example of a double exposure region in the embodiment of the present invention; FIG. 36 is a view showing an example of a double exposure region in the embodiment of the present invention; FIG. 37 is a view showing a double exposure process in the embodiment of the present invention; FIG. 38 is an explanatory diagram of double exposure processing in the embodiment of the present invention; FIG. 39 is an explanatory diagram of double exposure verification processing in the embodiment of the present invention; and FIG. 40 is double exposure verification in the embodiment of the present invention. FIG. 41 is an explanatory diagram of a non-exposure area verification process in the embodiment of the present invention; FIG. 42 is an explanatory diagram of a non-exposure area verification process in the embodiment of the present invention; and FIG. 43 is an implementation of the present invention. FIG. 44 is an explanatory diagram of a verification result in the embodiment of the present invention; FIG. 45 is an explanatory diagram of the verification result in the embodiment of the present invention; Figure mistake a map of the shape of the data;

1‧‧‧Display Department

2‧‧‧ keyboard

3‧‧‧ Mouse

4‧‧‧Program Storage

5‧‧‧Data Archives Storage Department

6‧‧‧Archives Storage Department

7‧‧‧CPU

8‧‧‧Storage Department

9‧‧‧ Panel substrate window

10‧‧‧mask window

11‧‧‧Menu window

12‧‧‧ Panel substrate

13‧‧‧Photomask

16‧‧‧Operation Department

102‧‧‧Exposure area

Claims (133)

A reticle verification system includes: a storage unit for storing graphic data of an exposure element contained in a reticle for exposure of a flat panel display, and a coordinate representation of a grid dot, indicating the exposure element on the display panel a coordinate information of the exposure position; a layout graphic element generating unit generates a layout graphic element on the display panel corresponding to the exposure element according to the graphic data and the coordinate information of the exposure element stored in the storage unit; a verification unit, And determining, according to the positional relationship of the plurality of layout graphic elements on the display panel generated by the layout graphic element generating unit, the exposure element; and a display unit displaying the verification result of the verification unit. The reticle verification system according to claim 1, wherein the display unit has at least a window for displaying a verification result, and the verification unit performs calculation between grid grids corresponding to the layout pattern elements. Processing, verifying the exposure elements, and the display unit displays the graphic obtained by the verification result of the verification unit to the window. The reticle verification system of claim 1, wherein the reticle data comprises an intermediate layer defining a transistor pattern, or an external database defining a transistor pattern for the intermediate layer, and including There is a table structure based on the index structure to define an intermediate layer or an external database defining the transistor pattern as needed Expansion unit. The reticle verification system of claim 1, wherein the reticle data comprises an intermediate layer defining a transistor pattern, or an external database defining a transistor pattern for the intermediate layer, and including There is an expansion unit that constructs the table structure with the intermediate layer or the external database defining the transistor pattern as needed according to the index structure. The photomask verification system according to claim 1, wherein the verification unit has a difference extraction unit that performs the logical layout processing of the two layout graphic elements, and performs any one of the layout graphic elements and The logical XOR processing or the difference processing of the region corresponding to the layout pattern element among the graphic elements obtained by the logical OR result, thereby extracting the difference between the two layout pattern elements. The photomask verification system according to claim 2, wherein the verification unit has a difference extraction unit that performs the logical layout processing of the two layout graphic elements, and performs any one of the layout graphic elements and The logical XOR processing or the difference processing of the region corresponding to the layout pattern element among the graphic elements obtained by the logical OR result, thereby extracting the difference between the two layout pattern elements. The photomask verification system of claim 3, wherein the verification unit has a difference extraction unit that performs the logical layout processing of the two layout graphic elements, and performs any one of the layout graphic elements and The logical XOR processing or difference of the region corresponding to the layout graphic element in the graphic element obtained by the above logical OR result Processing to extract the difference between the above two layout graphic elements. The photomask verification system of claim 4, wherein the verification unit has a difference extraction unit that performs the logical layout processing of the two layout graphic elements, and performs any one of the layout graphic elements and The logical XOR processing or the difference processing of the region corresponding to the layout pattern element among the graphic elements obtained by the logical OR result, thereby extracting the difference between the two layout pattern elements. The reticle verification system according to claim 1, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 2, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 3, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 4, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing of two layout graphic elements. The amount of overlap. The reticle verification system of claim 5, wherein the verification unit comprises an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 6, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The photomask verification system of claim 7, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 8, wherein the verification unit includes an overlap amount detecting unit that detects the two layout graphic elements by performing logical AND processing on two layout graphic elements. The amount of overlap. The reticle verification system of claim 9, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 10, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 11, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 12, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 13, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 14, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 15, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 16, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 9, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 10, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 11, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 12, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 13, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 14, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 15, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The reticle verification system of claim 16, wherein the verification unit includes an offset verification unit that verifies whether the amount of overlap detected by the overlap amount detecting unit satisfies the indicated offset value. The photomask verification system according to claim 9, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 10, wherein the verification unit includes an element determination unit, after the overlap amount detecting unit detects that there is no overlap amount of the two layout pattern elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 11, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. Logical OR processing, when two layout graphics are confirmed When the element forms a result of a closed figure, it is judged that the two layout pattern elements are continuous graphic elements. The photomask verification system according to claim 12, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 13, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 14, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 15, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. Logical OR processing, when two layout graphics are confirmed When the element forms a result of a closed figure, it is judged that the two layout pattern elements are continuous graphic elements. The photomask verification system according to claim 16, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 9, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 10, wherein the verification unit includes an element determination unit, after the overlap amount detecting unit detects that there is no overlap amount of the two layout pattern elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 11, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. Logical OR processing, when two layout graphic elements are confirmed When the result of forming a closed figure is determined, it is judged that the two layout graphic elements are continuous graphic elements. The photomask verification system according to claim 12, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 13, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 14, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 15, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. Logical OR processing, when two layout graphic elements are confirmed When the result of forming a closed figure is determined, it is judged that the two layout graphic elements are continuous graphic elements. The photomask verification system according to claim 16, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 17, wherein the verification unit includes a component determination unit, wherein the overlap detection unit detects that there is no overlap of the two layout graphic elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 18, wherein the verification unit includes a component determination unit, after the overlap detection unit detects that there is no overlap amount of the two layout graphic elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 19, wherein the verification unit includes an element determination unit, after the overlap amount detecting unit detects that there is no overlap amount of the two layout pattern elements, Logical OR processing, when two layout graphic elements are confirmed When the result of forming a closed figure is determined, it is judged that the two layout graphic elements are continuous graphic elements. The photomask verification system according to claim 20, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 21, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 22, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 23, wherein the verification unit includes an element determination unit, after the overlap amount detecting unit detects that there is no overlap amount of the two layout pattern elements, Logical OR processing, when two layout graphics are confirmed When the element forms a result of a closed figure, it is judged that the two layout pattern elements are continuous graphic elements. The photomask verification system according to claim 24, wherein the verification unit includes an element determination unit, after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 25, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 26, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 27, wherein the verification unit includes an element determination unit, after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements, Logical OR processing, when two layout graphic elements are confirmed When the result of forming a closed figure is determined, it is judged that the two layout graphic elements are continuous graphic elements. The reticle verification system according to claim 28, wherein the verification unit includes a component determination unit, after the overlap detection unit detects that there is no overlap amount of the two layout graphic elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 29, wherein the verification unit includes a component determination unit, after the overlap detection unit detects that there is no overlap amount of the two layout graphic elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 30, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The photomask verification system according to claim 31, wherein the verification unit includes an element determination unit that is performed after the overlap amount detection unit detects that there is no overlap amount of the two layout pattern elements. Logical OR processing, when two layout graphic elements are confirmed When the result of forming a closed figure is determined, it is judged that the two layout graphic elements are continuous graphic elements. The reticle verification system according to claim 32, wherein the verification unit includes an element determination unit, after the overlap amount detecting unit detects that there is no overlap amount of the two layout pattern elements, The logical OR process determines that the two layout graphic elements are continuous graphic elements when it is confirmed that the two layout graphic elements form a closed one of the graphics. The reticle verification system according to claim 1, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit. For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 2, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 3, wherein each of the exposure elements includes a graphic element and surrounds the graphic element a predetermined wide louver frame, the verification unit includes an end point verification unit for verifying whether the graphic exists within a range of a specified offset value for a grid grid on the display panel corresponding to an inner edge of the louver frame The end point of the feature graphic element of the layout. The reticle verification system of claim 4, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 5, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 6, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, Verification of the grid grid on the display panel corresponding to the inner edge of the louver frame Whether or not the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 7, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 8, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit. For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 9, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The photomask verification system according to claim 10, wherein Each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit for the mesh grid on the display panel corresponding to the inner edge of the louver frame , verify that the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 11, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 12, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 13, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For and The grid grid on the display panel corresponding to the inner edge of the louver frame verifies whether the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 14, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit. For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 15, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 16, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system according to claim 17, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit. For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 18, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 19, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit including an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 20, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, The verification unit includes an end point verification unit for verifying whether the end point of the layout graphic element of the graphic element exists within a range of the specified offset value for the grid grid on the display panel corresponding to the inner edge of the louver frame . The reticle verification system of claim 21, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 22, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 23, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, verify whether the layout of the graphic element exists within the range of the specified offset value The end point of the graphic element. The reticle verification system of claim 24, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 25, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 26, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 27, wherein each of the exposure elements includes a graphic element and surrounds the graphic element a predetermined wide louver frame, the verification unit includes an end point verification unit for verifying whether the graphic exists within a range of a specified offset value for a grid grid on the display panel corresponding to an inner edge of the louver frame The end point of the feature graphic element of the layout. The reticle verification system of claim 28, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 29, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 30, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, Verification of the grid grid on the display panel corresponding to the inner edge of the louver frame Whether or not the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 31, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 32, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 33, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The photomask verification system according to claim 34, wherein Each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit for the mesh grid on the display panel corresponding to the inner edge of the louver frame , verify that the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 35, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 36, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 37, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For and The grid grid on the display panel corresponding to the inner edge of the louver frame verifies whether the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 38, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 39, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit including an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 40, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 41, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 42, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit. For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 43, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 44, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, The verification unit includes an end point verification unit for verifying whether the end point of the layout graphic element of the graphic element exists within a range of the specified offset value for the grid grid on the display panel corresponding to the inner edge of the louver frame . The reticle verification system of claim 45, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit including an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 46, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit including an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 47, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, verify whether the layout of the graphic element exists within the range of the specified offset value The end point of the graphic element. The reticle verification system of claim 48, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 49, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 50, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 51, wherein each of the exposure elements includes a graphic element and surrounds the graphic element a predetermined wide louver frame, the verification unit includes an end point verification unit for verifying whether the graphic exists within a range of a specified offset value for a grid grid on the display panel corresponding to an inner edge of the louver frame The end point of the feature graphic element of the layout. The reticle verification system of claim 52, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 53, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 45, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit including an end point verification unit, Verification of the grid grid on the display panel corresponding to the inner edge of the louver frame Whether or not the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 55, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 56, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 57, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system according to claim 58 of the patent application, wherein Each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, and the verification unit includes an end point verification unit for the mesh grid on the display panel corresponding to the inner edge of the louver frame , verify that the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 59, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 60, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 61, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For and The grid grid on the display panel corresponding to the inner edge of the louver frame verifies whether the end point of the layout graphic element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 62, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 63, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system of claim 64, wherein each of the exposure elements includes a graphic element and a predetermined wide louver frame surrounding the graphic element, the verification unit includes an end point verification unit, For the grid grid on the display panel corresponding to the inner edge of the louver frame, it is verified whether the end point of the layout pattern element of the graphic element exists within the range of the specified offset value. The reticle verification system according to any one of claims 1 to 128, further comprising a specifying unit for designating an error layer containing an erroneous verification result, when the display unit is indicating the verification result When the error graphic information is displayed on the window, the error graphic information of the error layer specified by the specified unit is displayed in the window unit in the layer unit. The reticle verification system of claim 129, wherein the display unit has a dialog box different from a window displaying the verification result, the designated unit designating the error layer on the dialog box, the display The unit displays the number of errors on the dialog box, and should specify the unit's designation of the error layer, and display the error graphic information of the layer to the window. A computer program product for causing a computer to function as a photomask verification system according to any one of claims 1 to 128. A computer program product that enables a computer to function as a photomask verification system as described in claim 129 of the patent. A computer program product that enables a computer to function as a reticle verification system as described in claim 130 of the patent.