KR101041263B1 - Reticle inspection system and program recording medium - Google Patents

Abstract

An object of the present invention is to be able to verify in advance the exposure result by the exposure element installed in the reticle (reticle).

In addition, the CPU 7 of the present invention refers to the figure data and coordinate information of the exposure element stored in the data file storage 5 of the storage unit 8, and the panel layout element on the display panel corresponding to the exposure element. And verify the error of the exposure element by determining the positional relationship of the plurality of panel layout elements on the display panel. The display unit 1 displays the verification result in the panel substrate window 9 or the reticle window 10.

Description

Reticle inspection system and program recording medium

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reticle verification system for verifying whether or not reticle data is created so that desired exposure can be performed, and more particularly, to a reticle verification system for verifying reticle data for flat panel display production.

Reticle data for producing a flat panel display (FPD) is formed by defining a short frame on the panel layout data, cut out as an exposure element (hereinafter also referred to as a repeating element), and the figure data of the exposure element and the exposure position on the panel substrate. It contains coordinate information indicating.

When the reticle data is transferred onto the panel substrate of the FPD, it is transferred onto the panel substrate of the FPD by the exposure apparatus by using coordinate information for arranging the exposure elements of the reticle data.

At this time, if there is an error in the figure data or the coordinate information of the exposure element installed in the reticle, the reticle is rendered useless and the panel substrate is made useless. In particular, when creating reticle data for flat panel display, division of the exposure area by human hands is often necessary, and a situation is likely to cause mistakes.

In order to prevent this, a method of simulating and verifying an exposure apparatus from reticle figure data and coordinate information is considered. Here, in the relationship between an exposure apparatus and a simulation, there exists a technique which aims at cost optimization of an exposure apparatus, for example. Patent Literature 1 describes a technique for providing a method for optimizing measurement conditions by optimizing measurement conditions by reducing time and effort in an exposure apparatus using a simulator. However, Patent Document 1 merely discloses an invention in which the measurement conditions are optimized.

In general, the size of the panel substrate for flat panel display is a size that greatly exceeds the exposure range of the exposure apparatus. Therefore, the reticle to be mounted on the exposure apparatus is smaller than the panel substrate, and on the reticle, an element obtained by cutting off a portion of the panel substrate is disposed as the exposure element.

When exposing with an exposure apparatus using a reticle, a panel substrate for flat panel displays is manufactured by repeatedly placing and exposing the exposure elements on the reticle.

In this way, when the reticle is created, the display panel area is divided and the display layout data is cut to produce the exposure elements of the reticle, and when the display panel is manufactured, the panel substrate is produced by repeating exposure to the layout data. It is easy to cause mistakes during cutting and repeated placement of exposure elements.

In addition, since division of the display panel area is necessary even when the layout data is not cut, the repetitive arrangement of the exposure elements must be specified. At this time, mistakes in the instructions of the repetition are very common. Therefore, some verification means for verifying the exposure result in advance in the pre-manufacturing process is desired.

[Patent Document 1] Japanese Patent Laid-Open No. 2006-140204

An object of the present invention is to provide a reticle verification system capable of verifying an exposure result by an exposure element provided in a reticle in advance.

In addition, an object of the present invention is to provide a reticle verification system capable of verifying an exposure result by an exposure element in advance by simulating the operation of the exposure apparatus.

Moreover, this invention makes it a subject to provide the program for reticle verification suitable for building the said reticle verification system by implementing on a computer.

According to the present invention, memory means for storing figure data of an exposure element included in a flat panel display exposure reticle, coordinate information displayed by coordinates of grid lattice points and indicating an exposure position of the exposure element on a display panel; Layout figure element generating means for generating a layout figure element on the display panel corresponding to the exposure element based on the figure data and the coordinate information of the exposure element stored in the storage means; There is provided a reticle verification system comprising verification means for verifying the exposure element on the basis of the positional relationship of a plurality of layout figure elements on the display panel and display means for displaying the result verified by the verification means. .

The layout figure element generating means generates a layout figure element on the display panel corresponding to the exposure element based on the figure data and the coordinate information of the exposure element stored in the storage means. The detecting means verifies the exposure element based on the positional relationship of the plurality of layout figure elements on the display panel generated by the layout figure element generating means. The display means displays the result verified by the verification means.

Here, the display means has at least a window for displaying a verification result, and the verification means verifies the plurality of exposure elements by performing arithmetic processing of grid grids corresponding to the plurality of layout figure elements, and displays the display. The means may be configured to display on the window a figure obtained as a result of the verification by the verification means.

Further, the data of the reticle has a middle layer defining a transistor figure or an external library defining a transistor figure as an intermediate layer, and a table which expands the intermediate layer or external library defining the transistor figure as necessary by a pointer structure. You may comprise so that the developing means which has a structure may be provided.

In addition, the verification means performs a logical OR processing of the two layout figure elements, and then performs a logic XOR process or difference of an area corresponding to the layout figure element among any one of the layout figure elements and the figure elements obtained as a result of the logical OR. The processing may be performed so as to have difference extraction means for extracting the difference between the two layout figure elements.

The verification means may be configured to include overlap amount detection means for detecting the overlap amount of the two layout figure elements by performing a logical AND process of the two layout figure elements.

The verification means may be configured to include offset verification means for verifying whether or not the overlap amount detected by the overlap amount detection means satisfies the indicated offset value.

Further, the verification means detects that the overlap amount detection means does not have the overlap amount of the two layout figure elements, and then performs a logical OR process to confirm that a result of forming two layout figure elements as one closed figure is confirmed. The two layout figure elements may be provided so as to include element discriminating means for discriminating them as continuous figure elements.

In addition, each of the exposure elements includes a figure element and a blind frame having a predetermined width surrounding the figure element, and the verification means is predetermined for a grid grating on the display panel corresponding to the blind frame internal combustion. In the range of an offset value, you may comprise so that end point verification means which verifies whether the end point of the layout figure element of the said figure element exists.

Also, when the display means displays error figure information on a window displaying the verification result, and has designation means for designating an error layer including the verification result of the error, the error figure of the error layer designated by the designation means. Information may be displayed on the window in units of layers.

The display means has a dialog box different from the window displaying the verification result, the designation means designates the error layer on the dialog box, and the display means displays the number of errors on the dialog box. At the same time, in response to the designation of the error layer by the designation means, the error figure information of the layer may be displayed on the window.

Moreover, according to this invention, the program for making a computer function as a reticle verification system in any one of the above is provided.

The computer functions as the reticle verification system according to any one of the above by executing the program.

The reticle data exposure verification system of the present invention can verify the exposure result by the exposure element provided in the reticle in advance.

In addition, by simulating the operation of the exposure apparatus, it is possible to verify the exposure result by the exposure element in advance.

In addition, the program of the present invention enables the computer to execute the reticle data exposure verification system.

EMBODIMENT OF THE INVENTION Hereinafter, the reticle verification system and the reticle verification program of embodiment of this invention are demonstrated.

In addition, although it mentions later in detail, the reticle verification system of embodiment of this invention is comprised by the reticle verification program which builds a reticle verification system by running one or more computers and the said computer. The computer also functions as a reticle data creation system for creating reticle data by executing a reticle data creation program. In addition, in each figure, the same code | symbol is attached | subjected to the same part.

1: is a figure which shows the relationship between the panel substrate for flat panel displays (FPD), and a reticle in embodiment of this invention, FIG. 1 (a) is a top view, and FIG. 1 (b) is a side view.

In Fig. 1, reference numeral 101 denotes a panel substrate, 102 an exposure region of an exposure apparatus (not shown) with guaranteed characteristics, 103 an exposure region of an exposure apparatus, 104 a light source mechanism, 105 a light shielding mechanism, and 106 a reticle. 107 denotes an exposure surface. The panel substrate 101 may be made of glass, plastic film, or the like.

Recent flat panel displays are enlarged as shown in a liquid crystal display panel or a plasma display panel, so that the exposure apparatus cannot collectively expose the panel substrate 101 (see the plan view in Fig. 1 (a)). Therefore, there is a need to divide the exposure area into some form and perform repeated exposure. The positional relationship between the exposure apparatus and the panel substrate 101 is a light source system mechanism 104, a light shield system mechanism 105, a reticle 106, an exposure surface 107, and a panel substrate 101 when viewed from a light source. Although not described in 1, a lens system mechanism is added thereto (see also the side view of FIG. 1 (b)).

In addition, the light shielding system mechanism 105 is a rectangular mechanical mechanism for mechanically shielding light from a light source.

2 is a diagram showing a relationship between panel layout data on a panel substrate and reticle layout data on a reticle in an embodiment of the present invention.

In FIG. 2, the liquid crystal panel 201 is an example in which one large panel layout data A1 is present on the panel substrate 210 as the panel layout data 211. In the case of the liquid crystal panel 201, the panel layout data A1 is divided, and a data group having a repeating structure is extracted in correspondence with the short frame 213, and the reticle layout data 206 is placed on the reticle 205. Shall be.

Usually, in this case, division of the exposure area with cutting of the panel layout data A1 is performed. In this embodiment, each element of the reticle layout data corresponding to each divided element (panel layout element) of panel layout data is called an exposure element or a repeating element. The reticle layout data is constituted by a plurality of exposure elements. 212 is an exposure area whose properties are guaranteed.

The liquid crystal panel 202 is a case where the medium panel layout data A2 and A3 exist as panel layout data. Also in this case, it is common to create the panel layout data A2 and A3 by dividing the exposure area with the cutting of the panel layout data, and to create a data group having a repeating structure corresponding to the short frame 213.

The liquid crystal panel 203 is a case of panel layout data in which a plurality of small panel layout data A4 and A5 are arranged on a panel substrate. In such a case, a plurality of panel layout data A4 and a plurality of panel layout data A5 are generated in correspondence with the short frame 213, respectively, and the generated reticle layout data 206 is disposed on the reticle 205 to perform exposure. The operation to reduce the number of times is required. Therefore, in this case, division of the exposure area is usually required, but no cutting of the panel layout data is involved.

The liquid crystal panel 204 is a case where three types of panel layout data of medium panel layout data A2 and small panel layout data A4 and A5 exist on a panel substrate. In such a case, the medium-sized panel layout data A2 is generated in correspondence with the short frame 213 by dividing the exposure area accompanying the cutting of the panel layout data, and the small layout data A4 and A5 do not involve cutting the panel layout data. An exposure area division is performed, which is generated in correspondence with the short frame 213 to be the reticle layout data 206.

As described above, in the case of manufacturing the reticle, a data group having a repeating structure is extracted from the panel layout data 211 of the panel substrate 210 and arranged as a plurality of short frames 213 on the reticle 205. Create the reticle layout data. At this time, the short frame area having a high commonality is extracted.

In any case, it is important to confirm that there is no erroneous data by performing exposure apparatus simulation. This is because the division of the exposure area for repeating arrangements is necessary even when the panel layout data is not cut, and mistakes are likely to occur when specifying the repeating arrangements. The short frame data in the reticle data is a figure element in which a blind frame is set, which is called an exposure element or a repeating element.

Before describing the reticle verification system according to the embodiment of the present invention in detail, the procedure for creating the reticle data will first be outlined.

3 and 4 are views showing a general processing procedure when creating reticle data from panel layout data, and FIG. 3 shows a display unit 1 of a reticle verification system (functioning as a reticle production system at the time of producing a reticle). Fig. 4 is a flowchart showing a processing procedure of a CPU (not shown) constituting the reticle production system.

FIG. 3A shows panel layout data 211 on the panel substrate 210. FIG. 3B shows setting of the short frame 213 onto the panel substrate 210 and onto the reticle 205. FIG. Fig. 3 (c) shows the arrangement of the short frame 213, and the extraction by cutting the panel layout data 211 on the panel substrate 210 (for example, cutting along the short frame 213), Processing at the time of generating a correction pattern (not shown) and generating a blind frame (not shown) is shown.

3 (d) shows coordinate information of the reticle output from the reticle design system. The coordinate information includes information on the width and height of the reticle layout data (also referred to as an exposure element or a repetition element in this embodiment) corresponding to each shot frame as exposure element data, and information on a position where the repetition element is repeatedly arranged. (Repeat batch information) is included.

3 and 4, the reticle data creation process will be described schematically. When creating the reticle data, the CPU first loads the panel layout data 211 (step S401) and the panel substrate 210. On the panel layout data 211, a plurality of shot frames 213 are set, and the shot frames 213 are arranged on the reticle 205 to create the reticle layout data 206 (step S402).

Next, the exposure area is divided based on the shot frame 213. At this time, since wiring data exists immediately below the designated short frame 213, this should be cut off. Here, there are cases where a pattern (correction pattern) having a wider width than the cut portion is generated in the data cut portion (steps S403 and S404) and not generated (step S405).

When the correction pattern is not generated, the short frame 213 is overlapped and defined, and then the process proceeds to processing step S406 (step S405). By configuring in this way, when exposing, multiple exposure of the exposure data itself can prevent the erroneous cutting of the data by the slight misalignment.

When generating the correction pattern, the process proceeds to processing step S406 after generating the correction pattern (steps S403 and S404). When the correction pattern is generated, it is common for the correction pattern itself to be subjected to multiple exposures, and as a result, miscution due to minute misalignment is prevented.

In the process step S402, in the case of division | segmentation of the exposure area which does not involve cutting | disconnection of data, it transfers to the generation process (step S406) of the frame (blind frame) of the predetermined width immediately surrounding an exposure area.

In the blind frame generation process of processing step S406, a blind frame is generated with a specified width. The correction pattern is composed of a pattern wider than the wiring pattern, and the blind frame is configured such that the inner edge thereof corresponds to the outer edge of the correction pattern.

As a result, an exposure element (repeating element) composed of data of the exposure area and the blind frame is produced. Further, coordinate information corresponding to the exposure element is created.

Finally, the process is terminated by outputting the reticle layout data and coordinate information corresponding to the layout data (step S407). The layout data is panel layout data to which reticle layout data and data of the short frame 213 are added.

Here, the reticle layout data is information defining the figure of the exposure element, and is a data file composed of rectangular figures, pencil figures, figures whose widths are defined in the center line, and intermediate modules constituting the figure data as figure data.

As described above, the coordinate information is information defining the exposure position of the exposure element included in the reticle layout data. The name, height, width, and repetitive arrangement information (repetition frequency and arrangement coordinate information) of the exposure element are described. Text file.

In addition, reticle data means the information comprised by the said reticle layout data and coordinate information.

5 is a diagram illustrating a structure of panel layout data formed on a panel substrate. The uppermost module is called the top module 511, and there is one of them. All other modules are bound to this top module 511. This is the layout data submodule 512 to 515, which may be layered. In the case of a liquid crystal panel, for example, in the case of a liquid crystal panel, the module includes layout data 516, wiring data 517, and through hole arrangement data 518 of each transistor of the thin film transistor and the liquid crystal driver.

These transistors, wirings, and through holes have names (batch data is library name, wiring data is wiring type name, through hole data is through hole name), and the contents are library files (batch module library, wiring type library, through hole). A hall library 519, and the library is identified by name matching.

In addition, since the transistor data is used abundantly, the library format may be managed independently of the panel layout data.

6 is a diagram illustrating a structure of reticle data. It is basically the same structure as the panel layout data. There is one top module 521 as well. Under the top module 521, a plurality of repeating elements 522 and 523 exist as lower modules, which become a basic unit of reticle data.

As the data constituting the repetitive element as an exposure element, blind frame data 524, correction pattern data 525, cut data and non-cut data 526, and short frame data 527 as exposure object data. There is. In addition, there are the width and height data 528 of the repeating elements, the repeating element arrangement data 529, the layout submodule data 530 in the short frame after cutting, the arrangement data 535, and the through hole data 536.

The layout data that the module has is similar to the panel layout data. For example, in the case of a liquid crystal panel, the layout data 531, the wiring data 532, and the through hole data 533 of the thin film transistors and the respective transistors of the liquid crystal driver unit are included. have. The layout data 531, wiring data 532, and through hole data 533 of these transistors have names, and the contents thereof are library files (batch module library, wiring type library, through hole library, alignment mark library). It is stored in 534, and it is confirmed by name matching with the library.

As in the case of the panel, all have a data structure which determines whether or not the names match in the library file. In addition, although not used at the time of exposure, it also retains short frame data.

In addition, since transistor data is versatile, the library may be managed independently of the reticle data.

FIG. 7 is a table showing examples of the physical layer, each data class, and layer code of the reticle layout data in the case of the metal first and second layers.

For example, in the case of the first metal layer (aluminum first layer), the short frame data is the layer code 101, the blind frame data is the layer code 102, the pattern data is the layer code 104, and the correction pattern is the layer code ( 105, the two metal layers (aluminum second layer) are similarly defined, and each layer cord is made independent and can be processed independently. These layer codes are commonly used for each repeating element. In other words, if the physical layer and the data class are the same, the layer codes are common among the repeating elements.

The data of the reticle shown in FIGS. 6 and 7 is finally filed, but the contents thereof include a rectangular figure, a pen figure, a figure whose width is defined in a center line, and a module in which these figure data are combined as a middle layer module or a library module. It is composed of modules. It is a transistor module to be utilized as a middle layer module or a library module.

Since the number of transistor modules is large and the amount of data becomes large when they are expanded and held, they are usually output in a middle layer defined format as a library module.

Here, when the figure data is compared with the GDS format used as a de facto standard in the field related to the present embodiment, a rectangular figure is a rectangle, a pencil figure is a boundary, and a figure is defined with a width at the center line. Is a path, and the module which combined these figure data is called a cell.

Fig. 8 is a diagram showing coordinate information output processing performed by a reticle production system by executing a coordinate information output program, which shows numerical expressions and arrangement rules of repeating elements for a panel substrate and a reticle (including alignment marks).

In Fig. 8, reference numeral 801 denotes a panel substrate, 802 denotes panel layout data, and 803 denotes an XY center coordinate of the panel substrate (in this example, coincides with the center coordinates of the four short frames A.) (0,0), 804 Is an alignment mark (the coordinates are coordinates (X0, Y0) based on the center coordinates (0,0) of the panel substrate 801).

805, 808, and 811 are reticles and 807 are exposure areas with guaranteed properties. 806, 809, 810, 812, and 813 are repeating elements corresponding to the short frames A, B1, C1, B2, and C2, respectively.

In the example of FIG. 8, one repeating element 806 is formed in the reticle 805, two repeating elements 809 and 810 are formed in the reticle 808, and two repeating elements 812 and 813 are formed in the reticle. 811 is formed.

Exposure data including blind frames are created on the reticles 805, 808, and 811 as repeating elements 806, 809, 810, 812, and 813, respectively. In other words, the repeating element is composed of blind frame, cut data, correction pattern, and exposure data that is not cut data. This is the basis of the short information.

In this embodiment, even if there is no repetition, it is called a repetition element. The number of repetitions when there is no repetition is zero. In the example of FIG. 8, the number of repeating elements 806 corresponding to the short frame A is 2x2 (= 4) (the number of repetitions is 2x2-1) (therefore, iteration which is a set of repeating elements A). A set 814 is formed.), The number of repetitions of the repeating elements 809, 810, 812, and 813 corresponding to the short frames B1, C1, B2, and C2 is zero.

Each repeating element has a name. Each repeating element is given a width W and a height H with respect to the coordinate center of each repeating element itself. Each repeating element is arranged based on the center coordinates of the repeating set constituted by the repeating element. In the example of the figure, the center coordinates (0,0) of the panel substrate 801 correspond to this, and are arrange | positioned with respect to the center coordinates (0,0).

On the other hand, as the layout data of the reticle, each repeating element is arranged at coordinates whose center position is based on the position of the center coordinate of the reticle.

For the alignment mark, the panel substrate 801 is disposed at a position relative to the center coordinates (0,0) of the panel substrate 801, and the reticle is disposed at a position relative to the center coordinate of the reticle. Alignment marks are stored and defined in the library file.

9 is a diagram showing coordinate information output processing performed by the reticle production system by executing a coordinate information output program as in the above, and shows an example of coordinate information output. As shown in FIG. 9, the output result at the time of generating three reticles 805, 808, 811 in which repeating elements are arrange | positioned from the panel layout data 802 on the panel substrate 801 is shown.

Here, as the exposure short information, the name of the repeating element, the number of repeating elements, the width and the height and the arrangement position designated as the short information on the panel substrate, and the repeating element name, the width, the height and the arrangement position as the short information on the reticle The example provided to a user as coordinate information is shown.

10 to 12 are diagrams illustrating a division processing method of an exposure area, and show two division forms, and FIG. 11 generates a correction pattern 1004 when dividing and cutting the panel layout data 1003 of FIG. 10. 12 illustrates an example in which the correction pattern is not generated when the panel layout data 1003 of FIG. 10 is divided and cut.

That is, when generating the correction pattern 1004, in Figs. 10 and 11, the data (for example, wiring data) 1003 is cut directly under the short frame 1002, and a predetermined length? The correction patterns 1004 and 1004 extended by the length are generated successively. At this time, the correction pattern 1004 may be configured to be wider by a predetermined length than the cut portion from a position inside the predetermined length than the cut portion. In this way, the correction pattern 1004 is formed in the portion 1007 where the double exposure is performed.

A blind frame 1005 of a predetermined width is formed such that the outer position of the correction pattern 1004 and the inner position of the blind frame 1005 overlap a predetermined amount with a small amount of offset. In this manner, exposure element data having a correction pattern is created. The inner edge 1006 of the blind frame 1005 is a portion that extends by a predetermined length Δ minutes from the short frame 1002. The inner edge of the blind frame 1005 becomes the outer edge of the exposure area.

As described above, in the case of generating and cutting the correction pattern 1004, the cutting of the data 1003 is performed directly under the short frame 1002, and the correction pattern 1004 is a double exposure in which both of the adjacent exposure elements are exposed. The panel layout data, which is formed as an area and formed by adjacent exposure elements, is secured by the correction pattern 1004.

On the other hand, when cutting without generating a correction pattern, layout data is overlapped. When overlapping, as shown in FIG. 12, it cut | disconnects in the part extended by the predetermined length (DELTA) minutes from the shot frame 1002. As shown in FIG. Similarly, the adjacent short frames 1001 are also cut at portions extended by a predetermined length Δ minutes to form a reticle. In this manner, the overlap portion 1008 is formed in the portion 1007 where the double exposure is performed.

A blind frame 1005 of a predetermined width is formed such that the outer position of the overlap portion 1008 and the inner position of the blind frame 1005 overlap a predetermined amount with a predetermined amount of offset. As described above, the exposure element data having the overlap portion 1008 is created. The inner edge 1006 of the blind frame 1005 is a portion extended by Δ minutes from the short frame 1002. The inner edge of the blind frame 1005 becomes the outer edge of the exposure area.

FIG. 13 is a diagram showing an exposure element cut in the short frame 1002 having an oblique portion 1301, and is an example of an exposure element in which a correction pattern 1004 is formed.

In Fig. 13, when the short frame 1002 having the oblique portions 1301 can be set, it is possible to easily extract the repeating structure, which is effective.

In the correction patterns 1004 and 1004, predetermined correction values are set in the inward direction and the outward direction along the longitudinal direction of the cut wiring data 1003. Further, as for the values of the correction patterns 1004 and 1004 in the width direction of the wiring data 1003, predetermined correction values are set for both of the width directions sandwiching the wiring data 1003. The width of the blind frame 1005 can be specified in the horizontal direction Wh and the vertical direction Wv.

The correction pattern 1004 corresponding to the horizontally cut end is a rectangle, and the correction pattern 1004 corresponding to the diagonal portion 1301 is a parallelogram.

As shown in FIG. 13, when the blind frame 1005 including the oblique part 1301 is included in the inner edge 1006, the double exposure by the correction patterns 1004 and 1004 is necessary for the data cutting part. .

1 to 13 describe how reticle layout data and coordinate information are created. In this embodiment, the panel layout data synthesized from the reticle layout data and the coordinate information thus created is verified, and the reticle data exposure verification is performed as a result.

FIG. 14 is a block diagram showing the configuration of the reticle verification system according to the present embodiment, and is an example configured by a computer and a program executed by the computer. The reticle verification system of the present embodiment includes a central processing unit (CPU), a plurality of program groups running on the CPU, a storage device for storing program groups and data, an input device composed of a keyboard or a mouse, and a display. It is equipped with a device.

To explain the outline of the reticle verification system of this embodiment, the reticle verification system of this embodiment functions as an exposure apparatus simulator, and displays reticle layout data displayed on the reticle window on the panel substrate window based on the coordinate information. The figure is added to the figure processing to perform verification, and the addition of a function for displaying an error figure constitutes a reticle verification system. The window displaying the error figure is, for example, a panel substrate window.

The program consists of three steps: initial reticle layout data and coordinate information import, creation of internal tables, calculation of the grid grids of figures and figures, accompanying verification processes, and verification result figures display. Divided. All of these program functions are executed by operating the commands displayed on the menu window.

As a display window of the figure, at least a panel substrate window, which is a display of the verification result figure, is required. A figure display function is not necessarily required for the input portion and the calculation portion, but it is more convenient to have a figure display function for operation confirmation.

In Fig. 14, the reticle verification system includes a display unit 1 constituted by a liquid crystal display panel or the like, an operation unit 16 constituted by a keyboard 2 or a mouse 3, a central processing unit (CPU) 7, a magnetic disk. The storage part 8 comprised by the apparatus, semiconductor memory, etc. is provided.

On the display unit 1, the panel substrate window 9 for operating the panel layout data on the panel substrate 12, the reticle window 10 for operating the reticle layout data on the reticle 13, and the operation by the operation unit 16 are operated. It is configured to display at least three windows of the instructing menu window 11. The operation of setting the short frame set on the panel substrate window 9 as the short frame on the reticle window 10 is performed between the windows.

The verification result of the reticle data is displayed on the display unit 1, but may be displayed on all of the panel substrate window 9, the reticle window 10, and the menu window 11. In addition, when displaying the verification result of the reticle data, each window 9-11 may be erased and only a verification result may be displayed in the area | region where each said window 9-11 existed.

The reticle production work or the verification work is performed by selecting the command displayed on the menu window 11 by the operation unit 16 so that the operation unit 16 has the function of the command, and the operation unit 16 is operated to operate the panel substrate. Various operations such as setting a short frame on the window 9, moving the panel substrate window 9 and the reticle window 10, and setting a corresponding short frame on the reticle window 10 are performed.

The storage unit 8 stores data files such as a reticle data generation program executed by the CPU 7, a program storage unit 4 storing a reticle verification program, and input / output data and intermediate data during processing. A file storage section 5 and a file storage section 6 for storing reference files such as rule files and library files are provided.

The program is composed of a short frame setting program, a repeat structure verification program, a blind frame minimum gap verification program, a data cutting program, a correction pattern generating program, a blind frame generating program, and a coordinate information list output as a program for a reticle production system. Programs and programs called input / output programs of various data.

These functions such as short frame setting, repeating structure verification, minimum space between blind frames verification, data cutting, correction pattern generation, blind frame generation, and coordinate information list output are all selected by the operation unit 16 on the command displayed on the menu window. Is executed.

The reticle data verification program includes an input processing part program, a verification processing part program by graphic arithmetic processing, and a verification result display part program.

The file structure includes a panel layout data file as an input file, a reticle layout data file as an output file, a coordinate information list file, and a library file as a reference file and a rule file as a file structure for a reticle production. In addition, the panel layout data file, the reticle layout data file, and the coordinate information list file, which are data files, are stored in the data file storage unit 5. The library file and the rule file which are reference files are stored in the reference file storage unit 6.

The reticle verification file configuration includes a reticle layout data and coordinate information file as an input file, a reticle data file and a coordinate information list file as an output file, and a library file and a rule file as a reference file.

In this manner, a reticle design system for executing the reticle layout or a reticle data verification system for verifying the reticle data is configured.

Here, the display part 1, the operation part 16, and the memory | storage part 8 comprise the display means, the operation means, and the storage means, respectively.

When the display means, the operation means, and the storage means function as the reticle production system, they can function as follows.

For example, the display means can display a panel substrate window displaying at least panel layout data of the panel substrate, a reticle window displaying reticle layout data, and a menu window displaying commands of the operation means.

The operation means selects and inputs a command displayed in the menu window. As a result, it is possible to perform an operation such as specifying a repeating arrangement for the short frame set on the panel layout data of the panel substrate.

The storage means can function as a main memory device and an external memory device. The storage means can store generation conditions including a condition capable of cutting the panel layout data, the width of the correction pattern, and the minimum distance between the blind frames. In addition, the storage conditions set by the operation means can be stored in the storage means.

In the case of the reticle production system, the CPU 7 constitutes a reticle data generation means, an iterative verification means, and a blind frame interval verification means. The reticle data generating means cuts out the panel layout data corresponding to the short frame set on the panel substrate window by the operation means and extracts the extracted panel layout data as partial panel layout data. By forming a correction pattern at an end portion of the data and simultaneously forming a blind frame whose inner edge corresponds to the outer edge of the correction pattern, exposure element data corresponding to the partial panel layout data may be generated on the reticle window. The reticle data generating means may generate the exposure element data so as to satisfy the generating condition.

The reticle data generating means includes: extracting means for cutting out panel layout data corresponding to a short frame set on the panel substrate window by the operation means and extracting the extracted panel layout data as partial panel layout data; and the cut data is included in the partial panel layout data. And a correction pattern generating means for forming a correction pattern at an end of the cut data, and a blind frame generating means for forming a blind frame whose inner edge corresponds to the outer edge of the correction pattern, the exposure corresponding to the partial panel layout data. Element data may be generated on the reticle window.

In addition, the iterative verification means can compare and inquire whether or not the panel layout data corresponding to the short frame and the repetitive arrangement-designated region match.

In addition, the blind frame interval verifying means may verify whether the blind frames are separated by more than a predetermined minimum interval when there are a plurality of the blind frames.

On the other hand, when the display means, the operation means, and the storage means function as the reticle verification system, they can function as follows.

For example, the display means may display the result verified by the verification means. In addition, the display means may have a window for displaying at least the verification result. In addition, the display means can display a figure obtained as a result of the verification by the verification means on the window.

In addition, when the error figure information is displayed on a window displaying the verification result, the display means may display the verification result figure information of the error layer designated by the designation means on the window in units of layers. Also, the display means has a dialog box different from the window displaying the verification result, displays the number of errors on the dialog box, and displays the verification result figure information of the layer in response to designation of the error layer by the designation means. Can be displayed on the window.

The operation means can function as a designation means. The designation means may designate an error layer that contains an error verification result. The designation means can also designate an error layer on a dialog box different from that of the window.

The storage means can be displayed by the figure data of the exposure element included in the flat panel display exposure reticle and the coordinates of the grid lattice points, and can store the coordinate information indicating the exposure position of the exposure element on the display panel.

In addition, the CPU 7 can function as layout figure element generating means, verification means and development means.

The layout figure element generating means can generate the layout figure element on the display panel corresponding to the exposure element based on the figure data and the coordinate information of the exposure element stored in the storage means.

The verification means may verify the exposure element based on the positional relationship of the plurality of layout figure elements on the display panel generated by the layout figure element generation means. Further, the figure data of the exposure element is composed of at least three types of line data whose width is defined in the line information, rectangular data and polygon data describing each vertex, and the verification means includes a grid corresponding to the plurality of layout figure elements. The plurality of exposure elements can be verified by performing arithmetic processing between the grids.

The verification means performs a logical OR process of the two layout figure elements, and then performs the logical XOR process or the difference processing of the one of the layout figure elements and the figure element obtained as a result of the logical OR. It may have a difference extraction means for extracting the difference of.

The verification means may include overlap amount detection means for detecting an overlap amount of the two layout figure elements by performing a logical AND process of the two layout figure elements.

The verification means may include offset verification means for verifying whether or not the overlap amount detected by the overlap amount detection means satisfies the indicated offset value.

The verification means detects that the overlap amount detection means does not have the overlap amount of the two layout figure elements, and then performs a logical OR process to confirm that the results of forming the two layout figure elements into one closed figure are determined. The layout figure element may be provided with element discriminating means for discriminating that it is a continuous figure element.

The data of the reticle may be configured to have an intermediate layer defining a transistor figure or an external library defining a transistor figure as an intermediate layer. In this case, the developing means may include an intermediate layer or an external library defining the transistor figure, The pointer structure allows you to have a table structure that expands as needed.

In addition, each exposure element includes a figure element and a blind frame of a predetermined width surrounding the figure element, and the verification means is within a range of a predetermined offset value with respect to the grid grating on the display panel corresponding to the blind frame inner edge. End point verification means for verifying whether or not there is an end point of the layout figure element of the figure element may be provided.

The program stored in the storage means can cause a computer having display means, operation means, storage means and a CPU as a reticle verification system having the above function.

15 is a flowchart illustrating processing of the reticle verification system according to the embodiment of the present invention.

In Fig. 15, the reticle layout data to be input is so-called GDS format representation format data, which is data in a format expressed by a plurality of grid grid points whose coordinate values are known points, and is data in a format that allows an intermediate hierarchy structure. . The reticle data file includes graphic data of an exposure element included in a flat panel display exposure reticle.

Usually, a transistor layer is taken as an intermediate layer. In some cases, the transistor hierarchy may be mounted separately from the reticle layout data file as an external library. However, even if attached separately, it is substantially equivalent to the middle layer.

The coordinate information describing the repetitive arrangement position and the like of the repeating elements described in the reticle layout data file is usually a text file. The coordinate information is displayed by the coordinates of the grid lattice points and includes information indicating the exposure position of the exposure element on the display panel.

The processing includes an input processing step of executing an input processing program stored in the program storage section 4 (step S151), and a calculation processing of grid grid points of figures and figures, which executes a verification processing program by figure calculation processing. By the verification processing steps (steps S152 and S153) and the display step (step S154) for displaying the verification results for executing the verification result display program.

In the input processing step (step S151), the CPU 7 performs an input process of retrieving the reticle layout data file and the coordinate information file from the data file storage unit 5, and from the arrangement information of the repeating elements based on the coordinate information. The exposure element data structure on the panel substrate is created.

Here, it is created in a form having a table structure (table structure 1 of FIG. 17 to be described later) which can easily pick up another repeating element in spatial contact with one repeating element. In addition, when the reticle data has an intermediate layer, it is created in a form having a table structure (table structure 2 described later) that can easily pick up to the lowest layer while maintaining the intermediate layer for reducing the data amount.

Thereafter, the CPU 7 enters a verification process by arithmetic processing of figures (steps S152 and S153). There are logical operations and differential operations. As will be described in detail later, the subjects to be verified are divided into verification of the double exposure area, verification of the exposure exposure-1, verification of the exposure exposure-2, and verification of the non-exposure area.

The logical operations required to perform these verifications are AND, OR and XOR. Alternatively, differential operation may be applied instead of XOR. This logic process or difference process is both arithmetic processing of grid grid points. These arithmetic processing results are also stored as graphic data. The CPU 7 performs the processing of the processing step S153 for all the layers (step S153).

Finally, the CPU 7 performs a display process of displaying the figure of the result of the calculation process on the display unit 1 (step S154). The subjects to be verified are the verification of the double exposure area, the verification of the exposure exposure-1, the verification of the exposure exposure-2, and the verification of the non-exposure area, and therefore, based on the determination criteria (parameters) set by the operation unit 16, Any one of these is displayed in graphic data format. This figure data is data indicating an error.

What is important here is that arithmetic processing of logic processing or differential processing is processed in units of layers, and the exposure error data to be created is also stored in the data file storage unit 5 in units of layers. This is because the exposure is performed in units of layers, and therefore verification must be performed in units of layers. In addition, since the display unit 1 is used in units of layers even when the display unit 1 displays, the access time is faster when the error data is stored in units of layers.

In addition, when displaying the processing result on the display unit 1, the CPU 7 displays only the error data when the criterion for determining whether the error data is set, or simply when the criterion for determining whether the error data is not set. The processing result may be displayed. In addition, when displaying the processing result on the display unit 1, the CPU 7 does not necessarily display the figure, and simply displays the processing result when the error content or the error is not determined by characters or the like. You may comprise so that.

FIG. 16 is an explanatory diagram illustrating the relationship between the reticle layout data 162 on the reticle 13, the repeating element 163 in the reticle layout data 162, the coordinate information, and the panel layout data 161 on the panel substrate 12. to be.

FIG. 17 is a table structure 1 showing possible repeating elements 163 of multiple exposure, close exposure-1, and close exposure-2 in the repeating element 163 shown in FIG. It is stored in the data file storage section 5.

The table includes an address, an instance name, a repeating element name, the number of pointers of the double exposure or the close exposure-1 or the close exposure-2, and the pointer information.

Here, the address is an address indicating the order of arranged repeating element data, the instance name is a unique name given to the arranged repeating element, and the repeating element name is a library name of the repeating element described in the reticle data. In addition, an instance is a figure element of one united unit comprised of a single figure or a plurality of figure elements (for example, a cell or a device).

Each repeating element 163 included in the reticle layout data 162 disposed on the reticle 13 is exposed to a predetermined position on the panel substrate 12 based on the coordinate information, and the panel layout element corresponding to the panel substrate is exposed. Is formed. In the case of the repeating element 163 in which exposure is repeated, such as the repeating element A1_1, the exposure process is performed a predetermined number of times at a position determined by the coordinate information. As a result, panel layout data composed of a plurality of panel layout elements is formed on the panel substrate 12.

Since the logic processing or the differential processing between the repeating elements 163 disposed on the panel substrate 12 becomes the main processing, it is possible to easily pick up the adjacent repeating elements 163 from any given repeating elements 163. It is preferred that the structure can be.

Here, data of the width W and the height H of the repeating element 163 in the reticle layout data 162 is used. The width (W) and height (H) represent the minimum region where there is no data exceeding this. In the table structure 1, the repeating elements where the width (W) and the height (H) of each repeating element (163) are adjacent to each other. It holds a pointer to 163. The pointer is an address pointer, and an address given to the associated repeating element 163 is used as the pointer.

Here, three forms such as a form in which at least one of the width (W) direction region and the height (H) direction region overlap each other, such as an overlapping form, a contact form, and a form that exists next to each other by a grid lattice interval, are present. have. Since the width W and the height H of the outline shape are adjacent to each other, whether or not the exposure data is adjacent to each other is a separate problem even if they are adjacent to each other, but unless the width W and the height H are adjacent to each other, Are not adjacent to each other. In short, a table structure that makes it easy to search for suspicious places is created, and the structure that does not use the entire object for verification every time is adopted. As a result, the processing time can be shortened.

FIG. 18 is a diagram showing a data structure on a panel substrate created from reticle layout data and coordinate information, and FIG. 19 is a diagram showing table structure 2 corresponding to the data structure of FIG. 18, and a table structure maintaining a hierarchical structure. Indicates.

In FIG. 18, the repeating elements 182 and 188 which are arrange | positioned are provided in the lower layer of the tower module uniquely located in the top of a hierarchy. Arranged repeating elements 182 and 188 are, for example, transistor layers.

Under the arranged repeating element 182, a series hierarchical structure consisting of figure data 183, transistors TR1 184 and figure data 185, and transistors TR2 186 and figure data 187 The serial hierarchical structure is installed in parallel.

Under the arranged repeating element 188 is a series hierarchical structure consisting of figure data 189, transistors TR1 190 and figure data 191, and transistors TR2 192 and figure data 193. The serial hierarchical structure is installed in parallel.

19, the table includes an address, an instance name, a repeating element name, or a library name, a pointer to graphic data, a middle module instance name, a middle module library name, and a pointer to a middle layer library. Have.

The repeating element may have an intermediate layer, and in most cases it is a transistor layer. Since the amount of data becomes large when the transistor hierarchy is expanded, in this embodiment, dynamic (dynamic) processing is performed in which the data is held as a library in the pointer structure while the intermediate layer is not developed in advance, but expanded as needed. Is doing.

However, even if the same lower middle layer appears in two different middle layers, this method does not make common use. This is because even if the transistor appearing in the repeating element of interest is present in another repeating element, it can be fully developed with only the element of interest. In Fig. 19, an example in which the transistors TR1 and TR2 appear in different repeating elements but is independently registered in the table is shown.

20 and 21 are diagrams for explaining logic processing or difference processing and verification processing of figures, and show figure logic processing or figure difference processing for detecting one exposure area. Here, when one exposure is compared with an adjacent repeating element, it means the case where only one repeating element is exposed in the adjacent part.

For example, in FIG. 20, when the repeating element A of the reticle and the repeating element B of the reticle are arranged at the specified coordinates on the panel substrate, the panel layout elements corresponding to the repeating element A and the repeating element B overlap to form an area A '. , B 'is placed on the panel substrate.

A region A 'is a region on the panel substrate corresponding to the repeating element A, and part of the region B' on the panel substrate corresponding to the repeating element B is projected on this region. That is, the area A 'is a logical sum area of the overlap portion 2001 and the area corresponding to the repeating element A in the area on the panel substrate, and part of the panel layout element B' corresponding to the repeating element B is projected thereon.

Similarly, the region B 'is an area corresponding to the repeating element B and the logical sum region of the overlapping portion 2001 in the region on the panel substrate, in which part of the panel layout element A' corresponding to the repeating element A is projected. .

Therefore, as shown in Fig. 21, when XOR is taken for the panel layout element A on the panel substrate corresponding to the repeating element A and the panel layout element of the area A ', the area exists on one side but does not exist on the other side. Data of the (one exposure area) 2101 is extracted.

This is usually an overlap assignment mistake. This mistake may be a short frame designation mistake at the time of reticle data creation, a blind frame designation mistake at the time of reticle data creation, or a designation mistake of a batch coordinate. In general, the exposure data of the overlapping portions should be completely overlapped.

In addition, although it is called XOR here, the expression of taking a difference is also equivalent. In that case, the difference (A-A ') is taken, and if the result is positive, the data overlapping the data existing in the repeating element A and not present in the repeating element B overlaps. Instead, it can be said that data existing in the repeating element B is overlapped.

In this example it is the latter. To obtain the same information from the XOR result, take the XOR result and each AND of the repeating element A, the XOR result and the repeating element B. If the former result is logical 1, the data exists in repeating element A and not in repeating element B. If the latter result is logical 1, the data existing in the repeating element B instead of the repeating element A is overlapped.

The difference result is coded, so there is more information than simple logic process, and additional AND processing is required if you want to obtain information that is completely equivalent to difference process in XOR result. In summary, if the logic process is OR, XOR, AND, and the difference process is used, the OR and difference process results in a completely equivalent verification result as information.

22 to 24 are diagrams illustrating an OR process of detecting one exposure area using a grid grating.

Both logic processing and difference processing are performed between grid grids. Here, the definition of OR indicates that the grid grating is exposed if the result is logic 1, and that grid is not exposed if logic 0.

In FIG. 22, logical OR processing is performed on panel layout element A on the panel substrate corresponding to repeating element A and panel layout element B on the panel substrate corresponding to repeating element B, and as a result, panel layout elements of repeating elements A and B are performed. The result of the state where A and B overlapped by the overlap part 2001 is obtained. In FIG. 22, the centerline 2201 of the overlap portion 2001 is displayed on the grid.

FIG. 23 is a diagram in which the display corresponding to FIG. 22 is displayed by grid lattice points, and the center line 2201 of the corresponding overlap portion is written in order to make the drawing clear. That is, the processing result which took the exposure data L of the repeating element A, the exposure element R of the repeating element B, and these logical ORs is shown.

FIG. 24 is a logical value table showing the definition of the logical sum OR for each grid lattice point illustrated in FIG. 23. (Circle) is a logic value 0 and is a grid lattice point which is not exposed. Is a logic value 1 and is a grid lattice point to be exposed. The area enclosed by the triangle becomes an exposed area.

The diagram of the logical OR processing result shown in FIG. 23 is displayed on the display unit 1. The display position may be either the panel substrate window 9 or the reticle window 10. In addition, the panel substrate window 9, the reticle window 10, and the menu window 11 may be erased to display the processing result of FIG. It is also possible to display characters, and in this case, the panel substrate window 9, the reticle window 10, and the menu window 11 may be displayed, or these windows may be erased and the display unit 1 may be displayed. You can display the result of processing in characters throughout the parentheses.

25 and 26 are explanatory diagrams in the case where the exclusive OR operation or difference processing in FIG. 21 is performed using grid lattice points.

FIG. 25 shows the exposure data (panel layout element) of the repeating element A on the reticle L, the exposure data (panel layout element) of the region A 'on the panel substrate, and the logic XOR or difference thereof. .

FIG. 26 is a logic value table showing the definition of (LR) difference processing using an exclusive OR (XOR) for each grid lattice point of the exposure data L and R shown in FIG. 25 and each grid lattice point of the exposure data L and R; to be.

(Circle) is a logic value 0, and has shown the grid which the data to expose exists in both exposure data L and R, or the data to expose to both exposure data L and R does not exist. Denotes a grid in which the data to be exposed is exposed to either of the exposure data L or R as the logic value 1. FIG. Positive & tilde & indicates that there is data to be exposed to the exposure data L, and negative & tilde & indicates that there is data to be exposed to the exposure data R.

In this way, the exposed lattice point existing only in one region is detected. In the case of difference processing, information on which lattice points are exposed is also added in accordance with the positive and negative signs. As described above, in the case of XOR, only the results are found to be different, but in the case of difference, it is convenient because the positive negative sign can add information on which area the exposure data existed.

As a result of XOR or differential processing, in the case of logic 1, the grid represents figure data in which exposure data exists only on one side, and in the case of logic 0, the exposure data represents a grid which exists in both sides or does not exist in both sides.

27 and 28 are explanatory diagrams showing overlap of the most common panel layout elements.

FIG. 27 is a diagram showing the data 2707 to be exposed of the reticle by the grid lattice points 2704 not exposed and the grid lattice points 2705 exposed.

FIG. 28 is a diagram showing how the data 2707 is reproduced by the exposure data A and B obtained by exposing the repeated elements of the divided reticle based on the coordinate information.

Since the overlap amount of the overlap area 2703 is specified and the reticle layout data is created for the area to be divided and the exposure data 2707 to be cut immediately below it, it is necessary to verify whether it is correctly restored. have.

When the overlap amount is designated by the operation unit 16 as an offset value, it is stored in the storage unit 8, and the CPU 7 judges that it is not an error if it is within the range. In FIG. 27, FIG. 28, the center line 2706 of the overlap part 2703 is written in order to make it clear. In this example, the centerline 2706 is on-grid, but it may not be on-grid depending on the method of overlap.

FIG. 29 shows a repeating element (panel layout element) A (L) disposed on a panel substrate, FIG. 30 shows a repeating element B (R) arranged on a panel substrate, and FIG. 31 shows a panel substrate. It is explanatory drawing which shows the AND of AND of repeating elements A and B arrange | positioned on it. 32 is a logical value table of AND of repeating elements A and B arranged on the panel substrate, and shows the definition of AND for each grid lattice point.

29 to 32, the arranged repeating elements A and B have an unexposed area and an exposure area by an unexposed grid lattice point 2901 and a grid lattice point 2902 exposed by?. Is indicated.

In addition, in FIG. 31, the repeating elements A and B which are arrange | positioned are overlapped by the overlap part 2703. As shown in FIG. This is the most common example of creating double exposure by overlap. The detected overlap part 2703 is not an error if it falls within the predetermined offset value within the specified width plus minus.

33-36 is a figure which shows the example of the double exposure area extracted by AND process. In addition, the non-exposed area and the exposure area are displayed by the grid lattice points which are not exposed as indicated by o and the grid lattice points which are exposed by o.

33 is the same as the example shown in FIGS. 29-32, and is the example in which two repeating elements A and B arrange | positioned on the panel board | substrate overlap only the overlap part 2703. In FIG. By the AND processing of the arranged repeating elements A and B, the overlap amount (offset value) is three grid gratings, which is an example normally determined to be normal.

Fig. 34 shows that two repeating elements A and B arranged on a panel substrate share only one grid lattice as the overlap portion 2703, and do not enter the predetermined offset value of the specified width plus minus, and usually is an error. This is an example. In this embodiment, the case where the overlap area is one grid grating as shown in FIG. 34 is referred to as fold exposure-1.

In the example of FIG. 35, two repeating elements A and B arranged on a panel substrate are adjacent to each other at intervals of one grid lattice. In this embodiment, this example is called exposure exposure-2, and it is judged that it is an error normally. In this example, the area of the AND processing result is not extracted, but if one closed figure is extracted by performing the OR process, it can be determined that the type of exposure exposure-2 is.

36 shows a data arrangement in which two repeating elements A and B arranged on a panel substrate are spaced apart by two or more grid grids. In this example, the region of the AND processing result is not extracted, and there are two repeating elements A and B arranged on the panel substrate, and at least one non-exposed area grid lattice point 3601 exists between the two grid lattice. . This is detected by extraction of the non-exposed area 3601 described later.

37 and 38 are explanatory views in the case of performing double exposure with respect to the reticle data which has a repeating element which added the correction pattern.

In FIG. 37, the first layer metal wiring 3702 and the second layer metal wiring 3703 in the panel layout data are cut out by the set short frame 1002.

When providing a correction pattern, as shown in FIG. 38, the 1st layer metal wiring 3702 and the 2nd layer metal are respectively in the edge part of the 1st layer metal wiring 3702 and the 2nd layer metal wiring 3703, respectively. The predetermined length width is wider than the width of the wiring 3703, and the correction pattern 1004 having a predetermined length in the longitudinal direction thereof is continuously formed integrally.

A blind frame 1005 of a predetermined width is formed so that the inner edge 1006 overlaps the outer edge side of the correction pattern 1004 by a predetermined length (for example, one grid lattice).

A blind frame 1005 of a predetermined width is formed so that the inner edge 1006 of the blind frame 1005 and the outer edge of the correction pattern 1004 overlap a predetermined length (for example, one grid lattice).

The blind frame 1005 and the correction pattern 1004 may not overlap each other, and the inner frame and the correction pattern 1004 of the blind frame 1005 may be in contact with each other.

Here, the generated correction pattern 1004 becomes the area 1007 which is a target of double exposure.

Therefore, as shown in Figs. 39 and 40, it is verified using the result of the AND process whether or not the correction pattern 1004 is properly a double exposure area.

That is, in Fig. 39, the repeating elements A and B arranged on the panel substrate are arranged so that the designated shot frame regions 3403 and 3904 in the shot frame 1002 overlap. As a result, the correction pattern 1004 of the repeating element A and the correction pattern 1004 of the repeating element B are overlapped and exposed twice, and on the panel substrate, the metal wiring 3901 of the repeating element A and the metal of the repeating element B are exposed. The wiring 3902 is formed continuously.

40 is an explanatory diagram showing this state using grid lattice points. 40, as a result of overlapping the short frame region 3403 of the repeating element A and the short frame region 3904 of the repeating element B and performing the AND logic process between the grid grid points of the repeating elements A and B, the continuous region A ', B' is formed. In addition, ● indicates grid lattice points exposed by logic 1, and ○ indicates grid lattice points not exposed by logic 0.

38 also illustrates the double exposure verification of the blind frame internal combustion 1006 and the figure data. That is, it is to verify how much the figure data (correction pattern 1004 in the case of FIG. 38) is inside the blind frame 1005. In this case, it is '1', that is, exposure exposure-1 (see FIG. 34). It is common to overlap one grid lattice. That is, the offset value, which is usually the overlap amount, is assumed to be normal for one grid lattice.

However, also in this case, an AND process is applied and an error occurs when the double exposure area is larger or smaller than the specified offset value.

The double exposure verification of the blind frame internal combustion 1006 and the figure data in FIG. 38 is somewhat different in this verification. That is, coordinate information is not necessary because only reticle layout data can be verified. However, when performing a series of processes as shown in FIG. 15, of course, it is also possible to perform a verification process with respect to the result of the arrangement | positioning based on coordinate information.

41 and 42 are explanatory views for explaining the verification processing for the presence or absence of the non-exposed area, that is, whether the entire area of the panel substrate is covered by the reticle layout data 162. FIG.

As shown in FIG. 41, the repeating element 163 in the reticle layout data 162 provided in the reticle 13 is exposed to the panel substrate 12 similarly on the basis of the coordinate information, and the panel substrate 12 The panel layout data 161 is similarly formed and arranged on the surface.

When arranging the repeating element 163 in the reticle layout data 162 on the panel substrate 12 based on the coordinate information, as shown in FIG. 42, the exposure target included in the inner edge of the blind frame of the repeating element 163. A logical OR of the area and the area of the panel substrate 12 corresponding to the exposure target area is taken. This is done for all the repeating elements 163, and if there is a grid grating of logic 0 on the panel substrate 12, the area is an error in the area not to be exposed.

41 shows an example in which a region 4101 is generated on the panel substrate 12 that is not covered with reticle data (no panel layout data is formed) because the repeating element R1 is missing. In this case, the CPU 7 recognizes it as an error.

The relationship between the logic processing of the reticle data and the verification items described above is as follows.

In the case of one exposure verification, the logic or difference processing takes an OR of A and B with respect to the figures A and B, and the exclusive OR of the region A 'and the figure A including the resulting figure A Take (A 'XOR A). Alternatively, the difference between the region A 'and the figure A including the figure A of the logical sum result is taken. As a detection item, data which exists only in the area | region containing the figure A, and existed in the area | region containing the figure B is detected (refer FIG. 20-FIG. 26).

In the case of the double exposure verification (including the exposure exposure-1), the logical processing or the differential processing takes a logical product (A AND B) of A and B with respect to the figures A and B. As a detection item, it detects a double exposure area, determines whether it is an error based on the set parameter, and if it determines with an error, outputs this determination result as an error report (FIGS. 27-36, 39, 40). Reference).

In the case of the exposure exposure-2, the logic process or the difference process takes a logical product (A AND B) of A and B with respect to the figures A and B. When this result is logical 0 (no figure) and the result of the logical sum (A OR B) of A and B forms one figure, the detection item is detected by the exposure exposure-2 region, and the set parameter is applied. On the basis of this, whether or not an error is determined is judged, and when it is determined as an error, this determination result is output as an error report (see FIGS. 39 and 40).

In the case of non-exposure verification, the logic process or the difference process arranges and expands all the reticle layout data on the panel substrate and performs an OR operation. As a detection item, grid lattice points at which the bits of the OR are not written (where the result of the OR processing is logical 0) are detected as the non-exposed areas (see FIGS. 41 and 42).

43 and 44 are explanatory diagrams for explaining the graphic display of the verification result. FIG. 43 is a diagram showing a dialog box 431 displayed on the display unit 1, and FIG. 44 is a panel substrate of the display unit 1. It is a figure which shows the error display of the graphic data format displayed on the window 12. FIG.

The setting of the verification condition is set by operating the operation button in the dialog box 431 by the operation unit 16. For example, since verification is performed in units of all layers, the operation unit 16 designates a layer to be displayed on the dialog box 431, and then specifies an error type to be displayed to instruct the search.

Here, the error types to be displayed are five kinds of exposure, single exposure, double exposure-1, close exposure-2, and non-exposure. Each error type can specify the color to display. In Fig. 44,? Indicates a grid lattice point (error grid lattice point) having an error of any of the five types of errors, and? Indicates a grid lattice point having no error.

The CPU 7 displays to the user how many error points there are based on the set conditions.

Subsequently, when the user operates each operation button in the display operation area 432 by the operation unit 16 and instructs the location of the error next, previous, first, or last, it is displayed on the panel substrate window 12 at that time. For an error area that is present, the indicated content is displayed.

It is common that the error point is displayed in several places. For example, if the next is designated, the left side is shifted to the right with the upper left as the starting point in the resolution displayed there. Display. In addition, if enlargement or reduction is instructed, graphic data enlarged or reduced for the displayed central coordinate is displayed.

45 is a diagram illustrating a data structure of a detected error figure. The error data is automatically generated and linked to the top module 451 by the module names of the error modules 452, 454, 456, and 458. The graphic data (453, 455, 457, 459) which become an error are linked directly under each error module (452, 454, 456, 458). The error modules 452, 454, 456, and 458 have the same instance name and library name. Therefore, even error data having the same shape is not shared. This is because errors occur basically independently of the panel substrate.

As described above, in the reticle verification system according to the embodiment of the present invention, the CPU 7 refers to the figure data and the coordinate information of the exposure element stored in the data file storage 5 of the storage 8. Thus, a panel layout element (layout figure element) on the display panel corresponding to the exposure element is generated, and a verification result based on the positional relationship of the plurality of panel layout elements is displayed on the display unit 1. In addition, when an error criterion is set, the positional relationship of the plurality of panel layout elements is determined to verify whether the exposure element is in error, and the verification result is displayed on the display unit 1. The display unit 1 displays the verification results in the panel substrate window 9 or the reticle window 10 or in a display area irrelevant to these windows.

As described above, the reticle verification system according to the present embodiment inputs the reticle layout data and the arrangement information of the exposure element (repetition element), simulates the operation of the exposure apparatus, and performs a graphic calculation process to perform exposure processing similarly. The reticle is used to verify whether or not proper panel layout data is formed on the panel substrate, in other words, to verify proper reticle.

That is, the reticle data can be verified by simulating the exposure apparatus and performing a graphic arithmetic operation on whether the generated reticle data is correct. This is particularly useful for verifying the reticle data used when manufacturing a flat panel display. According to the present embodiment, it is determined whether the panel substrate data created from the reticle layout data and the coordinate information is correctly exposed data. Can be verified.

In addition, since it becomes possible by adding the verification function based on the operation simulation of the exposure apparatus and the figure calculation process, it is possible to verify before entering the manufacturing process.

As a result, in the manufacture of flat panel displays, there is a great effect on the cost including the working time. In other words, by performing the reticle verification system according to the embodiment of the present invention before manufacturing, it is possible to prevent unnecessary cost burden in advance if it is confirmed that the reticle is correct data.

This is because they do not have to make such unnecessary expenditures at the cost of manufacturing time and analysis time, including reticle manufacturing cost, panel substrate manufacturing cost, labor cost in the case of mis-manufacturing. This effect is exactly the same in the case of simple repetition designation that only requires division of regions. This is because there are many cases of artificial designation mistakes in repetitive designation.

In addition, according to the present embodiment, it is possible to provide a reticle verification program for constructing the reticle verification system by executing on a computer having the display unit 1, the operation unit 16, the CPU 7, and the storage unit 8. Become. In addition, a reticle verification method is provided.

In the above embodiment, the reticle verification system is constructed using one computer, but may be constructed using a plurality of computers. In this case, the above programs can be configured as appropriately divided according to the system configuration.

It can be used for a reticle verification system which verifies reticles for manufacturing various displays such as liquid crystal displays. The computer can also be used for a program that functions as a reticle verification system that verifies various reticles for display production.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the relationship between the panel substrate for flat panel displays, and a reticle in embodiment of this invention.

FIG. 2 is a diagram showing a relationship between panel layout data on a panel substrate and reticle layout data on a reticle in an embodiment of the present invention.

3 is a diagram showing the overall display contents when generating reticle data in the embodiment of the present invention.

4 is a flowchart showing the overall processing when generating the reticle data in the embodiment of the present invention.

5 is a diagram illustrating a structure of panel layout data in the embodiment of the present invention.

6 is a diagram illustrating a structure of reticle data in the embodiment of the present invention.

7 is a table of reticle data in the embodiment of the present invention.

8 is a diagram showing coordinate information output processing in the embodiment of the present invention.

9 is a diagram showing coordinate information output processing in the embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a method of performing division processing of an exposure area in an embodiment of the present invention. FIG.

It is explanatory drawing which shows the division processing method of the exposure area in embodiment of this invention.

It is explanatory drawing which shows the division processing method of the exposure area in embodiment of this invention.

Fig. 13 is a view showing an exposure element in the embodiment of the present invention.

14 is a block diagram of a reticle verification system of an embodiment of the invention.

15 is a flowchart illustrating processing of the reticle verification system according to the embodiment of the present invention.

It is a figure which shows the relationship of the various data in embodiment of this invention.

17 is a data table in the embodiment of the present invention.

Fig. 18 is a diagram showing a data structure on a panel substrate in the embodiment of the present invention.

Fig. 19 shows a table structure corresponding to the data structure on the panel substrate in the embodiment of the present invention.

It is explanatory drawing which shows the various process of the figure in embodiment of this invention.

It is explanatory drawing which shows the various process of the figure in embodiment of this invention.

Fig. 22 is an explanatory diagram showing an OR process of detecting one exposure area in the embodiment of the present invention.

It is explanatory drawing which shows OR process of detection of one exposure area in embodiment of this invention.

24 is an explanatory diagram showing an OR process of detecting one exposure area in the embodiment of the present invention.

It is explanatory drawing which shows the exclusive OR process or difference process in embodiment of this invention.

It is explanatory drawing which shows the exclusive OR process or difference process in embodiment of this invention.

It is explanatory drawing which shows the overlap of exposure data in embodiment of this invention.

It is explanatory drawing which shows the overlap of exposure data in embodiment of this invention.

29 is a diagram showing repeating elements disposed on a panel substrate in an embodiment of the present invention.

30 is a diagram showing repeating elements disposed on a panel substrate in an embodiment of the present invention.

Fig. 31 is an explanatory diagram showing the logical product of the repeating elements arranged on the panel substrate in the embodiment of the present invention.

32 is a logic value table of repeating elements disposed on the panel substrate in the embodiment of the present invention.

It is a figure which shows the example of the double exposure area in embodiment of this invention.

It is a figure which shows the example of the double exposure area in embodiment of this invention.

It is a figure which shows the example of the double exposure area in embodiment of this invention.

It is a figure which shows the example of the double exposure area in embodiment of this invention.

37 is an explanatory diagram of a double exposure process in an embodiment of the present invention.

38 is an explanatory diagram of a double exposure process in an embodiment of the present invention.

39 is an explanatory diagram of a double exposure verification process in an embodiment of the present invention.

It is explanatory drawing of the double exposure verification process in embodiment of this invention.

41 is an explanatory diagram of a non-exposed area verification process in the embodiment of the present invention.

42 is an explanatory diagram of a non-exposed area verification process according to the embodiment of the present invention.

43 is an explanatory diagram of verification results in the embodiment of the present invention.

44 is an explanatory diagram of verification results in the embodiment of the present invention.

45 is a diagram showing a data structure of an error figure detected in the embodiment of the present invention.

Explanation of the sign

One… Display

2… keyboard

3 ... mouse

4… Program memory

5... Data file storage

6... File storage

7 ... CPU

8… Memory

9... Panel Board Window

10... Reticle windows

11... Menu window

12, 101, 210, 801... Panel board

13, 205, 805, 808, 811... Reticle

16... Control panel

102, 212... Exposure area

103... Exposed Area

104... Light source

105... Shading system

107... Exposed surface

162... Reticle layout data

163... Exposure Element (Repeating Element)

201-204. LCD panel

206... Reticle layout data

161, 211, 802, 1003... Panel layout data

213, 1002... Short frame

431... Dialog box

432... Display operation area

804... Alignment mark

806, 809, 810, 812, 813... Repeat element

1004... Correction pattern

1005... Blind frame

1006... Internal combustion

1007... Site to perform double exposure

1008, 2001, 2703... Overlap part

1301... Oblique line

2101... Single exposure area

2201, 2706... center line

2707... Exposure data

2704, 2705, 2901, 2902... Grid grid points

2707... data

3601... Non-exposed grid grid points

3702, 3703, 3901, 3902... Metal wiring

3903, 3904... Short frame area

Claims (11)

Storage means for storing figure data of the exposure element included in the flat panel display exposure reticle, coordinate information displayed by the coordinates of the grid lattice points, and indicating the exposure position of the exposure element on the display panel; Layout figure element generating means for generating a layout figure element on the display panel corresponding to the exposure element based on the figure data and the coordinate information of the exposure element stored in the storage means; Verification means for verifying the exposure element based on the positional relationship of a plurality of layout figure elements on the display panel generated by the layout figure element generation means; Display means having at least a window for displaying a result verified by the verification means, The verification means verifies the plurality of exposure elements by performing arithmetic processing of grid grid points corresponding to the plurality of layout figure elements, And the display means displays a figure obtained on the result of verification by the verification means on the window. delete delete The method of claim 1, The verification means performs logical OR processing of the two layout figure elements, and then performs logical XOR or differential processing of an area corresponding to the layout figure element among the one layout figure element and the figure element obtained as a result of the logical OR. And difference extracting means for extracting a difference between the two layout figure elements. The method of claim 1, And said verifying means comprises overlap amount detecting means for detecting an overlap amount of said two layout figure elements by performing a logical AND process of two layout figure elements. The method of claim 5, And the verifying means comprises offset verifying means for verifying whether or not the overlap amount detected by the overlap amount detecting means satisfies the indicated offset value. The method of claim 5, If the verification means detects that the overlap amount detection means does not have an overlap amount of the two layout figure elements, and performs a logical OR process, when it is confirmed that a result of forming two layout figure elements into one closed figure is confirmed, And the two layout figure elements are provided with element discriminating means for discriminating them as consecutive figure elements. The method of claim 1, Each of the exposure elements includes a figure element and a blind frame having a predetermined width surrounding the figure element, The verifying means includes end point verifying means for verifying whether or not an end point of a layout figure element of the figure element exists within a range of a predetermined offset value with respect to a grid lattice point on the display panel corresponding to the blind frame inner edge; Reticle verification system, characterized in that the. The method of claim 1, Specifying means for specifying an error layer in which an error verification result is included, And when the display means displays the error figure information on the window displaying the verification result, the error figure information of the error layer designated by the designation means is displayed on the window in units of layers. 10. The method of claim 9, The display means has a dialog box different from the window displaying the verification result, The designation means designates the error layer on the dialog box, And said display means displays the number of errors on said dialog box, and displays error figure information of said layer on said window in response to designation of an error layer by said designation means. A recording medium having recorded thereon a program for functioning as the reticle verification system according to any one of claims 1 and 4.

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