JPH10339942A - Layout pattern verification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily verify whether ROM code data is exactly converted into a ROM stage layout pattern data. SOLUTION: The layout pattern of all the bits of a ROM stage is generated by a check layout pattern data generating means 47 based on a ROM stage layout pattern converted by a ROM stage layout pattern data convesion means 46 and a ROM code conversion parameter. Then, a ROM rectangle obtained when the layout pattern is '0' or '1' and the check layout pattern data showing the address value of the ROM rectangle are superposed and displayed on a display.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout pattern verification apparatus for verifying layout pattern data of a ROM process required when a ROM process mask for an LSI with a built-in mask ROM is prepared.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional layout pattern verification device. In the figure, 1 is R
OM code data reading unit, 2 is a ROM code conversion parameter reading unit, 3 is a data storage unit that stores all input / output data, 4 is a data control unit that controls all input / output data, and 5 is a screen display of input / output data. A screen display unit 6 is a ROM process layout pattern data conversion unit that converts ROM code data into ROM process layout pattern data.

[0003] FIG. 7 shows a circuit diagram of an R in a mask ROM built-in LSI.
FIG. 3 is an explanatory diagram illustrating a logic circuit model of an OM block. Note that, in the logic circuit model of the ROM block shown in FIG. (A) The layout structure of this logic circuit model is CMOS
The layout pattern data corresponding to one bit (hereinafter, referred to as ROM rectangular pattern data) is a channel cut step, but is herein referred to as ROM step layout pattern data. (A) This logic circuit model has a 1-bit configuration (in the case of an n-bit configuration, n logic circuit models shown in FIG. 7 are configured in parallel). (C) The conversion of the ROM code is positive logic (a layout pattern is generated at bit 1).

In FIG. 7, reference numeral 11 denotes a signal line which is a ROM address bus in an LSI with a built-in mask ROM.
It has an 8-bit configuration of A0 to A7. An X address decoder 12 selects a ROM rectangle at the X coordinate in the ROM area. The lower 4 bits of the ROM address bus, A0 to A0,
It shall be selected by the combination of A3. 13 is a Y for selecting a ROM rectangle at the Y coordinate in the ROM area.
An address decoder, which is also selected by a combination of the upper four bits of the ROM address bus and A4 to A7. Reference numeral 14 denotes a select signal line in the X direction selected by the X address decoder 12, and it is assumed that any one of the select signal lines X0 to X7 is selected for the ROM address value. Reference numeral 15 denotes a Y-direction select signal line selected by the Y address decoder. Similarly, any one of the select signal lines Y0 to Y7 is selected for the ROM address value. 16 is the X address decoder 1
2 shows the position of the ROM rectangular pattern data at the intersection of the select signal lines selected by the Y and Y address decoders 13. In this logic circuit model, one ROM address always corresponds to one ROM rectangular pattern data.
8 = 64 ROM addresses.

Next, the operation of the conventional layout pattern verification device will be described. FIG. 6 is a flowchart showing the operation of the conventional layout pattern verification device. First, the ROM code data is read from the ROM code data reading unit 1.
(Step ST1). FIG.
The example of OM code data is shown. It should be noted that the logic circuit model in this description has a one-bit configuration, so the ROM code value is also one bit. Further, the ROM code conversion parameter is read from the ROM code conversion parameter reading unit 2 (step ST2).

FIG. 9 shows an example of ROM code conversion parameters read by the ROM code conversion parameter reading section 2. In the figure, 21 is the offset X coordinate position and offset Y coordinate position, 22 is the width W and height H of the ROM rectangle, 23 is the ROM rectangle interval in the X direction and Y direction ROM rectangle, and 24 is the X address decoder 12. Address bit number, 25 is address bit number, 26 is X
The truth values of the address bit numbers corresponding to the select signal lines 14 of 0 to X7 and 27 are the Y address decoder 13
, 28 is the address bit number, 2
Reference numeral 9 denotes the data indicating the truth value and the address bit number corresponding to the select signal line 15 of Y0 to Y7.

Returning to FIG. 6, according to the read ROM code conversion parameters, all addresses of the ROM code data are converted according to the following procedures (a) to (e) (step ST3). (A) The ROM code data reading unit 1 reads the ROM code data at one address, and if the data value of the address is "1", performs the processing from (b) onward, and if the data value is "0". Skips to the address address where the data value is "1".

(B) Convert the address of the ROM code into a binary number. FIG. 8 shows an example of ROM code data, in which 17 indicates an address, and 18 indicates a ROM code value. Address address in this ROM code data, 0
In the conversion example of 010H, 0010H (HEX) is 0
000 0000 0001 0000 (binal
y). Note that each bit is A from the LSB side of the binary number.
Description will be given as 0 to A15. (C) Find selected positions of X address decoder 12 and Y address decoder 13. This selection position is determined by the RO
Determined with reference to the M code conversion parameters. RO in FIG.
In the conversion example using the M code conversion parameters, the position selected by the X address decoder 12 is the X0 select signal line in the first column from the left, which is the position selected by bits A0 to A3 and 0000 (binary). The position selected by the Y address decoder 13 is the Y1 select signal line in the second row from the bottom, which is the position selected by bits A4 to A7, 0001 (binary).

(D) The ROM rectangle corresponding to the selected position selected by each of the select signal lines is the ROM rectangle shown in FIG.
The X coordinate and the Y coordinate of the ROM rectangle 16 are obtained. The X coordinate of the ROM rectangle 16 is the X coordinate of the lower left vertex of the ROM rectangle.
6 is determined based on the offset X coordinate which is the X coordinate of the lower left vertex. The Y coordinate is the Y coordinate of the lower left vertex of the ROM rectangle.
It is a coordinate and is obtained by an offset Y coordinate which is a Y coordinate of a lower left vertex of the ROM rectangle 16+ (rectangle height + rectangular interval) × (number of rectangles from lower left-1). (E) The RO coordinate is added to the X coordinate and Y coordinate obtained in (d) above.
ROM rectangle width W specified by M code conversion parameter
By creating the ROM rectangular pattern data at the height H, the ROM rectangular pattern data is formed at the selected position selected by each of the select signal lines.

After converting all the addresses of the ROM code data in the above procedure, the ROM process layout pattern data is displayed on the screen display section (step ST4), and the RO
It is visually confirmed that the M code data is correctly converted to the ROM process layout pattern data. FIG.
Is an explanatory diagram showing an example of the ROM process layout pattern data displayed in this way, and 30 is the ROM process layout pattern data.

[0011]

Since the conventional layout pattern verification apparatus is configured as described above, there are the following problems. It is difficult to easily verify whether the ROM code data is correctly converted to the ROM process layout pattern data, and verification of the arrangement coordinates of the verified ROM rectangular pattern data requires generation of all-bit ROM rectangular pattern data. However, it is not easy to confirm which address address each of the ROM rectangular pattern data logically corresponds to. Therefore, the ROM code data list shown in FIG. There is a problem that it is not easy to visually verify the ROM process layout pattern data shown in FIG.

Further, when performing the verification, the ROM process layout pattern data shown in FIG. 10 depends on the ROM code data, and it is necessary to understand and collate the contents of the ROM code data. Further, since the ROM code conversion parameter is set by the operator, for example, when all the ROM code data shown in FIG. 8 are “1” or “0”, even if the ROM code conversion parameter is incorrect, There is a possibility that ROM process layout pattern data similar to the case where there is no error in the conversion parameters may be created.
There has been a problem that an error in the OM code conversion parameter does not appear in the table.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and the ROM code data can be correctly stored in the RO.
Whether or not the data has been converted to the M-process layout pattern data, in particular, which address address logically corresponds to the ROM rectangular pattern data can be easily confirmed.
It is an object of the present invention to obtain a layout pattern verification device capable of easily knowing an error in a ROM code conversion parameter.

[0014]

According to a first aspect of the present invention, there is provided a layout pattern verification apparatus comprising: a ROM process layout pattern converted by a ROM process layout pattern data converting unit; Display control means for superimposing the data on the layout pattern data for display on the display.

According to a second aspect of the present invention, there is provided a layout pattern verifying apparatus including a display control means for displaying a ROM process layout pattern on a display so as to be distinguishable from the inspection layout pattern data. It is.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of the layout pattern verification device according to the first embodiment of the present invention. The layout pattern verification apparatus according to the first embodiment extracts coordinates and address addresses for all bits from the ROM code conversion parameter, and compares the ROM rectangle for all bits and the address address corresponding to each ROM rectangle with a layout for verification. The pattern data is visually displayed on the same screen together with the ROM process layout pattern data.
Then, by displaying the ROM process layout pattern data and the inspection layout pattern data in a superimposed manner, whether or not the ROM code data is correctly converted to the ROM process layout pattern data,
It is easy to confirm which address address the rectangular pattern data logically corresponds to, and also to easily confirm a setting error of the ROM code conversion parameter and the like.

In FIG. 1, reference numeral 41 denotes a ROM code data reading section (ROM) for reading ROM code data consisting of an address address and a data value set at each of the address addresses.
Code data reading means), 42 is an RO for converting the ROM code data into a ROM process layout pattern.
ROM code conversion parameter reading unit (ROM code conversion parameter reading means) for reading M code conversion parameters; 43, a data storage unit for storing all input / output data;
44 reads, processes, and stores all input / output data, and further stores ROM process layout pattern data converted by the ROM process layout pattern data conversion unit 46 and reference layout pattern data created by the reference layout pattern data creation unit 47. It is a data control unit (display control unit) that performs a process of superimposing and displaying on a display (not shown).

Reference numeral 45 denotes a screen display unit for displaying input / output data on a screen; 46, a ROM process layout pattern data converting unit (ROM process layout pattern data converting means) for converting the ROM code data into ROM process layout pattern data; Based on the ROM code conversion parameters, a ROM rectangle when the layout pattern of all bits in the ROM process is “0” or “1” (all bits “1” in this embodiment), A check layout pattern data creating unit (check layout pattern data creating means) for creating check layout pattern data indicating the address value of the check pattern.

Next, the operation will be described. FIG. 2 is a flowchart showing the operation of the layout pattern verification apparatus according to the first embodiment. The following description is based on the logic circuit model shown in FIG. First, RO
The M code data is read by the ROM code data reading unit 41 (step ST11). R to read in this case
The OM code data is the same as the ROM code data shown in FIG. Next, the ROM code conversion parameter is read by the ROM code conversion parameter reading unit 42 (step ST12). The ROM code conversion parameters to be read in this case are the same as those shown in FIG. Then, the ROM code data is converted into ROM process layout pattern data by the ROM process layout pattern data converter 46 according to the ROM code conversion parameter (step ST13).

The conversion into the ROM process layout pattern data is performed according to the following procedure. (A) ROM code data is read by the ROM code data reading unit 41 at one address, and if the data value of the address is "1", the processing after (b) is performed; if the data value is "0", Skips to the address address where the data value is "1". (B) Convert the address of the ROM code into a binary number. An example of conversion of the address 0010H using the ROM code data shown in FIG.
X) is 0000 0000 0001 0000 (bi
nally). Note that each bit is described as A0 to A15 from the LSB side of the binary number.

(C) Next, the selected positions of the X address decoder 12 and the Y address decoder 13 are obtained. This selection position is obtained with reference to the ROM code conversion parameters shown in FIG. An example of conversion using the ROM code conversion parameter is shown in FIG.
A0 to A3 bits, 0000 (bi)
2) is a select signal line of X0 in the first column from the left, which is the position selected by (nary). Also, the Y address decoder 13
Is selected at bits A4 to A7, 0001 (bi
2) is the select signal line of Y1 in the second row from the bottom, which is the position selected by (nary).

(D) A ROM rectangle (reference numeral 3 in FIG. 10) corresponding to the selected position selected by each of the select signal lines.
The X coordinate and the Y coordinate of the ROM rectangle indicated by 0 are obtained. In this case, the X coordinate of the ROM rectangle 30 is the RO coordinate.
The X coordinate of the lower left vertex of the M rectangle is obtained based on the offset X coordinate which is the X coordinate of the lower left vertex of the ROM rectangle 16 shown in FIG. The Y coordinate is the Y coordinate of the lower left vertex of the ROM rectangle, and is the offset Y coordinate which is the Y coordinate of the lower left vertex of the ROM rectangle 16 shown in FIG. It is determined by the equation (1). (E) The X coordinate and Y coordinate obtained in (d) above are added to the R
ROM rectangular pattern data is created with the width W and height H of the ROM rectangle specified by the OM code conversion parameters.

In accordance with the above procedure, all the addresses of the ROM code data are converted, the ROM rectangular pattern data shown in FIG. 10 is created, and the ROM rectangular pattern data is converted into the ROM process layout pattern data. The ROM rectangular pattern data shown in FIG. 10 is displayed and output, for example, by coloring. As a result,
When the ROM rectangular pattern data and the inspection layout pattern data are displayed in a superimposed manner on the display, the ROM rectangular pattern data can be easily identified from the inspection layout pattern data. Also, ROM rectangular pattern data is logically
It is easy to confirm which address of the code data corresponds to which address. Also, 1 which is output simultaneously with the ROM rectangle
An error in the ROM code conversion parameter can be easily known from the ROM address in hexadecimal notation.

Next, reference layout pattern data is created according to the ROM code conversion parameters (step ST14). FIG. 3 shows the layout pattern data for reference. The procedure for creating the layout pattern data for inspection is as follows: (1) Referring to the ROM code conversion parameters shown in FIG. 7, an address address corresponding to the intersection of the X0 select signal line and the Y0 select signal line shown in FIG. (Lower 8 bits). The bit value of the address corresponding to the X0 select signal line at the left end position of the X address decoder 12 is a value of A0 to A3 bits, and is 00
00 (binary), and the bit value of the address address corresponding to the Y0 select signal line at the lower end position of the Y address decoder 13 is the value of A4 to A7 bits,
000 (binary).

(2) When the bit value of the address is "0" or "1", the bit value of the address is determined to be "1" in this embodiment and the bit value of the address is set to RO.
Convert to M address value. The conversion to the ROM address value is such that the upper 4 bits are 0000 and the lower 4 bits are 0000.
Which is 00H in hexadecimal. (3) Next, the X coordinate and the Y coordinate of the ROM rectangle 16 (corresponding to the ROM rectangle 51 in FIG. 3) corresponding to the intersection of the X0 select signal line and the Y0 select signal line are obtained. X coordinate is X
This is the X coordinate of the lower left vertex of the ROM rectangle 16 on the 0 select signal line, and is the offset X coordinate. The Y coordinate is the Y coordinate of the lower left vertex of the ROM rectangle 16 on the Y0 select signal line, and is the offset Y coordinate.

(4) The X coordinate and the Y coordinate obtained in the above (3) are added to the R coordinate specified by the ROM code conversion parameter.
ROM rectangular pattern data is created using the width W and the height H of the OM rectangle. The ROM rectangular pattern data R
ROM address 00 for upper 8 bits in OM rectangle
A text indicating a ROM address 0000H composed of H and the lower 8 bits of the address 00H obtained in (1) is created. (5) The above procedure (1) to (4) is performed according to the ROM rectangle (the layout pattern of all the bits in the ROM process) corresponding to all the intersections of the X0 select signal line to the X7 select signal line and the Y0 select signal line to the Y7 select signal line. ). As a result, the layout pattern data for inspection in which the ROM address and the ROM rectangle shown in FIG. 3 are simultaneously displayed is created.

Returning to FIG. 2, the display screen section 45 displays (1)
The layout pattern data for reference created in the procedures (5) to (5) and the ROM process layout pattern data converted in the procedures (a) to (e) are displayed in a superimposed manner (step ST15). Check visually for any problems. FIG. 4 shows an image diagram in which the layout pattern data for reference and the ROM process layout pattern data are displayed in an overlapping manner.

As described above, in the first embodiment, R
The ROM rectangular pattern data created from the ROM address and the data value of the OM code data and the layout pattern data for inspection in which the hexadecimal ROM address and the ROM rectangle are simultaneously output are displayed in a superimposed manner. Since the ROM rectangular pattern data is displayed so as to be distinguishable from the reference layout pattern data, the ROM rectangular pattern data
It is possible to easily confirm which address address of the code data corresponds, and it is possible to easily know the error of the ROM code conversion parameter by the hexadecimal ROM address address which is output simultaneously with the ROM rectangle. There is an effect that a layout pattern verification device can be obtained.

[0029]

As described above, according to the first aspect of the present invention, the ROM process layout pattern converted by the ROM process layout pattern data conversion means and the ROM process layout pattern
The ROM rectangle when the layout pattern of all the bits in the ROM process created by the reference layout pattern data creating means based on the code conversion parameter is “0” or “1”, and the address value of each ROM rectangle. Since the layout pattern data for inspection is superimposed and displayed on the display, whether or not the ROM code data is correctly converted to the ROM process layout pattern data, in particular, the ROM rectangular pattern data is logically converted to the ROM code data. It is possible to easily confirm which address address corresponds, and it is also possible to easily know an error in the ROM code conversion parameter from the address value of the layout pattern data for inspection which is simultaneously output while being superimposed on the ROM rectangular pattern data. Has the effect of becoming

According to the second aspect of the present invention, the layout pattern of the ROM process is configured to be distinguishable from the layout pattern data for inspection and superimposed on the display, so that the data value is "0" or The ROM process layout pattern corresponding to the ROM code data of "1" is easily identified from the reference layout pattern data, and the
There is an effect that it is possible to know whether or not the data has been converted to the OM process layout pattern data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a layout pattern verification device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the layout pattern verification device according to the first embodiment of the present invention;

FIG. 3 is an explanatory diagram showing inspection layout pattern data created by an inspection layout pattern data creation unit of the layout pattern verification device according to the first embodiment of the present invention;

FIG. 4 is an image diagram in which reference layout pattern data and ROM process layout pattern data are displayed in a superimposed manner in the layout pattern verification device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional layout pattern verification device.

FIG. 6 is a flowchart showing the operation of a conventional layout pattern verification device.

FIG. 7 is an explanatory diagram showing a logic circuit model of a ROM block in an LSI with a built-in mask ROM.

FIG. 8 is an explanatory diagram showing an example of ROM code data read by a ROM code data reading unit.

FIG. 9 is an explanatory diagram illustrating an example of ROM code conversion parameters read by a ROM code conversion parameter reading unit.

FIG. 10 is an explanatory diagram showing an example of ROM process layout pattern data.

[Explanation of symbols]

41 ROM code data reading unit (ROM code data reading unit), 42 ROM code conversion parameter reading unit (ROM code conversion parameter reading unit), 44 data control unit (display control unit), 46 ROM process layout pattern data conversion unit (ROM) A process layout pattern data conversion unit), 47 a check layout pattern data creation unit (check layout pattern data creation unit);

Claims (2)

[Claims] 1. ROM code data reading means for reading ROM code data; ROM code conversion parameter reading means for reading ROM code conversion parameters for converting the ROM code data into a ROM process layout pattern; RO read by means
ROM process layout pattern data conversion means for converting M code data into a ROM process layout pattern in accordance with the ROM code conversion parameter read by the ROM code conversion parameter reading means; and all bits of the ROM process based on the ROM code conversion parameter. Layout pattern is “0” or “1”
Checking layout pattern data creating means for creating checking layout pattern data indicating the ROM rectangle and the address value of the ROM rectangle at the time of: ROM process layout pattern converted by the ROM process layout pattern data converting means; A layout pattern verification apparatus comprising: display control means for superimposing the layout pattern data for inspection created by the layout pattern data creating means for overlay on the display. 2. The layout pattern verification apparatus according to claim 1, wherein the display control means displays the ROM process layout pattern on the display so as to be distinguishable from the inspection layout pattern data.