TWI384565B - 半導體封裝方法 - Google Patents
半導體封裝方法 Download PDFInfo
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- TWI384565B TWI384565B TW097132006A TW97132006A TWI384565B TW I384565 B TWI384565 B TW I384565B TW 097132006 A TW097132006 A TW 097132006A TW 97132006 A TW97132006 A TW 97132006A TW I384565 B TWI384565 B TW I384565B
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Description
本發明係關於一種半導體封裝方法,且更特定言之,係關於一種封裝後無需熱硬化之半導體封裝方法,其中使用一滿足預定條件之晶粒黏合劑,且膠態(B-階段)固化製程後該晶粒黏合劑之固化度作為一控制要素,因此封裝後不再需要一獨立之熱硬化製程,因此製程效率得以提高。
晶粒膏(die paste)作為粘合劑在堆疊晶片、或黏著一晶片至諸如印刷電路板(PCB)或一半導體裝置封裝製程中之一引線架之類的一支撐元件中具有廣泛應用。
在特定類型之半導體封裝中,一半導體晶粒或晶片藉由粘合劑機械連接至一基板,且在該半導體晶粒或晶片與該基板間形成電連接。該基板被連接至另一電器裝置或一外部電源。可藉由一係列步驟製造該半導體封裝。另一選擇為,藉由一粘合劑將一半導體晶粒或晶片機械連接至一基板,且可保存預定時段。
若已藉由一係列步驟製造一半導體封裝,一粘合劑施加至一基板上,一半導體晶片黏著至該粘合劑,且該粘合劑藉由加熱固化,或藉由加熱與施壓固化。一無溶劑液體、或膏狀粘合劑、或固體狀粘合劑可能適合。該液態或膏狀粘合劑藉由加熱固化與硬化。同時,一粘合劑施加至一基板上時,停止半導體封裝製程,且往後延遲組裝製程,該粘合劑應結實牢固以完好保存半導體。固體狀粘合劑具有凝膠收縮程度最小或較小之特點,且能精確控制介面厚度與晶粒傾斜度,所謂介面即該半導體晶片與該粘合劑間之接觸面。
在某些半導體封裝申請案中,由於製程之故,一膏狀粘合劑比一粘結膜效果更佳。然而,該膏狀粘合劑需要控制介面與圓角。在此情形下,可使用如吾人所知之可膠態(B-stageable)粘合劑之
粘合劑。若粘合劑材料為固體,則在一溶劑裏分散或溶解該固體使其成為膏狀,且施加該膏至一基板上。隨後加熱該粘合劑,以蒸發該溶劑,因此一未固化之固態粘合劑留在該基板上。若粘合劑材料為液體或膏狀,施加該粘合劑至一基板上,加熱,且使其部分固化成固態。
經由網版印刷以一預定式樣施加如此一晶粒黏合劑至一元件上,經歷膠態(B-階段)固化製程,於常溫下擱置一天或一天以上,且在晶粒黏著之前經歷一預乾燥製程以除去任何殘留之水分。該預乾燥製程能防止隨後之高溫製程中由於該晶粒黏合劑中殘留之水分而導致該晶粒黏合劑出現空隙,因此其在傳統半導體封裝方法中必不可少。晶粒黏著製程完成後,實施一固化製程以改善該晶粒黏合劑之耐熱性與可靠性。最後,完成引線接合製程後,用一環氧樹脂塑封材(EMC)實施封裝製程,用以保護該黏著之晶片,且絕對有必要實施一熱硬化製程,以改善該環氧樹脂塑封材之耐熱性與黏著力。
如上所述,從施用該晶粒黏合劑至封裝(用一封裝材料保護),該傳統半導體封裝方法需要幾個加熱製程。這不利於提高製程效率且不經濟。相關行業已嘗試簡化製程,本發明即係在此技術背景下應運而生。
本發明之一目標係提供一種半導體封裝方法,其消除傳統半導體封裝方法中施加晶粒黏合劑後之預乾燥製程及封裝後之熱硬化製程,確保產品之穩定性、可靠性、耐熱性及黏著性,且實現一簡單製程。
根據本發明,該半導體封裝方法包括以下之步驟S1~S5。首先,經由網版印刷施加一晶粒黏合劑至一元件之上表面(步驟S1);膠態(B-階段)固化具有該晶粒黏合劑之元件(步驟S2);黏著一晶粒至該膠態(B-階段)固化後之晶粒黏合劑上(步驟S3);在該晶粒與該元件之間實施一引線接合製程(步驟S4);最後,封
裝該產物之外側(步驟S5)。此時,實施步驟S2之該膠態(B-階段)固化製程後,以具有一固化度的晶粒黏合劑顯示其熱容量降低80%至100%。實施步驟S3,使得黏著該晶粒後常溫下該晶粒黏合劑保持10 kg f/cm2或更高之黏合強度。
較佳地,若步驟S2之後在溫度為85℃、濕度為85%之條件下擱置該晶粒黏合劑1天或1天以上,則該晶粒黏合劑之吸水率為0.5%或更低。
較佳地,實施步驟S3之該晶粒黏著製程,使得該晶粒與該晶粒黏合劑之黏著面積為所施加之晶粒黏合劑全部面積的50~100%。較佳地,該晶粒黏合劑之玻璃轉換溫度為50℃至100℃。
下文將參照附圖描述本發明之若干較佳具體實施例。描述之前應瞭解該說明書及所附申請專利範圍中所用之術語不應理解為限於一般意義及字典意義,而應根據該發明者對術語最為合適之定義之原則,基於與本發明之技術方面一致之意義與概念而予以解釋。因此,此處提議之描述僅係為說明之目的之一較佳實例,無限定本發明範圍之意圖,因此應瞭解在不偏離本發明之精神與範圍之情況下其可具有另外之等同與更改。
為實現上述目標,一半導體封裝方法包括圖1所示之步驟S1~S5。
圖1為圖示說明根據本發明之一半導體封裝方法之流程圖。
(S1)網版印刷步驟
在一元件上實施一網版印刷製程,舉例言之,一印刷電路板(PCB)基板或一引線架,施加一晶粒黏合劑至該元件之上表面。
(S2)膠態(B-階段)固化步驟
在該具有晶粒黏合劑之元件上實施膠態(B-階段)固化製程。該膠態(B-階段)固化製程可藉由單獨使用、順序組合使用或同時使用加熱或紫外線輻射(UV)實施。該膠態(B-階段)固化製程後,以熱容計該晶粒黏合劑之固化度顯示降低80%至100%。該
固化度可藉由一微差掃描卡計儀測量。此時,較佳之分析條件係在溫度增加速度固定為10℃/min下,作為控制條件測量該晶粒黏合劑之固化度時,研究熱容之降低。
較佳地,若步驟S2之後在溫度為85℃、濕度為85%之條件下擱置該晶粒黏合劑1天或1天以上,則該晶粒黏合劑之吸水率為0.5%或更低。若該晶粒黏合劑滿足上述條件,則根據本發明之該半導體封裝方法不需要傳統半導體封裝方法中必不可少之預製程條件,但在此說明中,該晶粒黏合劑之性能並未受到影響。
(S3)晶粒黏著步驟
黏著一晶粒至該膠態(B-階段)固化後之晶粒黏合劑上。在該步驟S3中,晶粒黏著後,常溫下該晶粒黏合劑之附著強度保持為10 kg f/cm2或更高。實施該晶粒黏著製程,使得該晶粒與該晶粒黏合劑之黏著面積為所施加之晶粒黏合劑全部面積之50~100%。此時該晶粒黏合劑之玻璃轉換溫度(Tg)為50℃至100℃。若該晶粒黏合劑之玻璃轉換溫度條件得以滿足,則根據本發明之該半導體封裝方法不需要傳統半導體封裝方法中必不可少之晶粒黏合劑熱硬化製程。
(S4)引線接合步驟
該被黏著之晶粒與該元件彼此引線接合。
(S5)封裝步驟
封裝該被引線接合之產物之外側。為了封裝,通常應用使用一環氧樹脂塑封材(EMC)之封裝製程。若該晶粒黏合劑所需之上述製程條件與性質條件得以滿足,則根據本發明之該半導體封裝方法不需要用一單獨之熱硬化製程以改善封裝材料與該晶粒黏合劑之耐熱性,但能滿足所要求之性質條件。
在上文中,已參照該等附圖詳細描述本發明之若干較佳具體實施例。然而,應瞭解該詳細描述與該等特定實例係顯示本發明之較佳具體實施例,其僅係以說明之方式給出,因此根據此詳細說明,對於熟悉此項技藝之人士在本發明之精神與範圍內進行各
種變更與修改係顯而易見的。
本發明在施用一晶粒黏合劑之後不需要一預乾燥製程、且在封裝後不需要一熱硬化製程,而該預乾燥製程與該熱硬化製程在傳統半導體封裝方法中必不可少,但本發明能維持該晶粒黏合劑之性能,藉此提供一能保持一合成半導體產品可靠性之簡單製程。
(S1)‧‧‧網版印刷
(S2)‧‧‧膠態(B-階段)固化
(S3)‧‧‧晶粒黏著
(S4)‧‧‧引線接合
(S5)‧‧‧封裝
以上結合附圖之詳細說明將更為充分地描述本發明,然而,此處提出之描述僅為一以說明目的給出之較佳實例,並無限定本發明範圍之意圖。
圖1為一圖示說明根據本發明之一半導體封裝方法之流程圖。
(S1)‧‧‧網版印刷
(S2)‧‧‧膠態(B-階段)固化
(S3)‧‧‧晶粒黏著
(S4)‧‧‧引線接合
(S5)‧‧‧封裝
Claims (4)
- 一種半導體封裝方法,其包括:(S1)經由網版印刷施加一晶粒黏合劑至一元件之一上表面;(S2)膠態(B-階段)固化具有該晶粒黏合劑之元件;(S3)黏著一晶粒至該膠態(B-階段)固化後之晶粒黏合劑上;(S4)引線接合該晶粒至該元件上;及(S5)封裝該產物之外側,其中實施步驟S2之該膠態(B-階段)固化製程後,若以熱容計該晶粒黏合劑之固化度顯示降低80%至100%,且其中實施步驟S3,使得黏著該晶粒後常溫下該晶粒黏合劑保持10 kg f/cm2或更高之黏合強度。
- 如申請專利範圍第1項所述之半導體封裝方法,其中若步驟S2之後在溫度為85℃、濕度為85%之條件下擱置該晶粒黏合劑1天或1天以上,則該晶粒黏合劑之吸水率為0.5%或更低。
- 如申請專利範圍第1或2項所述之半導體封裝方法,其中實施步驟S3之該晶粒黏著製程,使得該晶粒與該晶粒黏合劑之黏著面積為所施加之晶粒黏合劑全部面積之50%~100%。
- 如申請專利範圍第1或2項所述之半導體封裝方法,其中該晶粒黏合劑之玻璃轉換溫度(Tg)為50℃至100℃。
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US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US6121553A (en) * | 1997-03-03 | 2000-09-19 | Hitachi Chemical Company, Ltd. | Circuit boards using heat resistant resin for adhesive layers |
US6265782B1 (en) * | 1996-10-08 | 2001-07-24 | Hitachi Chemical Co., Ltd. | Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film |
US20020050585A1 (en) * | 2000-08-31 | 2002-05-02 | Tobita Masayuki | Heat conductive adhesive film and manufacturing method thereof and electronic component |
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US5208188A (en) * | 1989-10-02 | 1993-05-04 | Advanced Micro Devices, Inc. | Process for making a multilayer lead frame assembly for an integrated circuit structure and multilayer integrated circuit die package formed by such process |
US6265782B1 (en) * | 1996-10-08 | 2001-07-24 | Hitachi Chemical Co., Ltd. | Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film |
US6621170B2 (en) * | 1996-10-08 | 2003-09-16 | Hitachi Chemical Company, Ltd. | Semiconductor device, substrate for mounting semiconductor chip, processes for their production, adhesive, and double-sided adhesive film |
US6121553A (en) * | 1997-03-03 | 2000-09-19 | Hitachi Chemical Company, Ltd. | Circuit boards using heat resistant resin for adhesive layers |
US20020050585A1 (en) * | 2000-08-31 | 2002-05-02 | Tobita Masayuki | Heat conductive adhesive film and manufacturing method thereof and electronic component |
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KR20090020382A (ko) | 2009-02-26 |
TW200910476A (en) | 2009-03-01 |
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