TWI382518B - 具有擴展的電壓範圍的功率器件的自保護結構及方法 - Google Patents

具有擴展的電壓範圍的功率器件的自保護結構及方法 Download PDF

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Publication number
TWI382518B
TWI382518B TW098116523A TW98116523A TWI382518B TW I382518 B TWI382518 B TW I382518B TW 098116523 A TW098116523 A TW 098116523A TW 98116523 A TW98116523 A TW 98116523A TW I382518 B TWI382518 B TW I382518B
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Taiwan
Prior art keywords
power device
semiconductor power
overcurrent protection
source
protection layer
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TW098116523A
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English (en)
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TW200950053A (en
Inventor
Francois Hebert
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Alpha & Omega Semiconductor
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Priority claimed from US12/156,305 external-priority patent/US8441109B2/en
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW200950053A publication Critical patent/TW200950053A/zh
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Publication of TWI382518B publication Critical patent/TWI382518B/zh

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Description

具有擴展的電壓範圍的功率器件的自保護結構及方法
本發明一般涉及一種用於保護器件的結構及方法。更特別地，本發明涉及一種通過利用一具有正向溫度係數的導電材料來保護運行於高壓下的有源器件免受由短路引起的過電流損害的優化電路結構及方法。
在高功率環境中，功率器件經常會在“短路”環境中損壞，並且設置有該功率器件的系統中的其他元件也會因此受損。所以，最好功率器件可以在一個開路狀態中損壞，更好的是可以完全避免器件損壞。防止器件受損可以通過整合一個作為器件一部分的或器件外的保護電路來實現。在半導體器件中一種特殊的保護是在接合襯墊前的圖案化內連接中設置一可熔連接，例如第1A圖所示的金屬保險絲或多晶矽保險絲。然而，如第1B圖所示，這樣的結構在超高電流應用中存在一限制，即，其需要多個保險絲和襯墊，由此造成電路板尺寸的加大，從而在製造和實際應用中對成本造成不利影響。另一個伴隨多個保險絲和襯墊而產生的缺點是萬一併不是所有的保險絲在過流環境中都熔斷，則保險絲未熔斷的器件有源區域就會受損。另外，例如金屬保險絲，多晶矽保險絲或其他的“損壞-開路”保護電路這樣的附加保護電路通常對器件或系統的性能會產生負面影響。保險絲保護還有一個缺點，就是這樣的保護是不可以重置的，一旦保險絲斷開，即使過流環境消除了，但保險絲連接依然是斷開的。
為了克服這些限制，應用正溫度係數(positive temperature coefficient，PTC)材料來實現可重置的過電流保護器件。已知的多種例如聚合物PTC(PPTC)這樣的PTC材料，在市場上被商業應用為“多晶矽保險絲(Polyfuse)”、“多晶矽開關(Polyswitch)”和“多開關(Multiswitch)”。這些產品的形態為嵌入碳粒的一片塑膠。當塑膠溫度低時，所有碳粒彼此連接，形成一貫穿器件的導電路徑。當塑膠溫度升高時，其產生擴展，促使碳粒分開，並導致器件電阻的迅速增加。例如BiTiO3熱敏電阻，該器件具有高非線性電阻/溫度反應並被用作開關，不用於成比例的溫度測量。PTC應用由美國專利4,238,812和多種作為商業產品的PTC材料所提供的資料頁所公開。PTC保護的效力顯示為，當溫度升高時，電阻升高五個數量級。
儘管正溫度係數(PTC)材料在電子器件過電流保護中的應用已為公眾所知，但在PTC材料實際應用中仍然存在技術限制和難點。如第1C圖所示，PTC保護電路通常通過將具有隨溫度增加電阻的PTC材料的保護器件連接到負載形成。然而，為了能形成保護，通常要求自加熱用來升高溫度，這就要求器件具有I2R降(drop)，並具有防止熱量下降的特殊裝置(mounting)，由此會降低器件保護的效力。與此同時，較大的電阻可以引起更多的自加熱以達到更高的保護。然而，這對功率系統的性能有負面影響。也可選擇，通過增加更多的電路元件，以外部加熱來加熱PTC材料，但增加的電路元件會造成電流限制保護佔用較大的體積。
另一個在應用PTC材料的保護器件中會遇到的困難存在于 運行于高電壓的器件中。出於減少功率消耗和增加運行效率的緣故，通常需要減少保護電路的電阻。然而，當保護電路的電阻減少，保護的電壓等級也趨於降低。在某些應用中，器件需要運行于高電壓等級下，所應用的具有正溫度係數(PTC)材料的保護電路的電壓等級的減少會造成主要的缺點與限制。另外，當PTC保護電路關閉，其載入在所施加的(漏-源)電壓上。因此，PTC器件的電壓等級需要等於或超過所施加的電壓。在更高壓的應用中，要求PTC器件具有相應的高電壓等級，這就使得即便在普通運行環境中也增加了PTC器件的電阻。
特別的，申請日為2007年1月25日的美國專利申請11/657,862公開了一種新的器件結構，該申請中公開的內容被結合於本申請中作為參考。該11/657,862的申請所公開的器件結構具有一與有源器件漏極串聯的PTC保護層。然而該器件結構具有一個缺點，即PTC結構的電壓等級必須等於或大於所施加的電壓，由此限制了這類保護電路的應用範圍。
因此，在電路設計及器件製造領域中仍然存在提供一種新的優化的結構和製造方法以解決上述困難的要求。特別的，存在提供新的優化的PTC保護的實現結構以克服上述限制和困難的需要。
因此，本發明的一個方面是提供一種新的優化的可重置的PTC保護結構，其可工作於任何增強模式器件和任何電壓等級的情況下，以此，上述的困難和限制可以得到解決。
本發明的一個方面是通過在有源器件的源極連接處應用 PTC(positive temperature coefficient)保險絲保護層，使得在這個新結構中PTC結構被系統或外部電路固有地保護。當過電流和高溫情況產生時，PTC保險絲對FET柵極控制電壓施加一回饋電壓，從而使電晶體自動關斷。
本發明的一個方面是PTC保險絲保護層堆疊於FET上，以此將保險絲應用於FET的源極連接。
本發明的一個方面是在源極器件的源極連接處應用PTC保險絲保護層，其中，所實現的標準頂部源極垂直增強模式FET具有設置於半導體襯底底部的漏極。PTC結構形成於FET的頂部，並連接到源極。在這個新結構中，由於PTC保險絲對FET柵極控制電壓施加一回饋電壓使電晶體自動關斷，從而PTC結構被系統或外部電路固有地保護。
本發明的一個方面是在源極器件的源極連接處應用PTC保險絲，其中，所實現的底部源極垂直增強模式FET具有設置於半導體襯底底部的源極。PTC結構形成於FET的底部並連接到源極。同樣的，在這個新結構中，由於PTC保險絲對FET柵極控制電壓施加一回饋電壓使電晶體自動關斷，從而PTC結構被系統或外部電路固有地保護。
本發明的一個方面是在源極器件的源極連接處應用PTC保險絲，電子器件中的升溫被自動加諸於PTC材料上，另外，所實現的PTC保護具有最小的寄生電阻增加和擴展的電壓範圍，以此，上述的在目前的PTC保護中所遇到的困難和限制將被克服。
本發明的一個方面是在源極器件的源極連接處應用PTC保 險絲，其在電子器件中與發熱元件或區域具有優化的熱耦合，同時，所提供的這樣的耦合具有最小的耦合或寄生電阻的增加。
本發明的一個方面是在源極器件的源極連接處應用PTC保險絲，以提供一新的優化的PTC保護結構，該PTC保護結構可以方便地通過標準封裝技術實現，由此，對於製造成本的不利影響可被避免。
本發明的一個方面是在源極器件的源極連接處應用PTC保險絲，以提供一新的優化的PTC保護結構，該PTC保護結構可以通過不增加封裝尺寸實現，由此，減少了對製造成本產生不利影響的可能。
本發明的一個方面是在活動器件的源極連接處應用PTC保險絲，以提供一新的優化的PTC保護結構，該PTC保護保險絲層由例如陶瓷類(ceramic-based)PTC材料或聚合物類(polymeric-based)PTC(PPTC)材料這樣的PTC材料構成。
大致地，本發明的一個優選實施例中公開了一種垂直半導體功率器件，其具有由半導體襯底的頂部表面和底部表面構成的一垂直電流路徑以導通貫穿襯底的電流。該半導體功率器件還包括一過電流保護層，該過電流保護層由具有正溫度係數(PTC)電阻的材料構成，並且該過電流保護層構成為垂直電流路徑的一部分，其連接到源極，並對垂直半導體功率器件的柵極提供一回饋電壓，以限制電流的通過，從而在任何電壓下保護半導體功率器件。在一典型實施例中，過電流保護層由可重置的電流限制材料構成。在另一典型實施例中，過電流保護層貼覆於底部表面。在另一典型實施例中，過電流保護層貼覆 於半導體功率器件的頂部表面，並具有連接源極的接合線。在另一典型實施例中，過電流保護層設置於組成半導體功率器件源極的半導體襯底底部表面和引線框架之間。
本發明還進一步公開了一種製造整合有過電流保護的電子器件的方法。該方法包括設置由電流限制材料構成的過電流保護層以連接電子器件源極的步驟。該方法還包括在半導體功率器件的頂部表面上設置一層正溫度係數材料以作為電流限制保護層的步驟，半導體功率器件的頂部表面作為半導體功能器件的源極。該方法還包括在半導體功率器件的底部表面上設置一層正溫度係數材料以作為電流限制保護層的步驟，半導體功率器件的底部表面作為半導體功能器件的源極。
本領域普通技術人員在結合多幅附圖閱讀了後續的對於本發明優選實施例的詳細敍述後，本發明的這些和其他的內容和優點將變得顯而易見。
第2圖是具有PTC保護的FET 100的簡要示意圖(其也可作為保險絲FET的參考)，其包括一由具有正溫度係數(PTC)的材料構成的電阻110，結構為一連接到源極的導電層，並提供一回饋電壓來控制柵-源電壓。當受保護的器件溫度上升時，PTC電阻110的電阻值也增大，一旦達到PTC限制(trip)溫度時，電阻會劇烈增加。在這個保護結構中，任何的源極到漏極的電流(Ids)增加都會在PTC結構110兩端間產生壓降Vptc，從而降低FET控制電壓Vgs。特別的，電壓所具有的函數關係可以表示為： Vgs=Vgs’+Vptc
Vgs’=Vgs-Vptc
當器件溫度高於PTC限制溫度時，PTC結構兩端間的壓降Vptc遠大於柵極至源極的電壓Vgs’，即Vptc>>Vgs’，並導致FET關閉或切斷。所選擇的限制溫度用以保護保險絲FET避免過電流的環境。因此，受保護的FET的電壓變化自動保護PTC結構，使其自身免受過電壓。另外，保險絲FET結構也可以應用於任何的漏極電壓，只需要符合僅有的要求，即PTC結構必須與受PTC結構保護的FET的柵-源電壓等級相匹配，即PTC結構的電壓等級需要與FET的柵-源電壓等級相同或更高。PTC結構的電壓等級獨立於漏極(漏-源)電壓，即與漏極(漏-源)電壓無關。甚至於在高電壓(高漏-源電壓)應用中，PTC結構可以具有一低電壓等級，而因此提供了在普通運行環境中保險絲FET所具有的低電阻。
第3A、3B和3C圖分別為實際應用的具有這樣的PTC保護結構的垂直DMOS的電路圖、側面剖視圖和俯視圖，其具有頂部源極和底部漏極結構。一FET器件100’安裝於印刷電路板(PCB)160上，並通過引線框架150的引腳連接到設置於PCB頂部的柵極連接150-G和源極連接150-S。一具有底部漏極140的垂直DMOS器件設置於引線框架150的頂部，並具有頂部源極金屬120。一PTC保護結構設置於源極金屬層120的頂部，其分別包括PTC層110’-PTC和頂部及底部電極層110’-e1、110’-e2。該PTC層110’-PTC可以包括一由陶瓷類(ceramic-based)PTC材料或聚合物類(polymeric-based)PTC (PPTC)材料或其他任何適合的PTC材料組成的PTC保護保險絲層。接合線125連接於頂部電極110’-e1和引線框架150-S之間。接合線125-G連接於柵極襯墊130和引線框架150-G之間。PTC結構貼覆設在FET的有源源極區域。PTC結構、DMOS、接合線和部分的引線框架被封裝入一模塑膠(molding compound)中，以形成一半導體封裝。
第4A、4B和4C圖分別為實際應用的具有這樣的PTC保護結構的垂直DMOS的電路圖、側面剖視圖和俯視圖，其具有底部源極和頂部漏極結構。一FET器件100”安裝於印刷電路板(PCB)160上，並通過引線框架150的引腳連接到設置於PCB頂部的柵極連接150-G和漏極連接150-D。一具有底部源極120’的垂直DMOS器件設置於PTC保護結構110’的頂部，PTC保護結構110’設置於引線框架150的頂部。PTC保護結構包括分別由頂部及底部電極層110’-e1和110’-e2作為襯墊的PTC層110’-PTC。接合線125-D連接形成在VDMOS器件頂部的頂部漏極連接金屬140’和引線框架150-D，該VDMOS器件具有底部源極120’。接合線125-G連接於柵極襯墊130和引線框架150-G之間。在這個FET器件中，PTC電極110’-e1直接連接於底部源極120’，並且PTC電極110’-e2直接連接於引線框架150。
第3A至4C圖所示的連接PTC結構至源極的基本結構可以被應用實施於任何電壓範圍的器件保護，而不受PTC最大電壓等級的限制，其如同在PTC至漏極連接保護結構中所遇到的限制。另外，保護結構可應用於任何增強模式的FET器件中， 包括低壓(LV)溝槽柵極VDMOS(垂直雙擴散金屬氧化物半導體)FET，平面VDMOS FET，E-模式HEMT(高電子遷移率電晶體，high electron mobility transistors),E-模式SiT(靜電感應電晶體，static induction transistor)和JFET(結柵場效應電晶體，junction gate FET)。另外，在所示的接合線封裝中，也可以使用電鍍接合來優化性能。
第5圖所示為一標準垂直DMOS(VDMOS)功率MOSFET晶片200的剖視圖。一VDMOS器件200安裝於印刷電路板(PCB)260上，並通過引線框架250的引腳連接到設置在PCB上面的柵極連接250-G和源極連接250-S。垂直DMOS器件200具有一設置於引線框架250之上的底部漏極240，以及一例如鋁源極接觸層的頂部源極金屬220。一由無電的鍍鎳金形成的氧化電阻層形成於鋁表面上，並最好貼覆於PTC保護結構210。通過標準背部金屬工藝形成位於MOSFET晶片上的漏極，該MOSFET晶片使用例如鈦鎳銀、或鈦金、或鉻金層的標準背部金屬層，以形成如底部電極240這樣的漏極。一PTC保護結構包括一PTC層210-PTC和頂部及底部電極層210-e1和210-e2。電極層210-e1和210-e2可以通過將鎳金分別按壓印刷在PTC層210-PTC的頂部的底部形成。接合線225連接頂部電極210-e1和引線框架的源極連接250-S。接合線225-G連接於柵極襯墊230和引線框架的柵極連接250-G之間。PTC結構貼覆設在FET的有源源極區域上。在封裝過程中，首先應用導電環氧樹脂將MOSFET器件貼覆設於引線框架250。然後，在源極金屬層220的頂部上應用導電環氧樹脂層，將PTC結構210 貼覆設於源極金屬層220的頂部表面。利用接合線工藝將連接PTC結構210的源極接合線225-S結合至引線框架上的源極連接250-S，以及將連接柵極襯墊230的柵極接合線225-G接合至引線框架上的柵極連接250-G。通過將器件封裝入一模塑膠270中用以保護VDMOS晶片，以完成封裝工藝。
第6圖是另一個與第5圖所示的器件類似的標準VDMOS封裝200’，區別在於在封裝工藝中，首先應用一焊膏取代導電環氧樹脂來將MOSFET器件貼覆設於引線框架250上。然後，在源極金屬層220的頂部上應用焊膏，將PTC結構210貼覆設於源極金屬層220的頂部表面。利用接合線工藝，將連接PTC結構210的源極接合線225-S接合至引線框架上的源極連接250-S，以及將連接柵極襯墊230的柵極接合線225-G接合至引線框架上的柵極連接250-G。通過將器件封裝入一模塑膠270中用以保護VDMOS晶片，以完成封裝工藝。第7圖是另一個與第6圖所示的器件類似的標準VDMOS封裝200”，區別在於在完成接合線工藝之後，但封裝步驟進行之前，形成一覆蓋MOSFET器件和PTC結構210，以及覆蓋部分的接合線225和部分的引線框架250的塑膠團頂部(glob top)225。該塑膠團頂部225允許形成於晶片頂部表面的PTC結構210產生熱膨脹。
第8圖所示為一底部源極LDMOS晶片300的剖視圖。底部源極LDMOS器件300由一印刷電路板(PCB)360支撐，並設置於引線框架350之上，且通過設置於PCB頂部上的柵極連接350-G和漏極連接350-D連接到引線框架350。一具有底部源極320的垂直LDMOS器件設置於位於引線框架350頂部上 的PTC保護結構310之上。一PTC保護結構包括一PTC層310-PTC和頂部及底部電極層310-e1和310-e2，該頂部和底部電極層310-e1和310-e2可以分別通過將鎳金按壓印刷於PTC層310-PTC的頂部的底部形成。接合線325-D將形成於底部源極LDMOS器件頂部上的頂部漏極接觸金屬340連接到引線框架上的漏極連接350-D。接合線325-G連接於柵極襯墊330和引線框架的柵極連接350-G之間。在這個底部源極LDMOS器件中，PTC保護結構310直接連接於底部源極320。在封裝過程中，首先應用一焊膏將PTC保護結構310貼覆設於引線框架350上。然後，在PTC保護結構310的頂部上應用焊膏，將MOSFET器件的源極320貼覆設於PTC保護結構310之上。利用接合線工藝，將連接漏極340的漏極接合線325-D接合至引線框架上的漏極連接350-D，以及將連接柵極襯墊330的柵極接合線325-G接合至引線框架上的柵極連接350-G。通過將器件封裝入一封裝結構370中用以保護底部源極LDMOS晶片，從而完成封裝工藝。如第8圖和第9圖所示器件的封裝工藝還可以進一步改進，即在完成接合線工藝之後，最終封裝步驟之前，加入形成一塑膠團頂部的步驟，從而，使PTC保護結構310具有更好的熱膨脹柔韌性。
第9圖所示為一底部源極LDMOS晶片300’的剖視圖。底部源極LDMOS器件300’由一印刷電路板(PCB)360支撐，並設置於引線框架350的頂部，且通過設置於PCB頂部上的柵極連接350-G和漏極連接350-D連接到引線框架350。一具有底部源極320的垂直LDMOS器件設置於位於引線框架350頂 部上的PTC保護結構310之上。一PTC保護結構包括一PTC層310-PTC和頂部及底部電極層310-e1和310-e2，該頂部和底部電極層310-e1和310-e2分別可以通過將鎳金按壓印刷於PTC層310-PTC的頂部的底部形成。接合線325-D將形成於具有底部源極320的底部源極LDMOS器件頂部的頂部漏極連接金屬340連接到引線框架的漏極連接350-D。接合線325-G連接於柵極襯墊330和引線框架的柵極連接350-G之間。在這個底部源極LDMOS器件中，PTC保護結構310直接連接底部源極320。在封裝過程中，首先應用一導電環氧樹脂將PTC保護結構310貼覆設於引線框架350上。然後，在PTC保護結構310的頂部上應用導電環氧樹脂層，將MOSFET器件的源極320貼覆設於PTC保護結構310之上。利用接合線工藝，將連接漏極340的漏極接合線325-D接合至引線框架的漏極連接350-D，以及將連接柵極襯墊330的柵極接合線325-G接合至引線框架的柵極連接350-G。通過將器件封裝入一封裝結構370中用以保護底部源極LDMOS晶片，從而完成封裝工藝。如第8圖和第9圖所示器件的封裝工藝，還可以進一步改進，即在完成接合線工藝之後，最終封裝步驟之前，加入形成一塑膠團頂部的步驟，從而，使PTC保護結構310具有更好的熱膨脹柔韌性。
第10圖所示為一標準垂直DMOS(VDMOS)功率MOSFET晶片400的剖視圖。VDMOS器件400由一印刷電路板(PCB)460支撐，並通過設置於PCB頂部上的柵極連接450-G和源極連接450-S連接到引線框架450。垂直DMOS器件400具有設置於引線框架450頂部上的底部漏極440，和例如為鋁源極接 觸層的頂部源極金屬420。通過無電的鍍鎳金可以在暴露的鋁層表面形成的一氧化電阻層。通過標準背部金屬工藝形成位於MOSFET晶片上的漏極，該MOSFET晶片使用例如鈦鎳銀、或鈦金、或鉻金層以形成如底部電極440這樣的漏極。一PTC保護結構包括一PTC層410-PTC和頂部及底部電極層410-e1和410-e2，該頂部和底部電極層410-e1和410-e2分別通過將鎳金按壓印刷於PTC層410-PTC的頂部的底部形成。頂部金屬板425-S-P將頂部電極410-e1連接至引線框架的源極連接450-S。接合線425-G連接於柵極襯墊430和引線框架的柵極連接450-G之間。PTC保護結構貼覆設於FET的有源源極區域上。在封裝過程中，首先應用一焊膏將MOSFET器件貼覆設於引線框架450上。然後，在源極金屬層420的頂部上應用焊膏，將PTC保護結構410貼覆設於源極金屬層420的頂部表面。
也可以選擇使用別的具有類似功能的材料來代替焊膏，例如導電環氧樹脂。使用一頂部金屬板接合工藝，將連接PTC保護結構410的源極頂部金屬板425-S-P接合到引線框架的源極連接450-S，並且，用柵極接合線425-G連接柵極襯墊430和引線框架的柵極連接450-G。通過應用升溫使焊料回流，並將器件封裝入一模塑膠470中，來保護VDMOS晶片，然後切割引線框架，並焊接或鋸斷晶片至VDMOS MOSFET晶片中，以完成封裝工藝。第11圖所示為另一個與第10圖所示的半導體功率器件400相似的標準VDMOS MOSFET功率器件400’。僅有的區別是第10圖中所示的柵極接合線425-G現在被柵極頂部金屬板425-G-P取代，其連接柵極襯墊430和引線框架的柵極 連接450-G。
第12圖所示為一底部源極LDMOS晶片500的剖視圖。底部源極LDMOS器件500由位於引線框架550下的印刷電路板(PCB)560支撐。引線框架550具有設置於PCB 560頂部的柵極連接550-G和漏極連接550-D。具有底部源極520的垂直LDMOS器件設置於PTC保護結構510的頂部上，該PTC保護結構510設置於引線框架550的頂部上。一PTC保護結構包括一PTC層510-PTC和頂部及底部電極層510-e1和5410-e2，該頂部和底部電極層510-e1和510-e2分別通過將鎳金按壓印刷於PTC層510-PTC的頂部的底部形成。頂部接合金屬板525-D-P將頂部漏極接觸金屬540連接至引線框架的漏極連接550-D，該頂部漏極接觸金屬540形成於具有底部源極520的底部源極LDMOS器件的頂部。柵極接合金屬板325-G將柵極襯墊530連接至引線框架的柵極連接550-G。在這個底部源極LDMOS器件中，PTC保護結構510直接連接至底部源極520。在封裝過程中，首先應用焊膏將PTC保護結構510貼覆設於引線框架550上。然後，在PTC保護結構510的頂部上應用焊膏，用以將MOSFET器件的源極520貼覆設於PTC保護結構510上。也可以選擇使用類似的合適的材料來代替焊膏，例如導電環氧樹脂。使用金屬板接合工藝，將連接到漏極540的漏極頂部金屬板525-D-P接合至引線框架的漏極連接550-D，並且，用柵極接合金屬板525-G-P連接柵極襯墊530和引線框架的柵極連接550-G。通過應用升溫使焊料回流，並將器件封裝入一模塑膠570中，用以保護底部漏極LDMOS晶片，以完成封裝工藝。
上述的第4A圖至第12圖中所示的PTC層，例如PTC層110’-PTC、210-PTC、310-PTC、410-PTC和510-PTC，可以包括一由陶瓷類PTC材料或聚合物類PTC(PPTC)材料或其他任何適合的PTC材料組成的PTC保險絲保護層。這些PTC材料包括如美國專利4,238,812中所公開的摻雜鈦酸鋇陶瓷(doped ceramic of barium titanate)，儘管該材料由於在高溫下會變得易碎而在應用中受到限制。PTC材料還可以包括導電聚合物，如美國專利4,238,812中所公開的，其具有分佈於大部分聚合物層中的微顆粒導電填充物，並由羅氏(Raychem)和其他公司成功地投入商業應用，用於製造厚度大約為0.5埃的PTC保險絲層，並以PoluFuseTM作為產品商標。
PTC器件的頂部和底部電極可以分別由任何含金的金屬、銅、合金、或複合層結構組成，該複合層結構例如為金，鎳金等等。
儘管本發明的內容已經通過上述現有優選實施方式作了詳細介紹，但應當認識到上述的公開不應被認為是對本發明的限制。在本領域技術人員閱讀了上述內容後，對於本發明的多種修改和替代都將是顯而易見的。所以，後續的權利要求書應當被視作覆蓋了所有落入本發明真正精神和範圍內的所有修改和替代。
100’‧‧‧FET器件
FET‧‧‧保險絲
110’-e1、110’-e2、210-e1、210-e2、310-e1、310-e2、410-e1、410-e2、510-e1、510-e2‧‧‧電極層
110，-PTC、210-PTC、310-PTC、410-PTC、510-PTC‧‧‧PTC層
110’、310‧‧‧保護結構
PTC、positive temperature coefficient‧‧‧應用正溫度係數
125-G、125-D‧‧‧接合線
130、230、330、430、530‧‧‧柵極襯墊
140、240、440‧‧‧底部漏極
150、150-S、150-G、150-D、250、 250-G、250-S、350、350-D、350-G、450、450G、450S、550、550D、550G‧‧‧引線框架
160、PCB、260、360、460、560‧‧‧印刷電路板
110‧‧‧電阻
200、400‧‧‧MOSFET晶片
210、410、510‧‧‧保護結構
120、220、420、520‧‧‧源極金屬層
225-S‧‧‧源極接合線
225-G、325-G‧‧‧柵極接合線
270‧‧‧模塑膠
300、500‧‧‧底部源極LDMOS晶片
320‧‧‧源極
325-D‧‧‧漏極接合線
340、540‧‧‧金屬
425-S-P、525-D-P‧‧‧頂部金屬板
第1A至1C圖所示為用於保護器件不受短路損害的過電流保護的不同實現結構。
第2圖所示為PTC保護電路連接源極的簡要示意圖。
第3A、3B和3C圖分別為具有本發明的PTC保護的標準垂直DMOS(雙擴散金屬氧化物半導體)功率MOSFET器件的電路圖、側面剖視圖和俯視圖。
第4A、4B和4C圖分別為具有本發明的PTC保護的底部源極LDMOS功率MOSFET器件的電路圖、側面剖視圖和俯視圖。
第5圖至第12圖所示為本發明中的由PTC結構保護的半導體功率器件的不同實施例的側面剖視圖。
100’‧‧‧FET器件
FET‧‧‧保險絲
110’-e1、110’-e2‧‧‧電極層
110’-PTC‧‧‧PTC層
110’‧‧‧保護結構
PTC、positive temperature coefficient‧‧‧應用正溫度係數
120‧‧‧頂部源極金屬
125-G‧‧‧接合線
130‧‧‧柵極襯墊
140‧‧‧底部漏極
150、150-S、150-G‧‧‧引線框架
160、PCB‧‧‧印刷電路板

Claims (30)

  1. 一種垂直半導體功率器件，包括：由半導體襯底的頂部表面和底部表面構成的一垂直電流路徑，以導通貫穿半導體襯底的電流；以及一由具有正溫度係數電阻的材料構成的過電流保護層，其作為所述的垂直電流路徑的一部分，並連接到所述的垂直半導體功率器件的源極，用以限制貫穿的電流，從而在任何的電壓下可以保護半導體功率器件，而不受所述的過電流保護層的電壓等級的限制。
  2. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的過電流保護層由可重置的電流限制材料組成。
  3. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，垂直半導體功率器件為一底部源極半導體功率器件，所述的過電流保護層直接貼覆設於底部源極上，並連接半導體功率器件的底部源極。
  4. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，垂直半導體功率器件具有一設置於半導體功率器件頂部表面的源極，所述的過電流保護層直接貼覆設於半導體功率器件的源極的頂部表面上。
  5. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的過電流保護層具有與半導體功率器件的柵源電壓等級相匹配的電壓等級。
  6. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的過電流保護層還包括由具有正溫度係數電阻 的材料組成的設置於PTC層的上面和下面的頂部電極層和底部電極層。
  7. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的過電流保護層還包括由具有正溫度係數電阻的材料組成的設置於PTC層的上面和下面的頂部電極層和底部電極層，其中所述的頂部和底部電極層由銅，或者由金、鎳金組成的複合層結構，或者包含金的金屬，或者合金構成。
  8. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，垂直半導體器件具有一底部電極層，該底部電極層由所述的半導體功率器件的底部表面的標準回蝕金屬構成。
  9. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：還包括金屬內連接，其連接所述的半導體功率器件的頂部表面的電極和引線框架的電極。
  10. 如申請專利範圍第9項所述的垂直半導體功率器件，其特徵在於：其中，所述的半導體功率器件是一底部源極MOSFET器件，其具有設置於底部表面的源極，其中所述的半導體功率器件設置於所述的過電流保護層上，通過所述的金屬內部連接將所述的MOSFET器件的頂部漏極連接到引線框架的漏極電極。
  11. 如申請專利範圍第9項所述的垂直半導體功率器件，其特徵在於：其中，所述的半導體功率器件是一底部漏極MOSFET器件，其具有設置於該MOSFET器件的頂部表面的源極，所述的MOSFET器件被所述的過電流保護層覆蓋，通過所述的金屬內部連接將所述的過電流保護層連接到引線框架的源極電極。
  12. 如申請專利範圍第9項所述的垂直半導體功率器件，其特徵 在於：其中，所述的半導體功率器件是一具有設置於器件頂部表面的柵極襯墊的MOSFET器件，通過所述的金屬內部連接，連接所述的柵極襯墊和引線框架上的柵極電極。
  13. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：還包括一覆蓋所述半導體功率器件的塑膠團頂部，其允許由其覆蓋下的過電流保護層產生熱膨脹。
  14. 如申請專利範圍第9項所述的垂直半導體功率器件，其特徵在於：其中，所述的金屬內部連接由導電金屬板或接合線構成。
  15. 如申請專利範圍第14項所述的垂直半導體功率器件，其特徵在於：其中，所述的半導體器件具有一設置於該半導體器件頂部表面上的柵極襯墊，並具有一柵極導電金屬板連接所述的柵極襯墊和引線框架上的柵極電極。
  16. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的半導體功率器件為一具有設置於頂部表面上的源極的垂直MOSFET器件，其包括一氧化電阻金屬層，其通過一貼覆介質配合，可貼覆到所述的過電流保護層上，以減少所述的頂部表面上的源極與過電流保護層之間的接觸電阻。
  17. 如申請專利範圍第16項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於頂部表面上的電極包括一由金構成的氧化電阻金屬層。
  18. 如申請專利範圍第16項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於頂部表面上的電極包括一氧化電阻金屬層，該氧化電阻金屬層由頂部為金的鎳，即鎳金合金構成。
  19. 如申請專利範圍第16項所述的垂直半導體功率器件，其特 徵在於：其中，所述的位於頂部表面上的電極通過由環氧樹脂構成的貼覆介質貼覆到所述的過電流保護層上。
  20. 如申請專利範圍第16項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於頂部表面上的電極通過由焊接劑構成的帖覆介質帖覆到所述的過電流保護層。
  21. 如申請專利範圍第1項所述的垂直半導體功率器件，其特徵在於：其中，所述的半導體功率器件為一具有設置於底部表面上的電極的垂直DMOS器件，其包括一氧化電阻金屬層，該氧化電阻金屬層通過一貼覆介質配合，可貼覆到所述的過電流保護層上，以減少所述的底部表面上的電極與過電流保護層之間的接觸電阻。
  22. 如申請專利範圍第21項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於底部表面上的電極包括一由金構成的氧化電阻金屬層。
  23. 如申請專利範圍第21項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於底部表面上的電極包括一氧化電阻金屬層，該氧化電阻金屬層由頂部為金的鎳，即鎳金合金構成。
  24. 如申請專利範圍第21項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於底部表面上的電極通過由環氧樹脂構成的貼覆介質貼覆到所述的過電流保護層上。
  25. 如申請專利範圍第21項所述的垂直半導體功率器件，其特徵在於：其中，所述的位於底部表面上的電極通過由焊接劑構成的貼覆介質貼覆到所述的過電流保護層上。
  26. 一種保護垂直半導體功率器件的方法，該器件具有半導體襯 底的一頂部表面和一底部表面，並構成一垂直電流路徑用以導通貫穿的電流，該方法包括：設置一由具有正溫度係數電阻的材料構成的過電流保護層，作為所述的垂直電流路徑的一部分，連接到所述的垂直半導體功率器件的源極，並對垂直半導體功率器件的柵極提供一回饋電壓，以限制電流的貫穿從而達到過電流保護，其不受限於所述的過電流保護層的電壓等級。
  27. 如申請專利範圍第26項所述的方法，其特徵在於：其中，所述的設置過電流保護層的步驟還包括：設置由可重置的電流限制材料組成的過電流保護層的步驟。
  28. 如申請專利範圍第27項所述的方法，其特徵在於：其中，所述的設置所述的過電流保護層的步驟還包括：貼覆所述的過電流保護層於底部源極半導體功率器件的底部表面上，以直接連接半導體功率器件的底部源極的步驟。
  29. 如申請專利範圍第27項所述的方法，其特徵在於：其中，所述的設置所述的過電流保護層的步驟還包括：貼覆所述的過電流保護層於底部漏極半導體功率器件的頂部表面上，以直接連接半導體功率器件的頂部源極的步驟。
  30. 如申請專利範圍第27項所述的方法，其特徵在於：其中，所述的設置所述的過電流保護層的步驟還包括：設置所述的過電流保護層具有與半導體功率器件的柵-源電壓等級相匹配的電壓等級的步驟。
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