CN101593776B - 具有扩展的电压范围的功率器件的自保护结构及方法 - Google Patents

具有扩展的电压范围的功率器件的自保护结构及方法 Download PDF

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CN101593776B
CN101593776B CN2009101411522A CN200910141152A CN101593776B CN 101593776 B CN101593776 B CN 101593776B CN 2009101411522 A CN2009101411522 A CN 2009101411522A CN 200910141152 A CN200910141152 A CN 200910141152A CN 101593776 B CN101593776 B CN 101593776B
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power device
semiconductor power
vertical semiconductor
current protection
over current
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CN101593776A (zh
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弗兰茨娃·赫尔伯特
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Chongqing Wanguo Semiconductor Technology Co ltd
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Alpha and Omega Semiconductor Inc
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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    • H01L2924/1304—Transistor
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract

一种垂直半导体功率器件，其包括由半导体衬底的顶部表面和底部表面构成的一垂直电流路径，以导通贯穿的电流。该半导体功率器件还包括一由具有正温度系数电阻的材料构成的过电流保护层，该过电流保护层作为垂直电流路径的一部分，并连接到所述的垂直半导体功率器件的源极，用以对垂直半导体功率器件的栅极提供一反馈电压，以限制电流的贯穿，从而在任何的电压下保护半导体功率器件。

Description

具有扩展的电压范围的功率器件的自保护结构及方法
技术领域
本发明一般涉及一种用于保护器件的结构及方法。更特别地，本发明涉及一种通过利用一具有正向温度系数的导电材料来保护运行于高压下的有源器件免受由短路引起的过电流损害的优化电路结构及方法。 
背景技术
在高功率环境中，功率器件经常会在“短路”环境中损坏，并且设置有该功率器件的系统中的其它元件也会因此受损。所以，最好功率器件可以在一个开路状态中损坏，更好的是可以完全避免器件损坏。防止器件受损可以通过整合一个作为器件一部分的或器件外的保护电路来实现。在半导体器件中一种特殊的保护是在接合衬垫前的图案化内连接中设置一可熔连接，例如图1A所示的金属保险丝或多晶硅保险丝。然而，如图1B所示，这样的结构在超高电流应用中存在一限制，即，其需要多个保险丝和衬垫，由此造成电路板尺寸的加大，从而在制造和实际应用中对成本造成不利影响。另一个伴随多个保险丝和衬垫而产生的缺点是万一并不是所有的保险丝在过流环境中都熔断，则保险丝未熔断的器件有源区域就会受损。另外，例如金属保险丝，多晶硅保险丝或其它的“损坏-开路”保护电路这样的附加保护电路通常对器件或系统的性能会产生负面影响。保险丝保护还有一个缺点，就是这样的保护是不可以重置的，一旦保险丝断开，即使过流环境消除了，但保险丝连接依然是断开的。 
为了克服这些限制，应用正温度系数(positive temperature coefficient，PTC)材料来实现可重置的过电流保护器件。已知的多种例如聚合物PTC(PPTC)这样的PTC材料，在市场上被商业应用为“多晶硅保险丝(Polyfuse)”、“多晶硅开关(Polyswitch)”和“多开关(Multiswitch)”。这些产品的形态为嵌入碳粒的一片塑料。当塑料温度低时，所有碳粒彼此连接，形成一贯穿器件的导电路径。当塑料温度升高时，其产生扩展，促使碳粒分 开，并导致器件电阻的迅速增加。例如BiTiO3热敏电阻，该器件具有高非线性电阻/温度反应并被用作开关，不用于成比例的温度测量。PTC应用由美国专利4,238,812和多种作为商业产品的PTC材料所提供的数据页所公开。PTC保护的效力显示为，当温度升高时，电阻升高五个数量级。 
尽管正温度系数(PTC)材料在电子器件过电流保护中的应用已为公众所知，但在PTC材料实际应用中仍然存在技术限制和难点。如图1C所示，PTC保护电路通常通过将具有随温度增加电阻的PTC材料的保护器件连接到负载形成。然而，为了能形成保护，通常要求自加热用来升高温度，这就要求器件具有I2R降(drop)，并具有防止热量下降的特殊装置(mounting)，由此会降低器件保护的效力。与此同时，较大的电阻可以引起更多的自加热以达到更高的保护。然而，这对功率系统的性能有负面影响。也可选择，通过增加更多的电路元件，以外部加热来加热PTC材料，但增加的电路元件会造成电流限制保护占用较大的体积。 
另一个在应用PTC材料的保护器件中会遇到的困难存在于运行于高电压的器件中。出于减少功率消耗和增加运行效率的缘故，通常需要减少保护电路的电阻。然而，当保护电路的电阻减少，保护的电压等级也趋于降低。在某些应用中，器件需要运行于高电压等级下，所应用的具有正温度系数(PTC)材料的保护电路的电压等级的减少会造成主要的缺点与限制。另外，当PTC保护电路关闭，其加载在所施加的(漏-源)电压上。因此，PTC器件的电压等级需要等于或超过所施加的电压。在更高压的应用中，要求PTC器件具有相应的高电压等级，这就使得即便在普通运行环境中也增加了PTC器件的电阻。 
特别的，申请日为2007年1月25日的美国专利申请11/657,862公开了一种新的器件结构，该申请中公开的内容被结合于本申请中作为参考。该11/657,862的申请所公开的器件结构具有一与有源器件漏极串联的PTC保护层。然而该器件结构具有一个缺点，即PTC结构的电压等级必须等于或大于所施加的电压，由此限制了这类保护电路的应用范围。 
因此，在电路设计及器件制造领域中仍然存在提供一种新的优化的结构和制造方法以解决上述困难的要求。特别的，存在提供新的优化的PTC保护的实现结构以克服上述限制和困难的需要。 
发明内容
因此，本发明的一个方面是提供一种新的优化的可重置的PTC保护结构，其可工作于任何增强模式器件和任何电压等级的情况下，以此，上述的困难和限制可以得到解决。 
本发明的一个方面是通过在有源器件的源极连接处应用PTC(positivetemperature coefficient)保险丝保护层，使得在这个新结构中PTC结构被系统或外部电路固有地保护。当过电流和高温情况产生时，PTC保险丝对FET栅极控制电压施加一反馈电压，从而使晶体管自动关断。 
本发明的一个方面是PTC保险丝保护层堆叠于FET上，以此将保险丝应用于FET的源极连接。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝保护层，其中，所实现的标准顶部源极垂直增强模式FET具有设置于半导体衬底底部的漏极。PTC结构形成于FET的顶部，并连接到源极。在这个新结构中，由于PTC保险丝对FET栅极控制电压施加一反馈电压使晶体管自动关断，从而PTC结构被系统或外部电路固有地保护。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝，其中，所实现的底部源极垂直增强模式FET具有设置于半导体衬底底部的源极。PTC结构形成于FET的底部并连接到源极。同样的，在这个新结构中，由于PTC保险丝对FET栅极控制电压施加一反馈电压使晶体管自动关断，从而PTC结构被系统或外部电路固有地保护。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝，电子器件中的升温被自动加诸于PTC材料上，另外，所实现的PTC保护具有最小的寄生电阻增加和扩展的电压范围，以此，上述的在目前的PTC保护中所遇到的困难和限制将被克服。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝，其在电子器件中与发热元件或区域具有优化的热耦合，同时，所提供的这样的耦合具有最小的耦合或寄生电阻的增加。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝，以提供一新的优化的PTC保护结构，该PTC保护结构可以方便地通过标准封装技 术实现，由此，对于制造成本的不利影响可被避免。 
本发明的一个方面是在源极器件的源极连接处应用PTC保险丝，以提供一新的优化的PTC保护结构，该PTC保护结构可以通过不增加封装尺寸实现，由此，减少了对制造成本产生不利影响的可能。 
本发明的一个方面是在活动器件的源极连接处应用PTC保险丝，以提供一新的优化的PTC保护结构，该PTC保护保险丝层由例如陶瓷类(ceramic-based)PTC材料或聚合物类(polymeric-based)PTC(PPTC)材料这样的PTC材料构成。 
大致地，本发明的一个优选实施例中公开了一种垂直半导体功率器件，其具有由半导体衬底的顶部表面和底部表面构成的一垂直电流路径以导通贯穿衬底的电流。该半导体功率器件还包括一过电流保护层，该过电流保护层由具有正温度系数(PTC)电阻的材料构成，并且该过电流保护层构成为垂直电流路径的一部分，其连接到源极，并对垂直半导体功率器件的栅极提供一反馈电压，以限制电流的通过，从而在任何电压下保护半导体功率器件。在一典型实施例中，过电流保护层由可重置的电流限制材料构成。在另一典型实施例中，过电流保护层贴覆于底部表面。在另一典型实施例中，过电流保护层贴覆于半导体功率器件的顶部表面，并具有连接源极的接合线。在另一典型实施例中，过电流保护层设置于组成半导体功率器件源极的半导体衬底底部表面和引线框架之间。 
本发明还进一步公开了一种制造整合有过电流保护的电子器件的方法。该方法包括设置由电流限制材料构成的过电流保护层以连接电子器件源极的步骤。该方法还包括在半导体功率器件的顶部表面上设置一层正温度系数材料以作为电流限制保护层的步骤，半导体功率器件的顶部表面作为半导体功能器件的源极。该方法还包括在半导体功率器件的底部表面上设置一层正温度系数材料以作为电流限制保护层的步骤，半导体功率器件的底部表面作为半导体功能器件的源极。 
本领域普通技术人员在结合多幅附图阅读了后续的对于本发明优选实施例的详细叙述后，本发明的这些和其它的内容和优点将变得显而易见。 
附图说明
图1A至1C所示为用于保护器件不受短路损害的过电流保护的不同实现结构。 
图2所示为PTC保护电路连接源极的简要示意图。 
图3A、3B和3C分别为具有本发明的PTC保护的标准垂直DMOS(双扩散金属氧化物半导体)功率MOSFET器件的电路图、侧面剖视图和俯视图。 
图4A、4B和4C分别为具有本发明的PTC保护的底部源极LDMOS功率MOSFET器件的电路图、侧面剖视图和俯视图。 
图5至图12所示为本发明中的由PTC结构保护的半导体功率器件的不同实施例的侧面剖视图。 
具体实施方式
图2是具有PTC保护的FET 100的简要示意图(其也可作为保险丝FET的参考)，其包括一由具有正温度系数(PTC)的材料构成的电阻110，结构为一连接到源极的导电层，并提供一反馈电压来控制栅-源电压。当受保护的器件温度上升时，PTC电阻110的电阻值也增大，一旦达到PTC限制(trip)温度时，电阻会剧烈增加。在这个保护结构中，任何的源极到漏极的电流(Ids)增加都会在PTC结构110两端间产生压降Vptc，从而降低FET控制电压Vgs。特别的，电压所具有的函数关系可以表示为： 
Vgs＝Vgs’+Vptc 
Vgs’＝Vgs-Vptc 
当器件温度高于PTC限制温度时，PTC结构两端间的压降Vptc远大于栅极至源极的电压Vgs’，即Vptc＞＞Vgs’，并导致FET关闭或切断。所选择的限制温度用以保护保险丝FET避免过电流的环境。因此，受保护的FET的电压变化自动保护PTC结构，使其自身免受过电压。另外，保险丝FET结构也可以应用于任何的漏极电压，只需要符合仅有的要求，即PTC结构必须与受PTC结构保护的FET的栅-源电压等级相匹配，即PTC结构的电压等级需要与FET的栅-源电压等级相同或更高。PTC结构的电压等级独立于漏极(漏-源)电压，即与漏极(漏-源)电压无关。甚至于在高电压(高漏-源电压)应用中，PTC结构可以具有一低电压等级，而因此提供了在普通运行环境中保险丝FET所具有的低电阻。 
图3A、3B和3C分别为实际应用的具有这样的PTC保护结构的垂直DMOS的电路图、侧面剖视图和俯视图，其具有顶部源极和底部漏极结构。一FET器件100’安装于印刷电路板(PCB)160上，并通过引线框架150的引脚连接到设置于PCB顶部的栅极连接150-G和源极连接150-S。一具有底部漏极140的垂直DMOS器件设置于引线框架150的顶部，并具有顶部源极金属120。一PTC保护结构设置于源极金属层120的顶部，其分别包括PTC层110’-PTC和顶部及底部电极层110’-e1、110’-e2。该PTC层110’-PTC可以包括一由陶瓷类(ceramic-based)PTC材料或聚合物类(polymeric-based)PTC  (PPTC)材料或其它任何适合的PTC材料组成的PTC保护保险丝层。接合线125连接于顶部电极110’-e1和引线框架150-S之间。接合线125-G连接于栅极衬垫130和引线框架150-G之间。PTC结构贴覆设在FET的有源源极区域。PTC结构、DMOS、接合线和部分的引线框架被封装入一模塑料(molding compound)中，以形成一半导体封装。 
图4A、4B和4C分别为实际应用的具有这样的PTC保护结构的垂直DMOS的电路图、侧面剖视图和俯视图，其具有底部源极和顶部漏极结构。一FET器件100”安装于印刷电路板(PCB)160上，并通过引线框架150的引脚连接到设置于PCB顶部的栅极连接150-G和漏极连接150-D。一具有底部源极120’的垂直DMOS器件设置于PTC保护结构110’的顶部，PTC保护结构110’设置于引线框架150的顶部。PTC保护结构包括分别由顶部及底部电极层110’-e1和110’-e2作为衬垫的PTC层110’-PTC。接合线125-D连接形成在VDMOS器件顶部的顶部漏极连接金属140’和引线框架150-D，该VDMOS器件具有底部源极120’。接合线125-G连接于栅极衬垫130和引线框架150-G之间。在这个FET器件中，PTC电极110’-e1直接连接于底部源极120’，并且PTC电极110’-e2直接连接于引线框架150。 
图3A至4C所示的连接PTC结构至源极的基本结构可以被应用实施于任何电压范围的器件保护，而不受PTC最大电压等级的限制，其如同在PTC至漏极连接保护结构中所遇到的限制。另外，保护结构可应用于任何增强模式的FET器件中，包括低压(LV)沟槽栅极VDMOS(垂直双扩散金属氧化物半导体)FET，平面VDMOS FET，E-模式HEMT(高电子迁移率晶体管，high electron mobility transistors)，E-模式SiT(静电感应晶体管，static induction transistor)和JFET(结栅场效应晶体管，junction gate FET)。另外，在所示的接合线封装中，也可以使用电镀接合来优化性能
图5所示为一标准垂直DMOS(VDMOS)功率MOSFET芯片200的剖视图。一VDMOS器件200安装于印刷电路板(PCB)260上，并通过引线框架250的引脚连接到设置在PCB上面的栅极连接250-G和源极连接250-S。垂直DMOS器件200具有一设置于引线框架250之上的底部漏极240，以及一例如铝源极接触层的顶部源极金属220。一由无电的镀镍金形成的抗氧化金属层形成于铝表面上，并最好贴覆于PTC保护结构210。通过标准背部金属工艺形成位于MOSFET芯片上的漏极，该MOSFET芯片使用例如钛镍银、或钛金、或铬金层的标准背部金属层，以形成如底部电极240这样的漏极。一PTC保护结构包括一PTC层210-PTC和顶部及底部电极层210-e1和210-e2。电极层210-e1和210-e2可以通过将镍金分别按压印刷在PTC层210-PTC的顶部的底部形成。接合线225连接顶部电极210-e1和引线框架的源极连接250-S。接合线225-G连接于栅极衬垫230和引线框架的栅极连接250-G之间。PTC结构贴覆设在FET的有源源极区域上。在封装过程中，首先应用导电环氧树脂将MOSFET器件贴覆设于引线框架250。然后，在源极金属层220的顶部上应用导电环氧树脂层，将PTC结构210贴覆设于源极金属层220的顶部表面。利用接合线工艺将连接PTC结构210的源极接合线225-S结合至引线框架上的源极连接250-S，以及将连接栅极衬垫230的栅极接合线225-G接合至引线框架上的栅极连接250-G。通过将器件封装入一模塑料270中用以保护VDMOS芯片，以完成封装工艺。 
图6是另一个与图5所示的器件类似的标准VDMOS封装200’，区别在于在封装工艺中，首先应用一焊膏取代导电环氧树脂来将MOSFET器件贴覆设于引线框架250上。然后，在源极金属层220的顶部上应用焊膏，将PTC结构210贴覆设于源极金属层220的顶部表面。利用接合线工艺，将连接PTC结构210的源极接合线225-S接合至引线框架上的源极连接250-S，以及将连接栅极衬垫230的栅极接合线225-G接合至引线框架上的栅极连接250-G。通过将器件封装入一模塑料270中用以保护VDMOS芯片，以完成封装工艺。图7是另一个与图6所示的器件类似的标准VDMOS封装200”，区别在于在完成接合线工艺之后，但封装步骤进行之前，形成一覆盖MOSFET器件和 PTC结构210，以及覆盖部分的接合线225和部分的引线框架250的塑料团顶部(glob top)225。该塑料团顶部225允许形成于芯片顶部表面的PTC结构210产生热膨胀。 
图8所示为一底部源极LDMOS芯片300的剖视图。底部源极LDMOS器件300由一印刷电路板(PCB)360支撑，并设置于引线框架350之上，且通过设置于PCB顶部上的栅极连接350-G和漏极连接350-D连接到引线框架350。一具有底部源极320的垂直LDMOS器件设置于位于引线框架350顶部上的PTC保护结构310之上。一PTC保护结构包括一PTC层310-PTC和顶部及底部电极层310-e1和310-e2，该顶部和底部电极层310-e1和310-e2可以分别通过将镍金按压印刷于PTC层310-PTC的顶部的底部形成。接合线325-D将形成于底部源极LDMOS器件顶部上的顶部漏极接触金属340连接到引线框架上的漏极连接350-D。接合线325-G连接于栅极衬垫330和引线框架的栅极连接350-G之间。在这个底部源极LDMOS器件中，PTC保护结构310直接连接于底部源极320。在封装过程中，首先应用一焊膏将PTC保护结构310贴覆设于引线框架350上。然后，在PTC保护结构310的顶部上应用焊膏，将MOSFET器件的源极320贴覆设于PTC保护结构310之上。利用接合线工艺，将连接漏极340的漏极接合线325-D接合至引线框架上的漏极连接350-D，以及将连接栅极衬垫330的栅极接合线325-G接合至引线框架上的栅极连接350-G。通过将器件封装入一封装结构370中用以保护底部源极LDMOS芯片，从而完成封装工艺。如图8和图9所示器件的封装工艺还可以进一步改进，即在完成接合线工艺之后，最终封装步骤之前，加入形成一塑料团顶部的步骤，从而，使PTC保护结构310具有更好的热膨胀柔韧性。 
图9所示为一底部源极LDMOS芯片300’的剖视图。底部源极LDMOS器件300’由一印刷电路板(PCB)360支撑，并设置于引线框架350的顶部，且通过设置于PCB顶部上的栅极连接350-G和漏极连接350-D连接到引线框架350。一具有底部源极320的垂直LDMOS器件设置于位于引线框架350顶部上的PTC保护结构310之上。一PTC保护结构包括一PTC层310-PTC和顶部及底部电极层310-e1和310-e2，该顶部和底部电极层310-e1和310-e2分别可以通过将镍金按压印刷于PTC层310-PTC的顶部的底部形成。接合线 325-D将形成于具有底部源极320的底部源极LDMOS器件顶部的顶部漏极连接金属340连接到引线框架的漏极连接350-D。接合线325-G连接于栅极衬垫330和引线框架的栅极连接350-G之间。在这个底部源极LDMOS器件中，PTC保护结构310直接连接底部源极320。在封装过程中，首先应用一导电环氧树脂将PTC保护结构310贴覆设于引线框架350上。然后，在PTC保护结构310的顶部上应用导电环氧树脂层，将MOSFET器件的源极320贴覆设于PTC保护结构310之上。利用接合线工艺，将连接漏极340的漏极接合线325-D接合至引线框架的漏极连接350-D，以及将连接栅极衬垫330的栅极接合线325-G接合至引线框架的栅极连接350-G。通过将器件封装入一封装结构370中用以保护底部源极LDMOS芯片，从而完成封装工艺。如图8和图9所示器件的封装工艺，还可以进一步改进，即在完成接合线工艺之后，最终封装步骤之前，加入形成一塑料团顶部的步骤，从而，使PTC保护结构310具有更好的热膨胀柔韧性。 
图10所示为一标准垂直DMOS(VDMOS)功率MOSFET芯片400的剖视图。VDMOS器件400由一印刷电路板(PCB)460支撑，并通过设置于PCB顶部上的栅极连接450-G和源极连接450-S连接到引线框架450。垂直DMOS器件400具有设置于引线框架450顶部上的底部漏极440，和例如为铝源极接触层的顶部源极金属420。通过无电的镀镍金可以在暴露的铝层表面形成的一抗氧化金属层。通过标准背部金属工艺形成位于MOSFET芯片上的漏极，该MOSFET芯片使用例如钛镍银、或钛金、或铬金层以形成如底部电极440这样的漏极。一PTC保护结构包括一PTC层410-PTC和顶部及底部电极层410-e1和410-e2，该顶部和底部电极层410-e1和410-e2分别通过将镍金按压印刷于PTC层410-PTC的顶部的底部形成。顶部金属板425-S-P将顶部电极410-e1连接至引线框架的源极连接450-S。接合线425-G连接于栅极衬垫430和引线框架的栅极连接450-G之间。PTC保护结构贴覆设于FET的有源源极区域上。在封装过程中，首先应用一焊膏将MOSFET器件贴覆设于引线框架450上。然后，在源极金属层420的顶部上应用焊膏，将PTC保护结构410贴覆设于源极金属层420的顶部表面。 
也可以选择使用别的具有类似功能的材料来代替焊膏，例如导电环氧树脂。使用一顶部金属板接合工艺，将连接PTC保护结构410的源极顶部金属板425-S-P接合到引线框架的源极连接450-S，并且，用栅极接合线425-G连接栅极衬垫430和引线框架的栅极连接450-G。通过应用升温使焊料回流，并将器件封装入一模塑料470中，来保护VDMOS芯片，然后切割引线框架，并焊接或锯断晶片至VDMOS MOSFET芯片中，以完成封装工艺。图11所示为另一个与图10所示的半导体功率器件400相似的标准VDMOS MOSFET功率器件400’。仅有的区别是图10中所示的栅极接合线425-G现在被栅极顶部金属板425-G-P取代，其连接栅极衬垫430和引线框架的栅极连接450-G。 
图12所示为一底部源极LDMOS芯片500的剖视图。底部源极LDMOS器件500由位于引线框架550下的印刷电路板(PCB)560支撑。引线框架550具有设置于PCB 560顶部的栅极连接550-G和漏极连接550-D。具有底部源极520的垂直LDMOS器件设置于PTC保护结构510的顶部上，该PTC保护结构510设置于引线框架550的顶部上。一PTC保护结构包括一PTC层510-PTC和顶部及底部电极层510-e1和5410-e2，该顶部和底部电极层510-e1和510-e2分别通过将镍金按压印刷于PTC层510-PTC的顶部的底部形成。顶部接合金属板525-D-P将顶部漏极接触金属540连接至引线框架的漏极连接550-D，该顶部漏极接触金属540形成于具有底部源极520的底部源极LDMOS器件的顶部。栅极接合金属板325-G将栅极衬垫530连接至引线框架的栅极连接550-G。在这个底部源极LDMOS器件中，PTC保护结构510直接连接至底部源极520。在封装过程中，首先应用焊膏将PTC保护结构510贴覆设于引线框架550上。然后，在PTC保护结构510的顶部上应用焊膏，用以将MOSFET器件的源极520贴覆设于PTC保护结构510上。也可以选择使用类似的合适的材料来代替焊膏，例如导电环氧树脂。使用金属板接合工艺，将连接到漏极540的漏极顶部金属板525-D-P接合至引线框架的漏极连接550-D，并且，用栅极接合金属板525-G-P连接栅极衬垫530和引线框架的栅极连接550-G。通过应用升温使焊料回流，并将器件封装入一模塑料570中，用以保护底部漏极LDMOS芯片，以完成封装工艺。 
上述的图4A至12中所示的PTC层，例如PTC层110’-PTC、210-PTC、310-PTC、410-PTC和510-PTC，可以包括一由陶瓷类PTC材料或聚合物类PTC(PPTC)材料或其它任何适合的PTC材料组成的PTC保险丝保护层。 这些PTC材料包括如美国专利4,238,812中所公开的掺杂钛酸钡陶瓷(dopedceramic of barium titanate)，尽管该材料由于在高温下会变得易碎而在应用中受到限制。PTC材料还可以包括导电聚合物，如美国专利4,238,812中所公开的，其具有分布于大部分聚合物层中的微颗粒导电填充物，并由罗氏(Raychem)和其它公司成功地投入商业应用，用于制造厚度大约为0.5埃的PTC保险丝层，并以PoluFuseTM作为产品商标。 
PTC器件的顶部和底部电极可以分别由任何含金的金属、铜、合金、或复合层结构组成，该复合层结构例如为金，镍金等等。 
尽管本发明的内容已经通过上述现有优选实施方式作了详细介绍，但应当认识到上述的公开不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。所以，后续的权利要求书应当被视作覆盖了所有落入本发明真正精神和范围内的所有修改和替代。 

Claims (31)

1.一种垂直半导体功率器件，包括：
由半导体衬底的顶部表面和底部表面构成的一垂直电流路径，以导通贯穿半导体衬底的电流；以及
一由具有正温度系数电阻的材料构成的过电流保护层，其作为所述的垂直电流路径的一部分，并直接物理连接到所述的垂直半导体功率器件的源极，且对垂直半导体功率器件的栅极提供一反馈电压，用以限制贯穿的电流，从而在任何的电压下可以保护垂直半导体功率器件，而不受所述的过电流保护层的电压等级的限制。
2.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的过电流保护层由可重置的电流限制材料组成。
3.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，垂直半导体功率器件为一底部源极垂直半导体功率器件，所述的过电流保护层直接贴覆设于底部源极上，并连接垂直半导体功率器件的底部源极。
4.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，垂直半导体功率器件具有一设置于垂直半导体功率器件顶部表面的源极，所述的过电流保护层直接贴覆设于垂直半导体功率器件的源极的顶部表面上。
5.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的过电流保护层具有与垂直半导体功率器件的栅源电压等级相匹配的电压等级。
6.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的过电流保护层还包括设置于由具有正温度系数电阻的材料组成的PTC层的上面和下面的顶部电极层和底部电极层。
7.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的过电流保护层还包括设置于由具有正温度系数电阻的材料组成的PTC层的上面和下面的顶部电极层和底部电极层，其中所述的顶部和底部电极层由铜，或者由金、镍金组成的复合层结构，或者合金构成。
8.如权利要求6所述的垂直半导体功率器件，其特征在于：所述的顶部和底部电极层由包含金的金属构成。
9.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，垂直半导体功率器件具有一底部电极层。
10.如权利要求1所述的垂直半导体功率器件，其特征在于：还包括金属内连接，其连接所述的垂直半导体功率器件的顶部表面的电极和引线框架的电极。
11.如权利要求10所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件是一底部源极MOSFET器件，其具有设置于底部表面的源极，其中所述的垂直半导体功率器件设置于所述的过电流保护层上，通过所述的金属内连接将所述的MOSFET器件的顶部漏极连接到引线框架的漏极电极。
12.如权利要求10所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件是一底部漏极MOSFET器件，其具有设置于该MOSFET器件的顶部表面的源极，所述的MOSFET器件被所述的过电流保护层覆盖，通过所述的金属内连接将所述的过电流保护层连接到引线框架的源极电极。
13.如权利要求10所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件是一具有设置于器件顶部表面的栅极衬垫的MOSFET器件，通过所述的金属内连接，连接所述的栅极衬垫和引线框架上的栅极电极。
14.如权利要求1所述的垂直半导体功率器件，其特征在于：还包括一覆盖所述垂直半导体功率器件的塑料团顶部，其允许由其覆盖下的过电流保护层产生热膨胀。
15.如权利要求10所述的垂直半导体功率器件，其特征在于：其中，所述的金属内连接由导电金属板或接合线构成。
16.如权利要求15所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件具有一设置于该垂直半导体功率器件顶部表面上的栅极衬垫，并具有一栅极导电金属板连接所述的栅极衬垫和引线框架上的栅极电极。
17.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件为一具有设置于顶部表面上的源极的垂直MOSFET器件，所述的设置于顶部表面上的源极包括一抗氧化金属层，所述的抗氧化金属层通过一贴覆介质配合，贴覆到所述的过电流保护层上，以减少所述的顶部表面上的源极与过电流保护层之间的接触电阻。
18.如权利要求17所述的垂直半导体功率器件，其特征在于：其中，所述的设置于顶部表面上的源极包括一由金构成的抗氧化金属层。
19.如权利要求17所述的垂直半导体功率器件，其特征在于：其中，所述的设置于顶部表面上的源极包括一抗氧化金属层，该抗氧化金属层由顶部为金的镍。 
20.如权利要求17所述的垂直半导体功率器件，其特征在于：其中，所述的设置于顶部表面上的源极通过由环氧树脂构成的贴覆介质贴覆到所述的过电流保护层上。
21.如权利要求17所述的垂直半导体功率器件，其特征在于：其中，所述的设置于顶部表面上的源极通过由焊接剂构成的贴覆介质贴覆到所述的过电流保护层。
22.如权利要求1所述的垂直半导体功率器件，其特征在于：其中，所述的垂直半导体功率器件为一具有设置于底部表面上的源极的垂直DMOS器件，所述的设置于底部表面上的源极包括一抗氧化金属层，该抗氧化金属层通过一贴覆介质配合，贴覆到所述的过电流保护层上，以减少所述的底部表面上的源极与过电流保护层之间的接触电阻。
23.如权利要求22所述的垂直半导体功率器件，其特征在于：其中，所述的位于底部表面上的源极包括一由金构成的抗氧化金属层。
24.如权利要求22所述的垂直半导体功率器件，其特征在于：其中，所述的位于底部表面上的源极包括一抗氧化金属层，该抗氧化金属层由顶部为金的镍。
25.如权利要求22所述的垂直半导体功率器件，其特征在于：其中，所述的位于底部表面上的源极通过由环氧树脂构成的贴覆介质贴覆到所述的过电流保护层上。
26.如权利要求22所述的垂直半导体功率器件，其特征在于：其中，所述的位于底部表面上的源极通过由焊接剂构成的贴覆介质贴覆到所述的过电流保护层上。
27.一种保护垂直半导体功率器件的方法，该器件具有半导体衬底的一顶 部表面和一底部表面，并构成一垂直电流路径用以导通贯穿的电流，该方法包括：
设置一由具有正温度系数电阻的材料构成的过电流保护层，作为所述的垂直电流路径的一部分，直接物理连接到所述的垂直半导体功率器件的源极，并对垂直半导体功率器件的栅极提供一反馈电压，以限制电流的贯穿从而达到过电流保护，其不受限于所述的过电流保护层的电压等级。
28.如权利要求27所述的方法，其特征在于：其中，所述的设置过电流保护层的步骤还包括：设置由可重置的电流限制材料组成的过电流保护层的步骤。
29.如权利要求28所述的方法，其特征在于：其中，所述的设置所述的过电流保护层的步骤还包括：贴覆所述的过电流保护层于底部源极垂直半导体功率器件的底部表面上，以直接连接垂直半导体功率器件的底部源极的步骤。
30.如权利要求28所述的方法，其特征在于：其中，所述的设置所述的过电流保护层的步骤还包括：贴覆所述的过电流保护层于底部漏极垂直半导体功率器件的顶部表面上，以直接连接垂直半导体功率器件的顶部源极的步骤。
31.如权利要求28所述的方法，其特征在于：其中，所述的设置所述的过电流保护层的步骤还包括：设置所述的过电流保护层具有与垂直半导体功率器件的栅-源电压等级相匹配的电压等级的步骤。 
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