TWI381491B - Manufacturing Method of NOR - type Flash Memory with Phosphorus Arsenic Ion Planting - Google Patents

Description

Method for manufacturing NOR type flash memory with phosphorus and arsenic ion implantation

The invention relates to a method for manufacturing a flash memory, and more particularly to a method for manufacturing a NOR flash memory with phosphorus and arsenic ion implantation.

Flash memory is a non-volatile memory that saves information when there is no external power supply. This saves the device itself from wasting power on the data, plus fast The flash memory also has the characteristics of repeated reading and writing, small size, high capacity and portability, which makes the flash memory particularly suitable for use on portable devices. At present, the range of NOR flash memory applications, in addition to the motherboard on the personal computer will use the NOR flash memory to store BIOS data, mobile phones, handheld devices will also use NOR flash memory to store system data, borrow Its high-speed reading speed meets the booting requirements of handheld devices.

With the evolution of semiconductor processes, memory capacity continues to increase, yield improvement and process difficulty are increasingly emerging, and the limitations of physical phenomena are becoming increasingly apparent. Therefore, all parties are committed to seeking any steps or methods that can improve the memory yield.

The bungee junction is one of the main factors affecting the defect of NOR flash memory components. In order to improve the performance of the memory device, a metallization process is conventionally performed, that is, a metal silicide layer is deposited on the drain region by using a self-aligned silicidation process to reduce the contact resistance. The current flows first through the metal halide layer with a lower resistance and then into the drain region. The metal telluride layer must have a certain depth in the gate region of the drain to reduce contact resistance. Therefore, the metal telluride layer may cause loss of the drain region when formed, and the loss increases the leakage current of the drain region.

Since ion implantation in the source/drain region is directly related to the electrical properties of the memory device, in order to optimize the design of the device, it is necessary to be able to grasp the optimal ion implantation energy and dose to reduce the component. Defects and improved production yield of memory components.

The main object of the present invention is to provide a method for manufacturing a NOR-type flash memory, which utilizes a specific ion implantation energy and a dose to reduce defects caused by the metallization process and improve the production yield of the memory device.

In order to achieve the above object, the present invention provides a method for fabricating a NOR-type flash memory with phosphorous arsenic ion implantation, comprising: forming a gate structure on a semiconductor substrate; performing a deep doped source ion cloth Forming a deep doped first source region in the semiconductor substrate on one side of the gate structure; performing a shallow doped drain ion implantation process on the other side of the gate structure Forming a shallow doped first drain region in the substrate, the first drain region and the first source region are respectively located in the semiconductor substrate on both sides of the gate structure; on both sides of the gate structure Forming an insulating layer spacer on the semiconductor substrate; and performing a deep doped drain ion implantation process to form a deep doped second drain region in the semiconductor substrate on one side of the gate structure, wherein The first drain region overlaps the second drain region, and the deep doped drain ion implantation process comprises two implantation processes, a first deep doped bungee ion implantation process, and the use thereof Ion is arsenic, and a second deep doped bungee ion implantation process Their use is phosphorus ions.

In an embodiment of the invention, the first deep doped dopant ion implantation process has a dose of about 2×10 15 to 4×10 15 (atom/cm 2 ) and an energy of about 40 to 50 (Kev).

In an embodiment of the invention, the second deep doped drain ion implantation process has a dose of about 2×10 14 2×10 15 (atom/cm 2 ) and an energy of about 20-30 (Kev).

In an embodiment of the invention, the insulating layer spacer is selected from the group consisting of yttrium oxide (SiOx), tantalum nitride (SiNx), yttrium oxynitride (SiONx), or a combination of lanthanum oxide and tantalum nitride.

In an embodiment of the invention, a metallization process is further included, which includes the steps of: forming an auto-aligned germanide layer on the gate structure and the surface of the first drain region; depositing a dielectric layer, And defining the dielectric layer to form an automatic alignment contact opening on the self-aligned germanide layer above the first drain region; and filling the self-aligned contact opening with a conductive material to form a metal connection line.

In another embodiment of the invention, the second deep doped drain ion implantation process is performed prior to the first deep doped drain ion implantation process.

Therefore, the method for manufacturing the NOR-type flash memory with the phosphorus-arsenic ion implant of the present invention can change the characteristic performance of the bungee implant, thereby reducing the defects caused by the metallization process on the memory component and improving the production. rate.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying drawings. In the various figures and embodiments, the same elements will be given the same symbols.

The manufacturing method of the NOR type flash memory of the invention mainly comprises implanting phosphorus and arsenic ions into one of the drain regions of the memory component, and reducing memory device defects through specific implant energy and dose control. Improve yield. An embodiment of the invention is an N-channel NOR-type semiconductor memory structure having an N-type source/drain ion implantation region. The first to sixth figures show cross-sectional views of the NOR type flash memory of the embodiment of the present invention at different process steps.

First, referring to the first figure, a gate structure 102 is formed on a semiconductor substrate 100. The gate structure 102 includes a tunnel oxide layer 102a, a floating gate 102b, and a dielectric layer 102c. And a control gate 102d (control gate). The material of the semiconductor substrate 100 may be bismuth (Si), germanium (SiGe), silicon on insulator (SOI), silicon germanium on insulator (SGOI), and insulating layer. Germanium On Insulator (GOI). In the present embodiment, the material of the semiconductor substrate 100 is germanium, and boron is doped therein to make the semiconductor substrate 100 a P-type semiconductor substrate.

Referring to the second figure, a reticle 202 is formed on the semiconductor substrate 100 to cover one side of the gate structure 102. A deep doped source ion implantation process 204 is performed to form a deep doped first source region 206 in the semiconductor substrate 100 on one side of the gate structure 102. In the P-based embodiment, the ions used in the deep doped source ion implantation process 204 are phosphorus and arsenic to reduce the parasitic resistance of the first source region.

Referring to the third figure, a shallow doped drain ion implantation process 302 is performed on the semiconductor substrate 100 on the other side of the gate structure 102 by using a Lightly Doped Drain (LDD) implant. A first drain region 304 is formed. The first source region 206 and the first drain region 304 are respectively located in the semiconductor substrate 100 on both sides of the gate structure. In this embodiment, the ions used in the shallow doping dopant ion implantation process are arsenic, which is used to reduce short channel effect, improve performance, and enhance memory writing efficiency.

Referring to FIG. 4A, an insulating layer spacers 402, 404 are formed on each side of the gate structure 102 by deposition and etching techniques. 402, 404 may be a silicon oxide (SiO _x), silicon nitride (SiN _x), silicon oxynitride (SiON _x) or a combination of silicon oxide and silicon nitride of the insulating spacer layer (SiO _x + SiN _x). As shown in FIG. 4A, the insulating layer spacer is yttrium oxide (SiO _x ) or yttrium oxynitride (SiON _x ); as shown in FIG. 4B, the insulating layer spacer is tantalum nitride (SiN _x ); As shown in Fig. 4C, the insulating layer spacer is a combination of yttrium oxide and tantalum nitride (SiO _x + SiN _x ), the yttrium oxide is a fan-shaped insulating layer spacer in the figure, and the tantalum nitride is L-shaped insulating in the figure. A layer spacer; wherein, in this embodiment, the manufacturing process of the memory element is continued by taking the fourth A picture as an example. The foregoing deposition technique may be: chemical vapor deposition (CVD), rapid thermal annealing Vapof Deposition (RTCVD), and atomic layer deposition (Atomic Layer Deposition) of the source gas including NH ₃ and SiH ₄ . ALD); and the etching technique may be a dry or wet etch of an anisotropic etch to remove the insulating layer on the vertical surface to form the insulating layer spacers 402, 404.

Next, referring to FIG. 5, a deep doped drain ion implantation process 502 is performed to form a second doped second drain region 504 in the semiconductor substrate 100 on the side of the gate structure 102. The deep doped bionic ion implantation process comprises two implantation processes, and the ions used in the first deep doped bionic ion implantation process are arsenic, and the dose is about 2×10 ¹⁵ ～4×10. ¹⁵ atoms / square centimeter (atom / cm ² ), energy is about 40 ~ 50 kiloelectron volts (Kev). The ion used in the second deep doping of the bionic ion implantation process is phosphorus, and the dose is about 2×10 ¹⁴ to 2×10 ¹⁵ atoms/cm ² , and the energy is about 20 to 30 thousand electrons. Kev. In another embodiment of the invention, the order of the first and second deep doped drain ion implantation processes can be interchanged.

Referring to the sixth figure, the above steps are followed to perform a metallization process, and an auto-alignment telluride layer 506 is formed on each of the second drain region 504 and the gate structure 102. Next, a dielectric layer 508 is deposited, the dielectric layer 508 is defined, and an auto-aligned contact opening is formed on the self-aligned germanide layer 506 over the first drain region 304, and then filled with a conductive material. The self-aligning contact openings form a metal wire 510. In this embodiment, the material of the self-aligned germanide layer 506 may be heat resistant such as cobalt (Co), titanium (ti), nickel (nickel, Ni) or molybdenum (Mo). metal.

The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that this embodiment is only used to describe a part of the structure of the memory unit in the present invention, and should not be construed as limiting the present invention. range. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100. . . Semiconductor substrate

102. . . Gate structure

102a. . . Tunneling oxide layer

102b. . . Floating gate

102c. . . Dielectric layer

102d. . . Control gate

202. . . Mask

204. . . Deep doped source ion implantation process

206. . . First source region

302. . . Shallow-doped bungee ion implantation process

304. . . First bungee zone

402. . . Oxide wall

404. . . Oxide wall

502. . . Deep doped bionic ion implantation process

504. . . Second bungee zone

506. . . Automatic alignment of the telluride layer

508. . . Dielectric layer

510. . . Metal connection

The first to sixth figures show cross-sectional views of the NOR type flash memory of the embodiment of the present invention at different process steps.

100. . . Semiconductor substrate

102. . . Gate structure

206. . . First source region

304. . . First bungee zone

402. . . Oxide wall

404. . . Oxide wall

504. . . Second bungee zone

506. . . Automatic alignment of the telluride layer

508. . . Dielectric layer

510. . . Metal connection

Claims (6)

A method for manufacturing a NOR flash memory with phosphorous arsenic ion implantation, the method comprising: forming a gate structure on a semiconductor substrate; performing a deep doped source ion implantation process on the gate structure Forming a deep doped first source region in the semiconductor substrate on one side; performing a shallow doped drain ion implantation process to form a shallow doped one in the semiconductor substrate on the other side of the gate structure a first drain region, the first source region and the first source region are respectively located in the semiconductor substrate on both sides of the gate structure; and an insulating layer is formed on the semiconductor substrate on both sides of the gate structure a layer spacer; and performing a deep doped drain ion implantation process, forming a deep doped second drain region in the semiconductor substrate on one side of the gate structure, wherein the first drain region is The second drain region overlaps, and the deep doped drain ion implantation process comprises two implantation processes, a first deep doped bionic ion implantation process, the ions used are arsenic, and a second The second deep doped bionic ion implantation process uses ions of phosphorus. The manufacturing method according to claim 1, wherein the dose of the first deep doped drain ion implantation process is 2×10 ¹⁵ 4×10 ¹⁵ (atom/cm ² ), and the energy is 40~ 50 (Kev). The manufacturing method according to claim 1, wherein the dose of the second deep-doped bungee ion implantation process is 2×10 ¹⁴ 2×10 ¹⁵ (atom/cm ² ), and the energy is 20~ 30 (Kev). The manufacturing method of claim 1, wherein the second deep doped gate ion implantation process is performed before the first deep doped drain ion implantation process. The manufacturing method according to claim 1, wherein the insulating layer spacer is selected from the group consisting of cerium oxide (SiO _x ), cerium nitride (SiN _x ), cerium oxynitride (SiON _x ) or cerium oxide and tantalum nitride. Combine one of them. The manufacturing method of claim 1, further comprising a metallization process comprising the steps of: forming an auto-alignment telluride layer on the gate structure and the surface of the first drain region; depositing a dielectric layer defining a dielectric layer to form an auto-aligned contact opening on the self-aligned germanide layer over the first drain region; and filling the self-aligned contact opening with a conductive material To form a metal connection.