TWI411101B - NOR-type flash memory structure with high doping drain region and its manufacturing method - Google Patents

Abstract

The invention relates to a NOR type Flash member structure and the manufacturing method thereof, it is mainly to utilize highly doped ion implantation process to implant a highly doped drain area, which is overlapped with lightly doped drain area. Therefore, the depth of drain area contact surface can be reduced to improve short-channel effect, meanwhile the digging-through phenomenon on lightly doped drain area can also be avoided while etching a contact hole.

Description

NOR type flash memory structure with highly doped drain region and manufacturing method thereof

The present invention relates to a NOR type flash memory structure and a method of fabricating the same, and more particularly to a NOR type flash memory structure having a highly doped drain region and a method of fabricating the same.

Flash memory is a non-volatile memory that saves information when there is no external power supply. This saves the device itself from wasting power on the data, plus fast The flash memory also has the characteristics of repeated reading and writing, small size, high capacity and portability, which makes the flash memory particularly suitable for use on portable devices. At present, the range of NOR flash memory applications, in addition to the motherboard on the personal computer will use the NOR flash memory to store BIOS data, mobile phones, handheld devices will also use NOR flash memory to store system data, borrow Its high-speed reading speed meets the booting requirements of handheld devices.

With the advancement of technology, the flash memory process technology has also entered the nano-era, in order to accelerate the operating rate of components, increase the accumulation of components, and reduce the operating voltage of components, etc., the channel of the component gate The shrinkage of the length and thickness of the oxide layer is an inevitable trend. The size of the miniature component not only increases the density of the integrated circuit per unit area, but also enhances the current driving capability of the component itself, which is a two-pronged approach, but in fact it is not. The gate width of the device has been reduced from the previous micron (10 ^-6 meters) to the current nano (10 ^-9 meters), and the short channel effect (Short) is caused by the miniaturization of the components and the shortening of the gate width. Channel Effect is getting more and more serious, and one of the solutions to avoid the short channel effect is to reduce the junction depth of the source/drain.

In the case of Lightly Doped Drain (LDD), it can improve the component's Breakdown Voltage, improve the threshold voltage characteristics, and reduce the Hot Carrier Effect. Although the lightly doped drain reduces the high electric field of the drain junction and effectively improves the reliability of the component, the shallow junction depth caused by the lightly doped gate is easily etched when the contact hole is etched. The phenomenon of wearing, and destroying the structure of the memory.

Therefore, how to improve the drain region to avoid the phenomenon of tunneling caused by etching the contact hole becomes quite important.

The main object of the present invention is to provide a NOR-type flash memory with a highly doped drain region, which reduces the junction depth of the drain region to improve the short channel effect, and also avoids etching the contact hole. The lightly doped bungee zone causes the phenomenon of digging.

In order to achieve the above object, the present invention provides a highly doped bungee region NOR type flash memory structure, comprising: a semiconductor substrate having a two-gate structure thereon; and a first drain region a lightly doped region in the semiconductor substrate between the two gate structures; a first source region in the semiconductor substrate outside the two of the two gate structures; wherein the first source a junction depth in the semiconductor substrate is greater than the first drain region a highly doped drain region in the semiconductor substrate between the two gate structures and overlapping the first drain region, and the junction of the highly doped drain region in the semiconductor substrate The depth is deeper than the first drain region; the second automatic alignment metal halide layer is above the two gate structures; and a barrier plug separates the two gate structures.

In order to achieve the above object, the present invention provides a method for fabricating a NOR-type flash memory structure having a highly doped drain region, comprising: providing a semiconductor substrate; forming a two-gate structure over the semiconductor substrate; Performing a lightly doped ion implantation process in the semiconductor substrate between the two gate structures to form a lightly doped first drain region, respectively forming a semiconductor substrate on the outer side of the two gate structures Lightly doping the source region, and performing a source ion implantation process, respectively forming a first source region in the semiconductor substrate outside the two gate structures, wherein the first source region is in the semiconductor The junction depth in the substrate is deeper than the first drain region; an L-shaped spacer is formed between the two gate structures, and the two L-shaped spacers are located above the first drain region; Doping an ion implantation process to form a highly doped drain region between the two gate structures, wherein the highly doped drain region overlaps the first drain region, and the highly doped drain region The junction depth in the semiconductor substrate is deeper than the first drain region; Between the two barrier gate structure formed in a plug.

Thereby, the NOR-type flash memory structure of the present invention and the manufacturing method thereof can avoid the phenomenon of the tunneling of the lightly doped drain region when the contact hole is etched.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying drawings. In the various figures and embodiments, the same elements will be given the same symbols.

Referring first to the first drawing, a partial cross-sectional view of the flash memory structure of the present invention is shown. A gate structure 102 is formed on a semiconductor substrate 100. The gate structures 102 include a tunneling oxide layer 102a, a floating gate 102b, and a dielectric layer 102c. The gate 102d is controlled and a region 103 is formed. The semiconductor substrate 100 may be made of germanium, SiGe, silicon on insulator (SOI), silicon germanium on insulator (SGOI), germanium on insulator (GOI). In the embodiment, the semiconductor substrate 100 is a germanium substrate.

Then, referring to the second figure, a lightly doped ion implantation process 201 is performed, and lightly doped Drain (LDD) is implanted in the semiconductor substrate 100 of the two gate structures 102 to form a lightly doped region. The source region 202 and a first drain region 204. In the embodiment of the present invention, the semiconductor structure is a P-type semiconductor structure, and the ion used in the lightly doped ion implantation process 201 is arsenic, and the dose is about 1×10 ¹⁴ ~7× ^{10 14} (ion/cm ² ), and the energy is about It is 10~30 (Kev). The two lightly doped source regions 202 and the first drain regions 204 are an N-doped region, and the junction depth in the semiconductor substrate 100 is about 200. .

Then, referring to the third and second figures, a reticle 302 is formed on the semiconductor substrate 100, and the first drain region 204 is covered by the reticle 302. A source ion implantation process 301 is performed to deepen the ion implantation depth of the two lightly doped source regions 202 in the semiconductor substrate 100 to become two first source regions 304, and the first source regions 304 and The first drain region 204 is asymmetric. Similarly, in the P-type semiconductor structure, the ions used in the source ion implantation process 301 are arsenic, and the dose is about 1×10 ¹⁴ ~7× ^{10 15} (ion/cm ² ), and the energy is about 10~30 (Kev). . The first source region is an N-doped source region, and the junction depth in the semiconductor substrate 100 is about 200. .

Next, referring to the fourth figure, a first oxide layer wall 401 and a second oxide layer 402 are formed, and a conventional deposition technique such as chemical vapor deposition (CVD) in which the source gas contains NH ₃ and SiH _{4 is used} . ), rapid thermal chemical vapor deposition (RTCVD), atomic layer deposition (ALD), deposition of an oxide layer 404. The thickness of the oxide layer 404 can be between 200 To 1500 , in this embodiment, about 750 .

Next, referring to the fourth and fifth figures, the oxide layer 404 is etched into a plurality of Oxide spacers 502a-d by an etching process using dry or wet etching. Another etching process is performed to etch the second oxide layer 402 into two L-shaped spacers 504a, 504b and etch the first oxide layer wall 401. Finally, a highly doped drain region 508 is formed between the two gate structures 102 via a highly doped gate ion implantation process 506. The highly doped drain region 508 overlaps the first drain region 204, and the junction depth of the highly doped drain region 508 in the semiconductor substrate 100 is deeper than the first drain region 204. The ion used in the highly doped drain ion implantation process 506 is arsenic, and the dose is about 5× ^{10 14 8} × ^{10 15} (ion/cm ² ), and the energy is about 20-55 (Kev). The highly doped bungee region The junction depth of 508 in the semiconductor substrate 100 is about 600. . The junction profile of the first drain region 204 and the highly doped drain region 508 is steep and is different from the smooth junction appearance of the first source regions 304. Wherein the highly doped germanium region is an N doping. Thus, due to the implantation of the highly doped drain region 508, when the lightly doped first drain region 204 is etched in the contact hole, the shallower junction depth causes the first drain region 204 to be dug. The phenomenon of wearing does not destroy the structure of the memory.

Next, referring to the sixth figure, a metal telluride layer composed of cobalt (co), titanium (titanium, Ti), nickel (nickel, Ni) or molybdenum (Mo) is formed on the surface, and a The rapid thermal annealing process is performed to form a self-aligned metal halide layer 602a, 602b and 602c (salicide layer) for reducing the driving force of the parasitic resistance lifting element.

Next, referring to the seventh figure, following the above steps, a contact etch stop layer 702 (CESL) is deposited on the semiconductor substrate 100, which may be SiN, oxynitride, or yttrium oxide. And so on, in this embodiment, is SiN. The contact hole etch stop layer 702 is deposited to a thickness of 100 to 1500 . Next, an inter-layer dielectric (IGD), such as SiO ₂ , is deposited over the contact hole etch stop layer 702.

Finally, referring to the eighth figure, a contact hole 802 is non-uniformly etched from the interlayer dielectric layer 704 to the interface by a conventional photoresist mask process. The etch stop layer 702 is touched. A barrier plug 804 is deposited to form a NOR-type flash memory structure having a highly doped drain region as shown in FIG.

The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that this embodiment is only used to describe a part of the structure of the memory unit in the present invention, and should not be construed as limiting the present invention. range. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100‧‧‧Semiconductor substrate

102‧‧‧ gate structure

102a‧‧‧ Tunneling Oxidation Layer

102b‧‧‧Floating gate

102c‧‧‧ dielectric layer

102d‧‧‧Control gate

103‧‧‧Area

201‧‧‧Lightly doped ion implantation process

202‧‧‧Lightly doped source region

204‧‧‧First bungee area

301‧‧‧Source ion implantation process

302‧‧‧Photomask

304‧‧‧First source region

401‧‧‧First Oxide Wall

402‧‧‧Second oxide layer

404‧‧‧Oxide layer

502a~d‧‧‧Oxide spacer

504a~b‧‧‧L-shaped spacer

506‧‧‧Highly doped bungee ion implantation process

508‧‧‧Highly doped bungee zone

602a~c‧‧‧Automatic alignment of metal telluride layers

702‧‧‧Contact hole etch stop layer

704‧‧‧Interlayer dielectric layer

802‧‧‧ contact hole

804‧‧‧ Barrier plug

The first to eighth figures show cross-sectional views of the flash memory structure of the embodiment of the present invention at different process steps.

100‧‧‧Semiconductor substrate

102‧‧‧ gate structure

204‧‧‧First bungee area

304‧‧‧First source region

401‧‧‧First Oxide Wall

402‧‧‧Second oxide layer

502a~d‧‧‧Oxide spacer

504a~b‧‧‧L-shaped spacer

508‧‧‧Highly doped bungee zone

602a~c‧‧‧Automatic alignment of metal telluride layers

702‧‧‧Contact hole etch stop layer

704‧‧‧Interlayer dielectric layer

802‧‧‧ contact hole

804‧‧‧ Barrier plug

Claims (8)

A NOR-type flash memory structure having a highly doped drain region, comprising: a semiconductor substrate having a two-gate structure thereon; and a first drain region being a lightly doped region a lightly doped source region in the semiconductor substrate outside the two gate structures, the lightly doped source region and the first drain region Having the same implant depth in the semiconductor substrate; a first source region is disposed in the semiconductor substrate outside the two gate structures; wherein the first source region is in the semiconductor substrate The junction depth is deeper than the first drain region, and a portion of the first source region overlaps the lightly doped source region; a highly doped drain region is the semiconductor between the two gate structures In the substrate, and overlapping with the first drain region, and the junction depth of the highly doped drain region in the semiconductor substrate is deeper than the first drain region, wherein the first source region is in the semiconductor The junction depth in the substrate is deeper than the highly doped drain region; the second is automatically aligned with the metal halide layer, Respectively above the two gate structures; plug and a barrier, the two lines spaced gate structures. The NOR flash memory structure of claim 1, wherein the first drain region, the first source region, and the highly doped drain region are an N-type doped region. The NOR flash memory structure of claim 1, further comprising an auto-alignment metal halide layer located above the first drain region. A method for fabricating a NOR-type flash memory structure having a highly doped drain region, comprising: providing a semiconductor substrate; forming a two-gate structure over the semiconductor substrate; and the semiconductor between the two gate structures Directly performing a lightly doped ion implantation process to form a lightly doped first drain region in a manner in which no other layer structure is located above the first drain region and the lightly doped source region. Forming the lightly doped source region in the semiconductor substrate outside the two gate structures, and performing a source ion implantation process, respectively forming the semiconductor substrate on the outer side of the two gate structures a first source region, wherein a depth of a junction of the first source region in the semiconductor substrate is deeper than the first drain region, the lightly doped source region and the first drain region are on the semiconductor substrate The middle system has the same implant depth; between the two gate structures, two L-shaped spacers are respectively formed, and the two L-shaped spacers are located above the first drain region; performing a highly doped ion implantation process Forming a high doping between the two gate structures a pole region, wherein the highly doped drain region overlaps the first drain region, and a junction depth of the highly doped drain region in the semiconductor substrate is deeper than the first drain region, the first source The junction region of the polar region in the semiconductor substrate is deeper than the highly doped drain region; and a barrier plug is formed between the two gate structures. The manufacturing method of claim 4, wherein the step of forming an L-shaped spacer between the two gate structures further comprises: depositing an oxide layer on the two L-type spacers; etching the oxidation Forming a contact hole; and forming an automatic alignment metal salicide layer on the two gate structures and the surface of the first drain region. The manufacturing method according to claim 4, wherein the ion used in the lightly doped ion implantation process is arsenic, and the dose is about 1×10 ¹⁴ to 7× ^{10 14} (ion/cm ² ), and the energy is about 10 ~30 (Kev). The manufacturing method according to claim 4, wherein the ion used in the source ion implantation process is arsenic, and the dose is about 1×10 ¹⁴ to 7× ^{10 14} (ion/cm ² ), and the energy is about 10~. 30 (Kev). The manufacturing method of claim 4, wherein the ion used in the highly doped gate ion implantation process is arsenic, and the dose is about 5× ^{10 14 8} × ^{10 15} (ion/cm ² ), and the energy is about It is 20~55 (Kev).