CN104465381B - A kind of manufacture method of half floating-gate device of planar channeling - Google Patents
A kind of manufacture method of half floating-gate device of planar channeling Download PDFInfo
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- CN104465381B CN104465381B CN201310433668.0A CN201310433668A CN104465381B CN 104465381 B CN104465381 B CN 104465381B CN 201310433668 A CN201310433668 A CN 201310433668A CN 104465381 B CN104465381 B CN 104465381B
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 230000005465 channeling Effects 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 81
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 229920005591 polysilicon Polymers 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims description 69
- 238000007667 floating Methods 0.000 claims description 56
- 238000005530 etching Methods 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000003989 dielectric material Substances 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 238000003475 lamination Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 29
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 239000013049 sediment Substances 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention belongs to semiconductor device processing technology field, and in particular to a kind of manufacture method of half floating-gate device of planar channeling.The present invention prepares half floating-gate device of planar channeling using rear grid technique, after source contact zone and drain contact area is formed, first etch away polysilicon control grid expendable material, then metal control grid material is made to occupy the position of original polysilicon control grid expendable material, form metal control gate, metal control gate can be avoided to be damaged in source contact zone and the high-temperature annealing process in drain contact area, improve the performance of half floating-gate device of planar channeling.Meanwhile the present invention also manufactures the source contact zone of half floating-gate device and drain contact area using self-registered technology, technical process simply and stably, reduces production cost.
Description
Technical field
The invention belongs to semiconductor device processing technology field, and in particular to a kind of system of half floating-gate device of planar channeling
Make method.
Background technology
A kind of half floating-gate device of the planar channeling proposed in Chinese patent 201310006320.3, its profile such as Fig. 1
It is shown, half floating-gate device of planar channeling be included in formed the Semiconductor substrate 600 with the first doping type Nei with
The source region 601 of second of doping type and drain region 602, with the first doping type between source region 601 and drain region 602
Semiconductor substrate forms the channel region of device.The first described doping type is n-type, and second of doping type is p-type, or
Person, the first described doping type are p-type, and second of doping type is n-type.
The gate dielectric layer 603 formed with device on source region 601, drain region 602 and channel region, and drain region 602 it
On gate dielectric layer 603 in formed with a floating boom open area 604.Cover gate dielectric layer 603 and the shape of floating boom open area 604
The Cheng Youyi floating boom 605 with the first doping type as charge-storage node, the impurity in floating boom 605 pass through
Floating boom open area 604 under floating boom 605, which diffuses to, forms diffusion region 802 in drain region 602 so that floating boom 605 and leakage
Area 602 forms pn-junction contact.
Cover the control gate that floating boom 605 is formed formed with second layer insulation film 606, covering second layer insulation film 606
607 exceed floating boom 605, cover and surround floating boom 605 along the length on channel direction.The both sides of control gate 607 formed with
Grid curb wall 608.In the both sides of grid curb wall 608, the ion doped region formed with high concentration in source region 601 and drain region 602,
Respectively as source contact zone 609 and drain contact area 610.Simultaneously device also include by conductive material is formed for by source region 601,
Source electrode 611 that control gate 607, drain region 602, Semiconductor substrate 600 are connected with outer electrode, control grid electrode 612, electric leakage
Pole 613 and the hearth electrode 614 of Semiconductor substrate.
The manufacturer of half floating-gate device of planar channeling as indicated with 1 is also proposed in Chinese patent 201310006320.3
Method, it is half floating-gate device that planar channeling is prepared by first grid technique, that is, source, drain contact is re-formed after being initially formed control gate
Area.At present, metal gates and high dielectric constant material gate medium are in integrated circuits by large-scale use, using metal gate material
Material, which can not only reduce resistance, can also eliminate poly-si depletion effect.But the resistance to elevated temperatures of metal gates is poor,
And need to carry out high annealing after being formed in source, drain contact area in first grid technique, this can cause to damage to the metal gate formed before
Wound.
The content of the invention
In view of this, it is an object of the invention to a kind of manufacture method for half floating-gate device for proposing planar channeling.
The purpose of the present invention is achieved by the following technical programs：
A kind of manufacture method of half floating-gate device of planar channeling, half floating boom device of planar channeling is prepared using rear grid technique
Part, after source contact zone and drain contact area is formed, polysilicon control grid expendable material is first etched away, then makes metal control gate material
Material occupies the position of original polysilicon control grid expendable material, forms metal control gate.
A kind of manufacture method of half floating-gate device of planar channeling as described above, comprises the following steps：
One layer of light is deposited in the semiconductor substrate surface with the first doping type for having formed fleet plough groove isolation structure
Photoresist simultaneously forms figure by photoetching process；
Using photoresist as mask, the both sides of the photoresist in the Semiconductor substrate form mixed with second respectively
The source region of miscellany type and drain region, the Semiconductor substrate with the first doping type between the source region and the drain region
Form the channel region of device；
First layer insulation film is formed on the surface of the Semiconductor substrate, and etches the first layer insulation film and is formed
Floating boom open area, the floating boom open area are located on the drain region, and it is close to the side edge of channel region and institute
The distance for stating channel region is more than 1 nanometer；
One layer of polysilicon with the first doping type is deposited on the exposed surface of established structure；
The position of device floating gate is defined by photoetching process, then there is the first using photoresist as described in mask etching
The polysilicon of doping type, the remaining polysilicon with the first doping type forms the floating boom of device after etching, described floating
Grid at least cover the channel region and the floating boom open area, and by positioned at described floating between the floating boom and the drain region
Floating boom open area under grid forms pn-junction contact；
Exposed first layer insulation film is fallen as mask etching using the floating boom；
Second layer insulation film is formed in the surface deposition of formed structure；
One layer of sacrifice polysilicon material is deposited on the second layer insulation film, and in the sacrifice polysilicon material
On deposit third layer insulation film；
The third layer insulation film and sacrifice polysilicon material are etched by photoetching process and etching technics, remained after etching
Remaining sacrifice polysilicon material forms the polysilicon control grid expendable material of device, and the polysilicon control grid expendable material is on edge
Length on channel direction exceedes the floating boom, and covers and surround the floating boom；
The formed structure of covering is deposited to form the 4th layer of insulation film, and the 4th layer of insulation film carve
To form grid curb wall in the both sides of the polysilicon control grid expendable material, exposure is etched away along the grid curb wall afterwards
The second layer insulation film gone out；
Source and drain etching is carried out in the both sides of the grid curb wall, and the opening position after source and drain etching passes through epitaxy technique shape
Into source contact zone and drain contact area；
The formed structure deposit first layer interlevel dielectric material of covering, is polished until exposing polysilicon control afterwards
Grid expendable material；
The polysilicon control grid expendable material exposed is etched away, it is thin to continue to etch away the second layer insulation exposed afterwards
Film；
Formed structure surface deposition layer 5 insulation film and metal control grid material, be polished afterwards so that
Metal control grid material after polishing occupies the position of original polysilicon control grid expendable material, so as to form metal control
Grid；
The formed structure deposit second layer interlevel dielectric material of covering, then in the second layer interlevel dielectric material and
Contact hole is formed in first layer interlevel dielectric material, and forms source electrode, drain electrode and gate electrode.
A kind of manufacture method of half floating-gate device of planar channeling as described above, etch away the polysilicon control exposed
After grid expendable material, retain second layer insulation film, afterwards on second layer insulation film deposit layer 5 insulation film and
Metal controls grid material.
A kind of manufacture method of half floating-gate device of planar channeling as described above, etch away the polysilicon control exposed
After grid expendable material, retain second layer insulation film, directly deposit metal control gate material on second layer insulation film afterwards
Material.
A kind of manufacture method of half floating-gate device of planar channeling as described above, the first described doping type is n-type,
Second of doping type is p-type；Or the first described doping type is p-type, second of doping type is n-type.
A kind of manufacture method of half floating-gate device of planar channeling as described above, the first layer insulation film, second
Layer insulation film and layer 5 insulation film be respectively silica, silicon nitride, silicon oxynitride, have high dielectric constant value it is exhausted
Edge material is any one in the lamination between them, and the grid curb wall, third layer insulation film and the 4th layer are absolutely
Edge film is respectively any one in silica or silicon nitride.
A kind of manufacture method of half floating-gate device of planar channeling as described above, the Semiconductor substrate be monocrystalline silicon,
Polysilicon is any one in the silicon on insulator.
A kind of manufacture method of half floating-gate device of planar channeling as described above, the opening position after source and drain etching pass through
Epitaxy technique extension SiGe or carbofrax material, to form the source contact zone and drain contact area.
A kind of manufacture method of half floating-gate device of planar channeling as described above, after grid curb wall is formed, without
Source and drain etches and epitaxy technique, directly forms height in source region and drain region by the method for ion implanting in the both sides of grid curb wall
The doped region of concentration, to form the source contact zone and drain contact area.
A kind of manufacture method of half floating-gate device of planar channeling as described above, is carved by photoetching process and etching technics
Lose the third layer insulation film and sacrifice polysilicon material, remaining sacrifice polysilicon material forms the polycrystalline of device after etching
Silicon control gate expendable material, and the polysilicon control grid expendable material surpasses in the length along channel direction only in drain region side
Cross floating boom.
A kind of manufacture method of half floating-gate device of planar channeling of the present invention, planar channeling is prepared using rear grid technique
Half floating-gate device, after source contact zone and drain contact area is formed, first etch away polysilicon control grid expendable material, then make gold
Category control grid material occupies the position of original polysilicon control grid expendable material, forms metal control gate, can avoid metal
Control gate is damaged in source contact zone and the high-temperature annealing process in drain contact area, improves half floating-gate device of planar channeling
Performance.Meanwhile the present invention also manufactures the source contact zone of half floating-gate device and drain contact area, technical process using self-registered technology
Simply and stably, production cost is reduced.
Brief description of the drawings
Fig. 1 is the profile of half floating-gate device of the planar channeling in Chinese patent 201310006320.3；
Fig. 2 to Figure 11 is half floating boom of the manufacture method manufacture planar channeling of half floating-gate device of the planar channeling of the present invention
The process chart of one embodiment of device；
Figure 12 is the plane ditch of the double memory cell of the manufacture method manufacture of half floating-gate device of the planar channeling of the present invention
The profile of one embodiment of the half floating-gate device structure in road；
Figure 13 is the manufacture method manufacture of half floating-gate device of the planar channeling of the present invention by the half of multiple planar channelings
The circuit diagram of the memory cell array of floating-gate device composition.
Embodiment
The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings.In figure, for convenience
Illustrate, be exaggerated layer and the thickness in region, shown size does not represent actual size.Reference chart is that the idealization of the present invention is implemented
The schematic diagram of example, the embodiment shown in the present invention should not be considered limited to the given shape in region shown in figure, but wrap
Include resulting shape, such as deviation caused by manufacture.Such as the curve for etching to obtain generally has the characteristics of bending or be mellow and full,
But in embodiments of the present invention, represented with rectangle, the expression in figure is schematical, but this should not be construed as limiting this
The scope of invention.In the following description, used term substrate can be understood as including just in technique processing simultaneously
Semiconductor substrate, it may be included in other film layers prepared thereon.
Described below is the manufacture method manufacture plane using a kind of half floating-gate device of planar channeling of the present invention
The technological process of one embodiment of half floating-gate device of raceway groove.
First, as shown in Fig. 2 forming fleet plough groove isolation structure（Not shown in figure）There is the first doping type
Semiconductor substrate 200 one layer of photoresist 301 of surface deposition and mask, exposure, development form figure, then noted by ion
Enter technique in the Semiconductor substrate 200, the both sides of photoetching offset plate figure that are formed are formed with second doping type respectively
Source region 201 and drain region 202, and between source region 201 and drain region 202 there is the first doping type Semiconductor substrate to be formed
The channel region of device.Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or be silicon on insulator.The first doping class
Type is p-type, and second of doping type is n-type；Or it is corresponding, the first doping type is n-type, and second of doping type is p
Type.
After divesting photoresist 301, in the superficial growth first layer insulation film 203 of Semiconductor substrate 200, first layer insulation
Film 203 can be silica, silicon nitride, silicon oxynitride, the insulating materials with high dielectric constant value or be they it
Between lamination.Then one layer of photoresist is deposited on first layer insulation film 203 and floating boom is defined by photoetching process and is opened
The position in mouth region domain 204, the first layer insulation film 203 exposed is then fallen as mask etching using photoresist and opened with forming floating boom
Mouth region domain 204, divest after photoresist as shown in Figure 3.Floating boom open area 204 is located on drain region 202, and it is close to raceway groove
The side edge in area and the distance of channel region are more than 1 nanometer.
Next, depositing one layer of polysilicon with the first doping type on the exposed surface for formed structure, connect
And one layer of photoresist is deposited on the polysilicon with the first doping type formed and is defined by photoetching process
The position of the floating boom of device, the polysilicon with the first doping type exposed is then fallen as mask etching using photoresist,
The remaining polysilicon with the first doping type forms the floating boom 205 of device after etching.Then with floating boom 205 be mask after
It is continuous to etch away the first layer insulation film 203 exposed, divest after photoresist as shown in Figure 4.Floating boom 205 should at least cover raceway groove
Area and floating boom open area 204.Impurity in floating boom 205 can pass through the floating boom open area 204 under floating boom 205
Formation diffusion region 402 in drain region 202 is diffused to, and pn-junction is formed with drain region 202 by the floating boom 205 of floating boom open area 204 and connect
Touch.
Next, the structure deposit second layer insulation film 206 that covering is formed, second layer insulation film 206 can be
Silica, silicon nitride, silicon oxynitride, the insulating materials with high dielectric constant value are the lamination between them.Then
One layer of sacrifice polysilicon material is deposited on second layer insulation film 206, and the 3rd is deposited on sacrifice polysilicon material
Layer insulation film 401, third layer insulation film 401 are silica or are silicon nitride.Then photoetching process and etching are passed through
Technique etches formed third layer insulation film 401 and sacrifice polysilicon material, remaining sacrifice polysilicon material after etching
Polysilicon control grid expendable material 207 is formed, polysilicon control grid expendable material 207 should exceed along the length on channel direction
Floating boom 205, and cover and surround floating boom 205, divest after photoresist as shown in Figure 5 a.Optionally, photoetching process and etching are passed through
Technique etches third layer insulation film 401 and sacrifice polysilicon material, and remaining sacrifice polysilicon material forms device after etching
Polysilicon control grid expendable material 207, polysilicon control grid expendable material 207 along channel direction only in drain region 202 1
The length of side exceedes floating boom 205, as shown in Figure 5 b.
Deposit to form the 4th layer of insulation film next, covering formed structure, and the to being formed the 4th layer of insulation
Film carve to form grid curb wall 208 in the both sides of polysilicon control grid expendable material 207, afterwards along grid curb wall
208 continue to etch away the second layer insulation film 206 exposed, as shown in Figure 6.Grid curb wall 208 can be silica or
Person is silicon nitride, and the 4th layer of insulation film is silica or silicon nitride.
Next, source and drain etching is carried out in the both sides of the grid curb wall 208 formed, and the opening position after source and drain etching
By epitaxy technique extension SiGe or carbofrax material, to form source contact zone 209 and drain contact area 210, such as Fig. 7 a institutes
Show.Optionally, can be etched without source and drain and epitaxy technique, and directly by the method for ion implanting in the He of source region 201
The ion doped region of high concentration is formed in drain region 202 respectively, to form source contact zone 209 and drain contact area 210, such as Fig. 7 b institutes
Show.
Next, as shown in Figure 7a, the formed structure deposit first layer interlevel dielectric material 211 of covering, and passing through
Mechanical polishing technology is learned to be polished the first layer interlevel dielectric material 211 formed until exposing polysilicon control grid sacrifice
Material 207, as shown in Figure 8.Then the polysilicon control grid expendable material 207 exposed is etched away, and continues to etch away exposure
The second insulation film 206 layer by layer, as shown in Figure 9.Then layer 5 insulation film is formed in the surface deposition of formed structure
212 and metal control grid material, carry out chemically-mechanicapolish polishing that make it that metal after polishing controls grid material to occupy original afterwards
The position of polysilicon control grid expendable material 207, to form metal control gate 213, as shown in Figure 10.Optionally, can not carve
Eating away second layer insulation film 206, and directly to form layer 5 exhausted for deposit after polysilicon control grid expendable material 207 is etched away
Edge film 212 and metal control grid material, or, second layer insulation film 206 is not etched away, and is etching away polysilicon control
Second layer insulation film 206 is directly covered after grid expendable material 207 and forms metal control grid material.Layer 5 insulation film 212
It can be silica, silicon nitride, silicon oxynitride, the insulating materials with high-k or be lamination between them.
Finally, as shown in figure 11, formed structure deposit second layer interlevel dielectric material 214 is covered, then in institute's shape
Into second layer interlevel dielectric material 214 and first layer interlevel dielectric material 211 in form contact hole, and formed source electrode 215,
Drain electrode 217 and gate electrode 216, the technique are the technique known to industry.
Figure 12 is the double memory cell using a kind of manufacture method manufacture of half floating-gate device of planar channeling of the present invention
Planar channeling half floating-gate device structure one embodiment, it is by half floating boom of two planar channelings as shown in figure 11
Device is formed, and half floating-gate device of two planar channelings is into symmetrical structure.As shown in figure 12, two planar channelings
Half floating-gate device has shared drain region 202, drain contact area 210 and drain electrode 217, half floating boom of the planar channeling of double memory cell
Device architecture can store the data of two.
Figure 13 is such as to be schemed by multiple using what a kind of manufacture method of half floating-gate device of planar channeling of the present invention manufactured
The circuit diagram of the memory cell array of the half floating-gate device composition of planar channeling shown in 11.As shown in figure 13, a plurality of
In the line SL 603a-603b of source, wherein any one is connected with the source electrode of multiple half floating-gate devices.In a plurality of wordline WL 601a-
In 601d, wherein any one is connected with the control gate in multiple half floating-gate devices.In multiple bit lines BL 602a-602d,
Wherein any one is connected with the drain electrode of multiple half floating-gate devices.Any one in multiple bit lines BL 602a-602d can with it is more
The combination of any one in bar wordline WL 601a-601d can choose a half independent floating-gate device.Wordline WL 601a-
601d can be chosen by word line address de-coder 901, and bit line BL 602a-602d can select control module 902 by a bit line
Choose, bit line selection control module 902 generally comprises an address decoder, a MUX and one group of sensing amplification
Device.Meanwhile source line SL 603a can be connected with 603b with common source line or a source line options control module.
As described above, without departing from the spirit and scope of the invention, can also form many has very big difference
Embodiment.It should be appreciated that except as defined by the appended claims, the invention is not restricted to described specific in the description
Example.
Claims (9)
- A kind of 1. manufacture method of half floating-gate device of planar channeling, it is characterised in that：Planar channeling is prepared using rear grid technique Half floating-gate device, after source contact zone and drain contact area is formed, first etch away polysilicon control grid expendable material, then make gold Category control grid material occupies the position of original polysilicon control grid expendable material, forms metal control gate, specifically includes as follows Step：Formed in the semiconductor substrate surface with the first doping type for having formed fleet plough groove isolation structure with second The source region of doping type and drain region, the lining of the semiconductor with the first doping type between the source region and the drain region Bottom forms the channel region of device；First layer insulation film is formed on the surface of the Semiconductor substrate, and etches the first layer insulation film and forms floating boom Open area, the floating boom open area are located on the drain region, and it is close to the side edge of channel region and the ditch The distance in road area is more than 1 nanometer；One layer of polysilicon with the first doping type is deposited on the exposed surface of established structure；The position of device floating gate is defined by photoetching process, then using photoresist as described in mask etching there is the first to adulterate The polysilicon of type, the remaining polysilicon with the first doping type forms the floating boom of device after etching, and the floating boom is extremely Cover the channel region and the floating boom open area less, and between the floating boom and the drain region by positioned at the floating boom it Under floating boom open area formed pn knot contact；Exposed first layer insulation film is fallen as mask etching using the floating boom；Second layer insulation film is formed in the surface deposition of the structure formed；One layer of sacrifice polysilicon material is deposited on the second layer insulation film, and on the sacrifice polysilicon material Deposit third layer insulation film；It is remaining after etching by photoetching process and the etching technics etching third layer insulation film and sacrifice polysilicon material Sacrifice polysilicon material forms the polysilicon control grid expendable material of device, and the polysilicon control grid expendable material is along raceway groove Length on direction exceedes the floating boom, and covers and surround the floating boom；The formed structure of covering deposits to form the 4th layer of insulation film, and the 4th layer of insulation film is carried out back quarter with The both sides of the polysilicon control grid expendable material form grid curb wall, etch away what is exposed along the grid curb wall afterwards Second layer insulation film；Source and drain etching is carried out in the both sides of the grid curb wall, and the opening position after source and drain etching forms source by epitaxy technique Contact zone and drain contact area；The formed structure deposit first layer interlevel dielectric material of covering, is polished sacrificial up to exposing polysilicon control grid afterwards Domestic animal material；The polysilicon control grid expendable material exposed is etched away, it is thin to continue to etch away the second layer insulation exposed afterwards Film；Grid material is controlled in the surface deposition layer 5 insulation film and metal of formed structure, is polished afterwards so that polishing Metal control grid material afterwards occupies the position of original polysilicon control grid expendable material, so as to form metal control gate；Cover The formed structure deposit second layer interlevel dielectric material of lid, then in the second layer interlevel dielectric material and first layer interlayer Contact hole is formed in dielectric material, and forms source electrode, drain electrode and gate electrode.
- A kind of 2. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Etch away After the polysilicon control grid expendable material exposed, retain second layer insulation film, formed sediment afterwards on second layer insulation film Product layer 5 insulation film and metal control grid material.
- A kind of 3. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Etch away After the polysilicon control grid expendable material exposed, retain second layer insulation film, it is straight on second layer insulation film afterwards Connect deposit metal control grid material.
- A kind of 4. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Described A kind of doping type is n types, and second of doping type is p types；Or the first described doping type is p types, institute It is n types to state second of doping type.
- A kind of 5. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Described One layer of insulation film, second layer insulation film and layer 5 insulation film are respectively silica, silicon nitride, silicon oxynitride, tool There is the insulating materials of high dielectric constant value or for any one in the lamination between them, the grid curb wall, third layer Insulation film and the 4th layer of insulation film are respectively any one in silica or silicon nitride.
- A kind of 6. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Described half Conductor substrate is monocrystalline silicon, polysilicon or is any one in silicon on insulator.
- A kind of 7. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：In source Opening position after water clock erosion is by epitaxy technique extension SiGe or carbofrax material, to form the source contact zone and miss Touch area.
- A kind of 8. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：In shape Into after grid curb wall, without source and drain etching and epitaxy technique, the method for directly passing through ion implanting in the both sides of grid curb wall The doped region of high concentration is formed in source region and drain region, to form the source contact zone and drain contact area.
- A kind of 9. manufacture method of half floating-gate device of planar channeling according to claim 1, it is characterised in that：Pass through light Carving technology and etching technics etch the third layer insulation film and sacrifice polysilicon material, and remaining polysilicon is sacrificial after etchingDomestic animal material forms the polysilicon control grid expendable material of device, and the polysilicon control grid expendable material is along raceway groove side The length only in drain region side exceedes floating boom upwards.
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| PCT/CN2014/070278 WO2014108065A1 (en) | 2013-01-09 | 2014-01-08 | Planar channel semiconductor device and manufacturing method therefor |
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| CN112864221B (en) * | 2019-11-27 | 2022-04-15 | 苏州东微半导体股份有限公司 | Semiconductor super junction power device |
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| CN112908998B (en) * | 2021-03-25 | 2022-10-21 | 复旦大学 | Manufacturing method of semi-floating gate memory and semi-floating gate memory |
| CN113140624A (en) * | 2021-03-29 | 2021-07-20 | 上海华力集成电路制造有限公司 | Structure and preparation method of integrated high-K metal gate and oxide polysilicon gate |
| CN113471294B (en) * | 2021-07-27 | 2022-06-17 | 武汉新芯集成电路制造有限公司 | Manufacturing method of semi-floating gate transistor |
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