CN101826487B - Manufacturing method of flash memory component - Google Patents
Manufacturing method of flash memory component Download PDFInfo
- Publication number
- CN101826487B CN101826487B CN2009100045069A CN200910004506A CN101826487B CN 101826487 B CN101826487 B CN 101826487B CN 2009100045069 A CN2009100045069 A CN 2009100045069A CN 200910004506 A CN200910004506 A CN 200910004506A CN 101826487 B CN101826487 B CN 101826487B
- Authority
- CN
- China
- Prior art keywords
- drain region
- grid structures
- semiconductor substrate
- implanting ions
- memory component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention relates to a manufacturing method of a flash memory component, which comprises the following steps: providing a semiconductor substrate; forming two gate structures on the substrate; carrying out an ion implantation process to respectively form a first source region in the substrate at two outer sides of the two gate structures, and carrying out an ion implantation process in the substrate between the two gate structures to form a first drain region; carrying out a pocket type implantation process in the substrate between the two gate structures to form two doped regions at two sides of the first drain region; positioning an L-shaped clearance wall above the first drain region; carrying out an ion implantation process to form a second drain region below the first drain region, wherein the first drain region and the second drain region have abrupt junction appearance compared with the first source regions; and forming a potential barrier plug on the first drain region. The manufacturing method of the memory component of the invention can reduce the drain reading voltage, and the pocket type implantation process is used for improving the short channel effect.
Description
Technical field
The invention relates to a kind of manufacturing approach of internal memory, especially about the manufacturing approach of a kind of flash memory (flash memory) assembly.
Background technology
Along with the progress of semiconductor process techniques, the technology of memory subassembly also strides into nanometer era.The micro size of components not only can improve the integrated circuit density of unit are, and also the current driving ability of lifting subassembly itself simultaneously is to kill two birds with one stone, yet in fact really not so.(Short Channel Effects SCE) with the gate pole leakage current, makes and comes the usefulness of the lifting subassembly more and more difficult that becomes with reduction passage length and micro thickness of grid oxide layer to get into the short-channel effect that nanometer era brings.
With lightly doped drain (Lightly Doped Drain, LDD), can improve assembly breakdown voltage (Breakdown Voltage), improve critical voltage characteristic, reduce hot carrier effect (Hot CarrierEffect).Though lightly doped drain has reduced the high electric field of drain junction, the reliability of effective lifting subassembly, along with dwindling gradually of size of components, penetration (Punch Through) phenomenon is more serious.Therefore, pocket type implantation process (Pocket Implant) structure just is suggested the short-channel effect that improves this penetration phenomenon.Though yet pocket type implantation process is improved the short channel effect of assembly,, therefore have the phenomenon of drain current degeneration (IDSAT Degradation) because of the highly doped cause of channel.
Therefore how to improve the doping level in this source electrode, drain electrode and pocket type implantation process district and connect face outward appearance (Junction Profile), quite important to improve above shortcoming and to obtain the balance point that makes this assembly obtain peak efficiency with regard to what become.
Summary of the invention
Main purpose of the present invention is providing a kind of manufacturing approach of flash memory component; The generation that makes carrier is near the connect face place of source/drain in Semiconductor substrate; And can promote hot injection efficiency and can and then reduce drain voltage improve short channel effect (Short Channel Effects, SCE).
For reaching above-mentioned purpose, the present invention provides a kind of manufacturing approach of flash memory component, and it comprises: semi-conductive substrate is provided; Form two grid structures in this Semiconductor substrate top; Carry out an implanting ions technology and in this Semiconductor substrate in two outsides of this two grid structure, form one first source area respectively; Carry out an implanting ions technology again in this Semiconductor substrate between this two grid structure and form lightly doped one first drain region, wherein the doping content of this 2 first source area and this first drain region is inequality; In this Semiconductor substrate between this two grid structure, utilize a pouch-type cloth to plant (Pocket Implant) technology and form two doped regions in these both sides, first drain region; Between this two grid structure, form a L shaped clearance wall respectively, this two L shaped clearance wall is positioned at this top, first drain region; Deposition one oxide layer on this L type clearance wall; This oxide layer of etching is to this surface, first drain region; On this two grid structure, respectively form one and aim at metal silicide layer (salicide) automatically with this surface, first drain region; Carry out an implanting ions to form one second drain region in below, this first drain region, wherein this first and second drain region has the precipitous face that a connects outward appearance compared to this first source area; On this first drain region, form a potential barrier plug (barrier plug).
By this, the manufacturing approach of memory subassembly of the present invention can reduce drain reading voltage and utilize pocket type implantation process improve short-channel effect (Short Channel Effects, SCE).
Description of drawings
Fig. 1 is the fragmentary cross-sectional view of flash memory component of the present invention;
Fig. 2 forms a mask for the present invention, carries out the flash memory component profile of one source pole implanting ions processing step on Semiconductor substrate;
Fig. 3 carries out the flash memory component profile of an implanting ions processing step for the present invention;
Fig. 4 carries out the flash memory component profile of pouch-type implanting ions processing step for the present invention;
Fig. 5 forms the flash memory component profile of oxide layer wall, silicon nitride layer and deposited oxide layer processing step for the present invention;
Fig. 6 carries out the flash memory component profile of etching technics step for the present invention;
Fig. 7 forms an automatic flash memory component profile of aiming at the metal silicide layer processing step for the present invention;
Fig. 8 deposits the flash memory component profile of a contact hole etching stop layer process step on Semiconductor substrate for the present invention;
Fig. 9 forms the flash memory component profile of flash memory component processing step for the present invention.
Drawing reference numeral:
100 Semiconductor substrate
102 grid structures
The 102a tunnel oxide
The 102b floating gate
The 102c dielectric layer
The 102d control gate
103 passages
105 source electrode implanting ions technologies
106 implanting ions technologies
202 masks
204 first source areas
302 first drain regions
402 pouch-type implanting ions technologies
404 pouch-type implanting ions technologies
406 first doped regions
408 second doped regions
501 first oxide layer walls
502 second silicon nitride layers
504 oxide layers
602a～602d oxide layer spacer thing
The L shaped clearance wall of 604a
The L shaped clearance wall of 604b
606 drain ion cloth are planted technology
608 second drain regions
702a～702c aims at metal silicide layer automatically
802 contact hole etchings stop layer
Embodiment
For fully understanding the object of the invention, characteristic and effect, now through following concrete embodiment, and cooperate appended graphicly, the present invention is done a detailed description, after being illustrated in.In these different graphic and embodiment, identical assembly will use identical symbol.
At first with reference to Fig. 1, the fragmentary cross-sectional view of flash memory component of the present invention.Be shown among the figure and be formed with two grid structures 102 on the semi-conductive substrate 100, said these grid structures 102 comprise respectively: tunnel oxide 102a (tunnel oxide layer), floating gate 102b (floating gate), dielectric layer 102c, control gate 102d (control gate) and form a path 10 3.These Semiconductor substrate 100 materials can be silicon, SiGe, silicon-on-insulator (silicon on insulator; SOI), coated insulating layer SiGe (silicon germaniumon insulator; SGOI), coated insulating layer germanium (germanium on insulator, GOI); In present embodiment, this Semiconductor substrate 100 is a silicon substrate.
Then please with reference to Fig. 2, on this Semiconductor substrate 100, form a mask 202, the path 10 3 that this two grid structure is 102 can be contained by this mask 202.Carry out one source pole implanting ions technology 105, in this Semiconductor substrate 100 in two outsides of this two grid structure 102, form one first source area 204 respectively.With the P type is among the flash memory component embodiment of substrate, and the ion that uses in this source electrode implanting ions technology 105 is arsenic, and dosage is about 1 * 1014～8 * 1015 (ion/cm2), and energy is about 10～70 (Kev).
Then please be simultaneously with reference to Fig. 3; Carry out an implanting ions technology 106; Utilize lightly doped drain (Lightly Doped Drain in this Semiconductor substrate 100 between this two grid structure 102; LDD) cloth is planted and is formed one first drain region 302, and said these first source areas 204 are asymmetric shape with this first drain region 302.With the P type is among the flash memory component embodiment of substrate, and the ion that uses in this implanting ions technology is arsenic, and dosage is about 1 * 10
14～1 * 10
15(ion/cm2), energy is about 10～30 (Kev).
Then please with reference to Fig. 4, at first carry out a pouch-type implanting ions technology (Pocket Implant) 402, the side in this first drain region 302 forms one first doped region 406.Carry out a pouch-type implanting ions technology 404 again, the opposite side in this first drain region 302 forms one second doped region 408.This pouch-type implanting ions technology 402 and pouch-type implanting ions technology 404 only incident direction are different, and all the other implanting ions parameters are all identical haply, and and this Semiconductor substrate 100 between incident angle be about 15 °～60 °.Next said these pouch-type implanting ions can limit drain ion cloth and plant in the technology sideways diffusion of ion.The P type is among the flash memory component embodiment of substrate, and the ion that uses in this pouch-type implanting ions technology 402,404 is boron or boron difluoride (B or BF2), and dosage is about 5 * 10
12～5 * 10
14(ion/cm2), energy is about 10～60 (Kev).
Then, form one first oxide layer wall 501 and one second silicon nitride layer 502, utilize a known deposition technique more please with reference to Fig. 5, as: source gas comprises NH
3And SiH
4Chemical vapor deposition method (CVD), rapid thermal annealing chemical vapor deposition (rapid thermal chemical vapor deposition, RTCVD), (atomic layer deposition ALD), deposits an oxide layer 504 to ald.The thickness of the oxide layer 504 can be between 200
to 1500
In the present embodiment, the 750
Then please utilize dry type or wet etching to carry out an etching technics this oxide layer 504 is etched into a plurality of oxide layer spacer things (Oxide spacer) 602a～602d simultaneously with reference to Fig. 5 and Fig. 6.Carry out another etching technics again, this second silicon nitride layer 502 is etched into two L shaped clearance wall (L-shape) 604a, 604b and this first oxide layer wall 501 of etching., drain ion cloth forms one second drain regions 608 302 times in this first drain region after planting technology 606; Wherein this first drain region 302 is precipitous with the face that the connects outward appearance (junction profile) of this second drain region 608, and different with the face that smoothly the connects outward appearance of said these first source areas 204.So, because the drain region does not have the face that smoothly the connects outward appearance of source area, make the generation of hot carrier can promote hot carrier injection efficiency near meeting the face place.
Then see also Fig. 7, form in the surface one by cobalt (cobalt, Co), titanium (titanium; Ti), nickel (nickel; Ni) or molybdenum (molybdenum, the metal silicide layer that Mo) is constituted, and carry out a quick thermal annealing process technology; Automatically aim at metal silicide layer 702a, 702b and 702c (salicide layer) to form one, in order to reduce dead resistance lifting subassembly actuating force.
Then see also Fig. 8; The above-mentioned steps that continues, on this Semiconductor substrate 100 deposition one contact hole etching stop layer 802 (contact etch stop layer, CESL); It can be SiN, silicon oxynitride (oxynitride), silica (oxide) etc., is SiN in the present embodiment.This contact hole etching stop layer 802 deposit thickness be 100
to 1500
therefore, can be efficient this contact hole etching be stopped stress transfer that layer 802 produces to this path 10 3 by next-door neighbour's this two L shaped clearance wall 604a, 604b and this oxide layer spacer thing 602b, 602c.Then, and an interlayer dielectric substance layer 804 (inter-layerdielectric, ILD), as: silicon dioxide SiO2 is deposited on this contact hole etching and stops on the layer 802.
See also Fig. 9 at last, utilize known photo-resistive mask technology, with a contact hole 902 from this interlayer dielectric layer 804 non-equal tropism etch into this contact etching stop layer 802.Deposit a potential barrier plug 904 (barrier plug) again and form a flash memory component as shown in Figure 9.
The present invention discloses with preferred embodiment hereinbefore, it will be understood by those skilled in the art that so this embodiment only is used for describing a part of structure of internal storage location of the present invention, and should not be read as restriction scope of the present invention.It should be noted,, all should be made as and be covered by in the category of the present invention such as with the variation and the displacement of this embodiment equivalence.Therefore, protection scope of the present invention is when being as the criterion with what claim defined.
Claims (2)
1. the manufacturing approach of a flash memory component is characterized in that, said method comprises:
Semi-conductive substrate is provided;
Form two grid structures in said Semiconductor substrate top;
Carry out an implanting ions technology; In the said Semiconductor substrate in two outsides of said two grid structures, form one first source area respectively; Carry out an implanting ions technology again in the said Semiconductor substrate between said two grid structures and form lightly doped one first drain region, wherein the doping content of two said first source areas and said first drain region is inequality;
In the said Semiconductor substrate between said two grid structures, utilize a pouch-type cloth to plant (Pocket Implant) technology and form two doped regions in both sides, said first drain region;
Two inboards between said two grid structures form a L shaped clearance wall respectively, and two said L shaped clearance walls are positioned at top, said first drain region;
Carry out an implanting ions forming one second drain region in below, said first drain region, wherein said first and second drain region has the precipitous face that a connects outward appearance compared to two said first source areas;
Form a potential barrier plug in top, said first drain region.
2. manufacturing approach as claimed in claim 1 is characterized in that, the step that two inboards between said two grid structures form a L shaped clearance wall respectively more comprises:
Form one first oxide layer wall and one second silicon nitride layer in regular turn;
Deposition one oxide layer on said second silicon nitride layer;
The said oxide layer of etching, the said first oxide layer wall, and said second silicon nitride layer to this surface, first drain region, to form two said L shaped clearance walls;
More comprise after in the said implanting ions that carries out with the step that forms said second drain region in below, said first drain region:
On said two grid structures, respectively form one and aim at metal silicide layer automatically with surface, said first drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100045069A CN101826487B (en) | 2009-03-06 | 2009-03-06 | Manufacturing method of flash memory component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100045069A CN101826487B (en) | 2009-03-06 | 2009-03-06 | Manufacturing method of flash memory component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101826487A CN101826487A (en) | 2010-09-08 |
| CN101826487B true CN101826487B (en) | 2012-05-23 |
Family
ID=42690319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100045069A Active CN101826487B (en) | 2009-03-06 | 2009-03-06 | Manufacturing method of flash memory component |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101826487B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206579B (en) * | 2014-06-19 | 2018-07-20 | 中芯国际集成电路制造(上海)有限公司 | A method of making flash memory |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838343B2 (en) * | 2003-03-11 | 2005-01-04 | Powerchip Semiconductor Corp. | Flash memory with self-aligned split gate and methods for fabricating and for operating the same |
-
2009
- 2009-03-06 CN CN2009100045069A patent/CN101826487B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6838343B2 (en) * | 2003-03-11 | 2005-01-04 | Powerchip Semiconductor Corp. | Flash memory with self-aligned split gate and methods for fabricating and for operating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101826487A (en) | 2010-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101605150B1 (en) | In situ formed drain and source regions including a strain inducing alloy and a graded dopant profile | |
| US8318571B2 (en) | Method for forming P-type lightly doped drain region using germanium pre-amorphous treatment | |
| TW200402834A (en) | Method of forming a semiconductor device in a semiconductor layer and structure thereof | |
| CN101599459B (en) | Fabricating method of semiconductor device | |
| CN114267722A (en) | Semiconductor device and method of forming the same | |
| CN102044438B (en) | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof | |
| CN102983104B (en) | The manufacture method of CMOS transistor | |
| CN101826525B (en) | NOR type flash memory structure with double ion implantation and manufacturing method thereof | |
| CN101826487B (en) | Manufacturing method of flash memory component | |
| CN103094113B (en) | NMOS formation method, CMOS formation method | |
| CN101483140A (en) | MOS transistor manufacturing method capable of reducing leakage current | |
| CN205282480U (en) | FS type IGBT device with double buffering layer | |
| US20100230738A1 (en) | Nor flash memory structure with highly-doped drain region and method of manufacturing the same | |
| CN101826524B (en) | NOR type flash memory structure with highly doped drain region and manufacturing method thereof | |
| US8012825B2 (en) | Method of manufacturing the double-implant nor flash memory structure | |
| CN103377935B (en) | The manufacture method of MOS transistor | |
| CN102024763B (en) | Method for manufacturing NOR flash memory with phosphorus and arsenic ion injection | |
| TWI414045B (en) | Method of manufacturing flash memory element | |
| US20100227447A1 (en) | Method of manufacturing flash memory device | |
| CN102468162A (en) | Production method for n-channel metal oxide semiconductor (NMOS) field effect transistor | |
| CN101989549B (en) | Method for manufacturing n-metal-oxide-semiconductor (NMOS) transistor | |
| CN102054698B (en) | Method for improving threshold voltage of semiconductor device | |
| TWI381491B (en) | Manufacturing Method of NOR - type Flash Memory with Phosphorus Arsenic Ion Planting | |
| KR20090044550A (en) | Method for manufacturing semiconductor device | |
| CN102034762A (en) | Manufacturing method of NOR flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |