201011897 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種N0R型快閃記憶體結構及其製造 方法’更特別的是關於—種具有雙重離子植入之N〇r型快 閃記億體（flash mem〇17)結構及其製造方法。 【先前技術】 〇 快閃記憶體是一種非揮發性(non_volatile)的記憶體，即 在無外部電源供電時，也能夠保存資訊内容，這使得裝置 本身不需要浪費電力在資料的記憶上，再加上快閃記憶體 也具備重複讀寫、_小、容量高及便於攜㈣特性，這 使得快閃記憶體特別適合使用在攜帶式的裝置上。目前 型快閃記憶體應用的範圍，除了個人電腦上的主機板 會利用NOR型快閃記憶體儲存m〇s資料夕卜，手機、手持 裝^會使用N〇R型快閃記憶體來存放系統資料，籍由其 商速的讀取速度，滿足手持裝置的開機需求。 隨:科技的進步，快閃記憶體的製程技術也跨入奈米 :::為了加速元件的操作速率，增加元件的積集度，和 和氧乍電壓等等考量的因素’元件閘極的通道長度 ==層厚度的微較勢。_元件 可 “早位面積的積體電路密度，亦 電流驅動能力，可謂一兴ρ π η棱升70件本身的 件閘;&綠办 ,+ Μ于，W而事實上並非如此。元 什聞極線寬已從以往的微半 6 (10-9八Μ Ρ Α卡（公尺）縮減到現在的奈米 …士著兀件的微縮及閘極線寬的縮短卻使得短通 5 201011897 道效應（Short Channel Effect)越來越嚴重，而為避免短通道 效應對元件造成影響，其中之一解決方法即是降低源極/汲 極的接面深度來達成。 以輕摻雜汲極（Lightly Doped Drain, LDD)而言，可 扼面元件的朋潰電壓（Breakdown Voltage )、改善臨界電壓 的特性、降低熱载子效應（Hot Carrier Effect)。雖然輕摻 雜及極降低了汲極接面的高電場，有效的提升元件的可靠 度，然而輕摻雜汲極造成的淺接面深度卻容易在進行接觸 孔蝕刻時，造成汲極被挖穿的現象，而破壞了記憶體的結© 構：為了避免此-情形的發生’會再利用一高擦雜離子佈 植製程佈植—高摻雜練區，並與-輕掺脑極區重叠。 $此，使侍在汲極區接面深度降低以改善短通道效應的同 子亦鲍避免餘刻—接觸孔時，對該輕摻雜汲極區造成挖 穿的現象。然而’請參閱第十圖，係習知的快閃記憶體結 構“面2圖中於二閘極結構13()之間，此種離子佈植方 式^使知„亥幸！摻雜〉及極區132與該高摻雜汲Η201011897 IX. Description of the Invention: [Technical Field] The present invention relates to a NOR type flash memory structure and a method of fabricating the same, and more particularly to a N〇r type flash flash with double ion implantation Body (flash mem〇 17) structure and its manufacturing method. [Prior Art] 〇 Flash memory is a non-volatile memory, that is, it can save information content when there is no external power supply, which makes the device itself not waste power on the memory of the data. In addition, the flash memory also has the characteristics of repeated reading and writing, _small, high capacity and easy to carry (4), which makes the flash memory particularly suitable for use on portable devices. At present, the range of flash memory applications, in addition to the motherboard on the personal computer will use the NOR flash memory to store m〇s data, mobile phones, handheld devices will use N〇R flash memory to store The system data, based on its reading speed of the commercial speed, meets the booting requirements of the handheld device. With the advancement of technology, the flash memory process technology has also entered the nanometer::: In order to accelerate the operating rate of components, increase the component's accumulation, and the factors such as the oxygen voltage, etc. Channel length == micro-potential of layer thickness. _ components can be "earth area of the integrated circuit density, but also the current drive capability, can be described as a ρ π η edge rise 70 pieces of its own gate; & green, + Μ, W and in fact not the case. The width of the line has been reduced from the previous micro 6 (10-9 Μ Α Leica (meter) to the current nano... The miniature of the 兀 及 and the shortening of the gate width make the short pass 5 201011897 The Short Channel Effect is getting more and more serious. To avoid the short channel effect affecting the components, one of the solutions is to reduce the junction depth of the source/drain. (Lightly Doped Drain, LDD), the Breakdown Voltage of the kneading component, the improvement of the threshold voltage, and the reduction of the Hot Carrier Effect. Although lightly doped and extremely reduced in bungee The high electric field of the junction surface effectively improves the reliability of the component. However, the shallow junction depth caused by the lightly doped gate is easy to cause the drain hole to be punctured when the contact hole is etched, and the memory is destroyed. Structure: In order to avoid this - the occurrence of the situation It will be reused with a high-wipe ion implantation process—highly doped zone and overlapped with the lightly doped brain pole. $This reduces the depth of the junction in the bungee zone to improve the short channel effect. The son also avoids the residual—the phenomenon of the tunneling of the lightly doped bungee region when contacting the hole. However, please refer to the tenth figure, which is a conventional flash memory structure. Between the polar structures 13(), this ion implantation method enables the knowledge of "Hei Fu! Doping" and the polar region 132 and the highly doped 汲Η
面處136的電性遠姓線j水& 牧G 連…變侍相當脆弱。由於為了避免短通道 應的發生，如? .. 工*雜汲極區越做越薄，將使得脆弱的電性 因此，重進而影響快閃記憶體中載子的遷移率。 德 在避免紐通道效應及避免輕摻雜汲極區被挖穿 性紗，輕摻驗㈣與高摻雜汲極區接面處的電 。錢體巾载子的遷料不會降低即為本發明的 201011897 【發明内容】 本發明的主要目的在提供一種具有雙重離子植入之 NOR型快閃記憶體結構及其製造方法。於改善短通道效應 及避免輕摻雜汲極區在蝕刻時容易被挖穿的現象之後，加 強輕摻雜汲極區與高摻雜汲極區接面處的電性連結，使記 憶體中載子的遷移率不會降低。 為達上述目的，本發明係提供一種具有雙重離子植入 ❹ ❹ 之NOR型快閃記憶體結構，其包含：一半導體基底，於其 上具有二閘極結構；一輕摻雜汲極區，位於該二閘極結構 之間的該半導體基底中；一第一源極區，係位於該二閑極 結構之二外側的該半導體基底中；其中’該第一源極區於 該半導體基底中之接面深度較該輕摻雜沒極區深；一高撞 雜汲極區，係位於該二閘極結構間的該半導體基底中，並 與該輕摻雜沒極區重疊，且該高摻㈣極區於該半導體基 底中的接面深度較該輕摻雜没極區深；一鱗接雜汲極區， 係位於該二閘極結構間的該半導體基底中，並與該高接雜 ，極區^該，摻雜錄區重疊；二自動對準金屬石夕化物 層’係为別為於該二閘極結構上方；及 隔該二閘極結構。 羊插基係刀 為達上述目的，本發㈣提供—種財 :麵型快閃記憶體結構的製造方法，其包含::： 導體基底;於該半導體基底上方形成二心構= 閘極結構之間的該半導體基底中進行一：，於該- 程以形成一輕摻#、％ β p . /雜離子佈植製 雜祕區，並於該二閘極結構之二外側的 201011897 该半導體基底中分、 離子佈植製程，於t )成一輕推雜源極區；再進行—源極 中分別形成-第」:〜閉極結構之二外側的該半導體基底 基底中之接面深产^區’其中該第—源極區於該半導體 之間分別形成參雜沒極區深；於該二間極結構 掺雜沒極區切；、= 切:壁，該二1」卵雜係位於該輕 極結構間形成—古’ n摻雜離子佈植製程以於該二間 间穆雜汲極區，其中該高松雜 輕摻雜汲極區重聶， 力杉雜汲極區與該 且’且該高摻雜汲極區於該 的接面深度較該韧姑& /牛導體基底中 (軽摻雜汲極區深；於該二閘極社 該半導體基底中推γ * 朽位、、、口構之間的 區，並辦古捩 私離子佈植製程形成—鱗換雜沒極 °並^、°亥间摻雜汲極區及該輕摻雜汲極區重聶.於4 _ 閘極結構間形成—位障插栓。 且、^―' 藉此，本發明之NOR型快閃記憶體結構及其製造方法 能避免蝕刻該接觸孔時，對該輕摻雜汲極區造成挖穿的現 象。此外亦可使NOR型快閃記憶體中資料的寫入與抹除程 序更穩定、更可靠與具有更長的使用壽命。 【實施方式】 為充分瞭解本發明之目的、特徵及功效，茲藉由下述 具體之實施例，並配合所附之圖式，對本發明做—詳細說 明，說明於後。在這些不同的圖式與實施例中，相同的^ 件將使用相同的符號。 首先參照第一圖，係本發明快閃記憶體結構的部分剖 面圖。圖中顯示於一半導體基底100上形成有二閘極結構 201011897 102，該些閘極結構l〇2分別包含：穿隧氧化層i〇2a (tunneling oxide layer)、浮動閘 i〇2b (floating gate)、介 電層102c、控制閘l〇2d( control gate)及形成一通道103。 該半導體基底100材料可為矽、SiGe、絕緣層上覆矽（silicon on insulator, SOI )、絕緣層上覆石夕錯（snicon germanium 〇n insulator，SGOI)、絕緣層上覆鍺（gennanium on insulator, GOI);於本實施例中，該半導體基底1〇〇係為一矽基底。 接著请參照第二圖，進行一輕摻雜離子佈植製程201， 於該二閘極結構102之半導體基底1〇〇中利用輕摻雜汲極 (Lightly Doped Drain，LDD)佈植形成二輕摻雜源極區2〇2 及一輕摻雜汲極區204。於本發明實施例中該半導體結構 為一 P型半導體結構，該輕摻雜離子佈植製程2〇1中使用 的離子為砷，劑量約為lxl〇i4〜7xl〇14(i〇n/cm2)，能量約為 10〜30(Kev)。其中該二輕摻雜源極區2〇2及該輕摻雜汲極 區204係為一 N型摻雜區域，於該半導體基底1〇〇中之接 ❹ 面深度約為200 A。 /接著請同時參照第三圖及第二圖，於該半導體基底100 上形成一光罩302，該輕摻雜汲極區204會被該光罩 所涵蓋。進行一源極離子佈植製程301，加深該二輕推雜 源極區202於該半導體基底1〇〇内的離子佈植深度而成為 第'原極區304，該些第-源極區3〇4與該輕摻雜沒極 區204呈不對稱狀。相同地，於該p型半導體結構中，該 源極離^佈植製程301中使用的離子為坤，劑量約為ΐχΐ^ (i〇n/cm ) ’能置約為1〇〜3〇(Kev)。其中該第一源 201011897 極區304係為一 N摻雜源極區，於該半導體基底]〇〇中之 接面深度約為200 A。 接者清參照弟四圖，形成一第一氧化層壁4 01及·一第 二氧化層402，再利用一習知的沉積技術，如：來源氣體 包含NH3及SiHU的化學氣相沉積法（CVD)、快速熱退火 化予氣相儿積（rapid thermal chemical vapor deposition， RTCVD)、原子層沉積（atomic layer dep〇siti〇n，ALD)，沉 積一氧化層404。該氧化層404的厚度可介於200 A至1500 A ’在本實施例中約為750 A。 © 接著請同時參照第四圖及第五圖，利用乾式或濕式蝕 刻進行一蝕刻製程將該氧化層4〇4蝕刻成複數個氧化層間 隔物（Oxide spacer) 5〇2a〜d。再進行另一韻刻製程，將 該第二氧化層402蝕刻成二L形間隙壁（L_shape) 5〇如、 b及韻刻該第—氧化層壁術。進行—高摻雜沒極離子 佈植製程506於該二閘極結構1〇2之間形成一高換雜沒極 區508。其中該高摻雜汲極離子佈植製程506中使用的離 :為石中’劑制為5xl〇14〜8xl〇15(i〇n/cm2)，能量約為2〇 聶（_)該咼摻雜汲極區508與該輕摻雜没極區204重 f，且該高摻雜汲極區谓於該半導體基底1GQ中的接面 該輕摻雜汲極區204深。該高摻雜汲極區508於該 _中之接面深度料_A。該高摻極 &係為一N摻雜區域。 製程時參照第六圖及第五圖，進行一礙離子佈植 ;該二閘極結構102之間形成一磷摻雜汲極區 10 201011897 602，並與該高摻雜汲極區5〇8及該輕摻雜汲極區2〇4重 疊。該磷離子佈植製程6〇】中使用的離子為磷，劑量約為 lxlO15〜8xl015(ion/cm2)，能量約為 2〇〜5〇(Kev)，該磷摻 雜没極區602於該半導體基底中的接面深度約為2〇〇 a。 如此，由於該磷摻雜汲極區6〇2的植入，加強該輕摻雜汲 極區204與高摻雜汲極區5〇8之接面處6〇4的電性連結， 使§己憶體中載子的遷移率不會降低。 ❹ 接著請參閱第七圖，於表面形成一由鈷（cobalt，Co)、 鈦（tltamum，Ti)、鎳（nickel, Ni)或鉬（molybdenum，Mo ) 所構成之金屬矽化物層，並且進行一快速熱退火處理製 程’以形成一自動對準金屬矽化物層7〇2a、7〇2b與702c (salicidelayer)，用以降低寄生電阻提昇元件驅動力。 接著請參閱第八圖，接續上述步驟，於該半導體基底 1〇〇上沉積一接觸孔蝕刻停止層802(contact etch stop layer， CESL)’其可為SiN、氮氧化石夕（0Xynitride)、氧化石夕（〇xide) ❹等，在本實施例中為SiN。該接觸孔蝕刻停止層8〇2的沉 積厚度為100至15〇〇 A。接著，一層間介電質層8〇4 (inter-layer dielectric，ILD)，如：二氧化矽 si〇2，沉積在 該接觸孔蝕刻停止層8〇2之上。 最後請參閲第九圖，利用習知的光阻光罩製程，將一 接觸孔902從該層間介電質層8〇4非均向性地蝕刻到該接 觸蝕刻停止層802。再沉積一位障插栓9〇4 (bamerplug) 形成一如第八圖所示之具高摻雜汲極區的N〇R型快閃記 憶體結構。 11 201011897 本發明在上文中已以較佳實施例揭露，然熟習本項技 術者應理解的是，該實施例僅用於描繪本發明中記憶體單 元的一部分結構，而不應解讀為限制本發明之範圍。應注 意的是，舉凡與該實施例等效之變化與置換，均應設為涵 蓋於本發明之範疇内。因此，本發明之保護範圍當以下文 之申請專利範圍所界定者為準。 【圖式簡單說明】 第一圖到第九圖係顯示在不同製程步驟時，本發明實施例 ® 的快閃記憶體結構剖面圖。 第十圖係習知的快閃記憶體結構剖面圖。 【主要元件符號說明】 100 半導體基底 102 閘極結構 102a 穿隧氧化層 102b 浮動閘 102c 介電層 102d 控制閘 103 通道 130 閘極結構 132 輕摻雜没極區 134 南推雜 >及極區 136 接面處 12 201011897The electrical location of the 136 is far from the line j water & the animal husbandry G... the service is quite fragile. In order to avoid the occurrence of short-channel, the thinner and thinner the area will make the fragile electrical property, thus affecting the mobility of the carrier in the flash memory. In the avoidance of the New Channel effect and avoiding the lightly doped bungee zone being excavated by the yarn, the light is mixed (4) with the electricity at the junction of the highly doped bungee zone. SUMMARY OF THE INVENTION The main object of the present invention is to provide a NOR type flash memory structure having dual ion implantation and a method of fabricating the same. After improving the short channel effect and avoiding the phenomenon that the lightly doped bungee region is easily punctured during etching, the electrical connection between the lightly doped drain region and the highly doped drain region is enhanced to make the memory The mobility of the carrier will not decrease. To achieve the above object, the present invention provides a NOR-type flash memory structure having dual ion implantation, comprising: a semiconductor substrate having a two-gate structure thereon; a lightly doped drain region; Located in the semiconductor substrate between the two gate structures; a first source region is disposed in the semiconductor substrate outside the two of the two dummy structures; wherein the first source region is in the semiconductor substrate The junction depth is deeper than the lightly doped immersion region; a high collision dopant region is located in the semiconductor substrate between the two gate structures and overlaps the lightly doped immersion region, and the height The junction surface of the doped (tetra) pole region in the semiconductor substrate is deeper than the lightly doped polar region; a scale-connected drain region is located in the semiconductor substrate between the two gate structures, and is connected to the ground Miscellaneous, the polar region ^, the doped recording region overlap; the second automatic alignment metallization layer is not above the two gate structure; and the two gate structures. In order to achieve the above object, the present invention provides a method for manufacturing a surface type flash memory structure, which comprises: a conductor substrate; a bicentric structure is formed over the semiconductor substrate = a gate structure Between the semiconductor substrate, a process is performed to form a lightly doped #, % β p . /hetero-ion implanted secret region, and the outer surface of the two-gate structure is 201011897. In the substrate, the ion implantation process is performed by t) into a lightly pushing the source region; and then the source is formed separately - the first: the junction of the semiconductor substrate in the outer side of the second closed structure is deep ^区', wherein the first source region forms a doped polar region depth between the semiconductors; the two-pole structure is doped with a poleless region; and = cut: wall, the two 1" egg hybrid Between the light-pole structures, an ancient 'n-doped ion implantation process is formed in the two inter-substrate regions, wherein the high-sand-doped light-doped bungee region is heavy, and the Lishan hybrid region and the And 'and the highly doped drain region is at the junction depth of the crucible & / cattle conductor substrate (軽 doping The polar region is deep; in the second gate, the semiconductor substrate is pushed into the region between the γ* annihilation, and the mouth structure, and the ancient 捩 private ion implantation process is formed - the scale is replaced by the pole and the ^, ° The doped yttrium region between the hai and the lightly doped yttrium region is formed between the _ gate structure and the barrier plug. The NOR flash memory structure of the present invention is thereby obtained. The manufacturing method thereof can avoid the phenomenon of digging through the lightly doped drain region when etching the contact hole, and can also make the writing and erasing process of the data in the NOR type flash memory more stable and reliable. In order to fully understand the object, features and effects of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings. In the various drawings and embodiments, the same reference numerals will be used for the same parts. First, referring to the first figure, a partial cross-sectional view of the flash memory structure of the present invention is shown in a semiconductor substrate. A gate structure 201011897 102 is formed on 100, and the gate structures are formed L〇2 includes: a tunneling oxide layer, a floating gate, a dielectric gate 102c, a control gate, and a channel 103. The material of the semiconductor substrate 100 may be germanium, SiGe, silicon on insulator (SOI), snicon germanium 〇n insulator (SGOI), and gennanium on insulator. GOI); In this embodiment, the semiconductor substrate 1 is a germanium substrate. Then, referring to the second figure, a lightly doped ion implantation process 201 is performed, and light-doped drain (LDD) is implanted in the semiconductor substrate 1〇〇 of the two-gate structure 102 to form a light The source region 2〇2 and a lightly doped drain region 204 are doped. In the embodiment of the invention, the semiconductor structure is a P-type semiconductor structure, and the ion used in the lightly doped ion implantation process 2〇1 is arsenic, and the dose is about lxl〇i4~7xl〇14 (i〇n/cm2). ), the energy is about 10~30 (Kev). The lightly doped source region 2〇2 and the lightly doped drain region 204 are an N-type doped region having a depth of about 200 A in the semiconductor substrate. / Then, referring to the third and second figures, a photomask 302 is formed on the semiconductor substrate 100, and the lightly doped drain region 204 is covered by the photomask. A source ion implantation process 301 is performed to deepen the ion implantation depth of the second lightly-push source region 202 in the semiconductor substrate 1 to become a first-pole region 304, and the first-source regions 3 The crucible 4 is asymmetric with the lightly doped polar region 204. Similarly, in the p-type semiconductor structure, the source used in the source process 301 is Kun, and the dose is about ΐχΐ^(i〇n/cm)' can be set to about 1〇~3〇 ( Kev). The first source 201011897 pole region 304 is an N-doped source region, and the junction depth in the semiconductor substrate is about 200 A. Referring to the four drawings, a first oxide layer wall 410 and a second oxide layer 402 are formed, and a conventional deposition technique such as a chemical vapor deposition method in which the source gas contains NH3 and SiHU is used. CVD), rapid thermal annealing, rapid thermal chemical vapor deposition (RTCVD), atomic layer dep〇siti〇n (ALD), deposition of an oxide layer 404. The oxide layer 404 may have a thickness of between 200 A and 1500 A' in the present embodiment of about 750 A. © Next, please refer to the fourth and fifth figures at the same time, and perform an etching process by dry or wet etching to etch the oxide layer 4〇4 into a plurality of oxide spacers (Oxide spacer) 5〇2a~d. Another rhyme process is performed to etch the second oxide layer 402 into two L-shaped barriers (L_shape), such as b, and rhyme engraving the first oxide layer. The high-doped immersion ion implantation process 506 forms a high impurity-doped region 508 between the two gate structures 1〇2. The ion used in the highly doped gate ion implantation process 506 is: 5xl〇14~8xl〇15 (i〇n/cm2), and the energy is about 2〇N (_). The doped drain region 508 is heavier than the lightly doped gate region 204, and the highly doped drain region is deeper than the lightly doped drain region 204 in the junction of the semiconductor substrate 1GQ. The highly doped drain region 508 is at the junction depth _A in the _. The high doping & is an N-doped region. During the process, referring to the sixth and fifth figures, an ion implantation is performed; a phosphorus-doped drain region 10 201011897 602 is formed between the two gate structures 102, and the highly doped drain region 5〇8 And the lightly doped drain region 2〇4 overlaps. The ion used in the phosphorus ion implantation process is phosphorus, the dose is about lxlO15~8xl015 (ion/cm2), the energy is about 2〇~5〇(Kev), and the phosphorus doped non-polar region 602 is The junction depth in the semiconductor substrate is about 2 〇〇a. Thus, due to the implantation of the phosphorus-doped drain region 6〇2, the electrical connection of the junction of the lightly doped drain region 204 and the highly doped drain region 5〇8 is strengthened, so that § The mobility of the carriers in the memory will not decrease. ❹ Next, refer to the seventh figure to form a metal telluride layer composed of cobalt (Co), titanium (tltamum, Ti), nickel (nickel, Ni) or molybdenum (Mo) on the surface, and carry out A rapid thermal annealing process 'to form a self-aligned metal telluride layer 7〇2a, 7〇2b and 702c (salicidelayer) for reducing the driving force of the parasitic resistance lifting element. Next, referring to FIG. 8 , following the above steps, a contact etch stop layer 802 (CESL) is deposited on the semiconductor substrate 1 其, which may be SiN, NOx, oxidation. Shi Xi (〇xide), etc., in this embodiment, is SiN. The contact hole etch stop layer 8 〇 2 has a deposition thickness of 100 to 15 Å. Next, an inter-layer dielectric (ILD), such as cerium oxide si〇2, is deposited over the contact hole etch stop layer 8〇2. Finally, referring to the ninth figure, a contact hole 902 is non-uniformly etched from the interlayer dielectric layer 8〇4 to the contact etch stop layer 802 by a conventional photoresist mask process. A barrier plug 9〇4 (bamerplug) is deposited to form an N〇R-type flash memory structure having a highly doped drain region as shown in FIG. 11 201011897 The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that this embodiment is only used to describe a part of the structure of the memory unit in the present invention, and should not be construed as limiting the present invention. The scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be within the scope of the invention. Therefore, the scope of the invention is defined by the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS The first to ninth drawings show cross-sectional views of a flash memory structure of an embodiment of the present invention at different process steps. The tenth figure is a cross-sectional view of a conventional flash memory structure. [Main component symbol description] 100 semiconductor substrate 102 gate structure 102a tunnel oxide layer 102b floating gate 102c dielectric layer 102d control gate 103 channel 130 gate structure 132 lightly doped immersion region 134 south push impurity > 136 junction at 12 201011897
201 輕摻雜離子佈植製程 202 輕摻雜源極區 204 輕摻雜没極區 301 源極離子佈植製程 302 光罩 304 第一源極區 401 第一氧化層壁 402 第二氧化層 404 氧化層 502a〜d 氧化層間隔物 504a〜b L形間隙壁 506 高摻雜汲極離子佈植製程 508 南換雜〉及極區 601 磷離子佈植製程 602 磷摻雜汲極區 604 接面處 702a〜c 自動對準金屬矽化物層 802 接觸孔蝕刻停止層 804 層間介電質層 902 接觸孔 904 位障插栓 13201 lightly doped ion implantation process 202 lightly doped source region 204 lightly doped dopant region 301 source ion implantation process 302 photomask 304 first source region 401 first oxide layer wall 402 second oxide layer 404 Oxide layer 502a~d oxide spacer 504a~b L-shaped spacer 506 Highly doped drain ion implantation process 508 South exchange> and polar region 601 Phosphorus ion implantation process 602 Phosphorus doped bungee region 604 junction 702a~c automatically aligning the metallization layer 802 contact hole etch stop layer 804 interlayer dielectric layer 902 contact hole 904 barrier plug 13