KR100601053B1 - Transistor using impact ionization and method for manufacturing the same - Google Patents

Abstract

A transistor using collision ionization and a method of manufacturing the same are provided. According to the present invention, a gate dielectric layer, a gate, and first and second sidewall spacers are formed on a semiconductor substrate, and an impurity is implanted into the semiconductor substrate, thereby masking the gate and the first and second spacers. A first impurity layer spaced apart from the spacer and a second impurity layer extending overlapping under the second spacer are formed. Sources and drains that set the semiconductor substrate regions therebetween as ionization regions are formed on the semiconductor substrate so as to be self-aligned to the first and second spacers, respectively. In this case, the source is formed to include a first metal silicide layer to form a schottky junction with the ionization region, and the resistive contact with the second impurity layer portion and the second impurity layer region where the drain overlaps under the second spacer. and a second silicide film aligned with the second spacer to form an ohmic contact.

Collision ionization, avalanche breakdown, silicides, Schottky barriers, asymmetric source drains

Description

Transistor using impact ionization and method for manufacturing the same

1 is a schematic cross-sectional view for explaining a typical Schottky barrier transistor.

2A-2C are schematic diagrams of energy band diagrams for explaining the principle of operation of a typical Schottky barrier transistor.

3 is a cross-sectional view schematically illustrating a conventional collision ionization transistor.

FIG. 4 is a diagram schematically illustrating a simulation operation characteristic of a conventional collision ionization transistor.

5 is a schematic cross-sectional view for describing a collision ionization transistor using a conventional sidewall.

6 is a cross-sectional view schematically illustrating a collision ionization transistor according to an embodiment of the present invention.

7 is an energy band diagram schematically illustrating an operation of a collision ionization transistor according to an exemplary embodiment of the present invention.

8 to 11 are cross-sectional views schematically illustrating a method of manufacturing a collision ionization transistor according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a transistor device using breakdown voltage control of a junction by impact ionization and a method of manufacturing the same.

As semiconductor technology advances, there is an increasing demand for high performance / integrated devices. Typical transistors have been made to operate by Fermi-Dirac distribution and drift-diffusion transport of carriers. However, it is understood that the operation principle of the metal-oxide-semiconductor field effect transistor (MOSFET) is difficult to lower the subthreshold slope below 60 mV / decade at room temperature. As a result, there is a limitation in miniaturization of transistors.

As a technique for overcoming the limitation of the sector threshold voltage, a schottky barrier MOSFET has been proposed in which a carrier injection method uses tunneling rather than diffusion.

1 is a schematic cross-sectional view for explaining a typical Schottky barrier transistor. 2A through 2C are schematic views for explaining an operating principle of the Schottky barrier transistor of FIG. 1.

Referring to FIG. 1, a Schottky barrier transistor includes a gate dielectric layer 13 and a gate 14 on a channel region 12 of a substrate 11, and a source 16 and a drain 17 on the substrate 11. ) Is preferably a silicide which is a reactant of silicon and metal. Spacers 15 may be introduced into sidewalls of the gate 14.

Schottky barrier transistors were first proposed in the 1960s and have been studied recently. The cross-sectional structure is very similar to that of a typical MOSFET. Nevertheless, the Schottky barrier transistor uses silicide, which is a reactant of silicon and metal, without using a semiconductor material into which the source 16 and the drain 17 are implanted with impurities. As a result, a Schottky barrier is formed in the junction region of the silicon (Si) used as the source 16 and the drain 17 and the channel region 12.

Referring to FIG. 2A, the voltage V _GS between the gate 14 and the source 16 and the voltage between the drain 17 and the source 16 in the Schottky barrier transistor configured as shown in FIG. 1. When V _DS ) is 0 V, a high work function barrier exists between the channel region 12 and the source 16 of the substrate 11 such that no current flows in the channel region 12. At this time, a barrier (qφ _bp ) for holes is established between the source 16 and the channel region 12.

Referring to FIG. 2B, when V _GS is greater than the threshold voltage V _T of the channel region 12 and V _DS is 0V, a barrier qφ _bn between electrons is formed between the channel region 12 and the source 16. It is established but its width becomes thinner as shown, so that electrons can tunnel through this barrier qφ _bn .

Referring to FIG. 2C, when V _GS is applied to a value greater than the threshold voltage V _T of the channel region 12 and V _DS is greater than 0 V, a barrier to electrons between the channel region 12 and the source 16 is applied. Electrons tunneling (qφ _bn ) can flow through the channel region 12 from the source 16 to the drain 17.

Schottky barrier transistors operate in a manner that modulates the flow of current by controlling the tunneling of carriers through the Schottky barrier, as shown in FIGS. 1 and 2A-2C. However, the Schottky barrier transistor has a tunneling barrier and a gap between the junction of the source 16 or the drain 17 and the channel region 12, so that the parasitic resistance may increase, resulting in a small operating current. .

As another technique for overcoming the limitation of the sector threshold voltage, an impulse ionization transistor (I-MOS) has been proposed to amplify an operating current by using collision ionization to operate the transistor.

3 is a cross-sectional view schematically illustrating a conventional collision ionization transistor. 4 is a diagram schematically illustrating a simulation operation characteristic of a conventional collision ionization transistor.

Referring to FIG. 3, a collision ionization transistor has a pin diode structure in a silicon layer on an buried oxide film of a silicon on insulator (SOI) substrate 31, and an avalanche breakdown voltage by collision ionization at a junction. It uses the principle to amplify the current by controlling.

Referring to the operation principle of the I-MOS transistor, as shown in FIG. 1, when the gate voltage applied to the gate 33 accompanying the gate dielectric film 32 is low, it is introduced between the source 34 and the drain 35. The current ionization region (I-region) 37 becomes a substantially gate length so that no current flows. The ionization region 37 includes a region L _GATE overlapping the gate 33 and a non-overlapping region L _i near the gate 33.

As the gate voltage increases, the channel region under the gate 33 is inverted, and a relatively high electric field is formed in the I-region 37 while the substantial gate length is reduced. Accordingly, a current flows through the avalanche breakdown due to collision ionization in the I-region 37.

In this case, the source 34 may be a P ⁺ region having a predetermined thickness t _si , and the drain 35 may be an N ⁺ region. In addition, the gate dielectric layer 32 may be formed to have a constant equivalent oxide thickness t _ox .

As shown in FIG. 4, the I-MOS transistor of FIG. 3 is reported to have a subthreshold slope of 5 mV / decade as a result of the simulation.

Nevertheless, conventional I-MOS transistors require the source (34 in FIG. 3) and drain (35 in FIG. 3) junctions to be implanted with the opposite type of impurity and the I-region 37 having an offset. Because of the need to create a self-align process, it can be difficult to apply. The development of devices that can self-align by solving these vulnerabilities has been reported.

5 is a schematic cross-sectional view for describing a collision ionization transistor using a conventional sidewall.

Referring to FIG. 5, a conventional I-MOS transistor using sidewalls includes a step on the substrate 51 and a gate 53 accompanying the gate dielectric film 53 on the sidewall of the substrate 51. And a drain 54 and a source 55, and may include an insulating layer 56 and a spacer 57. Such a structure can be self-aligned, but the leakage current is relatively large according to the use of the bulk substrate 51, and has a structure different from that of a general MOSFET, and thus may be vulnerable to commercial process development or circuit design.

Therefore, there is a need for the development of transistors that can solve the weaknesses of these conventional transistors.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a collision ionization transistor capable of overcoming the limitation of device miniaturization in a MOSFET and to which a self-aligning process can be applied, and a manufacturing method thereof.

According to an aspect of the present invention, a gate dielectric layer is formed on a semiconductor substrate, a gate is formed on the gate dielectric layer, and first and second spacers are formed on both sidewalls of the gate, respectively. Forming an impurity in the semiconductor substrate so as to mask the gate and the first and second spacers so as to overlap the first impurity layer and the second spacer spaced apart from the first spacer. Forming an elongated second impurity layer, and forming a source and a drain on each of said first and second spacers to self-align said source and drain to set said semiconductor substrate region to an ionization region therebetween, The source includes a first metal silicide layer to form a schottky junction with the ionization region. And a second silicide layer aligned with the second spacer to form ohmic contact with the second impurity layer portion and the second impurity layer region overlapping the drain below the second spacer. The present invention provides a transistor manufacturing method using collision ionization including forming the drain.

According to another aspect of the present invention, a gate dielectric layer formed on a semiconductor substrate, a gate formed on the gate dielectric layer, first and second spacers respectively formed on both sidewalls of the gate, and the semiconductor to self-align to the first spacer A source including a first metal silicide layer formed on the substrate and configured to form a schottky junction with an ionization region set as the semiconductor substrate region under the gate and the first spacer, and between the source and the source; An impurity layer formed by oblique ion implantation into the semiconductor substrate such that an ionization region extends to a region below the second spacer, and an ohmic contact formed with the impurity layer and the impurity layer region to be aligned with the second spacer. Using collisional ionization comprising a drain formed including a silicide film One transistor structure is presented.

In this case, a silicon substrate or an SOI substrate may be used as the substrate. Alternatively, a low manor substrate or a silicon-low manor substrate may be used to lower the avalanche breakdown voltage.

The region of the semiconductor substrate set as the ionization region may include an intrinsic semiconductor region or a region doped with impurities of an opposite conductivity type to the second impurity layer at a doping concentration of at most 10 ¹⁶ cm ⁻³ .

The gate dielectric layer may include a thermal silicon oxide (SiO ₂ ), a chemical vapor deposition (CVD) silicon nitride (Si ₃ N ₄ ) film, or a silicon hafnium oxynitride (SiHfON) film.

Forming the first and second silicide films includes forming a metal film over the semiconductor substrate and covering the gate, silicifying the metal film, and selectively removing portions of the unsilicided metal film. Can be performed.

The metal film may be formed including any one selected from the group consisting of erbium, ytterbium, platinum, iridium, cobalt, nickel, and titanium.

According to the present invention, it is possible to overcome the limitation of device miniaturization in a MOSFET and to provide a collision ionization transistor and a method of manufacturing the same, which can be applied to a self alignment process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the invention are preferably to be interpreted as being provided to those skilled in the art to more fully describe the invention.

In an embodiment of the present invention, a collision ionization transistor comprising a source having a Schottky junction and a method of manufacturing the same are provided. The collision ionization transistor according to the embodiment of the present invention is provided with a first drain region of a lightly doped drain (LDD) region opposed to a source and a second drain region, preferably including silicide behind the first drain region. And an ionization region under adjacent offset sidewall spacers, a channel region under the gate and a gate accompanying the gate dielectric layer.

As an example of configuring an N-type I-MOS transistor, in accordance with an embodiment of the present invention, a silicide having a relatively low barrier to holes instead of a source junction formed of a conventional P ⁺ impurity region is formed. Or metal to form a source.

According to an embodiment of the invention, an ionization region (I-region) can be secured between a source formed of silicide and a channel region under the gate, preferably by being offset under the sidewall spacer toward the source. Accordingly, in the transistor according to the embodiment of the present invention, current may be amplified by collision ionization in the I-region by inversion of the channel according to the gate voltage. Accordingly, the transistor according to the embodiment of the present invention can operate as an I-MOS transistor having a relatively high subthreshold slope.

The structure of the source-side Schottky junction and the drain-side LDD of the transistor according to the embodiment of the present invention can contribute to reducing the hot carrier effect and can also improve the drive current by reducing the parasitic resistance. Holes generated by collision ionization by a high electric field in the drain side channel and accumulate in the substrate body can escape through a relatively low height Schottky barrier, preferably of a silicided source junction, thereby reducing HCE. Can be reduced.

According to an embodiment of the present invention, the drain junction may be formed including an LDD region preferably doped with N ⁻ through ion implantation, that is, oblique ion implantation, which is inclined at a relatively large angle before silicide formation. The LDD region can reduce the HCE by lowering the high field of the drain side channel. Since the LDD region is in ohmic contact with the silicide layer behind it, the parasitic resistance between the channels can be reduced to increase the driving current.

6 is a cross-sectional view schematically illustrating a collision ionization transistor according to an embodiment of the present invention. FIG. 7 is a schematic energy band diagram for explaining the operation of the collision ionization transistor according to the embodiment of the present invention.

Referring to FIG. 6, the collision ionization transistor according to the embodiment of the present invention may be configured to include a source 510 in the SOI substrate 100. In this case, the SOI substrate 100 may include a silicon layer 110 as an active region, a bottom oxide layer 120, and a bottom portion 130. In this case, the source 510 includes a metal or a metal silicide to form a Schottky barrier at an interface portion between the source 510 and the silicon layer 110 of the substrate 100.

In addition, the transistor may include a first drain 451 including a region of semiconductor material preferably doped with impurities and a second drain 550 behind. The second drain 550 may be formed of metal or metal silicide.

The gate 300 accompanying the gate dielectric layer 200 is formed on a portion of the SOI substrate 100, that is, a channel portion, between the source 510 and the first drain 451. The gate 300 may be formed of a metal gate to prevent generation of a depletion layer in the gate 300 and to reduce a resistance. The gate overlap region 101 is set below the gate 300.

Sidewall spacers 350 may be formed on the sidewalls of the gate 300 to include an insulating material. Among the two sidewall spacers 350, a first sidewall spacer 351 toward the source 510 is introduced to induce a region 103 offset below the gate 300 to be set. Thus, an offset region 103 set below the first sidewall spacer 351 and overlapping with the first sidewall spacer 351 and aligned with the first sidewall spacer 351 is not overlapped with the gate 300. The ionization region 105 including the gate overlap region 101 and the offset region 103 is set as an area between the source 510 and the first drain 451.

Meanwhile, the first drain 451 may be set as an area under the second side wall spacer 353. The first drain 451 is a region doped with impurities in the silicon layer 110 and may be preferably formed as a lightly doped drain (LDD) region. The second drain 550 behind the first drain 451 may preferably be formed including metal silicide, wherein the metal silicide forming the second drain 550 is opened by the sidewall spacers 353. It may be selectively formed only in the region of the layer 110. Accordingly, the second drain 550 is aligned with the second sidewall spacer 353, and the first drain 451 is formed by the second drain 550 aligned by the second sidewall spacer 353. The area will be limited.

In the process of forming the second drain 550 as the metal silicide, the metal silicide may be formed in the region of the adjacent silicon layer 110 exposed to the first sidewall spacer 351 together. Therefore, since the source 510 is formed including the metal silicide, the source 510 is formed to be aligned with the first sidewall spacer 351.

The silicon layer 110 of the SOI substrate 100 may be formed of intrinsic silicon that is not doped with impurities, or may be doped with p-type, for example, at a relatively low doping concentration of about 10 ¹⁵ cm ⁻³ . Thus, the ionization region 105, ie, the channel region, between the source 510 and the first drain 451 is either an intrinsic silicon region or a region doped with p-type impurities at low concentration.

Since the source 510 is preferably made of metal silicide, a Schottky barrier is constructed at the interface portion between the source 501 and the ionization region 105, in particular the offset region 103. In contrast, unlike the source 510, the first drain 451 is composed of an n ⁻ impurity doped region doped with n ^- type impurities, preferably under the second sidewall spacer 353. As such, the source 510 and the drains 451 and 550 are formed in an asymmetrical structure with respect to the gate 300.

Referring to FIG. 7, a negative source voltage (V _source ) is applied to a source 510 of a transistor according to an exemplary embodiment of the present invention as shown in FIG. 6, and positive (+) to drains 451 and 550. When applying a drain voltage (V _drain ) of a polar voltage, an energy band diagram as shown in FIG. 7 may be considered.

As shown in FIG. 7, when the gate voltage applied to the gate 300 of FIG. 6 is low such that the channel of the transistor is turned off, electrons at the drain cannot pass through the Schottky barrier. Although a small number of electrons or holes can enter the I-region (105 in FIG. 6), current does not reach an electric field sufficient to cause collision ionization in the I-region 105, so that current flows through the channel. It will not flow.

As the gate voltage rises to ON, the source's Schottky barrier becomes thinner and electrons are injected into I-region 105 through quantum mechanical tunneling. The injected electrons obtain sufficient kinetic energy by a high electric field above the threshold voltage in the I-region 105 to cause avalanche breakdown in the channel through collision ionization. Collision ionization creates new electron / hole hole pairs, electrons continue to be accelerated again by the electric field, and the hole holes descend into the valence band and flow back down to the source. Thus, the current flowing through the channel increases rapidly.

Hole holes in the channel can also cause collision ionization if they are accelerated toward the source by a high electric field. Since this multiplication of current occurs very rapidly, the subthreshold slope of the transistor becomes smaller than 10 mV / decade less than kT / q. Therefore, the I-MOS transistor according to the embodiment of the present invention can be effectively used for high performance / high speed digital applications.

PN junctions are used in conventional I-MOS transistors, and collision ionization is used by minor carriers in PN junctions. On the other hand, in the embodiment of the present invention, a Schottky junction between the I region 105 and the source 510 is used. In the Schottky junction, collision ionization by a majority carrier is used.

Accordingly, the transistor according to the embodiment of the present invention can implement more current amplification and lower breakdown voltage. An additional circuit configuration for applying a relatively large negative voltage to the source 510 is required in embodiments of the present invention, but the breakdown voltage can be significantly lowered to reduce the magnitude of the required voltage required for the operation of the transistor. have. Therefore, the transistor according to the embodiment of the present invention can greatly reduce power consumption.

Three methods can be considered as a method of lowering the breakdown voltage of a transistor according to an embodiment of the present invention.

에 비례하며, 애벌랜치 항복 전압은

에 비례한다. 그럼에도 불구하고, I-영역(105)에서의 도핑 농도가 10¹⁸cm^-3 정도 이상일 경우, I-영역(105)에서 밴드간 터널링에 의한 제너 항복이 일어날 수 있으므로, I-영역(105)에서의 불순물 농도는 그 이하인 것이 바람직하다. First, by relatively increasing the concentration of the doped impurities in the I-region 105, the avalanche breakdown voltage can be effectively lowered. The maximum field at the junction is the doping concentration of the I-region 105

Proportional to the avalanche breakdown voltage

Proportional to Nevertheless, when the doping concentration in the I-region 105 is about 10 ¹⁸ cm ⁻³ or more, zener breakdown may occur due to interband tunneling in the I-region 105, so that in the I-region 105, The impurity concentration of is preferably less than that.

Second, lowering the height of the Schottky barrier of the metal silicide constituting the source region 510 causes a larger number of electrons to be injected into the I-region 105 through quantum mechanical tunneling, which results in more collision ionization. Acceleration results in a relatively lower breakdown voltage.

Third, when using low manganese (Ge) or silicon low manganese (Si _X Ge _1-X ), which has a lower energy band gap than silicon (Si), as the I-region 105, collision The breakdown voltage can be reduced because it requires less kinetic energy to generate the electron / hole hole pair. In addition, further reducing the thickness of the gate dielectric layer 200 through scaling of the device may help to lower the breakdown voltage.

Referring back to FIG. 6, a low doped drain (LDD) structure is formed at the drain side of the transistor according to the embodiment of the present invention to reduce HCE due to a high electric field, thereby lowering an electric field. That is, the first drain 451 may be formed of an LDD region, and the rear second drain 550 may be formed of metal or metal silicide similarly to the source 510.

This LDD structure serves to reduce the parasitic resistance component due to the gap between the silicide and the channel behind it. In general, in bulk MOSFETs using bulk silicon substrates or partially-depleted (PD) SOI MOSFETs using partially doped SOI substrates, holes caused by HCE in the drain accumulate on the substrate, causing latch-up. Can be. However, in the transistor structure according to the embodiment of the present invention, the holes do not accumulate in the substrate 100 due to the negative voltage applied to the source 510 side, and all of them exit.

8 to 11 are cross-sectional views schematically illustrating a transistor manufacturing method using collision ionization according to an embodiment of the present invention.

Referring to FIG. 8, a gate 300 accompanying the gate dielectric layer 200 is formed on the substrate 100. The substrate 100 may use a semiconductor substrate, such as a silicon substrate, and may also use an SOI substrate as shown in FIG. 6. In this case, sidewall spacers 350 (351 and 353) for insulating the gate channel under the gate 300 may be formed on the sidewall of the gate 300 including an insulating material.

A series of process steps for forming the gate dielectric layer 200, the gate 300, and the sidewall spacer 350 for the transistor may be performed according to a general MOSFET fabrication process. For example, after forming the gate dielectric layer 200, forming and patterning a layer for the gate 300 on the gate dielectric layer 200, and forming an layer for the sidewall spacer 350 on the patterned structure and then anisotropic The etching may be performed to form a spacer.

The gate dielectric layer 200 may include a silicon oxide (SiO ₂ ) layer formed by thermally oxidizing silicon (Si). In addition, the gate dielectric layer 200 may be formed using a high dielectric constant thin film, such as a chemical vapor deposition (CVD) silicon nitride (Si ₃ N ₄ ) film or a silicon hafnium oxynitride (SiHfON) film.

In addition, the material used as the gate 300 electrode may use conductive polysilicon which is widely used at present. Nevertheless, the gate 300 can be formed of a metal gate that can prevent generation of a depletion layer and can also implement a lower gate resistance.

On the other hand, the sidewall spacer 350 is preferably formed of a material having a low dielectric constant k as possible. For example, the sidewall spacers 350 may include a thin film of an insulating material having a low dielectric constant such as silicon oxide (SiO ₂ ).

As shown in FIG. 6, the width of the sidewall spacers 350 may be determined in consideration of the conditions under which collision ionization may occur in the I-region 105. It may be understood that the ionization region 105 is set to include a gate overlap region 101 and an offset region 103 overlapping under the gate 300. In this case, since the gate overlap region 101 overlaps the gate 300, the length is set to the gate length L _GATE . The length (L _i) of the first sidewall spacer 351, the offset region 103 which can be set to the area overlapping the bottom adjacent to the second sidewall spacer is opposed to the 353, the source 510 may substantially impact ionization It can be understood as the length (L _i ) of the region in which it occurs, and can be determined depending on the width of the sidewall spacer 350.

As the size of the device decreases, the thickness of the gate dielectric layer 200, the length of the gate 300, and the gate voltage also decrease, so that the width of the sidewall spacer 350 may also decrease accordingly. The length (L _i) of the side wall spacers 350, the offset region 103 as shown in Figure 6 according to the width of the smaller can also be made small.

Referring to FIG. 9, asymmetric impurity layer structures 410 and 450 are formed in the semiconductor substrate 100 using the gradient ion implantation 401. In this case, the impurity layer structure 450 is formed by the first impurity layer 410 spaced apart from the first side wall spacer 351 by the gradient ion implantation process, the second impurity layer 450 is the second side wall spacer It may be formed to overlap the bottom of the (353) to form an asymmetrical structure around the gate (300).

The gradient ion implantation process may be performed by implanting impurities into the exposed semiconductor substrate 100 using the sidewall spacer 350 and the gate 300 as a mask. At this time, the implants 401 may be inclined at a large angle toward the drains 451 and 550 of FIG. 6 to form impurity structures 410 and 450 doped with N ⁻ , for example. In this case, the inclination angle of the ion implantation 401 may be set to, for example, approximately 45 degrees with respect to the surface of the substrate 100, but the second impurity layer 450 overlaps the second sidewall spacer 353. It may be set differently in consideration of the degree or the width of the second side wall spacer 353.

The second impurity layer 450 having the asymmetric impurity layer structure formed by the oblique ion implantation 401 extends to overlap the second sidewall spacer 353 of the transistor. 451 of FIG. 6. That is, the first drain 451 including the drain side LDD region is formed through ion implantation and subsequent heat treatment for activation so that impurities are implanted under the second sidewall spacer 353 to the portion where the gate channel starts. . On the source side, the gate structure acts as a mask for ion implantation, and the first impurity layer 410 is formed by doping impurities away from the gate channel and the first sidewall spacer 351.

The impurities implanted by the gradient ion implantation 401 may include phosphorus (P), arsenic (As), antimony (Sb), and the like.

Referring to FIG. 10, silicide layers 510, 530, and 550 are formed in a source, a drain, and a gate. Specifically, silicide films 510, 530, and 550 are formed by depositing a metal material on the entire surface of the substrate 100 and inducing heat treatment to cause a silicide reaction. Thereafter, the film portion of the unreacted metal material is removed by selective wet etching or the like.

Accordingly, a source 510 including a first silicide layer 510 having an end aligned with the first side wall spacer 351 is formed. In addition, a second silicide layer 530 that forms a gate together with conductive polysilicon is formed on the gate 300. In addition, a third silicide layer 550 having an end aligned with the second side wall spacer 353 is formed to contact the second impurity layer 450 forming the first drain 451 so as to be behind the first drain 451. The second drain 550 is electrically connected to the second drain 550.

The source 510 including the first silicide layer 510 forms a Schottky junction with the offset region 103 under the first sidewall spacer 351. The second drain 550 including the third silicide layer 550 carries the first drain 451 including the second impurity layer 450 in the form of an LDD structure. The first drain 451 is in contact with the gate overlap region 101 under the gate 300. Accordingly, the ionization region 105 is set in an asymmetrical structure with respect to the gate 300 between the source 510 and the drains 451 and 550. That is, the source 510 and the drains 451 and 550 are formed in an asymmetrical structure.

 Erbium, Ytterbium, Platinum, Iridium, Cobalt, Nickel, Titanium, or the like may be used as the metal material for forming the silicide. Depending on the metal selected, the height of the tunneling barrier for carrier injection on the source 510 side is determined. In addition, the breakdown voltage of the transistor also varies with the height of the tunneling barrier.

In the case of an N-type channel I-MOS transistor, for example, a first drain 451 is formed including an N ⁻ -type impurity layer and an ionization region 105 is doped with a relatively low concentration of intrinsic semiconductor region or P-type impurity. In this case, erbium or ytterbium having a relatively low height of the Schottky barrier for electrons is suitable for forming the first silicide film 510 forming the source 510.

In the case of a P-type channel I-MOS transistor, for example, a first drain 451 is formed including a P ⁻ -type impurity layer and an ionization region 105 is doped with a relatively low concentration of an intrinsic semiconductor region or N-type impurity. In this case, it may be more advantageous to lower the breakdown voltage by forming silicide using platinum and iridium having a relatively low height of the Schottky barrier for the hole. In addition, when implementing an intermediate Schottky barrier that can be used for both N-type and P-type transistors, it is preferable to form silicide using cobalt, nickel, or titanium.

Referring to FIG. 11, an interlayer insulating layer 600 is formed to cover and insulate the source 510, the drain 550, the gates 300 and 530, and the like. In this case, a process of planarizing the interlayer insulating layer 600 may be further introduced. Thereafter, a contact penetrating through the interlayer insulating layer 600, for example, the first contact 710 aligned and contacting on the source 510, and the second contact 730 aligned and contacting on the gates 300 and 530. And a third contact 750 aligned on and contacting the second drain 550. Thereafter, the first wire 810 electrically connected to the first contact 710, the second wire 830 electrically connected to the second contact 730, and the third contact 750 are electrically connected to the first contact 710. The device is completed by performing a metal wiring process to form the third wiring 850.

Such a transistor manufacturing method using collision ionization according to an embodiment of the present invention can apply a general MOSFET manufacturing process, and does not require a separate mask for forming the structure of the pinned ionization region 105 having an asymmetric structure. This is a self-alignable process. Therefore, it is possible to apply the current semiconductor device production technology to practical use of the transistor using the collision ionization according to the embodiment of the present invention.

As described above, the present invention provides a novel collision ionization that overcomes the limitations of device miniaturization in metal-oxide-semiconductor field effect transistors (MOSFETs) that control the switching of transistors by adjusting the height of conventional channel barriers. Transistor structure and manufacturing method can be presented.

The collision ionization transistor (I-MOSFET) according to the present invention can control the flow of current by controlling the breakdown voltage of the gated p-i-n junction structure. In addition, the manufacturing method proposed in the present invention can be easily applied to the conventional manufacturing process of the MOSFET.

According to the present invention, an I-MOS transistor using a schottky junction and collision ionization in an asymmetric LDD structure can be proposed. These transistor devices overcome the limitations of MOSFETs that have been advanced until recently based on Moore's law, and can be applied to ultra-high speed / high performance digital circuits based on new operating principles. It is also expected that silicon-based devices, which are currently driving the road map of integrated circuits, will continue to play a leading role in the future.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention. In addition, while the best embodiments have been disclosed in the drawings and specification, specific terminology used herein is for the purpose of describing the present invention in detail, and is intended to limit the scope of the invention as defined in the meanings and claims. It should not be understood as being used for Therefore, it should be understood by those skilled in the art that various modifications and equivalent other forms of modifications may be possible therefrom.

Claims (9)

Forming a gate dielectric film on the semiconductor substrate; Forming a gate on the gate dielectric layer; Forming first and second spacers on both sidewalls of the gate, respectively; An impurity is implanted into the semiconductor substrate to mask the gate and the first and second spacers so that the second impurity layer overlaps the first impurity layer and the second spacer spaced apart from the first spacer Forming a layer; And Source and drain for setting the semiconductor substrate region between each other as an ionization region are formed on the semiconductor substrate to be self-aligned to the first and second spacers, respectively, The source includes a first metal silicide layer to form a schottky junction with the ionization region to form the source, Wherein the drain is formed to include a second silicide layer aligned with the second spacer to form ohmic contact with the second impurity layer portion and the second impurity layer region overlapping under the second spacer. Transistor manufacturing method using collision ionization comprising the step of forming a. The method of claim 1, A method of manufacturing a transistor using collisional ionization, characterized by using a silicon substrate or a SOI substrate as the substrate. The method of claim 1, A method of manufacturing a transistor using collision ionization, characterized in that to use a low manirium substrate or a silicon-low manirium substrate to lower the avalanche breakdown voltage to the substrate. The method of claim 1, The region of the semiconductor substrate set as the ionization region may be an intrinsic semiconductor region or a region doped with impurities of opposite conductivity type to the second impurity layer at a doping concentration of at most 10 ¹⁶ cm ⁻³ . A transistor manufacturing method using collision ionization. The method of claim 1, The gate dielectric layer is A method of fabricating a transistor using collisional ionization, comprising a thermally oxidized silicon oxide (SiO ₂ ), a chemical vapor deposition (CVD) silicon nitride (Si ₃ N ₄ ) film, or a silicon hafnium oxynitride (SiHfON) film. The method of claim 1, Forming the first and second silicide layers Forming a metal film on the semiconductor substrate and covering the gate; Silicidating the metal film; And Selectively removing the unsilicided metal film portion. The method of claim 6, The metal film is A method for manufacturing a transistor using collision ionization, comprising any one selected from the group consisting of erbium, ytterbium, platinum, iridium, cobalt, nickel and titanium. A gate dielectric film formed on the semiconductor substrate; A gate formed on the gate dielectric layer; First and second spacers formed on both sidewalls of the gate, respectively; A first metal silicide film is formed on the semiconductor substrate so as to be self-aligned to the first spacer to form a schottky junction with an ionization region set as the first spacer and the semiconductor substrate region under the gate. sauce; And And forming an ohmic contact between the impurity layer and the impurity layer region formed by oblique ion implantation of an impurity into the semiconductor substrate such that the ionization region is set between the source and the region below the second spacer. And a drain formed by including a second silicide film aligned with two spacers. The method of claim 8, The first or second silicide film A transistor using collision ionization, which is formed by selective silicidation of a metal film formed of any one selected from the group consisting of erbium, ytterbium, platinum, iridium, cobalt, nickel and titanium.

Images