US20120220111A1 - Injection method with schottky source/drain - Google Patents
Injection method with schottky source/drain Download PDFInfo
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- US20120220111A1 US20120220111A1 US13/463,264 US201213463264A US2012220111A1 US 20120220111 A1 US20120220111 A1 US 20120220111A1 US 201213463264 A US201213463264 A US 201213463264A US 2012220111 A1 US2012220111 A1 US 2012220111A1
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000002347 injection Methods 0.000 title abstract description 5
- 239000007924 injection Substances 0.000 title abstract description 5
- 230000015654 memory Effects 0.000 claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 28
- 238000002513 implantation Methods 0.000 claims abstract description 13
- 230000004913 activation Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 26
- 238000003860 storage Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 239000000969 carrier Substances 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 239000002784 hot electron Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 9
- 238000001994 activation Methods 0.000 description 6
- 206010010144 Completed suicide Diseases 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000036039 immunity Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
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- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000003031 high energy carrier Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002715 modification method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000011232 storage material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
Description
- This application is a divisional of U.S. application Ser. No. 12/430,817 (Att. Docket P970074), filed on Apr. 27, 2009 and entitled INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN, now U.S. Pat. No. 8,183,617, the entire contents of which are hereby incorporated by reference.
- 1. Field of the invention
- The present invention relates generally to semiconductor fabrication methods and, more particularly, to the fabrication of non-volatile memory devices.
- 2. Description of Related Art
- Non-volatile MOS memory cells having a source and a drain disposed in a substrate and controlled by a gate may store data by trapping charges in a dielectric region of the gate. An unprogrammed cell may have substantially no charges trapped in the dielectric. A cell may be programmed by applying suitable programming voltages to the source, drain, and gate. The programming voltages may create an electric field in a channel between the source and drain that imparts energy to charges in the channel, enabling them to reach the dielectric region. The charges may become trapped in the dielectric region, thereby changing a threshold voltage of the cell. Forward and reverse reading methods are known by which the threshold voltage may be measured in order to determine whether a cell is programmed or unprogrammed. Some memory cells may store charge in separate portions of the dielectric region, thereby effectively storing more than one bit per cell.
- With scaled-down geometries, parasitic effects that may negatively affect performance of devices employing non-volatile MOS memory cells must be considered. For example, a short channel effect and punch-through issues are known to be detrimental to memory cell operation. Lower programming efficiency when channel hot electron programming is employed may also result due to a degraded lateral electric field.
- A need exists in the prior art for structures and methods that provide immunity from scaling issues in non-volatile MOS memory cells.
- The present invention addresses this need by providing, according to one aspect, a semiconductor non-volatile memory cell comprising a substrate, a source fabricated of silicide material in an upper surface of the substrate, a drain likewise fabricated of silicide material in an upper surface of the substrate, and a gate comprising an oxide-nitride-oxide (ONO) layer and disposed nominally between the source and the drain, the gate being fabricated at a level higher than the source and the drain, wherein a Schottky barrier is formed at an interface between the substrate and the silicide material of the source and at an interface between the substrate and the silicide material of the drain. In one embodiment of the semiconductor non-volatile memory cell the gate further comprises silicon. In another embodiment of the semiconductor non-volatile memory cell the gate comprises a silicide and the ONO layer. In yet another embodiment of the semiconductor non-volatile memory cell the gate comprises metal and the ONO layer. An embodiment of the semiconductor non-volatile memory cell has the Schottky barrier controlled by a position of the gate relative to a position of the source and to a position of the drain. In a particular embodiment of the semiconductor non-volatile memory cell, the gate is disposed above and between the source and the drain, a vertical extension of an edge of the source nearest the gate does not intersect the gate and a vertical extension of an edge of the drain nearest the gate does not intersect the gate.
- While the apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 U.S.C. §112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 U.S.C. §112 are to be accorded full statutory equivalents under 35 U.S.C. §112.
- Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one skilled in the art. In addition, any feature or combination of features may be specifically excluded from any embodiment of the present invention. For purposes of summarizing the present invention, certain aspects, advantages and novel features of the present invention are described. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular implementation of the present invention. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims that follow.
-
FIG. 1A is a cross-sectional diagram of a non-volatile memory cell after conventional storage layer and gate processes are performed; -
FIG. 1B is a cross-sectional diagram of the non-volatile memory cell ofFIG. 1A following capping with a silicide material; -
FIG. 1C is a cross-sectional diagram of the non-volatile memory cell ofFIG. 1B after formatting the silicide material to form a source, a drain and a gate in the memory cell; -
FIG. 2A is a cross-sectional diagram of a non-volatile memory cell configured with terminals for programming; -
FIG. 2B is an intrinsic energy band diagram for a non-volatile memory cell; -
FIG. 2C is an energy band diagram for a non-volatile memory cell with source/drain voltages applied; -
FIG. 2D is a an energy band diagram for a non-volatile memory cell with gate and source/drain voltages applied; -
FIG. 3A is a cross-sectional diagram of a Schottky device storing a localized charge; -
FIG. 3B is a plot of a simulated current-voltage (IV) characteristic of the Schottky device ofFIG. 3A with electrons trapped near a source side under unprogrammed, forward read, and reverse read conditions; -
FIG. 3C is a plot of a simulated IV characteristic of the Schottky device ofFIG. 3A with holes trapped near a source side under unprogrammed, forward read, and reverse read conditions; -
FIG. 4A is a plot of an experimental IV characteristic of the Schottky device ofFIG. 3A under reverse read conditions; -
FIG. 4B is a plot of an experimental IV characteristic of the Schottky device ofFIG. 3A under forward read conditions; -
FIG. 5A is a cross-sectional diagram of a non-volatile memory cell showing a Schottky barrier modified with non-overlapping source/drain and gate structures; -
FIG. 5B is a cross-sectional diagram of a non-volatile memory cell showing a Schottky barrier modified with source/drain edges substantially aligned with gate edges; -
FIG. 5C is a cross-sectional diagram of a non-volatile memory cell showing a Schottky barrier modified with overlapping source/drain edges and gate edges; -
FIGS. 6A-6C are a collection of three flow diagrams depicting alternative methods of modifying a Schottky barrier; -
FIGS. 7A a-7Cd are a collection of cross-sectional diagrams of a non-volatile memory cell portraying results of the methods ofFIGS. 6A-6C ; -
FIG. 8 is a flow diagram summarizing an implementation of another alternative method of modifying a Schottky barrier; and -
FIGS. 9A-9F are a collection of cross-sectional diagrams of a non-volatile memory cell elucidating results of the implementation ofFIG. 8 . - Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or similar reference numbers are used in the drawings and the description to refer to the same or like parts. It should be noted that the drawings are in simplified form and are not presumed, automatically, to be to precise scale in all embodiments. That is, they are intended to be examples of implementations of various aspects of the present invention and, according to certain but not all embodiments, to be to-scale. While, according to certain implementations, the structures depicted in these figures are to be interpreted to be to scale, in other implementations the same structures should not, In certain aspects of the invention, use of the same reference designator numbers in the drawings and the following description is intended to refer to similar or analogous, but not necessarily the same, components and elements. According to other aspects, use of the same reference designator numbers in these drawings and the following description is intended to be interpreted as referring to the same or substantially the same, and/or functionally the same, components and elements. In reference to the disclosure herein, for purposes of convenience and clarity only, directional terms, such as, top, bottom, left, right, up, down, over, above, below, beneath, rear, and front, are used with respect to the accompanying drawings. Such directional terms should not be construed to limit the scope of the invention in any manner.
- Although the disclosure herein refers to certain illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. The intent accompanying this disclosure is to discuss exemplary embodiments with the following detailed description being construed to cover all modifications, alternatives, and equivalents of the embodiments as may fall within the spirit and scope of the invention as defined by the appended claims. It is to be understood and appreciated that the process steps and structures described herein do not cover a complete process flow for the manufacture of the disclosed structures. The present invention may be practiced in conjunction with various integrated circuit fabrication and other techniques that are conventionally used in the art, and only so much of the commonly practiced process steps are included herein as are necessary to provide an understanding of the present invention. The present invention has applicability in the field of semiconductor devices and processes in general. For illustrative purposes, however, the following description pertains to a non-volatile memory device and a related method.
- Referring more particularly to the drawings,
FIG. 1A is a cross-sectional diagram of a partially fabricated non-volatile memory cell after conventional storage layer and gate processes are performed. Known methods may be employed to fabricate an array of such cells in asubstrate 10 composed of for example, bulk silicon or silicon-on-insulator (SOI). In some embodiments, thesubstrate 10 may be lightly doped with p-type atoms; in other embodiments thesubstrate 10 may be lightly doped with n-type atoms. A structure of a typical non-volatile memory cell fabricated using these methods may comprise astorage layer 15, which may comprise an oxide-nitride-oxide (ONO) layer. Other embodiments of thestorage layer 15 may comprise, in addition to nitride, high-k dielectric material or any other kind of non-volatile charge storage material. Examples of high-k dielectric material include hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide. The structure, further, may comprise agate structure 20 and insulatingspacers 25. Beginning with the structure ofFIG. 1A ,silicide material 30 may be applied over the structureFIG. 1A as illustrated inFIG. 1B , and a process (e.g., a thermal process) may be used to format a silicide resulting in a structure shown inFIG. 1C wherein the silicide defines asource 35, adrain 40 and agate contact 45. TheONO layer 15, thegate structure 20 and thegate contact 45 may be referred to as agate 21. Thegate 21 is disposed nominally between thesource 35 and thedrain 40 and typically lies at a higher level than either thesource 35 or thedrain 40. In operation, bias conditions applied to the source, drain, and gate may result in conduction current coming from carriers having energy sufficient to tunnel through a Schottky barrier, which is more particularly described below. High-energy carriers from a source side of a channel that forms between the source and drain my also inject into thestorage layer 15 when the bias conditions produce a suitable vertical electric field. -
FIG. 2A is a cross-sectional diagram of a non-volatile memory cell similar to that illustrated inFIG. 1C and including a schematic representation of terminals that may be used to operate (e.g., program and/or read) the cell, Specifically, asource terminal 36, adrain terminal 41 and agate terminal 46 are provided. Some embodiments also may include asubstrate terminal 11, The non-volatile memory cell is illustrated withelectrons 50 trapped in thestorage layer 15 at a source side of the memory cell. -
FIG. 2B is an intrinsic energy band diagram for a non-volatile memory cell. In an unbiased state, a Schottky barrier formed at a boundary of a semiconductor (e.g.,substrate 10 inFIG. 2A ) and a silicide (e.g., suicide forming thesource 35 and/or thedrain 40 inFIG. 2A ) is controlled by the silicide material. Asource 35/substrate 10 boundary (i.e., a boundary betweensource 35 andsubstrate 10;FIG. 2A ) is designated as 37; adrain 40/substrate 10 boundary is designated as 42. It should be noted that the Schottky barrier is ambipolar, which admits both p- and n-type substrates. When bias voltages are applied to thesource terminal 36 and thedrain terminal 41, a channel may form in thesubstrate 10 between thesource 35 and thedrain 40. Under this condition, the Schottky barrier may bend as illustrated inFIG. 2C , and hot carriers in the channel with sufficient energy may tunnel through the Schottky barrier. With bias voltages applied to thegate terminal 46, thesource terminal 36 and thedrain terminal 41, the Schottky barrier may appear as illustrated inFIG. 2D . The gate, source, and drain terminal voltages may be positive or negative, depending upon whether positive or negative carriers are to be injected into thestorage layer 50. It should be emphasized that hot carriers are injected into thestorage layer 15 at the source side, not the drain side, of the non-volatile memory cell. Although various bias conditions can be introduced to modify a Schottky barrier and, thereby, to control efficiency of programming in a non-volatile memory cell, methods described herein may provide alternatives to conventional methods. The herein-described methods avoid a high-temperature activation dosage process, so that short channel effect and punch-through are substantially eliminated as problem-causing issues. Rather, these methods employ a relatively low-temperature thermal silicidation process that may provide much more elasticity of process issues than do conventional methods. Further, these methods may be relatively insensitive to device scaling. -
FIG. 3A is a cross-sectional diagram of a Schottky device, i.e., non-volatile memory cell, with localized charge stored near a source side of the cell. Embodiments of devices described below may support physical 2-bit operation. That is, electrons/holes may be independently stored on a source side and a drain side of the cell. Three curves representing simulated current-voltage (IV) characteristics of the cell ofFIG. 3A are shown inFIG. 3B for a case where the localized stored charge comprises electrons. Afirst curve 60 corresponds to an IV characteristic of an unprogrammed cell. Asecond curve 65 corresponds to an IV characteristic of the cell having electrons stored near the source side under forward read conditions, and athird curve 70 corresponds an IV characteristic of the cell under reverse read conditions. Methods for reading non-volatile memory cells using forward read and reverse read techniques are known to those skilled in the art. - A similar set of simulated IV characteristics of the cell of
FIG. 3A is shown inFIG. 3C for a case where the localized stored charge comprises holes. As before, afirst curve 61 corresponds to an IV characteristic of an unprogrammed cell, and asecond curve 66 corresponds to an IV characteristic of the cell having holes stored near the source side under forward read conditions. Athird curve 71 corresponds to an IV characteristic of the cell under reverse read. conditions. - Experimental results corresponding to
FIG. 3B are shown inFIGS. 4A and 4B .FIG. 4A presents afirst curve 80 corresponding to an IV characteristic of an unprogrammed cell under reverse read conditions. Asecond curve 85 inFIG. 4A corresponds to an IV characteristic of a non-volatile memory cell having electrons trapped near a source side. Forward read results are presented inFIG. 4B wherein afirst curve 81 corresponds to an IV characteristic of an unprogrammed cell, and asecond curve 86 corresponds to an IV characteristic of a cell having electrons trapped near the source side under forward read conditions. Approximate program bias voltages for the characteristics presented inFIGS. 4A and 4B include a gate voltage ranging from about zero to about 10 volts, a source voltage ranging from about −5 to about 5 volts a substrate voltage ranging from about −3 to about 3 volts, and drain voltage ranging from about −3 to about 3 volts. Generally, the drain potential may be higher than the source potential, and gate potential may be higher than the drain voltage. The experimental results ofFIGS. 4A and 4B may be noted to be consistent with the simulated results ofFIG. 3B , It should be emphasized that electrons are injected into thestorage layer 15 at the source side, not the drain side, of the non-volatile memory cell. - Carrier injection efficiency and/or program efficiency is controlled by the Schottky barrier at interfaces of silicide/silicon, Modifying the Schottky barrier at the source side may improve program efficiency. The methods described herein may be combined with other techniques, including extra well dosage implantation, junction implantation, pocket implantation and gate implantation. Methods will now be described for modifying characteristics of the Schottky barrier,
- One method of modifying the Schottky barrier, as exemplified in
FIGS. 5A-5C , comprises controlling an overlap between the source/drain and the gate of a non-volatile memory cell.FIG. 5A is a cross-sectional diagram of a non-volatile memory cell of a type already introduced comprising asource 35, adrain 40, and agate 21 with thesource 35, thedrain 40 and agate contact 45 formed of silicide. The cell is fabricated with agap 55 between a vertical extension of thedrain 40 and an edge of thegate 21 nearest thedrain 40. A similar gap may exist between a vertical extension of thesource 35 and an edge of thegate 21 nearest thegate 35. In the illustrated example, carriers must tunnel through a relatively large barrier in order to reach thestorage layer 15, whereby best programming efficiency in the illustrated embodiment may be found by modifying the tunneling barrier. Tunneling behavior depends upon characteristics of materials and is relatively insensitive to device scaling. InFIG. 5B , a similar memory cell structure is illustrated, but with the Schottky junction (i.e., a source/substrate interface and/or a drain/substrate interface) being substantially aligned with an edge of thegate 21. In this case, a characteristic of the Schottky barrier may be controlled by characteristics of interfaces between suicide and silicon. According to yet another example,FIG. 5C illustrates a memory cell structure fabricated with anoverlap 56 between the Schottky junction and thegate 21. That is, a vertical extension of an edge of thedrain 40 overlaps an edge of thegate 21 nearest thedrain 40. Again, a similar gap may exist between a vertical extension of an edge of thesource 35 and an edge of thegate 21 nearest thesource 35. Working from this configuration, modifying bias conditions may improve programming efficiency. - Additional methods of modifying a Schottky barrier are diagrammed in
FIGS. 6A-6C and described with reference toFIG. 7A a-7Cd. The flow diagram ofFIG. 6A presents an implementation of one method of fabricating a memory cell employing a Schottky barrier. According to the illustrated implementation, which begins atstep 100, conventional storage layer and gate processes may be performed atstep 105 in a manner well understood by those skilled in the art. An active region may be patterned atstep 110 and a spacer may be formatted atstep 115 using known methods. An example of a result of followingsteps FIG. 1A . An implantation may be performed atstep 120 whereby atoms of a doping material are implanted in the structure resulting from (e.g., following) completion ofstep 115.FIG. 7A a illustrates one implementation ofstep 120 wherein animplant dosage 28 is directed at thestructure following step 115. Dopants implanted atstep 120 may be activated by employing, for example, a relatively low-temperature thermal process. Asilicide material 30 may be deposited (e.g., capped) on the structure ofFIG. 7A b atstep 130, followed by performance of a thermal process atstep 135 to format thesilicide material 30 and create a silicide that defines asource 35, adrain 40, andagate contact 45. ASchottky barrier 43 modified by the doping may form as a result, characteristics of which may be controlled by controlling (e.g., adjusting characteristics of) the steps of the implementation ofFIG. 6A . The implementation then or later (e.g., ultimately) can be terminated atstep 140. - An implementation of another method of fabricating a memory cell having a modified Schottky barrier is described in the flow diagram of
FIG. 68 . Steps 200-220 of the implementation ofFIG. 6B may be identical to corresponding steps 100-120 ofFIG. 6A , However, the implementation of FIG, 6B deposits silicide material 30 (FIG. 7B b) atstep 225 without a step of activating &pants implanted atstep 220. The process can be discerned from the schematics ofFIGS. 7B a and 7Bb. A thermal process performed atstep 230 then may both format a silicide and activate the &wants, thereby creating aSchottky barrier 43 modified by the doping as shown inFIG. 7B c. The implementation of the method ofFIG. 6B can be terminated atstep 235, - A further implementation of yet another method of fabricating a memory cell that includes a modified Schottky barrier is depicted in the flow diagram of
FIG. 6C . Again, steps 300-315 inFIG. 6C may be identical to corresponding steps 100-115 ofFIG. 6A . Atstep 320, asuicide material 30 is deposited over the structure formed afterstep 325 as illustrated inFIG. 7C a. Thesilicide material 30 may be formatted atstep 325 using a thermal process thereby forming a source, a drain and a gate contact as shown inFIG. 7C b. An implantation step may then be performed atstep 330 as described inFIG. 7C c wherein animplant dosage 28 of doping material is applied to the structure ofFIG. 7C b. The implantation may be activated atstep 335 as shown inFIG. 7C d to form aSchottky barrier 43 modified by doping. The implementation of the method can be terminated atstep 340. -
FIG. 8 illustrates yet another implementation of a method of fabricating a memory cell with a modified Schottky barrier comprising agate process. The process described in the flow diagram ofFIG. 8 , which may be integrated with any of the processes described above in connection withFIGS. 6A-6C , may act to adjust a gate workfunction. With reference toFIGS. 9A-9F , this implementation begins atstep 400 and continues by depositing gate material 20 (FIG. 9A ) onto acharge trapping layer 15 that overlies asubstrate 10, which may be formed of for example, lightly doped or intrinsic silicon. Thegate material 20 may comprise silicon. Agate structure 23 may be patterned atstep 410 using known methods as shown inFIG. 9B , and aspacer 25 may be formed on sides of thegate structure 23 atstep 415, again using known methods to form the structure depicted inFIG. 9C .Silicide material 30 may be deposited on the result ofstep 415 as shown inFIG. 9D , and animplantation 28 of doping atoms may be introduced at step 425 (cf,FIG. 9E ). An activation process, which may be a low-temperature thermal process, may be performed atstep 430 to activate the dopants and create a silicide that forms agate contact 45, asource 35, and adrain 40 as shown inFIG. 9F . By extending a time duration of the activation process, substantially all of thegate material 20 may be silicided, resulting in a fully silicided (FUSI)gate 22. ASchottky barrier 43 modified by doping may form between thesource 35/drain 40 and thesubstrate 10. As a variation on the method ofFIG. 8 , a metal gate may be formed to replace the FUSI gate, - Summarizing the
FIG. 6A , 6B, 6C and 8 Schottky-barrier modification methods,FIG. 6A describes an implantation and dosage activation followed by a silicidation process;FIG. 6B describes an implantation (and capping with silicide material) followed by simultaneous performance of the dosage activation and silicidation;FIG. 6C describes silicidation followed by dosage implantation and activation processes; andFIG. 8 describes formation of a fully silicided gate to create a memory cell having a modified Schottky barrier. These techniques, which may operate to provide significant immunity to problems arising from memory device miniaturization, support physical and electrical 1-hit and 2-bit operation, and the resultant memory cells are easily implemented in or as NOR/NAND type flash memories. Further, these methods may apply to operation of any type of non-volatile memories including, for example, floating gate and split gate structures. - In view of the foregoing, it will be understood by those skilled in the art that the methods of the present invention can facilitate formation and operation of non-volatile memory devices in an integrated circuit. In particular, the non-volatile memory devices may comprise dual bit cell structures. The above-described embodiments have been provided by way of example, and the present invention is not limited to these examples. Multiple variations and modification to the disclosed embodiments will occur, to the extent not mutually exclusive, to those skilled in the art upon consideration of the foregoing description. Additionally, other combinations, omissions, substitutions and modifications will be apparent to the skilled artisan in view of the disclosure herein. Accordingly, the present invention is not intended to be limited by the disclosed embodiments, but is to be defined by reference to the appended claims.
Claims (16)
1. A method of fabricating a non-volatile memory cell, the method comprising:
providing a substrate;
performing storage layer and gate processes over the substrate;
implanting dopants into the substrate;
capping with a silicide material over the substrate; and
formatting the silicide material;
wherein a Schottky barrier is formed in the substrate.
2. The method as set forth in claim 1 , further comprising activating the dopants.
3. The method as set forth in claim 1 , comprising programming the non-volatile memory cell.
4. The method as set forth in claim 3 , wherein the programming comprises injecting hot carriers.
5. The method as set forth in claim 4 , wherein the injecting comprises one or more of injecting hot electrons and injecting hot holes.
6. The method as set forth in claim 2 , wherein the activating occurs during the formatting of the silicide material.
7. The method as set forth in claim 2 , wherein the implanting is performed after the formatting of the silicide material.
8. The method as set forth in claim 2 , wherein the activating and the formatting comprise one or more low-temperature processes.
9. The method as set forth in claim 1 , wherein the implanting is preceded by patterning an active region and formatting a spacer.
10. The method as set forth in claim 1 , wherein the implanted dopants are activated by employing a relatively low-temperature thermal process.
11. The method as set forth in claim 10 , wherein the formatting comprises performing a thermal process to format the silicide material.
12. The method as set forth in claim 1 , wherein the formatting occurs prior to activation of the implanted dopants.
13. The method as set forth in claim 12 , wherein the formatting comprises performing a thermal process to activate the implanted dopants and format the silicide material whereby the Schottky barrier is modified by the dopant implantation and thermal process.
14. The method as set forth in claim 1 , wherein the capping and formatting are performed before the implanting.
15. The method as set forth in claim 14 , wherein the capping is preceded by patterning an active region and formatting a spacer.
16. The method as set forth in claim 15 , wherein the formatting of the silicide material comprises performing a thermal process.
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US12/430,817 US8183617B2 (en) | 2009-04-27 | 2009-04-27 | Injection method with Schottky source/drain |
US13/463,264 US20120220111A1 (en) | 2009-04-27 | 2012-05-03 | Injection method with schottky source/drain |
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US8183617B2 (en) | 2012-05-22 |
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