TWI375492B - Printed circuit board - Google Patents

Printed circuit board Download PDF

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Publication number
TWI375492B
TWI375492B TW98115495A TW98115495A TWI375492B TW I375492 B TWI375492 B TW I375492B TW 98115495 A TW98115495 A TW 98115495A TW 98115495 A TW98115495 A TW 98115495A TW I375492 B TWI375492 B TW I375492B
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Taiwan
Prior art keywords
metal pattern
circuit board
metal
element region
substrate
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TW98115495A
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Chinese (zh)
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TW201041457A (en
Inventor
Sung Lung Chen
Chao Yang Chen
Allen Hsu
Chin He Su
Chang Li Ho
Tung Sheng Chou
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Nan Ya Printed Circuit Board
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Priority to TW98115495A priority Critical patent/TWI375492B/en
Publication of TW201041457A publication Critical patent/TW201041457A/en
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Publication of TWI375492B publication Critical patent/TWI375492B/en

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Description

1375492 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種電路板,更特別關於一種可用於 X-ray非破壞檢測之電路板結構。 【先前技術】 我國的資訊電子工業近年來在蛛府及產業界的大力 # 推動下,已躋身成為世界主要的生產供應國,帶動了中游 之電子零組件業及上游原材料的蓬勃發展。在整個資訊、 通訊、以及消費性電子產業中,「印刷電路板」為不可或 缺之重要零組件。由印刷電路板業之產銷供需情形,即可 反咏出3C產業的榮枯興衰與技術水準之高低。印刷電路 板能將電子零组件連接在一起,使其發揮整體功能,因此 疋所有電子負訊產品不可或缺的基本構成要件。 印刷電路板(printed Circuit Board簡稱PCB )是依電 路設計,將連接電路零件的電氣佈線繪製佈線圖形,然後 鲁再以機械與化學加工、表面處理等方式,在絕緣體上使電 氣導體重現所構成的電路板。換言之,印刷電路板是搭配 電子零件之前的的基板。該類產品的作用是將各項電子零 件以電路板所形成的電子電路,發揮各項電子零組件的功 能’以達到信號處理的目的。由於印刷電路板設計品質的 良窥’不但直接影響電子產品的可靠度,亦可左右系統產 品整體的性能及競爭力。上述電路圖案是應用印刷、微 影、姓刻及電鍍等技術形成精密的配線,做為支撐電子零 件及零件間電路相互接續的組裝基地。因此,高密度化及1375492 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit board, and more particularly to a circuit board structure that can be used for X-ray non-destructive inspection. [Prior Art] In recent years, China's information electronics industry has become one of the world's major producers and suppliers, and has driven the booming development of the electronic components industry and upstream raw materials in the middle reaches. In the entire information, communications, and consumer electronics industries, "printed circuit boards" are indispensable components. The supply and demand situation of the printed circuit board industry can reverse the rise and fall of the 3C industry and the level of technology. Printed circuit boards connect electronic components together to make them function as a whole, making them an essential component of all electronic communication products. The printed circuit board (PCB) is designed according to the circuit, and the wiring pattern of the circuit parts is drawn, and then the electrical conductor is re-created on the insulator by mechanical and chemical processing, surface treatment, etc. Circuit board. In other words, the printed circuit board is the substrate before the electronic components. The function of this kind of product is to use the electronic circuit formed by the circuit board as the electronic circuit of the circuit board to achieve the purpose of signal processing. Due to the quality of printed circuit board design, it not only directly affects the reliability of electronic products, but also affects the overall performance and competitiveness of system products. The above circuit pattern is formed by applying techniques such as printing, lithography, surname etching and electroplating to form a precise wiring, and is used as an assembly base for supporting electronic components and circuits between components. Therefore, high density and

097040/9024-A51535-TW 1375492 多層化的配線形成技術成為印刷電路板製造業發展的主 流。 在多層電路板的設計中,基板之元件面(component side)及焊接面(solder side)最外層之金屬圖案(通常為銅層) 扮演焊球墊(ball pad),藉由錫球與外部其他電子元件接 線。由經驗可知,接線程度的好壞取決於最外層金屬圖案 的厚度。目前常見之最外層金屬圖案厚度的量測方法為抽 樣切片後,以電子顯微鏡量測厚度。由於切片為破壞性偵 測,僅能抽樣而無法進行全面量測,因此產品良率的控制 非常依賴抽樣的可靠性。再者,即使建立了完美的抽樣方 法,抽樣量測的樣品只能廢棄而無法作為商品販售,這將 提高生產成本。 綜上所述,目前仍需一種新的電路板結構以適用於非 破壞性量測外層金屬圖案之厚度。 .【發明内容】 本發明提供一種電路板,包括基板;第一金屬圖案, 位於基板之上表面上;第一介電層,位於第一金屬圖案上; 第二金屬圖案,位於第一介電層上;第一抗焊絕緣層,位 於第二金屬圖案上;其中第一抗焊絕緣層露出所有第一非 元件區之第二金屬圖案,以及部份第一元件區之第二金屬 圖案;其中第二金屬圖案具有第一非元件區及第一元件 區,且第一金屬圖案對應第一非元件區之部份不含有任何 金屬。 【實施方式】 本發明提供一種電路板結構10如第1圖所示。首先, 097040/9024-A51535-W 4 1375492 * · 提供基板11 ’其上表面為元件面11A,且下表面為焊接 面11B。基板材質可為紙質酚醛樹脂(paper phen〇lic resin)、複合環氧樹脂(c0mp0Site ep〇xy resin)、聚亞醒胺 樹脂(polyimide resin)、或玻璃纖維(glass fiber)。接著在基 板11兩侧依序形成金屬圖案13A及13B、介電層15A及 15B、金屬圖案17A及17B、抗焊絕緣層18A及18B。 金屬圖案之材質以銅為主,但亦可為鋁、鎳、金、或 上迷之舍金。將金屬層形成於基板11或介電層上的方法 0 可為濺鍍法、氣相沉積法、或化學電鍍法等常見方法。接 著以習知之微影製程圖案化金屬層,即可形成金屬圖案。 可以理解的是,同側之金屬圖案如13A及17A之間可藉 由導孔(vias)、埋孔(buried vias)、或盲孔(blind vias)等方 式連接(未圖示)。上述導孔係用以貫穿最内層及最外層之 金屬圖案,埋孔只連接部份内層之金屬圖案,而盲孔是將 部份内層金屬圖案連接至外層金屬圖案,不須貫穿所有金 屬圖案。 介電層之材質可為環氧樹脂(epoxy resin)、雙馬來亞 鲁 醯胺-三氮雜苯樹月旨(bismaleimide triacine,簡稱BT)、ABF 膜(ajinomoto built-up film)、聚苯醚(polyphenylene oxide, 簡稱PPE)、或聚四氟乙稀(polytetrafluorethylene,簡稱 PTFE)。介電層之形成方法可為物理方式之塗佈或熱壓合 等方法。 抗悍絕緣層18A及18B之材質可為綠漆,其形成方 法包含物理方式如塗佈等方法,具有複數個開口露出部份 金屬圖案17A及17B,用以與外部元件連線。連線方式可 利用焊球20拉出打線,或其他常見方式。此外,抗焊絕 5097040/9024-A51535-TW 1375492 Multi-layer wiring formation technology has become the mainstay of the development of printed circuit board manufacturing. In the design of a multilayer circuit board, the metal pattern of the outermost layer of the component side and the solder side of the substrate (usually a copper layer) acts as a ball pad, with solder balls and other external components. Wiring of electronic components. It is known from experience that the degree of wiring depends on the thickness of the outermost metal pattern. At present, the thickness of the outermost metal pattern is measured by measuring the thickness with an electron microscope after sampling. Since slicing is destructive and can only be sampled and cannot be fully measured, the control of product yield is highly dependent on the reliability of the sample. Furthermore, even if a perfect sampling method is established, the sampled sample can only be discarded and cannot be sold as a commodity, which will increase the production cost. In summary, there is still a need for a new circuit board structure suitable for non-destructive measurement of the thickness of the outer metal pattern. The present invention provides a circuit board including a substrate; a first metal pattern on the upper surface of the substrate; a first dielectric layer on the first metal pattern; and a second metal pattern on the first dielectric a first solder resist insulating layer on the second metal pattern; wherein the first solder resist insulating layer exposes the second metal pattern of all the first non-element regions, and the second metal pattern of the portion of the first device region; The second metal pattern has a first non-element region and a first device region, and the portion of the first metal pattern corresponding to the first non-element region does not contain any metal. [Embodiment] The present invention provides a circuit board structure 10 as shown in Fig. 1. First, 097040/9024-A51535-W 4 1375492 * The substrate 11' is provided with the upper surface of the element surface 11A and the lower surface of the substrate 11B. The material of the substrate may be paper phenocyanate resin, composite epoxy resin (c0mp0Site ep〇xy resin), polyamidide resin, or glass fiber. Next, metal patterns 13A and 13B, dielectric layers 15A and 15B, metal patterns 17A and 17B, and solder resist layers 18A and 18B are sequentially formed on both sides of the substrate 11. The metal pattern is made of copper, but it can also be aluminum, nickel, gold, or gold. The method 0 of forming a metal layer on the substrate 11 or the dielectric layer may be a common method such as a sputtering method, a vapor deposition method, or a chemical plating method. The metal pattern is then patterned by patterning the metal layer by a conventional lithography process. It can be understood that the metal pattern on the same side, such as 13A and 17A, can be connected by vias, buried vias, or blind vias (not shown). The via holes are used to penetrate the metal pattern of the innermost layer and the outermost layer. The buried vias only connect the metal patterns of the inner layers, and the blind holes connect the inner metal patterns to the outer metal patterns without passing through all the metal patterns. The material of the dielectric layer may be epoxy resin, bismaleimide triacine (BT), abinomoto built-up film, polyphenylene Polyphenylene oxide (PPE) or polytetrafluorethylene (PTFE). The method of forming the dielectric layer may be a physical coating or a thermocompression bonding method. The material of the anti-snoring insulating layers 18A and 18B may be a green lacquer, and the forming method includes a physical method such as coating, etc., and has a plurality of openings exposing a portion of the metal patterns 17A and 17B for connection with external components. The wiring method can be used to pull out the wire by the solder ball 20, or other common methods. In addition, anti-welding 5

097040/9024-A51535-TW 1375492 緣層需露出下述非元件區19B之金屬圖案17A及17B, 以利後續X-ray 測工作進行。 如第1圖所示,最外層之金屬圖案17A及17B可分 為元件區19A及非元件區19B。内層之金屬圖案13A及 13B之電路結構如導線均設置於對應元件區19A之部 份,而避開對應非元件區19B之部份。内層之金屬圖案 13A及13B對應非元件區19B之部份不具有任何金屬, 此部份可為氣隙(air gap)或被後續形成之介電層15 A及 15B填滿,因此用以測量非元件區19B厚度的X-ray將不 會受到内層金屬圖案13A及13B之干擾,進而準確量測 外層金屬圖案17A及17B之厚度。此非破壞性量測可用 於每一成品,可降低抽樣量測的不穩定性。 在本發明另一實施例中,更進一步含有其他内層之金 屬圖案21A及21B與介電層23A及23B,如第2圖所示。 在第2圖中,金屬圖案21A及21B對應非元件區19B之 部份並未如金屬圖案13A及13B —般不含有任何金屬, 而可含有電路結構如導線。這是因為X-ray之能量不足以 穿透至較内層之金屬圖案21A及21B,移除非元件區19B 之金屬圖案之設計只需應用於最接近金屬圖案17A及 17B之金屬圖案13A及13B即可。 但在電路板結構日益薄化之情況下,較内層之金屬圖 案21A及21B仍有可能會影響X-ray量測最外層金屬圖 案17A及17B之厚度。如此一來,金屬圖案21A及21B 之電路結構如導線均需設置於對應元件區19A之部份, 而避開對應非元件區19B之部份,如第3圖所示。如同金 屬圖案13A及13B,金屬圖案21A及2.1B對應非元件區 19B之部份不具有任何金屬的設計可有效避免干擾X-ray 6097040/9024-A51535-TW 1375492 The edge layer should expose the metal patterns 17A and 17B of the non-element region 19B described below for subsequent X-ray measurement work. As shown in Fig. 1, the outermost metal patterns 17A and 17B can be divided into an element region 19A and a non-element region 19B. The circuit structures of the inner metal patterns 13A and 13B, such as the wires, are disposed in portions of the corresponding element regions 19A while avoiding portions corresponding to the non-element regions 19B. The portions of the inner metal patterns 13A and 13B corresponding to the non-element regions 19B do not have any metal, and the portions may be air gaps or filled with subsequently formed dielectric layers 15 A and 15B, thereby measuring The X-ray of the thickness of the non-element region 19B will not be disturbed by the inner metal patterns 13A and 13B, thereby accurately measuring the thickness of the outer metal patterns 17A and 17B. This non-destructive measurement can be used on each finished product to reduce the instability of sampling measurements. In another embodiment of the present invention, the metal layers 21A and 21B and the dielectric layers 23A and 23B of the other inner layers are further included as shown in FIG. In Fig. 2, portions of the metal patterns 21A and 21B corresponding to the non-element regions 19B do not contain any metal as in the metal patterns 13A and 13B, but may contain circuit structures such as wires. This is because the energy of the X-ray is insufficient to penetrate the metal patterns 21A and 21B of the inner layer, and the design of the metal pattern for removing the non-element region 19B is applied only to the metal patterns 13A and 13B closest to the metal patterns 17A and 17B. Just fine. However, in the case where the circuit board structure is increasingly thinned, the inner metal patterns 21A and 21B may still affect the thickness of the outermost metal patterns 17A and 17B of the X-ray measurement. As a result, the circuit structures of the metal patterns 21A and 21B, such as the wires, need to be disposed in the corresponding element region 19A, while avoiding the portion corresponding to the non-element region 19B, as shown in FIG. Like the metal patterns 13A and 13B, the portions of the metal patterns 21A and 2.1B corresponding to the non-element region 19B do not have any metal can effectively avoid interference with the X-ray 6

097040/9024-A51535-TW 1375492 •量測最外層之金屬圖案17A及17B之厚度。 可以理解的是,上述之多層結構可進一步插置内層金 屬圖案與介電層於基板10及金屬圖案21a及21B之^, 並可視情況需要選擇性地移除插置之金屬圖案對應 件區19B的部份。 “ 在第1-3圖中,非元件區19B均位於電路板的角落部 匕然而本發明之非元件區應之位置可設置於其他部份 板中心。不論非元件區19B之設置位置為何,部份 ^有内層之金屬㈣對應非5件區的部份均 有任,金屬’以避免干擾\,量測外層金屬層之厚戶。 在弟1-3圖中,元件面11A及焊接面UB兩者 4 ^之1’但亦可為不重疊之情況如第4圖所示。第 *而,可增加製程彈 -定要重= =谭接的非元件區⑽ ^ 是並,=、13Β、17Α、17Β、21Α、 可依本身需要ϋ ί 一特疋電路結構。本技藝人士自 對就件區19Α\擇電適^^製。程及材料完成該些金屬圖案 隶後’雖然雙面均且,辦展么士磁达而 發明之結構^= 雖然本發明已以韋適用於單層電路板。 限定本發明,任何 二揭路如上’然其並非用以 和範圍内,當可作任者’在不脫離本發明之精神097040/9024-A51535-TW 1375492 • Measure the thickness of the outermost metal patterns 17A and 17B. It can be understood that the above-mentioned multilayer structure can further interpose the inner metal pattern and the dielectric layer on the substrate 10 and the metal patterns 21a and 21B, and optionally remove the interposed metal pattern corresponding portion 19B as occasion demands. Part of it. "In the first to third figures, the non-element regions 19B are located at the corners of the circuit board. However, the position of the non-element regions of the present invention may be set at the center of the other partial boards. Regardless of the position of the non-element regions 19B, Some of the metal with the inner layer (4) correspond to the non-5-part area, and the metal 'to avoid interference\, measure the thickness of the outer metal layer. In the brothers 1-3, the component surface 11A and the welding surface UB both 4^1' but can also be non-overlapping as shown in Figure 4. *, and can increase the processile - fixed weight = = non-component area of the tan (10) ^ Yes, =, 13Β, 17Α, 17Β, 21Α, can be used according to its own needs. 一 一 A special circuit structure. The skilled person is self-contained in the area of 19 Α \ select electricity ^ ^ system. The structure of the invention is the same as that of the invention. Although the present invention has been applied to a single-layer circuit board, the invention is not limited to the scope and scope of the present invention. The servant' does not depart from the spirit of the present invention

範圍當視後附之申請Ϊ利範 097040/9024-A51535-TW 1375492 【圖式簡單說明】 第1-4圖係本發明不同實施例之電路板剖示圖 【主要元件符號說明】 10〜電路板結構, 11〜基板, 11A〜元件面; 11B〜焊接面; 13A、13B、17A ' 17B、21A、21B-電路圖案; 15A、15B、23A、23B〜介電層; 18A、18B〜抗焊絕緣層; 19A〜元件區; 19B〜非元件區; 20〜焊球。Scope of the application is hereinafter referred to as Philip 097040/9024-A51535-TW 1375492 [Simplified illustration of the drawings] Figures 1-4 are schematic diagrams of circuit boards of different embodiments of the present invention Structure, 11~substrate, 11A~component surface; 11B~welding surface; 13A, 13B, 17A '17B, 21A, 21B-circuit pattern; 15A, 15B, 23A, 23B~ dielectric layer; 18A, 18B~ solder resist Layer; 19A ~ component area; 19B ~ non-element area; 20 ~ solder ball.

097040/9024-A51535-TW097040/9024-A51535-TW

Claims (1)

1375492 七、申晴專利範圍·· h一種電路板,包括: 一基板; 一,一金屬圖案,位於該基板之上表面上; 一第一介電層,位於該第一金屬圖案上; ―,二金屬圖案,位於該第一介電層上; i第二抗烊絕緣層,位於該第二金屬圖案上; 第二=ί —抗焊絕緣層露出所有該第-非元件區" -1 ’以及部份該第一元件區之第二金屬圖案 -^該第—金屬圖案具有一第一非元件區及一第一 含有^1Γ。—金屬圖案對應該第—非元件區之部份不 面係^&請專利範圍第1項所述之電路板,其中該上表 3.如申請專利範圍第〗項所述之 面係焊接面。 /、〒该上表 金屬請第1項所狀電路板,其中該第— -介if 第一非元件區之部份包括-氣隙或該第 5·如申請專利範圍第1項所述之電路板, :屬圖案夾設於該第一金屬圖案與該基板: 金屬圖案與該第-金屬圖案之間包括一第二介電層弟二 6. 如申請專利範圍第5項所述之電路板,复 金屬圖案對應該第—非元件區之部份不含有任何金^.。― 7. 如申請專利範圍第5項所述之電路板,其中。一 對應該第一非元件區之部份包括一氣隙或該; TW 097040/9024-A51535- 1375492 m專利範圍第1項所述之電路板,更包括: =金屬圖案,位於該基板之下表面下; 一 一;丨電層,位於該第四金屬圖案下; 二第五金相案’位於該第三介電層下; =二抗焊絕緣層,位於該第五金屬圖案下; nit該第二抗焊絕緣層露出所有該第二非元件區之 苴’以及部份該第二元件區之第五金屬圖案; “中該弟五金屬圖案具有_第二非元件區及一第二 人古L且該第四金屬圖案對應該第二非元件區之部份不 含有任何金屬。 9.如申請專利範圍第8項所述之 一 非元件區與該第二非元件區重疊。 才反,、中该弟 ^申請專利範圍第8項所述之電路板,其中該第四 對應該第二非元件區之部份包括—氣隙或該苐 一介電層。 11·如中請專利範圍帛8項所述之電路板,更包括第六 金屬圖案夾設於該第四金屬圖案與該基板之間,且該第六 金屬圖案與該第四金屬圖案之間包括—第四介電層。 12·如申請專利範圍第11項所述之電路板,其曰中該第 六金屬圖案對應該第二非元件區之部份不含有任何金屬。 13.如申請專利範圍第u項所述之電路板,其中該第 六金屬圖案對應該非元件區之部份包括—氣隙或該第/四 097040/9024-A51535-TW1375492 VII. Shen Qing Patent Range·· h A circuit board comprising: a substrate; a metal pattern on the upper surface of the substrate; a first dielectric layer on the first metal pattern; a second metal pattern on the first dielectric layer; a second anti-dye insulating layer on the second metal pattern; a second = ί - a solder resist insulating layer exposing all of the first-non-element regions " -1 And a portion of the second metal pattern of the first component region - the first metal pattern has a first non-element region and a first containing region. - the metal pattern corresponds to the portion of the first-non-element area that is not in the surface of the circuit board of the first aspect of the patent, wherein the above table 3. The surface welding as described in the scope of the patent application surface. /, 〒 the above table metal, please refer to the circuit board of the first item, wherein the first part of the first non-component area includes - air gap or the fifth paragraph as described in claim 1 a circuit board, wherein the pattern is sandwiched between the first metal pattern and the substrate: a second dielectric layer is included between the metal pattern and the first metal pattern. 6. The circuit of claim 5 The plate, the complex metal pattern corresponds to the portion of the first-non-component area that does not contain any gold. ― 7. For the circuit board described in item 5 of the patent application, wherein. The circuit board of the first aspect of the first non-component area includes an air gap or the TW 097040/9024-A51535-1375492 m patent range, further comprising: a metal pattern on the lower surface of the substrate One; one electric layer, located under the fourth metal pattern; two second hardware phase 'below the third dielectric layer; = two solder resist layer, located under the fifth metal pattern; nit the first The second solder resist insulating layer exposes all the second non-element regions and a portion of the fifth metal pattern of the second device region; "the middle five metal pattern has a second non-element region and a second human L and the portion of the fourth metal pattern corresponding to the second non-element region does not contain any metal. 9. A non-element region overlaps with the second non-element region as described in claim 8 of the patent application. The circuit board of claim 8, wherein the fourth pair of portions of the second non-element region includes an air gap or the first dielectric layer. The circuit board of item 8 includes a sixth metal pattern clamping Between the fourth metal pattern and the substrate, and a fourth dielectric layer between the sixth metal pattern and the fourth metal pattern. 12. The circuit board according to claim 11, wherein The sixth metal pattern corresponds to a portion of the second non-element region that does not contain any metal. 13. The circuit board of claim 5, wherein the sixth metal pattern corresponds to a portion of the non-element region Including - air gap or the fourth / 097040 / 9024 - A51535 - TW
TW98115495A 2009-05-11 2009-05-11 Printed circuit board TWI375492B (en)

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TWI375492B true TWI375492B (en) 2012-10-21

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