JP2004342686A - Multilayered wiring board, substrate for multilayered substrate, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayered wiring board from which a sufficient thermal expansion suppressing effect can be obtained without causing any restriction on the higher density and higher precision of via holes. <P>SOLUTION: A circuit pattern 24 is formed on the conductor layer 23 for circuit of a three-layer laminated material composed of the conductor layer 23, an insulating substrate layer 22, and a low-thermal expansion metallic layer 21. Lower holes 25 having larger diameters than the via holes 27 have are formed in the metallic layer 21. Then an adhesive layer 26 is provided on the surface of the metallic layer 21, and the via holes 27 are formed through the insulating substrate layer 22, metallic layer 21, and adhesive layer 26. In addition, a conductive material 29 which performs interlayer conduction is packed in the via holes 27. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer wiring board, a substrate for a multilayer substrate, and a method of manufacturing the same, and more particularly, to a multilayer wiring board used as a wiring board or a package substrate having two or more wiring layers, a substrate for a multilayer substrate, and a method of manufacturing the same. It is about.
[0002]
[Prior art]
In recent years, miniaturization of printed circuits has been progressing rapidly, supported by advances in manufacturing processes and materials, such as higher precision of photolithography and thinning of circuit materials.
[0003]
Conventionally, the pitch of a printed circuit is reduced by using a DIP (Dual Line-Package) method in which the I / O of a semiconductor (Si chip) is expanded in accordance with the printed circuit by a package using a wire bonding technique and a lead frame. And a QFP (Quad Flat Package) system, which has been developed to a flip chip bonding system in which a Si chip is directly bonded to a printing base. By adopting the flip chip bonding method, the mounting density can be significantly increased, the loss occurring in the transmission line can be eliminated, and the Si chip can be operated on the substrate without impairing the performance of the Si chip itself. .
[0004]
These technologies are called COB (Chip on Board), COF (Chip on Flexible Board, or Chip on Flex), and are employed in portable electronic devices and flat displays that require thinness.
[0005]
The COB and COF techniques include a method of directly connecting an I / O pad of a Si chip to an electrode on a printed circuit board, and a method of bonding a chip to a base slope at a non-electrode portion and connecting both electrodes by wire bonding. There is a way.
[0006]
The former technique is advantageous for minimizing connection losses. Since the coefficient of thermal expansion of Si is extremely smaller than the coefficient of thermal expansion of polyimide or epoxy resin used for general printed circuit boards, the difference in thermal expansion between the two due to heat generation of the chip and changes in environmental temperature. Is generated. Since this distortion increases as the chip size increases, the size of the chip to which the present connection technology can be applied is restricted, and there has been a problem that the reliability of electrical connection is inferior to that of a lead frame or wire bonding.
[0007]
In order to cope with such a problem, attempts have been made to improve materials and structures so that the thermal expansion of the printed circuit board approaches that of Si. In particular, a structure in which a material having a low thermal expansion coefficient is embedded in the insulating layer of a printed circuit board to suppress the thermal expansion of the entire substrate is capable of controlling the thermal expansion coefficient over a wide range by selecting the material to be embedded. Promising. The embedding type includes a metal foil (metal core) having a low thermal expansion coefficient embedded in an insulating resin (for example, Non-Patent Document 1) and a low thermal expansion resin embedded in an insulating resin (for example, Non-Patent Document 1). There is 2).
[0008]
A manufacturing process of a metal core type (conventional example 1) multi-layer substrate base material will be described with reference to FIGS.
[0009]
As shown in FIG. 4A, first, a pilot hole (opening) 102 is formed at a position corresponding to a through-hole of the low-thermal-expansion metal foil (metal core) 101 alone. A copper foil 104 is pressed on both sides with an insulating resin 103 interposed therebetween to obtain a laminated base material 100 having a conductor (copper foil 104) on both front and back surfaces as shown in FIG.
[0010]
Next, as shown in FIG. 4C, a through hole (through hole) 105 penetrating through the laminated base material 100 is processed, and an inner wall of the through hole 105 is plated to form an interlayer conductive portion 106. Then, as shown in FIG. 4E, the copper foil 104 on both sides is etched to form a circuit (land pattern 107), as shown in FIG. 4E.
[0011]
When this technology is applied to an IVH substrate capable of via-on-via, a manufacturing process as shown in FIGS. 5A to 5E is assumed.
[0012]
As shown in FIG. 5A, first, a prepared hole (opening) 202 is formed at a position corresponding to a through hole of the low-thermal-expansion metal foil 201 alone, and a hole is formed on one surface of the low-thermal-expansion metal foil 201. Is laminated with a copper foil 204 with the insulating resin 203 interposed therebetween and only the insulating resin 203 on the other surface to obtain a laminated base material 200 as shown in FIG. 5B.
[0013]
Next, as shown in FIG. 5C, a non-penetrating via hole 205 from which only the resin part of the laminated base material 200 is removed is opened, and the opened via hole 205 is filled with a conductive paste 206 (FIG. 5C). 5 (d)). Then, as shown in FIG. 5E, the copper foil 204 is etched to form a circuit (land pattern 207).
[0014]
A manufacturing process of a low-thermal-expansion-resin sandwiching method (conventional example 2) for a substrate for a multilayer substrate will be described with reference to FIGS.
[0015]
As shown in FIG. 7A, a resin three-layer laminate 300 as shown in FIG. 7B is obtained by sandwiching an insulating resin 302 on both sides of a low thermal expansion resin film 301. . In the case of resin, since it is non-conductive, it is not necessary to avoid a via in the low thermal expansion resin portion, so that the resin is laminated on the low thermal expansion resin film 301 without patterning.
[0016]
Next, as shown in FIG. 7C, via holes 303 are collectively opened in the low thermal expansion resin film 301 and the base resin (insulating resin 302) using a laser. Then, a copper foil 304 is adhered to one surface of the resin three-layer laminate 300 (see FIG. 7D), and then, as shown in FIG. Fill 305. Then, as shown in FIG. 7F, the copper foil 304 is etched to form a circuit (land pattern 306).
[0017]
[Non-patent document 1]
“Development of Multilayer Substrate with Low Thermal Expansion” Nitto TechnicaI Report Vol. 36, no. 1 May 1998 [Non-Patent Document 2]
"Batch laminating base layer technology and high-speed multilayer substrate technology" Nagano Prefectural Institute of Technology Open University Technical Conference Latest high-performance multilayer substrate technology 2002.7.24 Text 15 pages
[Problems to be solved by the invention]
In the base material for a multi-layer substrate of the metal core system (FIG. 5), since the low thermal expansion metal foil 201 which has been patterned in advance (prepared with a prepared hole 202) is used, the pattern of the low thermal expansion metal foil 201 and the pattern of the copper foil 204 are used. There is a limit in improving the matching accuracy, and there is a restriction on miniaturization of a via that is processed based on a circuit position (land pattern) by the copper foil 204.
[0019]
This is because the pattern of the low-thermal-expansion metal foil 201 cannot maintain the dimensional (positional) accuracy immediately after the processing due to a deformation in a process such as heating or pressing to which the laminated base material 200 is exposed after the pattern processing. Furthermore, since the low thermal expansion metal foil 201 is sandwiched between the softened resins from the front and back during pressing, it is difficult to maintain its flatness.
[0020]
FIG. 6 shows a state of misalignment when the via diameter is dv and the opening diameter of the prepared hole 202 of the low thermal expansion metal foil 20 is dl. In consideration of the deviation δ, when the opening diameter dl of the low thermal expansion metal foil 20 is increased with respect to the via diameter dv so that the via (conductive paste 206) and the low thermal expansion metal foil 201 are not electrically connected, the via density is increased. Accordingly, the area occupied by the low-thermal-expansion metal foil 201 in one laminated base material decreases, and a sufficient effect of suppressing thermal expansion cannot be obtained. For this reason, there is a restriction in increasing the density of vias. Therefore, it is necessary to improve the alignment accuracy and make the opening diameter dl closer to the d-via diameter dv.
[0021]
In the base material for a multilayer substrate of the low thermal expansion resin sandwiching method (FIG. 7), it is not necessary to form an opening (prepared hole) having a diameter slightly larger than the via in the low thermal expansion resin film 301, so that a portion having a high via density is sufficient. A large thermal expansion suppressing effect can be obtained. As a low thermal expansion resin, polyamide resin is effective, but the via is not formed smoothly because the melting point is high and the laser processability is significantly different from thermoplastic resin and thermosetting resin that can be applied as insulating base material. There is.
[0022]
FIG. 8 shows a typical example. The diameter of the via hole 303 is smaller than that of the opening diameter da near the surface because the opening 303A of the low thermal expansion resin film portion is narrowed. As described above, since it is difficult to form a via smoothly using materials having different workability, there is a restriction in miniaturizing the via. In particular, when the diameter of the via becomes small, the above-mentioned problem becomes apparent, and thus there is a restriction on the refinement of the via.
[0023]
The present invention has been made in order to solve the above-described problems, and in a metal core type multilayer substrate, high alignment accuracy can be ensured, and the opening diameter of the low thermal expansion metal layer can be made closer to the via diameter. It is an object of the present invention to provide a multilayer wiring board, a substrate for a multilayer substrate, and a method of manufacturing the same, which can provide a sufficient effect of suppressing thermal expansion without causing a restriction in increasing the density and definition of vias.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, a multi-layer substrate substrate according to the present invention includes an insulating base layer, a circuit conductor layer provided on one surface of the insulating base layer, and the insulating base layer. A circuit pattern is formed on the circuit conductor layer of the three-layer laminated material having the low thermal expansion metal layer provided on the other surface of the material layer, and the low thermal expansion metal layer of the three-layer laminated material has a diameter larger than a via hole. A pilot hole is formed, an adhesive layer is provided on the surface of the low thermal expansion metal layer, a via hole is formed through the insulating base material layer, the low thermal expansion metal layer, and the adhesive layer, and the via hole is formed. A conductive material that performs interlayer conduction is provided.
[0025]
In the base material for a multilayer substrate according to the present invention, both the circuit pattern and the prepared hole of the low-thermal-expansion metal layer are formed in the state of a three-layer laminated material including the circuit conductor layer, the insulating base material layer, and the low-thermal-expansion metal layer. Therefore, there is no alignment error between the circuit pattern and the lower hole of the low thermal expansion metal layer, and the opening diameter of the low thermal expansion metal layer can be made closer to the via diameter, thereby increasing the density and definition of vias. It is possible to miniaturize the prepared holes and vias without any restrictions.
[0026]
The substrate for a multilayer substrate according to the present invention includes a copper foil as the circuit conductor layer, a polyimide film as the insulating substrate layer, and Fe-Ni, Mo, Ta, Ti, Zr, as the low thermal expansion metal layer. A metal containing W as a main component and a thermoplastic polyimide can be used as the adhesive layer.
[0027]
Further, the base material for a multilayer substrate according to the present invention uses a thermoplastic resin for the insulating base material layer and the adhesive material layer, and sets the glass transition temperature of the thermoplastic resin constituting the insulating base material layer to the adhesiveness. It should be higher than the glass transition temperature of the thermoplastic resin constituting the material layer.
[0028]
Further, in the base material for a multilayer substrate according to the present invention, a liquid crystal polymer can be used as the heat-cleanable resin.
[0029]
In the multilayer wiring board according to the present invention, the multilayer substrate according to the above-described invention is used for at least one layer, and a multilayer substrate having a sufficient thermal expansion suppressing effect can be obtained.
[0030]
The method for producing a substrate for a multilayer substrate according to the present invention is characterized in that a three-layer laminate having a metal layer for a circuit on one side of an insulating substrate layer and a low thermal expansion metal layer on the other side is used as a starting material. A signal circuit in the circuit metal layer of the layer laminate, a step of forming a pilot hole having a diameter larger than the via hole in the low thermal expansion metal layer, and a step of forming an adhesive layer on the side of the low thermal expansion metal layer, Forming a via hole from the adhesive layer side; and providing a conductive material in the opened via hole.
[0031]
According to the method of manufacturing a substrate for a multilayer substrate according to the present invention, a three-layer laminate having a metal layer for a circuit on one surface of an insulating substrate layer and a low thermal expansion metal layer on the other surface is used as a starting material, Since the signal circuit is formed in the circuit metal layer of the starting material and the pilot hole is formed in the low thermal expansion metal layer, no alignment error occurs between the circuit pattern of the signal circuit and the lower hole of the low thermal expansion metal layer. The opening diameter of the metal layer can be made close to the via diameter, and there is no restriction in increasing the density and definition of the via, and the pilot hole and the via can be miniaturized.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows one embodiment of a substrate for a multilayer substrate according to the present invention.
[0033]
The multilayer substrate 10 of the present embodiment includes an insulating substrate layer 11, a circuit conductor layer 12 provided on one surface of the insulating substrate layer 111, and the other of the insulating substrate layer 11. A circuit pattern is formed on the circuit conductor layer 12 of the three-layer laminated material having the low thermal expansion metal layer 13 provided on the surface, and a diameter larger than the via hole 14 is provided at a position corresponding to the via hole of the low thermal expansion metal layer 13 of the three-layer laminated material. A pilot hole 15 is formed.
[0034]
Then, an adhesive layer 16 is provided on the surface of the low thermal expansion metal layer 13, a via hole 14 penetrating the insulating base material layer 11, the low thermal expansion metal layer 13, and the adhesive layer 16 is formed. Is filled with a conductive paste 17.
[0035]
Since the circuit conductor layer 12 and the low thermal expansion metal layer 13 are formed on the front and back surfaces of the same base material (insulating base material layer 11) from the beginning, this multi-layer substrate base material 10 can accurately determine the pattern of both. They can be matched and are suitable for circuit refinement.
[0036]
The insulating base material layer 11 uses a high heat-resistant resin such as polyimide, so that even if the adhesive flows in the bonding step, the positional accuracy (alignment, spacing) between the circuit conductor layer 12 and the low thermal expansion metal layer 13 is improved. Is maintained.
[0037]
In addition, by using a polyimide-based material for the adhesive layer 16, it is possible to form a smooth via by matching the workability with the insulating base material layer 11 and to cope with miniaturization of the via. Becomes possible.
[0038]
As shown in FIG. 2, the multilayer substrate having the fine circuit can be easily controlled by arbitrarily controlling the coefficient of thermal expansion by laminating the multilayer substrate 10 as a unit. be able to.
[0039]
The base material 10 for a multi-layer substrate has a low thermal expansion metal layer 13 interposed between an insulating base material layer 11 and an adhesive material layer 16 to reduce the thermal expansion coefficient of the entire base material. It is possible to arbitrarily control the coefficient of thermal expansion of the entire substrate by selecting the material of the material and selecting its thickness.
[0040]
Also, by sandwiching a high thermal expansion material instead of a low thermal expansion material, the thermal expansion coefficient of the entire base material can be increased, and it can be widely matched with various components mounted on the wiring board.
[0041]
Next, a manufacturing process of the multilayer wiring board according to the present invention will be described with reference to FIGS.
[0042]
A three-layer laminated material, which is a starting material for a substrate for a multilayer substrate, is produced as follows. First, a precursor of a polyimide made of polyamic acid is applied to a 45 wt% Fe-Ni alloy foil and baked, so that the Fe-Ni alloy layer 21 forming a low thermal expansion metal layer as shown in FIG. Then, a two-layer structure film made of the polyimide film 22 forming the insulating base material layer is prepared.
[0043]
Ni and Cu were sequentially sputtered on the polyimide film 22 of the two-layer structure film, and copper was electroplated using the sputter film as an electrode (seed layer). Thereby, as shown in FIG. 3B, the copper foil layer 23 is formed on the surface of the polyimide film 22 opposite to the side of the Fe—Ni alloy layer 21.
[0044]
The above is the same as the manufacturing method of a general copper clad laminated base material (CCL: Copper Clad Lamination). The first step is sometimes called a casting method, and the subsequent steps are sometimes called a metallizing method.
[0045]
In this manufacturing method, the choice of low expansion metal material is wide, and it is possible to use an alloy “Invar” in which Mn and carbon are added to Ni—Fe, and low thermal expansion metals such as Mo, Ta, Ti, Zr, and W. it can. Since the coefficient of thermal expansion is particularly low and an etching technique is established, an Fe / Ni-based alloy is effective.
[0046]
Since the formation of a plating film is widely performed industrially on the Fe—Ni alloy, a three-layer laminate material is formed by plating Fe—Ni and Cu on the front and back surfaces of the polyimide film 22 in addition to the above-described method. Can also be prepared. In this case, the thermal expansion coefficient of the entire substrate can be changed by increasing or decreasing the plating thickness.
[0047]
As the insulating base material layer, instead of the polyimide film 22, a heat curable film which shows adhesiveness by heating, such as a liquid crystal polymer, can be used. In this case, a three-layer laminated material can be produced by thermocompression-bonding a heat-curable film between a previously prepared copper foil and a low thermal expansion metal foil.
[0048]
As shown in FIG. 3C, the signal circuit 24 is formed by etching the copper foil layer 23 of the already manufactured three-layer laminated material, and the via is formed by etching the Fe—Ni alloy layer 21. The opening (prepared hole) 25 for ensuring the insulation isolation of the above was formed to be slightly larger than the via. Therefore, the signal circuit 24 and the opening 25 can be formed without an alignment error. By doing so, vias connecting circuits between adjacent layers can penetrate the Fe-Ni alloy layer 21 so as not to contact the layer.
[0049]
Next, as shown in FIG. 3D, a thermoplastic polyimide film 26 serving as an adhesive layer was attached to the Fe—Ni alloy layer 21 side. The adhesive is not limited to a film-like material, but can also be formed by applying a varnish-like material.
[0050]
A thermoplastic material other than polyimide can be used as the adhesive. Examples of such candidates include PEEK (Poly Ether Ether Keton), PEI (Poly Ether Imide), and a liquid crystal polymer.
[0051]
In particular, a liquid crystal polymer is a material that has received attention because of its small transmission loss in a high-frequency signal region. The glass transition of the material used for the adhesive layer in which both the insulating base layer and the adhesive layer of the four layers (copper foil layer / insulating layer / Fe—Ni alloy layer / adhesive layer) of the present invention are composed of liquid crystal polymer Selecting a material so that the temperature is lower than that of the insulating layer can also be effectively used in the present invention.
[0052]
Next, as shown in FIG. 3 (e), a laser was applied from the adhesive layer side to the copper foil layer / insulating layer (polyimide film 22) / Fe—Ni alloy layer / adhesive layer. Irradiation opened a via hole 27.
[0053]
In the via portion, the opening 25 is previously etched in the Fe / Ni alloy layer 21 sandwiched between the insulating layer (polyimide film 22) and the adhesive layer (thermoplastic polyimide film 26). The (insulating layer and adhesive layer) are easily removed, and a via hole 27 reaching the surface copper foil (signal circuit 24) can be formed.
[0054]
If necessary, a part of the surface copper foil may be penetrated to improve the filling property of the conductive material into the via. Also in the present embodiment, a small-diameter hole 28 is opened in the copper foil layer.
[0055]
Next, as shown in FIG. 3F, the conductive material 29 was printed and filled in the opened via hole 27 from the adhesive layer side. In the present embodiment, a polymer paste in which metal powder is dispersed in an epoxy resin is used as the conductive material 29. In the present invention, in addition to a conductive material using a resin as a binder, a technique for obtaining a stronger connection by filling with a low melting point metal such as solder or nanoparticles is also applicable.
[0056]
As described above, the filled conductive material 29 forms the base material 30 for a multilayer substrate having vias that electrically connect the front and back surfaces without contacting the Fe—Ni alloy layer 21.
[0057]
As shown in FIGS. 3 (g) and 3 (h), a plurality of (three) multi-layer wiring base materials 30 and a lowermost copper foil 31 produced by the same method are laminated and hot-pressed. Thermocompression bonding is performed by a press or the like to soften the adhesive layer (thermoplastic polyimide film 26) and perform interlayer bonding. Finally, as shown in FIG. 3 (i), the surface layer circuit 32 is formed by etching the lowermost copper foil 31 to complete the IVH multilayer wiring board.
[0058]
As a result, in the IVH multilayer wiring board using the metal core type substrate for a multilayer substrate, a sufficient effect of suppressing thermal expansion can be obtained without restricting the density and definition of vias.
[0059]
【The invention's effect】
As can be understood from the above description, the substrate for a multilayer substrate according to the present invention has a circuit pattern and a low thermal expansion in a state of a three-layer laminated material including a circuit conductor layer, an insulating substrate layer, and a low thermal expansion metal layer. Since both the lower holes of the metal layer are formed, no alignment error occurs between the circuit pattern and the lower hole of the low thermal expansion metal layer, and the opening diameter of the low thermal expansion metal layer can be made closer to the via diameter, There is no restriction on increasing the density and definition of vias, and it is possible to reduce the size of prepared holes and vias, and to obtain a sufficient effect of suppressing thermal expansion.
[Brief description of the drawings]
FIG. 1 is a sectional view showing one embodiment of a base material for a multilayer substrate according to the present invention.
FIG. 2 is a sectional view showing one embodiment of a multilayer wiring board according to the present invention.
FIGS. 3A to 3I are diagrams illustrating a process for manufacturing a multilayer substrate and a multilayer wiring board according to one embodiment.
4 (a) to 4 (e) are diagrams showing a manufacturing process of a base material for a multilayer substrate of Conventional Example 1. FIG.
5 (a) to 5 (e) are views showing a process for manufacturing a substrate for an IVH multilayer wiring board of Conventional Example 1. FIG.
FIG. 6 is a diagram showing a misalignment in Conventional Example 1.
7 (a) to 7 (f) are views showing a manufacturing process of a base material for a multilayer substrate according to Conventional Example 2. FIG.
FIG. 8 is a diagram showing a via shape defect in Conventional Example 2.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Multilayer board base material 11 Insulating base material layer 12 Circuit conductor layer 13 Low thermal expansion metal layer 14 Via hole 15 Prepared hole 16 Adhesive material layer 17 Conductive paste 21 Fe-Ni alloy layer 22 Polyimide film 23 Copper foil layer 24 Signal Circuit 25 opening (prepared hole)
26 thermoplastic polyimide film 27 via hole 28 hole 28
29 Conductive material 30 Multilayer wiring substrate 31 Copper foil 32 Circuit

Claims (6)

Three-layer laminate including an insulating base material layer, a circuit conductor layer provided on one surface of the insulating base material layer, and a low thermal expansion metal layer provided on the other surface of the insulating base material layer A circuit pattern is formed in the circuit conductor layer of the material, a prepared hole having a diameter larger than a via hole is formed in the low thermal expansion metal layer of the three-layer laminated material, and an adhesive layer is provided on a surface of the low thermal expansion metal layer. And a via hole penetrating through the insulating base material layer, the low thermal expansion metal layer, and the adhesive layer, and a conductive material for performing interlayer conduction is provided in the via hole. A copper foil as the circuit conductor layer, a polyimide film as the insulating base material layer, and a metal mainly composed of Fe-Ni, Mo, Ta, Ti, Zr, W as the low thermal expansion metal layer, The base material for a multilayer substrate according to claim 1, wherein a thermoplastic polyimide is used as the adhesive layer. Using a thermoplastic resin for the insulating base layer and the adhesive layer, the glass transition temperature of the thermoplastic resin constituting the insulating base layer is the glass transition temperature of the thermoplastic resin constituting the adhesive layer. 2. The substrate for a multilayer substrate according to claim 1, which is higher. 4. The substrate for a multilayer substrate according to claim 3, wherein a liquid crystal polymer is used as the heat-cleanable resin. A multilayer wiring board using the multilayer substrate according to any one of claims 1 to 4 for at least one layer. Starting from a three-layer laminate having a circuit metal layer on one side of the insulating base material layer and a low thermal expansion metal layer on the other side,
Forming a signal circuit in the circuit metal layer of the three-layer laminate and a pilot hole having a diameter larger than the via hole in the low thermal expansion metal layer;
Forming an adhesive layer on the side of the low thermal expansion metal layer,
Opening a via hole from the adhesive layer side,
Providing a conductive material in the opened via hole;
A method for producing a substrate for a multilayer substrate, comprising:

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