TWI374527B - A semiconductor device and a method for manufacturing of the same - Google Patents

A semiconductor device and a method for manufacturing of the same Download PDF

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Publication number
TWI374527B
TWI374527B TW094135613A TW94135613A TWI374527B TW I374527 B TWI374527 B TW I374527B TW 094135613 A TW094135613 A TW 094135613A TW 94135613 A TW94135613 A TW 94135613A TW I374527 B TWI374527 B TW I374527B
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TW
Taiwan
Prior art keywords
semiconductor wafer
semiconductor device
solder resist
semiconductor
layer
Prior art date
Application number
TW094135613A
Other languages
Chinese (zh)
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TW200629509A (en
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW200629509A publication Critical patent/TW200629509A/en
Application granted granted Critical
Publication of TWI374527B publication Critical patent/TWI374527B/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A first solder resist section and a second solder resist section are formed over an upper surface of a wiring board. A semiconductor chip is bonded onto the first solder resist section via an adhesive interposed therebetween. Electrodes of the semiconductor chip are respectively electrically connected to connecting terminals exposed through openings of the second solder resist section via bonding wires. An encapsulating resin is formed over the upper surface of the wiring board so as to cover the semiconductor chip and the bonding wires. A plane dimension of the first solder resist section is smaller than that of the semiconductor chip, and the encapsulating resin is filled even below an outer peripheral portion of a back surface of the semiconductor chip.

Description

九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置及其製造技術，尤其是關 於適用於，於佈線基板上搭載有半導體晶片之半導體裝置 及其製造技術且較為有效之技術。 【先前技術】 將半導體晶片搭載於佈線基板上，以接合線電性連接半 導體晶片之電極及佈線基板之連接端子，並對半導體晶片 以及接合線進行樹脂密封，將錫球連接於佈線基板之背 面，藉此製造半導體封裝形態之半導體裝置。於如此半導 體裝置中，存在有例如，略微大於稱為CSP(Chip Size Package，晶片尺寸密封）之晶片尺寸或半導體晶片之小型 半導體封裝。 於曰本專利特開2003 — 92374號公報（專利文獻丨）中，揭 示有如下技術，一種半導體裝置含有：佈線基板，其含有 主面、於主面上所形成之絕緣膜及自該絕緣膜露出且形成 於上述主面上之電極；半導體晶片，其經由接著材而固定 於佈線基板主面上之絕緣膜上；導電性導線，其連接佈線 基板主面之電極與半導體晶片之電極；以及密封體，其覆 蓋半導體晶片，佈線基板之主面以及電極，且於該種半導 體裝置中’於半導體晶片與電極之間藉由於絕緣膜深度全 部區域中除去絕緣膜而形成槽，故而接著材（絕緣性樹脂） 之流出部分將滯留於槽内而不會溢出槽，因此不會到達電 極中。 105491-971003.doc 1374527 [專利文獻1]日本專利特開2003 — 92374號公報 [發明所欲解決之問題] 根據本發明者之研討，首次瞭解到如下者。 如CSP形態之半導體裝置般，若使半導體封裝小型化， 則半導體晶片之端部與佈線基板電極之距離將會變近。於 使用接著材將半導體晶片固定於佈線基板上之情形時，若 該接著材流出至佈線基板之電極上，則會易於產生接合線[Technical Field] The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device suitable for mounting a semiconductor wafer on a wiring substrate and a manufacturing technique thereof, and a relatively effective technique . [Prior Art] A semiconductor wafer is mounted on a wiring board, and a connection terminal between the electrode of the semiconductor wafer and the wiring board is electrically connected to the bonding wire, and the semiconductor wafer and the bonding wire are resin-sealed, and the solder ball is connected to the back surface of the wiring substrate. Thereby, a semiconductor device in a semiconductor package form is manufactured. In such a semiconductor device, there is, for example, a small-sized semiconductor package which is slightly larger than a wafer size or a semiconductor wafer called a CSP (Chip Size Package). Japanese Patent Laid-Open Publication No. 2003-92374 (Patent Document No.) discloses a semiconductor device including a wiring substrate including a main surface, an insulating film formed on the main surface, and an insulating film. An electrode exposed on the main surface; a semiconductor wafer fixed to an insulating film on a main surface of the wiring substrate via a bonding material; and a conductive wire connecting the electrode of the main surface of the wiring substrate and the electrode of the semiconductor wafer; a sealing body covering a semiconductor wafer, a main surface of the wiring substrate, and an electrode, and in the semiconductor device, a groove is formed between the semiconductor wafer and the electrode by removing the insulating film in the entire region of the depth of the insulating film, so that the bonding material is The outflow portion of the insulating resin) stays in the groove and does not overflow the groove, so it does not reach the electrode. [Patent Document 1] Japanese Laid-Open Patent Publication No. 2003-92374 [Problems to be Solved by the Invention] According to the study of the present inventors, the following is known for the first time. As in the semiconductor device of the CSP form, when the semiconductor package is miniaturized, the distance between the end portion of the semiconductor wafer and the wiring substrate electrode becomes close. When the semiconductor wafer is fixed on the wiring substrate by using the bonding material, if the bonding material flows out onto the electrode of the wiring substrate, the bonding wire is likely to be generated.

對電極之連接不良，由此可能出現佈線基板之電極與接合 線間之電性連接之可靠性下降。 可以如下技術，即可以藉由於絕緣膜深度全部區域中除 去佈線基板之主面上所形成之絕緣膜，而於半導體晶片與 電極間形成槽之技術，使接著材（絕緣性樹脂）之流出部分 滯留於槽内而不會溢出肖’故可使其不致到達電極中。藉 此，可控制因接著材之流出而產生不良之情形。 曰 然而，以經由接著材將半導體晶片固定於佈線基板主面The connection of the electrodes is poor, and thus the reliability of the electrical connection between the electrodes of the wiring substrate and the bonding wires may be degraded. The technique of forming a groove between the semiconductor wafer and the electrode by removing the insulating film formed on the main surface of the wiring substrate in the entire region of the depth of the insulating film, and allowing the outflow portion of the adhesive material (insulating resin) It stays in the tank without overflowing, so it can not reach the electrode. By this, it is possible to control a situation in which a defect occurs due to the outflow of the material.曰 However, fixing the semiconductor wafer to the main surface of the wiring substrate via the bonding material

上之絕緣膜上之技術，將使半導體晶片之整個背面經由接 著材而接合於佈線基板主面上之絕緣膜上。接著材與密封 樹脂之密著性，低於半導體晶片與密封樹脂之密著性。由 此，若經過塗布之接著材自半導體晶片之外周部溢出，或 使晶片側面濕潤，則將由於接著材與密封樹脂之接合 增大，而料低㈣樹脂之㈣性。若㈣情脂之密著性 較低，則半導體裝置（半導體封裝）之可靠性或製造良率有 可能下降》 另 又 用於固定半導體晶片 之接著材若達到自半導體晶片 I05491-971003.doc ^74527 外周部溢出之位置為止，則將難以藉由半導體晶片外周部 而使佈線基板之電極接近配置，故而無法實現半導體裝置 之進一步小型化。 本發明《目的在於提供一種可提高半導體裝置可靠性之 技術。 本發明之其他目的在於提供—種可實現半導體封裝小型 化之技術。The technique on the insulating film is such that the entire back surface of the semiconductor wafer is bonded to the insulating film on the main surface of the wiring substrate via the bonding material. The adhesion between the material and the sealing resin is lower than that of the semiconductor wafer and the sealing resin. Therefore, if the coated adhesive material overflows from the outer periphery of the semiconductor wafer or wets the side surface of the wafer, the bonding between the adhesive material and the sealing resin is increased, and the (four) resin is low. If (4) the adhesion of the grease is low, the reliability or manufacturing yield of the semiconductor device (semiconductor package) may decrease. The other material for fixing the semiconductor wafer is obtained from the semiconductor wafer I05491-971003.doc ^ When the outer peripheral portion overflows from the position where the outer peripheral portion overflows, it is difficult to arrange the electrodes of the wiring substrate close to each other by the outer peripheral portion of the semiconductor wafer, and thus it is impossible to further reduce the size of the semiconductor device. SUMMARY OF THE INVENTION The object of the present invention is to provide a technique for improving the reliability of a semiconductor device. Another object of the present invention is to provide a technique for miniaturizing a semiconductor package.

本發明上述及其他目的與新賴特徵自本說明書之記述以 及附圖當可瞭解。 【發明内容】 兹簡單說明本中請案中所揭示之發明中具有代表性者之 概要如下。 本發明係於佈線基板p主面形成有第i絕緣膜^外 周之第2絕緣膜部，並於第旧緣膜部上接合有半導體曰片 之背面，而於佈線基板第1主面上，以覆蓋半導體晶片以The above and other objects and novel features of the present invention are apparent from the description of the specification and the drawings. SUMMARY OF THE INVENTION A brief summary of the invention disclosed in the present application is as follows. In the present invention, the second insulating film portion on the outer surface of the i-th insulating film is formed on the main surface of the wiring board p, and the back surface of the semiconductor chip is bonded to the first edge film portion, and on the first main surface of the wiring board. To cover the semiconductor wafer

及接合線之方式形成有密封樹脂’並於半導體晶片背面外 周部之下方亦填充有密封樹脂》 又，本發明係於引線接合半導體晶片之電 時’將接合線之-端連接於佈線基板之電極: 將接口線之他端連接於半導體晶片之電極。 [發明之效果] 兹簡單㈣藉由本申請案中所揭^ 者而獲得之效果如下。 有代表性 由於於半導體晶片背面之外周 下方亦冑充有密封樹 105491-971003.doc 1374527 脂’故而可提高半導體裝置之可靠性。 又，由於半導體晶片與密封樹脂之接合面積増加，故而 密封樹脂之密著性提高’因此可提高半導體裝置之製造良 率 〇 【實施方式】 以下實施形態中於方便性方面當其需要時，分割為複數 個部分加以說明，但除去特別明示之情形其等並非相互 毫無關係者，—方在於他方之-部分或全部之變形例、詳 細'補充說明等關係。又，於以下實施形態中，除去提及 要素之數量等（包含個數、數值、量、範圍等）之情形，特 別明不之情形以及於原理上明確㈣為敎數之情形等， 八並非限&於該特定數者，故既可為特定數以上亦 定數以下。爯去Λ & ”、二 八 々者於以下實施形態中，其構成要素（亦包 ,、驟等除去特別明示之情形以及於原理上明確 認為為需要之情形等’毋庸置言該等未必為需要者。同 樣’於以下實施形態中於提及構成要素等之形狀、位置 時’除去特別明示之情形以及於原理上明確可認為 非如此之情料，可設為實質上含有與該形狀等近似或 類U者等H述數值以及範圍内該情形亦為同樣。 以下，基於圖式詳細說明本發明之實施形態。再者，於 付鱼Γ月實靶形態之所有圖式中，對具有相同功能之構件 付與相同符號，且省略其 共®複說明。又’於以下貫施形態 γ 兀其於必要時 八 町外，原則上應該重複相同或同樣之部 分之說明。 105491-971003.doc 1374527 又，於實施形態中所使用 易於觀察圖式而將影線省略 觀察圖式而付與影線。 (實施形態1) 之圖式巾，即使剖面圖有時為 又，即使平面圖有時為便於 以及之製造步 參照圖式說明本實施形態之半導體裝置 驟。 、And the bonding wire is formed with a sealing resin 'and is filled with a sealing resin under the outer peripheral portion of the back surface of the semiconductor wafer.>> The present invention is for connecting the end of the bonding wire to the wiring substrate when the wire is bonded to the semiconductor wafer. Electrode: Connect the other end of the interface wire to the electrode of the semiconductor wafer. [Effect of the Invention] The effect obtained by the above (4) as disclosed in the present application is as follows. Typically, the reliability of the semiconductor device can be improved by sealing the lower side of the back surface of the semiconductor wafer with a sealing tree 105491-971003.doc 1374527. In addition, since the bonding area of the semiconductor wafer and the sealing resin is increased, the adhesion of the sealing resin is improved. Therefore, the manufacturing yield of the semiconductor device can be improved. [Embodiment] In the following embodiments, when it is necessary for convenience, the division is performed. For a number of parts, except for the case where it is specifically stated, the items are not related to each other, and the other side is a part or all of the variants and detailed 'supplementary explanations'. In addition, in the following embodiments, the number of the referenced elements (including the number, the numerical value, the quantity, the range, and the like) is excluded, and the case is particularly clear, and the principle is clear (4) is the case of the number of turns, etc. The limit & is limited to a specific number, and may be a specific number or more. In the following embodiments, the following elements are included in the following embodiments (including the case where the package is omitted, and the case where it is explicitly stated as necessary, etc.), which is not necessarily required. In the following embodiments, when a shape or a position of a component or the like is mentioned, the case where it is specifically described is removed, and it is clearly understood that it is not the case in principle, and the shape may be substantially included. The same applies to the numerical values and ranges in the range of the approximation or the class U. Hereinafter, the embodiments of the present invention will be described in detail based on the drawings. Further, in all the patterns of the target form of the fish, the target is Components having the same function are given the same reference numerals, and the description thereof is omitted, and the following descriptions of the same or the same parts should be repeated in principle except for the following forms: γ 兀 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 Doc 1374527 In addition, in the embodiment, it is easy to observe the drawing, and the hatching is omitted from the viewing pattern and is given a hatching. (In the first embodiment), even if the cross-sectional view is Even if the plan view is convenient and the manufacturing steps, the semiconductor device of the present embodiment will be described with reference to the drawings.

糸作為本發明一實施形態之半導體裝置！之上面圖， 圖2係其下面圖，圖3係其剖面圖（整體剖面圖），圖4係其主 要部分之剖面圓（部分放大剖面圖），圖5係其側視圖。圖^ 中A-A線之剖面大致對應於圖3，❸之端部附近區域之放 大圖大致對應於圖4。又’圖6係透視密封樹脂5時之半導 體裝置1之平面透視圖(上面圖)’圖7係透視密封樹脂5，半 導體晶片2以及接合線4時之半導體裝置丨之平面透視圖（上 面圖），即用於半導體裝置丄之佈線基板3之上面圖。再 者，於圖7中，用虛線表示半導體晶片2之外形。又圖7 為平面圖，但為易於理解，對第丨阻焊劑部丨4a，第2阻焊 劑部14b以及自第2阻焊劑部14b之開口部19露出之連接端 子15付與有影線。 _ 圖1至圖7所示之本實施形態之半導體裝置1係於佈線基 板3上搭載（接合、連接、安裝）有半導體晶片2之半導體裝 置（半導體封裝）’且其係例如作為略微大於晶片尺寸或半 導體晶片2之小型半導體封裝之csP(Chip Size Package)形 態的半導體裝置》 本實施形態之半導體裝置1具備有：半導體晶片2;佈線 105491.97I003.doc 1374527 基板3’其支持或搭載半導體晶片2;複數個接合線4,其 電性連接半導體晶片2表面之複數個電極（第2電極，焊 墊’墊電極）2a及對應於電極2a之佈線基板3之複數個連接 端子⑷電極，料，墊電極）15;密封樹脂（密封樹脂 部，密封部，密封體）5,其覆蓋含有半導體晶片2及接合 線4之佈線基板3之上面3a;以及複數個錫球（球電極突 起電極，電極，外部端子）6,其作為外部端子以區域陣列 配置而設置於佈線基板3之下面％中。 ，半導體晶片2中’與其厚度相交差之平面形狀為正方 形，且例如於含有單晶矽等之半導體基板（半導體晶圓）之 主面中形成各種半導體元件或半導體積體電路後，根據需 要進行半導體基板之背面外削，再藉由切割等將半導體基 板分離為各個半導體晶片2。半導體晶片2含有相互對向之 表面（半導體元件形成側之主面、上面）21?以及背面（與半導 體元件形成側之主面相反側之主面、下面）2c，並以該表 面2b朝向上方之方式而配置於佈線基板3上面（晶片支持 面）3a上，且半導體晶片2之背面2c經由接著材（晶粒接合 材，接合材，接著劑）8而接著並固定於佈線基板3之上面 3 a上。接著材8可使用例如絕緣性或導電性之膏材等。接 著材8之厚度，可設為例如2〇至3〇 左右。於半導體晶片 2之表面2b中，形成有複數個電極2a，而電極2a，電性連 接於形成於半導體晶片2内部或表層部分之半導體元件或 半導體積體電路。 佈線基板3含有絕緣性基材層（絕緣基板、芯材）丨i ;導體 105491-971003.doc 1374527 層（導體圖案，導體膜圖案，佈線層）12，其形成於基材層 U之上面lla以及下面lib ;阻焊劑層（絕緣膜，焊錫阻止 層）14,其係作為以覆蓋導體層12之方式而形成於基材層 U之上面11a以及下面11b上之絕緣層（絕緣體層，絕緣膜） 者。至於其他形態，亦可藉由積層有複數個絕緣層與複數 個佈線層之多層佈線基板而形成佈線基板3。 導體層12係經過圖案化處理而成為佈線基板3之佈線或 佈線層之導體圖案。導體層12含有導電性材料，且例如可 藉由使用電鍍法而形成之銅薄膜等而形成。形成有多數個 用以藉由基材層11上面11 a之導體層12而連接接合線4之連 接端子（電極，焊墊，墊電極）15，且形成有多數個用以藉 由基材層11下面lib之導體層12而連接錫球6之導電性焊盤 (電極，焊墊，端子）16〇又，於基材層形成有複數個 開口部（通孔，通道，貫通孔）17，而於各開口部17之側壁 上亦形成有導體層12。基材層u上面Ua之連接端子15經 由基材層11上面11a之導體層12(包含導體層12之抽引佈 線）’開口部17側壁上之導體層12及基材層u下面Ub之導 體層12’而電性連接於基材層u下面nb之焊盤16。由 此’半導體晶片2之複數個電極2 a經由複數個接合線4而電 性連接於佈線基板3之複數個連接端子15，進而經由佈線 基板3之導體層丨2而電性連接於佈線基板3之複數個焊盤 1 6。接合線4含有例如金絲等金屬細線。 阻焊劑層14具有作為保護導體層12之絕緣層（絕緣膜）之 功能’且例如含有有機系樹脂材料等絕緣體材料。又，阻 105491-971003.doc 12 Ϊ374527 焊劑層14’以覆蓋導體層12之方式形狀基材層u之上面 1 la以及下面llb上，且阻焊劑層14填充基材層u開口部η 之内部。由於阻焊劑層14填充基材層u之開口部17，故而 可防止用以將半導體晶片2接合於佈線基板3之接著材8自 開°卩1 7 Λ漏至佈線基板3之下面3 b側，又，可防止半導 體晶片2之背面2c自開口部17露出。又佈線基板3之導體 層12中，連接端子15與焊盤16自阻焊劑層14(之開口部）露 出。又，基材層11上面113以及下面Ub上之阻焊劑層14之 厚度’可設為例如20至30 μπι左右。 複數個焊盤16於佈線基板3之下面3b配置為陣列狀。於 各焊盤16附近形成有開口部17。又，於各焊盤16中連接有 錫球6。因此，於佈線基板3下面讣中複數個錫球6配置為 陣列狀。錫球6可作為半導體裝置丨之外部端子而起作用。 因此’半導體晶片2之複數個電極2a經由複數個接合線4而 電性連接於佈線基板3之複數個連接端子15，進而經由佈 線基板3之導體層12而電性連接於與佈線基板3之複數個焊 盤1 6以及複數個焊盤丨6相連接之複數個錫球6 ^再者，圖2 之錫球6數量與圖6、圖7之連接端子15數量並不一致，但 圖1至圖7係模式化表示半導體裝置}構造者，故半導體裝 置1中之錫球6數量或連接端子15數量可根據需要進行各種 變更，因此既可將半導體裝置1中之錫球6數量與連接端子 15數量設為相同，又亦可設為不同。又，並不與半導體晶 片2之電極2a電性連接之錫球6可用於散熱。 於本實施形態中’於佈線基板3上面3a形成有阻焊劑層 105491-971003.doc 13 1374527 4,而佈線基板3上面3a之阻谭劑層M含有·第”且谭劑部 (第！絕緣膜部）14a ’其位於半導體晶片2之了方（即佈線基 板3上面3a之中央部）；以及第2阻焊劑部(第2絕緣： 部_，其位於第】阻輝劑部…之外周（周圍）(即位於料 基板3上面33之外周部)。於第”且焊劑部w與第2阻谭劑 部14b之間’並未形成有阻焊劑層14而存在有露出基材層 U之區域(障壁區域)18,，第1阻焊劑部Ma與第2阻禪 劑部14b夾持區域18之方式而隔開。於區域以中亦露出 有用以連接連接端子15與開口部17側壁上之導體層12間之 抽引佈線（該抽引佈線亦含有導體層12，但於圖6、圖7之 平面圖中省略圖示）。 半導體晶片2經由接著材8而接合（搭載、連接、固定、 配置）於第1阻焊劑部14a上。第2阻焊劑部14b含有用以露 出連接端子15之開口部19<(如圖6所示，連接端子15具有 大致長方形圖案（導體圖案），而第2阻焊劑部14b之開口部 19形成為重疊於連接端子15用之導體圖案。因此，於連接 端子15之一部分（兩端部）上重合有第2阻焊劑部丨々^^。藉 由"T進步確實防止連接端子15剝離，‘故而可提高半導 體裝置之可靠性。 於自第2阻焊劑部1仆之開口部19所露出之連接端子15中 連接有接合線4。為易於或者穩固使接合線4連接至連接端 子15 ’而於自第2阻焊劑部14b至開口部19所露出之連接端 子15上面（接合線4之連接面）形成有鍍金層（或鍍鎳層（下層 側）與鑛金層（上層側）之積層膜）等。又，於第2阻焊劑部 105491-971003.doc -14· 14b，亦形成有作為 封裝札數之開口部20a。於第2阻焊劑 #14b中所形成之作 裝置^之製造㈣中之 數之開卩部池可用於半導體 之疋位或方向識別等。 半導體晶片2經由技笼以。Λ 由接者材8接合（搭載 '連接、固定、配 置）於佈線基板3上而1 ^ & Λ a之第1阻焊劑部14a上，該第！阻焊 劑部14a之平面尺寸[ 了（面積）’小於半導體晶片2之平面尺寸 積）因此’S搭載半導體晶片2時，於半導體晶片2背 面2<；之外周部(周邊部，端部附近區域)2d下方，並未延伸 (二在)有第1阻焊劑部l4a。因此，半導體晶片2之背面2c外 周。P 2d及背面2e之端部2f可位於未形成有阻焊劑層14之區 域1日8上。又’由於當將半導體晶片2於佈線基板3上進行晶 θ接（接δ )時’將接著材8配置於尺寸小於半導體晶片2 之第丨阻焊劑部l4a上，並接合有半導體晶片2,故而接著 材不a L伸（存在）於半導體晶片2之背面2c外周部2d上， 因此當將半導體晶片2晶片焊接於佈線基板3上時則不會 於半導體晶片2之背面2c外周部2d之下方存在有接著材8以 及阻焊劑層14。即，由於接著材8以及阻焊劑層14(第1阻 焊劑部14a)存在於較之半導體晶片2之側面2e(端部2f)之更 内側，故而半導體晶片2之背面2c外周部2d將會處於露出 狀態。因此，將會於半導體晶片2之背面2c外周部2d與佈 線基板3上面3a之間形成有空間（間隙）21。空間21於高度方 向上之尺寸（半導體晶片2之背面2c外周部2d與佈線基板3 上面3 a間之距離），大致相當於第1阻焊劑部14a之厚度 T!與接著材8之厚度I的總和（Hl=Tl + T2)。於形成密封樹 105491-971003.doc -15· 1374527 脂5時（脫模步驟），用以形成密封樹脂5之材料亦將填充於 半導體晶片2之背面2c外周部2d之下方空間21，故經過硬 化（固化）之密封樹脂5亦將填充於半導體晶片2之背面。外 周部2d之下方’經過硬化之密封樹脂5將覆蓋半導體晶片2 之表面2b ’半導體晶片2之側面2e及半導體晶片2之背面2c 外周部2d ’故而可提高半導體晶片2與密封樹脂5之密著性 (接著強度）’由此可提高半導體裝置1之可靠性。 密封樹脂5含有例如熱硬化性樹脂材料等樹脂材料等， 亦可包含填充料等。例如，亦可使用含有填充料之環氧樹 脂等形成密封樹脂5。密封樹脂5以覆蓋半導體晶片2以及 接合線4之方式而形成於佈線基板3上面3&上，且藉由密封 樹脂5而密封並保護半導體晶片2以及接合線4。 圖8係第Ub較例之半導體裝置1 〇 1之主要部分剖面圖（部 分放大剖面圖）’圖9係第2比較例之半導體裝置2〇 1之主要 部分剖面圖（部分放大剖面圖），圖1〇係第3比較例之半導體 裝置301之主要部分剖面圖（部分放大剖面圖），且分別表示 與本實施形態之圖4相對應之區域。 於圖8所示之第1比較例之半導體裝置丨〇1不同於本實施 形態’於去除連接端子15上之佈線基板1〇3上面1〇3&之整 個面上形成有阻焊劑層丨14 ’而於半導體晶片2之背面。外 周部2d之下方亦延伸有阻焊劑層丨14。因此，於第i比較例 之半導體裝置101中，當將半導體晶片2晶片焊接於佈線基 板103上時，含有膏材等之接著材8可能會漫過半導體晶片 2之背面2c端部而擴散，進而接著材8會流經阻焊劑層ιι4 105491-971003.doc -16· 1374527 之上面上而導致其擴散至連接端子15上為止。若接著材8 擴散（流出）至連接端子15上為止，則會易於產生接合線4對 連接端子15之連接不良，由此可能降低接合線4與連接端 子15間電性連接之可靠性。又，亦考慮如下，為防止接著 材8流出至連接端子15而將半導體晶片2端部與佈線基板^ 至連接端子15之距離加長，然而其將會導致半導體裝置大 型化（大面積化）。 於圖9所示之第2比較例之半導體裝置2〇1中，於佈線基 板203之上面203a中形成有含有第”且焊劑部214&與第2阻 焊劑部214b之阻焊劑層214，而於第j阻焊劑部21牦與第2 阻焊劑部214b之間，存在並未形成阻焊劑層214而露出有 佈線基板2〇3之4材層U之區域（障璧區域口丨8 ,而與本實 施形態不同，第1阻焊劑部214a之平面尺寸（面積），大於半 導體晶片2之平面尺寸（面積），且於半導體晶片2背面以全 部表面之下方延伸（存在）有第！阻焊劑部21牦。於第2比較 例之半導體裝置2G1中，當將半導體晶^ 2晶w接於佈線 基板203上後，可藉由設置第！阻焊劑部以乜與第2阻焊劑 邛214b之間露出有基材層u而無阻焊劑層214之區域（障壁 區域）218而防止含有膏材等之接著材8越過區域218擴散 至第2阻焊劑部214b上為止。藉此，可防止接著材8擴散至 連接编子15上為止，故而可提高接合線4連接端子Η間之 電性連接之可靠性。 然而，於圖9所示之第2比較例之半導體裝置2〇1中，第1 阻焊劑部2i4a之平面尺寸（面積）大於半導體晶片2之平面尺 105491-971003.doc 17 1374527 寸（面積）’故半導體晶片2之背面整個面經由接著材8而 接著於第1阻焊劑部214a。密封樹脂5與接著材8之密著性 (接著強度），低於半導體晶片2與密封樹脂5之密著性（接著 強度），因此，於第2比較例之半導體裝置2〇1中，密封樹 月曰5覆蓋半導體晶片2之表面2b以及側面2e，但密封樹脂5 並不覆蓋半導體晶片2之背面2c，半導體晶片2與密封樹脂 5之接合面積小於本實施形態1(之半導體裝置丨），因此半導 體晶片2與密封樹脂5之密著性（接著強度）可能低於本實施 形態1(之半導體裝置1)。進而，若用於固定半導體晶片2之 接著材8到達溢出於半導體晶片2外周部之位置，則難以藉 由半導體晶片2之外周部而接近配置佈線基板2〇3上之連接 端子15，因此與本實施形態1(之半導體裝置丨）相比半導 體裝置201之小型化將無法實現。 圖10所示之第3比較例之半導體裝置3〇1中，使接著材8 之塗布區域或塗布量小於第2比較例之半導體裝置2〇1。藉 此，當經由接著材8而將半導體晶片2接合於佈線基板2〇3 之上面203a之第1阻焊劑部14a上時，接著材8不會延伸（存 在）於半導體晶片2之背面2c外周部2d之下方，因而於半導 體晶片2之背面2c外周部2d與佈線基板2〇3之上面2〇3a間可 形成空間（間隙）22 1。藉此，當形成密封樹脂5時，亦可將 用以形成密封樹脂5之材料填充於空間221中，故而經過硬 化之密封樹脂5將會覆蓋半導體晶片2之表面2b、半導體晶 片2之側面2e及半導體晶片2之背面2C外周部2d，因此可提 高半導體晶片2與密封樹脂5之密著性（接著強度）。 105491-971003.doc 1374527 …、、而’於圖10所示之第3比較例之半導體裝置3〇1中，藉 由調節接著材8之塗布區域或塗布量而於半導體晶片2之背 面2C外周部2d與佈線基板203之上面203a間形成空間221， 因而存在有如下可能性：接著材8之塗布量過少而導致半 導體晶片2與佈線基板2〇3之接合強度下降，或接著材8之 塗布量過多而導致半導體晶片2之背面2c外周部2d與佈線 基板203之上面2〇3a間無法形成空間221。因此，將難以對 晶片焊接步驟進行管理，導致每個製品之不均一將變大。 又，亦考慮到藉由將平面尺寸（面積）小於半導體晶片2之晶 粒接合膜用作接著材8，而於半導體晶片2之背面2c外周部 2d與佈線基板2〇3之上面2〇3a間形成空間221，然而晶粒接 合膜價格高於膏型接著材，故而可能導致半導體裝置製造 成本增加。 又’圖10所示之第3比較例之半導體裝置3〇1不同於本實 施形態，由於第”且焊劑部214a延伸於半導體晶片2之背面 2c外周部2d之下方，故而當將半導體晶片2晶片焊接於佈 線基板203上時，於半導體晶片2之背面2c外周部2d與佈線 基板203之上面2〇3a之間所形成之空間221於高度方向上之 尺寸H2將會變低（變小）。空間221於高度方向上之尺寸％ 大致相當於接著材8之厚度ΚΗΠ)。若接著材8之厚度為 例如20至30 μπι左右，則空間221於高度方向上之尺寸^亦 將成為20至3〇 μιη左右。由於半導體晶片2之背面2c外周部 2d之下方空間221於高度方向上之尺寸H2較小，故而當形 成密封樹脂5時，可能出現如下情形，於用以形成密封樹 105491-971003.doc •19- 1374527 脂5之材料^所含有之填充料等將難以浸入到半導體晶月2 之背面2e外周部2d之下方空間221中，導致填充空間川之 密封樹月日5之成分比與其他區域之密封樹脂5之成分比出現 :均一化等，故經過硬化之密封樹脂5與半導體晶片2之密 著性（接著強度）將會下降。 對此，於本實施形態中，於佈線基板3之上面&形成 有：經由接著材8而將半導體晶片2接合於其上方之第！阻 焊劑部（第1絕緣膜部）14a，以及設置於第丨阻焊劑部i4a之 _ 周圍（外周）’且自開口部19露出有連接端子15之第2阻焊劑 部（第2絕緣膜部）〗4b。於第”且焊劑部與第2阻焊劑部 14b之間，存在有並未形成阻焊劑層“但露出有基材層u • 之區域（障壁區域）18。因此，當將半導體晶片2晶片焊接於 佈線基板3上時，可藉由設置第！阻焊劑部Ma與第2阻焊劑 部14b之間露出有基材層n而並無阻焊劑層14之區域（障壁 區域）18,而防止接著材8越過區域18擴散至第2阻焊劑部 14b上。藉此，可防止接著材8擴散至連接端子〗5上由此 可提高接合線4與連接端子15間之電性連接之可靠性。 又，即使將流動性相對較高之膏型接著材（接合材）用作接 著材8，亦可藉由設置第！阻焊劑部14a與第2阻焊劑部i4b 間並無阻焊劑層14區域（障壁區域）18，而防止含有膏材之 接著材8擴散至連接端子15上為止，因而可將較之晶粒接 合膜相對低價之膏型接著材用作接著材8，故而有利於降 低半導體裝置之製造成本。又，由於可藉由半導體晶片2 之外周部而接近配置佈線基板3之連接端子15，故而可使 105491-971003.doc •20· 1374527 半導體裝置進一步小型化。 進而’於本實施形態中，經由接著材8而將半導體晶片2 搭載並固定於第m焊劑部14a上，然而該第m焊劑部… 之平面尺寸（面積）小於半導體晶片2之平面尺寸（面積）。為 此，當經由接著材8而將半導體晶片2接合於佈線基板3上 面3a之第1阻焊劑部14a上時，於半導體晶片2之背面“外 周部2d之下方並未延伸有（存在）第1阻焊劑部以及接著 材8，而於半導體晶片2之背面2c外周部2d與佈線基板3上 面3 a之間形成有空間21。為此，當形成密封樹脂$時，由 於亦將用以形成密封樹脂5之材料填充於該空間2〗中，而 經過硬化之密封樹脂5將會覆蓋半導體晶片2之表面孔 '半 導體晶片2之側面2e及半導體晶片2之背面2C之外周部2d ’ 故而半導體晶片2與密封樹脂5之接合面積將會增大，因而 可提高半導體晶片2與密封樹脂5之密著性（接著強度），所 以可提高半導體裝置1之可靠性。如本實施形態所示，亦 使密封樹脂5旋轉進入至半導體晶片2之背面2(：側，並使密 封樹脂5充滿（填充）半導體晶片2之背面2c外周部2d與佈線 基板3之上面3 a之間’藉此可藉由密封樹脂5而將半導體晶 片2穩固密封於半導體晶片2之表面2b以及背面2c之兩面 (側面2e)中’因此可提高半導體晶片2與密封樹脂5之密著 性，故而可確實防止於半導體晶片2與密封樹脂5間產生剝 離等。 進而，於本實施形態中，可使於半導體晶片2之背面2c 外周部2d與佈線基板3上面3a之間所形成之空間21於高度 I0549l-971003.doc -21- 1374527 方向上之尺寸Hi較之第3比較例之半導體裝置3〇1之空間 221於向度方向上之尺寸Η:，僅大第}阻焊劑部14a之厚度 T^H^H2)。例如，若接著材8之厚度^為汕至儿叫^左 右’且第1阻焊劑部14a之厚度丁1為20至30 μηι左右，則可 使空間21於高度方向上之尺寸仏為利至⑼μιη左右。如此 般於本實施形態中，由於可使半導體晶片2之背面以外周 部2d之下方空間21於高度方向上之尺寸&相對較大故而 於形成密封樹脂5時（脫模步驟），用以形成密封樹脂5之材 料中所含有之填充料等，將易於浸入至半導體晶片2之背 面2c外周部2d之下方空間21中，故而可使填充空間21之密 封樹脂5之成分比與其他區域之密封樹脂5之成分比得到均 一化。藉此，可進一步提高經過硬化之密封樹脂5與半導 體晶片2之密著性（接著強度），因而可進一步提高半導體裝 置1之可靠性。 、 又，於本實施形態中，於第2阻焊劑部14b之内周部（與 第1阻焊劑部14a相對向之第2阻焊劑部I4b之内周部，與半 導體B曰片2之四邊相對向之第2阻焊劑部丨之内周部）之角 部（四角，轉角部）中，可使第2阻焊劑部14b之圖案退後至 半導體裝置】之外周方向（即冑離半導體晶片2之方向）， 即，於第2阻焊劑部14b内周部之角部（四角）中，設置有露 出有基材層11但並未形成有阻焊劑之阻焊劑後退部鳥。 藉由於第2阻焊劑部14b之内周部之角部（四角）使第· 焊劑部14b之圖案後退(即設置阻焊劑後退部)，而以傳 送脱模步驟㈣成密封樹脂5時，空氣將變得易於自半導 l〇549l-97i〇〇3.doc -22· 1374527 體晶片2之背面2c外周部2d與佈線基板3上面3a之間之空間 21中去除，因而可提高用以形成密封樹脂5之材料流動 性，故而可進一步提高密封樹脂對上述空間2 1之填充性。 為此，可進一步提高半導體晶片2與密封樹脂5之密著性 (接著強度），故而可進一步提高半導體裝置1之可靠性。 圖11係其他形態半導體裝置la之主要部分剖面圖，圖12 係其之平面透視圖（上面圖）。圖11與上述圖4相對應。又， 圖12與上述圖7相對應，且表示透視密封樹脂5、半導體晶 片2以及接合線4時之半導體裝置ia之平面透視圖（上面 圖）’即表示於半導體裝置la中所使用之佈線基板3之上面 圖。再者’於圖12中’用虛線表示半導體晶片2之外形。 又，圖12係平面圖，但為便於理解，將自第丨阻焊劑部 1 4 a ’第2阻焊劑部14 b以及第2阻焊劑部14 b之開口部19所 露出之連接端子15付與影線。 於上述半導體裝置1中，半導體晶片2之背面2c端部2f(半 導體晶片2之側面2e)位於並未形成有阻焊劑層丨4但露出有 基材層11之區域（障壁區域）18中，於圖11以及圖12所示之 半導體裝置U中，半導體晶片2之背面2c端部2f(半導體晶 片2之側面2e)位於第2阻焊劑部14b上。半導體裝置la之其 他構成大致與上述半導體裝置1相同。 半導體裝置la亦可獲得大致與半導體裝置1同樣之效 果，故包含於本發明之半導體裝置中。其中，如半導體裝 置1般半導體晶片2之背面2c端部2f(半導體晶片2之側面2e) 位於區域（障壁區域）18上者，較之如半導體裝置般半導 105491-971003.doc -23- 1374527 體晶片2之背面2c端部2f(半導體晶片2之側面㈣位於第2阻 焊劑部14b上者’可更加使半導體晶片2晶片焊接於佈線基 板3之上面3a時形成於半導體晶片2之背面2c外周部與佈 線基板3之上面3a間之空間21擴大，故於形成密封樹脂5時 填充料等將會易於浸入至半導體晶片2之背面2c外周部Μ 之下方空間21中’因此可使充滿空間21之密封樹脂5之成 分比與其他區域之密封樹脂5之成分比進一步均一。由 此，半導體裝置1更加有利於提高密封樹脂5與半導體晶片 2之密著性（接著強度）或可靠性。而另一方面，如半導體裝 置la般，可藉由使第2阻焊劑部14b延伸於半導體晶片2之 背面2c端部2f(半導體晶片2之側面2e)之下方’而使連接端 子15更加接近於半導體晶片2側，因而，半導體裝置〖a更 加有利於進行小型化（小面積化）。 其次，參照圖式說明本實施形態之半導體裝置之製造方 法。圖13至圖20係本實施形態之半導體裝置之製造步驟中 之剖面圖。圖21至圖23係模式性表示用於本實施形態半導 體裝置1之製造中的佈線基板31之製造步驟之一例示的平 面圖（上面圖）。圖24係本實施形態之半導體裝置製造步驟 中之主要部分剖面圖’其對應於與圖14相同之步驟階段 (晶片焊接步驟）。圖25係本實施形態之半導體裝置之製造 步驟中之平面圖（上面圖）’其對應於與圖15相同之步驟階 段。圖26、圖27係打線接合步驟之說明圖（主要部分剖面 圖）。圖28係本實施形態之半導體裝置之製造步驟中之主 要部分剖面圖，其對應於與圖16相同之步驟階段（脫模步 105491-971003.doc -24· 1374527 驟）。又，於圖21至圖28中亦表示有於下述切斷步驟中切 斷佈線基板3 1之切割區域（切割線）39。糸 As a semiconductor device according to an embodiment of the present invention! 2 is a cross-sectional view (overall cross-sectional view), FIG. 4 is a cross-sectional circle (partially enlarged cross-sectional view) of a main portion thereof, and FIG. 5 is a side view thereof. The cross section of the line A-A in Fig. 2 substantially corresponds to Fig. 3, and the enlarged view of the area near the end of the 大致 corresponds roughly to Fig. 4. 6 is a plan perspective view of the semiconductor device 1 when the sealing resin 5 is seen through (the above figure). FIG. 7 is a plan perspective view of the semiconductor device 2 when the semiconductor wafer 2 and the bonding wire 4 are laminated (top view) The upper surface of the wiring substrate 3 used for the semiconductor device. Further, in Fig. 7, the outer shape of the semiconductor wafer 2 is indicated by a broken line. Further, Fig. 7 is a plan view. However, for the sake of easy understanding, the second solder resist portion 4a, the second solder resist portion 14b, and the connection terminal 15 exposed from the opening portion 19 of the second solder resist portion 14b are hatched. The semiconductor device 1 of the present embodiment shown in FIGS. 1 to 7 is a semiconductor device (semiconductor package) on which a semiconductor wafer 2 is mounted (joined, connected, and mounted) on a wiring board 3, and is, for example, slightly larger than a wafer. Semiconductor device of the csP (Chip Size Package) type of the semiconductor package of the size or the semiconductor wafer 2 The semiconductor device 1 of the present embodiment includes: a semiconductor wafer 2; a wiring 105491.97I003.doc 1374527 A substrate 3' supporting or mounting a semiconductor wafer 2; a plurality of bonding wires 4 electrically connected to a plurality of electrodes (second electrode, pad 'pad electrode) 2a on the surface of the semiconductor wafer 2 and a plurality of connection terminals (4) electrodes corresponding to the wiring substrate 3 of the electrode 2a, a pad electrode 15; a sealing resin (sealing resin portion, sealing portion, sealing body) 5 covering the upper surface 3a of the wiring substrate 3 including the semiconductor wafer 2 and the bonding wires 4; and a plurality of solder balls (ball electrode protruding electrodes, The electrode (external terminal) 6 is provided as an external terminal in an area array arrangement and provided in the lower portion % of the wiring board 3. In the semiconductor wafer 2, a planar shape having a difference in thickness is square, and after forming various semiconductor elements or semiconductor integrated circuits in a main surface of a semiconductor substrate (semiconductor wafer) containing a single crystal germanium or the like, for example, The back surface of the semiconductor substrate is externally cut, and the semiconductor substrate is separated into individual semiconductor wafers 2 by dicing or the like. The semiconductor wafer 2 includes a surface (the main surface and the upper surface on which the semiconductor element is formed) 21 and a back surface (a main surface and a lower surface on the side opposite to the main surface on which the semiconductor element is formed) 2c, and the surface 2b faces upward. In this way, it is disposed on the upper surface (wafer support surface) 3a of the wiring board 3, and the back surface 2c of the semiconductor wafer 2 is then attached to the upper surface of the wiring substrate 3 via a bonding material (die bonding material, bonding material, adhesive) 8. 3 a. The material 8 can be, for example, an insulating or conductive paste or the like. The thickness of the material 8 can be set, for example, to about 2 〇 to 3 。. In the surface 2b of the semiconductor wafer 2, a plurality of electrodes 2a are formed, and the electrodes 2a are electrically connected to a semiconductor element or a semiconductor integrated circuit formed inside or in the surface portion of the semiconductor wafer 2. The wiring board 3 includes an insulating base material layer (insulating substrate, core material) 丨i; a conductor 105491-971003.doc 1374527 layer (conductor pattern, conductor film pattern, wiring layer) 12 formed on the upper surface of the substrate layer U11a And a solder resist layer (insulating film, solder resist layer) 14 as an insulating layer (insulator layer, insulating film) formed on the upper surface 11a and the lower surface 11b of the substrate layer U so as to cover the conductor layer 12 ) By. In other aspects, the wiring board 3 may be formed by laminating a plurality of wiring layers having a plurality of insulating layers and a plurality of wiring layers. The conductor layer 12 is patterned to form a conductor pattern of a wiring or a wiring layer of the wiring board 3. The conductor layer 12 contains a conductive material and can be formed, for example, by a copper thin film formed by an electroplating method or the like. A plurality of connection terminals (electrodes, pads, pad electrodes) 15 for connecting the bonding wires 4 by the conductor layers 12 on the upper surface 11 a of the substrate layer 11 are formed, and a plurality of layers are formed by the substrate layer. 11 below, the conductive layer (electrode, pad, terminal) of the solder ball 6 is connected to the conductor layer 12 of the lib, and a plurality of openings (through holes, vias, through holes) 17 are formed in the base layer. A conductor layer 12 is also formed on the side walls of the openings 17. The connection terminal 15 of the Ua on the substrate layer u passes through the conductor layer 12 of the upper surface 11a of the base material layer 11 (including the extraction wiring of the conductor layer 12), the conductor layer 12 on the side wall of the opening portion 17, and the conductor of the Ub under the substrate layer u. The layer 12' is electrically connected to the pad 16 of the nb under the substrate layer u. Thus, the plurality of electrodes 2 a of the semiconductor wafer 2 are electrically connected to the plurality of connection terminals 15 of the wiring substrate 3 via a plurality of bonding wires 4 , and are electrically connected to the wiring substrate via the conductor layer 丨 2 of the wiring substrate 3 . 3 of a plurality of pads 16. The bonding wire 4 contains a thin metal wire such as gold wire. The solder resist layer 14 has a function as an insulating layer (insulating film) for protecting the conductor layer 12, and includes, for example, an insulator material such as an organic resin material. Further, the resistance 105491-971003.doc 12 Ϊ 374527 the flux layer 14' is formed on the upper surface 1 la and the lower surface 11b of the substrate layer u so as to cover the conductor layer 12, and the solder resist layer 14 fills the inside of the opening portion η of the substrate layer u. . Since the solder resist layer 14 fills the opening portion 17 of the substrate layer u, the bonding material 8 for bonding the semiconductor wafer 2 to the wiring substrate 3 can be prevented from leaking from the opening 71 7 to the lower surface 3b side of the wiring substrate 3. Further, it is possible to prevent the back surface 2c of the semiconductor wafer 2 from being exposed from the opening portion 17. Further, in the conductor layer 12 of the wiring board 3, the connection terminal 15 and the pad 16 are exposed from the solder resist layer 14 (the opening portion). Further, the thickness ' of the upper surface 113 of the base material layer 11 and the solder resist layer 14 on the lower Ub may be, for example, about 20 to 30 μπι. A plurality of pads 16 are arranged in an array on the lower surface 3b of the wiring board 3. An opening 17 is formed in the vicinity of each of the pads 16. Further, a solder ball 6 is connected to each of the pads 16. Therefore, a plurality of solder balls 6 are arranged in an array in the lower surface of the wiring board 3. The solder ball 6 functions as an external terminal of the semiconductor device. Therefore, the plurality of electrodes 2a of the semiconductor wafer 2 are electrically connected to the plurality of connection terminals 15 of the wiring substrate 3 via the plurality of bonding wires 4, and are electrically connected to the wiring substrate 3 via the conductor layer 12 of the wiring substrate 3. The plurality of pads 16 and the plurality of pads 丨6 are connected to the plurality of solder balls 6 ^. Further, the number of the solder balls 6 in FIG. 2 is different from the number of the connection terminals 15 in FIGS. 6 and 7 , but FIG. 1 to 7 is a schematic representation of a semiconductor device}. Therefore, the number of solder balls 6 or the number of connection terminals 15 in the semiconductor device 1 can be variously changed as needed, so that the number of solder balls 6 in the semiconductor device 1 and the connection terminals can be made. The number of 15 is set to be the same or different. Further, the solder balls 6 which are not electrically connected to the electrodes 2a of the semiconductor wafer 2 can be used for heat dissipation. In the present embodiment, the solder resist layer 105491-971003.doc 13 1374527 4 is formed on the upper surface 3a of the wiring board 3, and the resist layer M of the upper surface 3a of the wiring board 3 contains the "the" and the tantalum portion (the! insulation). The film portion 14a' is located on the side of the semiconductor wafer 2 (that is, the central portion of the upper surface 3a of the wiring board 3); and the second solder resist portion (second insulation: portion _, which is located in the outer portion of the first retarder portion) (surrounding) (that is, on the outer peripheral portion of the upper surface 33 of the material substrate 3). The first and the solder resist portion w and the second resistive agent portion 14b are not formed with the solder resist layer 14 and the exposed substrate layer U is present. In the region (barrier region) 18, the first solder resist portion Ma and the second resist agent portion 14b are spaced apart from each other so as to sandwich the region 18. The region is also exposed to connect the connection terminal 15 and the side wall of the opening portion 17. The lead wiring between the upper conductor layers 12 (the lead wiring also includes the conductor layer 12, but is omitted in the plan views of FIGS. 6 and 7). The semiconductor wafer 2 is bonded via the bonding material 8 (mounting, connection, The second solder resist portion 14b is fixed to and disposed on the first solder resist portion 14a. The second solder resist portion 14b is included to expose the connection terminal 15 The opening 19 < (As shown in Fig. 6, the connection terminal 15 has a substantially rectangular pattern (conductor pattern), and the opening 19 of the second solder resist portion 14b is formed to overlap the conductor pattern for the connection terminal 15. Therefore, the connection is made. The second solder resist portion is overlapped on one portion (both end portions) of the terminal 15. By "T progress", the connection terminal 15 is prevented from being peeled off, so that the reliability of the semiconductor device can be improved. The bonding wire 4 is connected to the connection terminal 15 exposed by the opening portion 19 of the flux portion 1. The bonding wire 4 is connected to the connection terminal 15' in an easy or stable manner, and is exposed from the second solder resist portion 14b to the opening portion 19. The upper surface of the connection terminal 15 (the connection surface of the bonding wires 4) is formed with a gold plating layer (or a laminated film of a nickel plating layer (lower layer side) and a gold layer (upper layer side)). Further, in the second solder resist portion 105491- 971003.doc -14· 14b, the opening portion 20a is also formed as the number of packages. The opening pool of the device (4) formed in the second solder resist #14b can be used for semiconductors. Bit or direction identification, etc. In the first solder resist portion 14a of the 1 ^ & [The (area)' is smaller than the planar size of the semiconductor wafer 2) Therefore, when the semiconductor wafer 2 is mounted on the semiconductor chip 2, the outer surface (the peripheral portion, the vicinity of the end portion) 2d of the semiconductor wafer 2 is not extended ( Second, there is a first solder resist portion l4a. Therefore, the outer surface of the back surface 2c of the semiconductor wafer 2 is formed. The end portion 2f of P 2d and the back surface 2e may be located on the area 1 of 8 where the solder resist layer 14 is not formed. 'When the semiconductor wafer 2 is crystallized on the wiring substrate 3 (connected to δ), the bonding material 8 is disposed on the second solder resist portion 14a having a smaller size than the semiconductor wafer 2, and the semiconductor wafer 2 is bonded, Therefore, the bonding material is not present on the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2. Therefore, when the semiconductor wafer 2 is soldered to the wiring substrate 3, it does not exist on the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2. A backing material 8 and a solder resist layer 14 are present below. That is, since the bonding material 8 and the solder resist layer 14 (the first solder resist portion 14a) are present more inside than the side surface 2e (end portion 2f) of the semiconductor wafer 2, the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 will be In an exposed state. Therefore, a space (gap) 21 is formed between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring board 3. The dimension of the space 21 in the height direction (the distance between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3) substantially corresponds to the thickness T of the first solder resist portion 14a and the thickness I of the bonding material 8. The sum of (Hl = Tl + T2). When the sealing tree 105491-971003.doc -15·1374527 grease 5 is formed (release step), the material for forming the sealing resin 5 is also filled in the space 21 below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, so that The hardened (cured) sealing resin 5 is also filled on the back surface of the semiconductor wafer 2. Below the outer peripheral portion 2d, the hardened sealing resin 5 covers the surface 2b of the semiconductor wafer 2, the side surface 2e of the semiconductor wafer 2, and the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, so that the semiconductor wafer 2 and the sealing resin 5 can be made dense. The importance (following strength)' thus improves the reliability of the semiconductor device 1. The sealing resin 5 contains a resin material such as a thermosetting resin material, and may contain a filler or the like. For example, the sealing resin 5 may be formed using an epoxy resin or the like containing a filler. The sealing resin 5 is formed on the upper surface 3& of the wiring substrate 3 so as to cover the semiconductor wafer 2 and the bonding wires 4, and the semiconductor wafer 2 and the bonding wires 4 are sealed and protected by the sealing resin 5. FIG. 8 is a cross-sectional view (partially enlarged cross-sectional view) of a main portion of a semiconductor device 1 〇 1 of a second comparative example. FIG. 9 is a cross-sectional view (partially enlarged cross-sectional view) of a main portion of a semiconductor device 2〇1 of a second comparative example, Fig. 1 is a cross-sectional view (partially enlarged cross-sectional view) of a main portion of a semiconductor device 301 of a third comparative example, and shows a region corresponding to Fig. 4 of the present embodiment. The semiconductor device 1 of the first comparative example shown in FIG. 8 is different from the solder mask layer 14 formed on the entire surface of the wiring substrate 1〇3 on the connection terminal 15 in the present embodiment. 'On the back side of the semiconductor wafer 2. A solder resist layer 14 is also extended under the outer peripheral portion 2d. Therefore, in the semiconductor device 101 of the first comparative example, when the semiconductor wafer 2 is wafer-bonded to the wiring substrate 103, the adhesive material 8 containing the paste or the like may diffuse over the end portion 2c of the semiconductor wafer 2 to be diffused. Further, the bonding material 8 flows over the upper surface of the solder resist layer ιι 4 105491-971003.doc -16·1374527 to cause it to diffuse onto the connection terminal 15. If the material 8 is diffused (flowed) onto the connection terminal 15, the connection failure of the bonding wire 4 to the connection terminal 15 is liable to occur, whereby the reliability of the electrical connection between the bonding wire 4 and the connection terminal 15 may be lowered. Further, in order to prevent the distance between the end portion of the semiconductor wafer 2 and the wiring substrate 2 to the connection terminal 15 from being prevented from flowing out to the connection terminal 15, the semiconductor device may be made larger (larger area). In the semiconductor device 2〇1 of the second comparative example shown in FIG. 9, the solder resist layer 214 including the first and the solder portion 214 & and the second solder resist portion 214b is formed on the upper surface 203a of the wiring board 203. Between the jth solder resist portion 21A and the second solder resist portion 214b, there is a region in which the solder resist layer 214 is not formed and the wiring layer 2 of the wiring substrate 2〇3 is exposed (the barrier region port 8 is formed). Unlike the present embodiment, the first solder resist portion 214a has a larger planar size (area) than the planar size (area) of the semiconductor wafer 2, and extends (besides) the entire surface of the semiconductor wafer 2 with a solder resist. In the semiconductor device 2G1 of the second comparative example, after the semiconductor crystal wafer w is connected to the wiring substrate 203, the second solder resist portion 214b can be formed by the first solder resist portion. The base layer u is exposed without the region (barrier region) 218 of the solder resist layer 214, and the adhesive material 8 containing the paste or the like is prevented from diffusing over the region 218 to the second solder resist portion 214b. Thereby, the bonding material can be prevented. 8 spreads up to the connection of the cutter 15, so that the joint can be improved The reliability of the electrical connection between the terminals is the same. However, in the semiconductor device 2〇1 of the second comparative example shown in FIG. 9, the planar size (area) of the first solder resist portion 2i4a is larger than that of the semiconductor wafer 2. Plane ruler 105491-971003.doc 17 1374527 inch (area)', the entire surface of the back surface of the semiconductor wafer 2 is followed by the first solder resist portion 214a via the bonding material 8. The adhesion of the sealing resin 5 to the bonding material 8 (follow strength) The adhesion between the semiconductor wafer 2 and the sealing resin 5 is lower than that of the sealing resin 5, and therefore, in the semiconductor device 2〇1 of the second comparative example, the sealing tree 5 covers the surface 2b and the side surface 2e of the semiconductor wafer 2. However, the sealing resin 5 does not cover the back surface 2c of the semiconductor wafer 2, and the bonding area of the semiconductor wafer 2 and the sealing resin 5 is smaller than that of the first embodiment (the semiconductor device 丨), so the adhesion between the semiconductor wafer 2 and the sealing resin 5 ( The strength may be lower than that of the semiconductor device 1 of the first embodiment. Further, if the bonding material 8 for fixing the semiconductor wafer 2 reaches a position overflowing the outer peripheral portion of the semiconductor wafer 2, it is difficult to pass the semiconductor. Since the connection terminal 15 on the wiring board 2〇3 is disposed close to the outer peripheral portion of the sheet 2, the semiconductor device 201 can be made smaller than the semiconductor device 201 of the first embodiment (1). In the semiconductor device 3〇1 of the comparative example, the application region or the coating amount of the bonding material 8 is made smaller than that of the semiconductor device 2〇1 of the second comparative example. Thereby, the semiconductor wafer 2 is bonded to the wiring substrate 2 via the bonding material 8. When the first solder resist portion 14a of the upper surface 203a of the crucible 3 is formed, the subsequent material 8 does not extend (existing) under the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, and thus the outer peripheral portion 2d and the wiring on the back surface 2c of the semiconductor wafer 2 A space (gap) 22 1 is formed between the upper surface 2〇3a of the substrate 2〇3. Thereby, when the sealing resin 5 is formed, the material for forming the sealing resin 5 can be filled in the space 221, so that the cured sealing resin 5 covers the surface 2b of the semiconductor wafer 2 and the side 2e of the semiconductor wafer 2. Further, the outer peripheral portion 2d of the back surface 2C of the semiconductor wafer 2 can improve the adhesion (adjacent strength) between the semiconductor wafer 2 and the sealing resin 5. 105491-971003.doc 1374527, and in the semiconductor device 3〇1 of the third comparative example shown in FIG. 10, the outer periphery of the back surface 2C of the semiconductor wafer 2 is adjusted by adjusting the coating area or the coating amount of the bonding material 8. A space 221 is formed between the portion 2d and the upper surface 203a of the wiring board 203. Therefore, there is a possibility that the coating amount of the bonding material 8 is too small to cause a decrease in the bonding strength between the semiconductor wafer 2 and the wiring substrate 2?3, or coating of the bonding material 8. When the amount is too large, the space 221 cannot be formed between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 2?3a of the wiring board 203. Therefore, it will be difficult to manage the wafer soldering steps, resulting in a non-uniformity of each article. Further, it is also considered that by using the die-bonding film having a planar size (area) smaller than that of the semiconductor wafer 2 as the bonding material 8, the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface of the wiring substrate 2〇3 2〇3a The space 221 is formed, but the price of the die-bonding film is higher than that of the paste-type bonding material, which may result in an increase in manufacturing cost of the semiconductor device. Further, the semiconductor device 3〇1 of the third comparative example shown in FIG. 10 is different from the present embodiment in that the solder portion 214a extends below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, so that the semiconductor wafer 2 is used. When the wafer is soldered to the wiring board 203, the dimension H2 in the height direction of the space 221 formed between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 2〇3a of the wiring substrate 203 becomes lower (smaller). The dimension % of the space 221 in the height direction is approximately equivalent to the thickness 接着 of the backing material 8. If the thickness of the backing material 8 is, for example, about 20 to 30 μπι, the dimension of the space 221 in the height direction will also become 20 to The size H2 of the lower space 221 of the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 is smaller in the height direction. Therefore, when the sealing resin 5 is formed, the following may occur to form the sealing tree 105491- 971003.doc •19- 1374527 The material and the like contained in the material of the grease 5 are difficult to be immersed in the space 221 below the outer peripheral portion 2d of the back surface 2e of the semiconductor crystal moon 2, resulting in a filling space of the sealing tree of the moon 5 The composition ratio is different from the composition ratio of the sealing resin 5 in other regions: uniformity, etc., so that the adhesion (adhesive strength) of the cured sealing resin 5 and the semiconductor wafer 2 is lowered. In this embodiment, On the upper surface of the wiring board 3, a solder resist portion (first insulating film portion) 14a on which the semiconductor wafer 2 is bonded via the bonding material 8 and a second solder resist portion i4a are formed. The second solder resist portion (second insulating film portion) 4b of the connection terminal 15 is exposed from the opening portion 19 in the periphery (outer circumference). The first portion and the second solder resist portion 14b are present between the flux portion and the second solder resist portion 14b. The solder resist layer is not formed, but the region (the barrier region) of the substrate layer u is exposed. Therefore, when the semiconductor wafer 2 is soldered to the wiring substrate 3, the solder resist portion Ma and the first portion can be provided. The base material layer n is exposed between the solder resist portions 14b without the region (barrier region) 18 of the solder resist layer 14, and the adhesive material 8 is prevented from diffusing over the region 18 to the second solder resist portion 14b. Then the material 8 is diffused to the connection terminal 〖5, thereby The reliability of the electrical connection between the bonding wires 4 and the connection terminals 15. Further, even if a paste-type bonding material (bonding material) having a relatively high fluidity is used as the bonding material 8, the first solder resist portion can be provided. There is no solder resist layer 14 region (barrier region) 18 between 14a and the second solder resist portion i4b, and the paste 8 containing the paste material is prevented from diffusing to the connection terminal 15, so that the grain bonding film can be relatively low in price. Since the paste-type adhesive material is used as the adhesive material 8, it is advantageous in reducing the manufacturing cost of the semiconductor device. Further, since the connection terminal 15 of the wiring substrate 3 can be arranged close to the outer peripheral portion of the semiconductor wafer 2, 105491-971003 can be used. .doc •20· 1374527 Semiconductor devices are further miniaturized. Further, in the present embodiment, the semiconductor wafer 2 is mounted and fixed to the mth solder portion 14a via the bonding material 8, but the planar size (area) of the mth solder portion is smaller than the planar size (area) of the semiconductor wafer 2. ). Therefore, when the semiconductor wafer 2 is bonded to the first solder resist portion 14a of the upper surface 3a of the wiring board 3 via the bonding material 8, the back surface of the semiconductor wafer 2 is not extended (existing) below the outer peripheral portion 2d. The solder resist portion and the bonding material 8 are formed with a space 21 between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3. For this reason, when the sealing resin $ is formed, it is also used for formation. The material of the sealing resin 5 is filled in the space 2, and the hardened sealing resin 5 covers the surface hole 2 of the semiconductor wafer 2, the side surface 2e of the semiconductor wafer 2, and the outer surface 2d of the back surface 2C of the semiconductor wafer 2, and thus the semiconductor Since the bonding area between the wafer 2 and the sealing resin 5 is increased, the adhesion (adhesive strength) between the semiconductor wafer 2 and the sealing resin 5 can be improved, so that the reliability of the semiconductor device 1 can be improved. As shown in the present embodiment, The sealing resin 5 is also rotated into the back surface 2 (: side of the semiconductor wafer 2, and the sealing resin 5 is filled (filled) between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3 The semiconductor wafer 2 can be stably sealed by the sealing resin 5 on both the surface 2b and the back surface 2c of the semiconductor wafer 2 (the side surface 2e). Therefore, the adhesion between the semiconductor wafer 2 and the sealing resin 5 can be improved, so that it can be surely prevented. Further, peeling or the like occurs between the semiconductor wafer 2 and the sealing resin 5. Further, in the present embodiment, the space 21 formed between the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3 can be at a height I0549l- 971003.doc -21- 1374527 The dimension Hi in the direction is smaller than the dimension 221 of the space 221 of the semiconductor device 3〇1 of the third comparative example in the direction of the dimension Η: only the thickness of the large solder resist portion 14a T^H ^H2). For example, if the thickness of the backing material 8 is 汕 to the left and right and the thickness of the first solder resist portion 14a is about 20 to 30 μm, the size of the space 21 in the height direction can be made. In the present embodiment, the size of the lower space 21 of the back surface portion 2d of the semiconductor wafer 2 in the height direction can be made relatively large, so that the sealing resin 5 can be formed ( Demolding step) The filler or the like contained in the material of the sealing resin 5 is easily immersed in the space 21 below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, so that the composition ratio of the sealing resin 5 of the filling space 21 can be sealed with other regions. The composition ratio of the resin 5 is uniformized, whereby the adhesion (adhesive strength) between the cured sealing resin 5 and the semiconductor wafer 2 can be further improved, so that the reliability of the semiconductor device 1 can be further improved. In the embodiment, the inner peripheral portion of the second solder resist portion 14b (the inner peripheral portion of the second solder resist portion I4b facing the first solder resist portion 14a is opposite to the four sides of the semiconductor B sheet 2) In the corner portion (four corners, corner portion) of the inner peripheral portion of the solder resist portion, the pattern of the second solder resist portion 14b can be retracted to the outer circumferential direction of the semiconductor device (that is, the direction away from the semiconductor wafer 2). In other words, in the corner portion (four corners) of the inner peripheral portion of the second solder resist portion 14b, a solder resist retreating bird in which the base material layer 11 is exposed but no solder resist is formed is provided. When the pattern of the first flux portion 14b is retracted (that is, the solder resist retreating portion is provided) at the corner portion (four corners) of the inner peripheral portion of the second solder resist portion 14b, the sealing resin 5 is conveyed by the mold releasing step (4). It will become easy to remove from the space 21 between the outer peripheral portion 2d of the back surface 2c of the bulk wafer 2 and the upper surface 3a of the wiring substrate 3 from the semi-conductive l〇549l-97i〇〇3.doc -22· 1374527, and thus can be improved to form Since the material flowability of the sealing resin 5 is improved, the filling property of the sealing resin to the space 21 can be further improved. Therefore, the adhesion (adhesive strength) between the semiconductor wafer 2 and the sealing resin 5 can be further improved, so that the reliability of the semiconductor device 1 can be further improved. Fig. 11 is a cross-sectional view showing the main part of another form of semiconductor device 1a, and Fig. 12 is a plan perspective view (top view) thereof. Figure 11 corresponds to Figure 4 above. Further, Fig. 12 corresponds to Fig. 7 described above, and shows a plan view (top view) of the semiconductor device ia when the see-through sealing resin 5, the semiconductor wafer 2, and the bonding wires 4 are shown, which means the wiring used in the semiconductor device 1a. The top view of the substrate 3. Further, the shape of the semiconductor wafer 2 is indicated by a broken line in 'Fig. 12'. 12 is a plan view, but for the sake of understanding, the connection terminal 15 exposed from the second solder resist portion 14 a 'the second solder resist portion 14 b and the second solder resist portion 14 b is opened. Shadow line. In the semiconductor device 1, the end portion 2f of the back surface 2c of the semiconductor wafer 2 (the side surface 2e of the semiconductor wafer 2) is located in a region (barrier region) 18 in which the solder resist layer 4 is not formed but the substrate layer 11 is exposed. In the semiconductor device U shown in FIG. 11 and FIG. 12, the end portion 2f of the back surface 2c of the semiconductor wafer 2 (the side surface 2e of the semiconductor wafer 2) is located on the second solder resist portion 14b. The other configuration of the semiconductor device 1a is substantially the same as that of the semiconductor device 1 described above. The semiconductor device 1a can also obtain substantially the same effects as the semiconductor device 1, and is included in the semiconductor device of the present invention. Here, as in the case of the semiconductor device 1, the end portion 2c of the back surface 2c of the semiconductor wafer 2 (the side surface 2e of the semiconductor wafer 2) is located on the region (barrier region) 18, as compared with a semiconductor device like a semiconductor device 105491-971003.doc -23- 1374527 The back surface 2c end portion 2f of the bulk wafer 2 (the side surface (4) of the semiconductor wafer 2 is located on the second solder resist portion 14b" can be formed on the back surface of the semiconductor wafer 2 when the semiconductor wafer 2 wafer is soldered to the upper surface 3a of the wiring substrate 3 The space 21 between the outer peripheral portion of the 2c and the upper surface 3a of the wiring board 3 is enlarged, so that the filler or the like is apt to be immersed in the space 21 below the outer peripheral portion 背面 of the back surface 2c of the semiconductor wafer 2 when the sealing resin 5 is formed. The composition ratio of the sealing resin 5 in the space 21 is further uniform than the composition ratio of the sealing resin 5 in other regions. Thus, the semiconductor device 1 is more advantageous in improving the adhesion (adequate strength) or reliability of the sealing resin 5 to the semiconductor wafer 2. On the other hand, as in the case of the semiconductor device la, the second solder resist portion 14b can be extended by extending the lower end 2c of the semiconductor wafer 2 below the end 2f of the semiconductor wafer 2 (the side surface 2e of the semiconductor wafer 2) Since the terminal 15 is closer to the side of the semiconductor wafer 2, the semiconductor device is more advantageous for miniaturization (small area). Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to the drawings. Fig. 13 to Fig. 20 A cross-sectional view of the manufacturing process of the semiconductor device of the present embodiment. Fig. 21 to Fig. 23 are schematic views showing an example of a manufacturing process of the wiring substrate 31 used in the manufacture of the semiconductor device 1 of the present embodiment (above) Fig. 24 is a cross-sectional view showing the principal part of the manufacturing process of the semiconductor device of the present embodiment, which corresponds to the same step (wafer soldering step) as in Fig. 14. Fig. 25 is a plan view showing the manufacturing steps of the semiconductor device of the present embodiment. (above) 'corresponding to the same step as that of Fig. 15. Fig. 26 and Fig. 27 are explanatory diagrams of the wire bonding step (main part sectional view). Fig. 28 is the main manufacturing step of the semiconductor device of the embodiment. A partial cross-sectional view corresponding to the same step as that of Fig. 16 (mold step 105491-971003.doc -24·1374527). 21 to 28 is also expressed in the following step of cutting off the dicing region is cut (slit line) of a wiring board 3139.

再者’於衣實施形態中’就使用形成有連接為陣列狀之 複數個佈線基板3而獲得之多數個佈線基板（佈線基板母 體）3 1而製造各個半導體裝置丨之情形加以說明。該佈線基 板31係上述佈線基板3之母體，將佈線基板31於下述切斷 步驟中進行切斷並使之分離於各半導體裝置區域（基板區 域，早位基板區域）32者對應於半導體裝置i之佈線基板 3。佈線基板31含有如下構成，即作為由此形成有一個半 導體裝置1之區域之半導體裝置區域（基板區域、單位基板 區域）3 2複數排列為矩陣狀。 首先’準備佈線基板31。佈線基板31例如可以如下方式 而製造。In the embodiment of the present invention, a description will be given of a case where a plurality of wiring boards (wiring substrate bodies) 31 obtained by connecting a plurality of wiring boards 3 connected in an array are used to manufacture respective semiconductor devices. The wiring board 31 is a mother of the wiring board 3, and the wiring board 31 is cut in the cutting step described below and is separated from each semiconductor device region (substrate region, early substrate region) 32 corresponding to the semiconductor device. i wiring board 3. The wiring board 31 has a configuration in which a semiconductor device region (substrate region, unit substrate region) 3 2 in which a region of one semiconductor device 1 is formed is arranged in a matrix. First, the wiring board 31 is prepared. The wiring board 31 can be manufactured, for example, in the following manner.

於作為芯材之絕緣性基材層u上面ua以及下面上藉由 無電解電鍵(無電場電錢)法而形成無電解鍵銅層，並：由 電解鑛鋼層進行圖案化。此後，於無電㈣ 使銅層厚度變厚。可Γ::二=成電解鑛銅層’並 :積層膜(銅層），而形成上述導體層12。於圖21中，表示 藉由無電解鍍鋼層以及電 於基一上面，形成有通:::導 子一體圖案)之狀態。連接:子導:圖案^ 由包含於基材層丨丨上/、導體圖案33藉 含有電解鍍鋼層之積層膜:導二電解:銅層以及 )之抽引佈線（省略圖 105491-971003.doc •25- 1374527 示）而進行電性連接。x，雖未圖示，但於基材層η之下 面，藉由無電解錢銅層以及雷 增解鍍鋼層之積層膜亦形成有 焊盤16。又，由於使用電解電鍍法…於基材層Η之上 面11a亦形成有電錢佈線（供電線）34，故可經由該電鑛佈 線34供給特疋電位（電力），並於無電解錢銅層上形成電解 鑛銅層。 其次’如圖22所示，於基材層u上形成有開口部（通 孔通道貝通孔）17。開口部17形成於通孔用導體圖案 3 3之内側。 其次，藉由無電解電鍍法而於開口部17之側壁上形成無 電解鍍銅層。於該基材層U之開口部17侧壁上所形成之無 電—解鍍銅層將成為形成於開口部17側壁上之上述導體層 12。此後，如圖23所示，使用印刷法等以填充開口部口内 之方式而於基材層11上面lla以及下面上形成阻焊劑層 14。藉此，於基材層u之上面lu，形成有第1阻焊劑部 14a與第2阻焊劑部Mb。於基材層丨〗之上面Ua上，連接端 子15自阻焊劑層14(第2阻焊劑部14b)之開口部露出，而於 基材層11之下面上，則焊盤16自阻焊劑層14之開口部露 出。其次’於基材層U之上面Ua#及下面上之鍍銅層露 出部（即連接端子15以及焊盤16)上，藉由電解電鍍法而依 次形成鍍鎳層以及鍍金層。其後，可根據需要對基材層i ι 進行外形加工（切斷）形成佈線基板31。以如此方式而準備 之佈線基板31含有複數個於下述佈線基板31之切斷步驟中 通過分割而成為佈線基板3之半導體裝置區域（基板區域、 105491-971003.doc -26· 1J/4527 早位基板區域）32，且具有於佈線基板31上面3U之各半導 ，裝置區域32中所形成之第1阻焊劑部14a及於第!阻焊劑 邛l4a之外周所形成之第2阻焊劑部14b。An electroless bond copper layer is formed on the insulating base layer u as a core material and on the lower surface by an electroless bond (no electric field) method, and patterned by an electrolytic ore layer. Thereafter, the thickness of the copper layer is made thicker without electricity (4). It is possible to form: the above-mentioned conductor layer 12 is formed by a two-layered electrolytic copper layer 'and a laminated film (copper layer). In Fig. 21, a state in which a pass-through:::integrated pattern is formed by an electroless plated steel layer and an upper portion of the base is formed. Connection: sub-guide: pattern ^ from the substrate layer / /, the conductor pattern 33 by the electrolytic plating steel layer of the laminated film: lead two electrolysis: copper layer and) of the drawing wiring (omitted figure 105491-971003. Doc •25– 1374527) and electrically connected. x, although not shown, a pad 16 is formed on the underside of the substrate layer η by a laminate film of an electroless copper layer and a thunder-deposited steel layer. Further, since the electric charge wiring (power supply line) 34 is formed on the upper surface 11a of the base material layer by electrolytic plating, the special electric potential (electric power) can be supplied via the electric ore wiring 34, and the electroless copper is available. An electrolytic copper layer is formed on the layer. Next, as shown in Fig. 22, an opening portion (through hole channel through hole) 17 is formed in the base material layer u. The opening portion 17 is formed inside the through hole conductor pattern 3 3 . Next, an electroless copper plating layer is formed on the side wall of the opening portion 17 by electroless plating. The electroless-de-plated copper layer formed on the side wall of the opening portion 17 of the base material layer U becomes the above-mentioned conductor layer 12 formed on the side wall of the opening portion 17. Thereafter, as shown in Fig. 23, a solder resist layer 14 is formed on the upper surface 11a of the base material layer 11 and the lower surface so as to fill the inside of the opening portion by a printing method or the like. Thereby, the first solder resist portion 14a and the second solder resist portion Mb are formed on the upper surface of the base layer u. On the upper surface Ua of the substrate layer, the connection terminal 15 is exposed from the opening of the solder resist layer 14 (the second solder resist portion 14b), and on the lower surface of the substrate layer 11, the pad 16 is self-resisting the solder layer. The opening of 14 is exposed. Next, a nickel plating layer and a gold plating layer are sequentially formed on the upper surface Ua# of the base material layer U and the copper plating layer exposed portions on the lower surface (i.e., the connection terminals 15 and the pads 16) by electrolytic plating. Thereafter, the base material layer i can be subjected to outer shape processing (cutting) as needed to form the wiring substrate 31. The wiring board 31 prepared in this manner includes a plurality of semiconductor device regions which are divided into the wiring substrate 3 in the cutting step of the wiring substrate 31 described below (substrate region, 105491-971003.doc -26·1J/4527 early) The substrate region 32) has the respective semiconductors 3U on the upper surface of the wiring board 31, and the first solder resist portion 14a formed in the device region 32 and the second solder resist portion formed on the outer periphery of the solder resist 邛14a 14b.

於以上述方式所準備（製造）之佈線基板31上面3 la之各半 導體裝置區域32上如圖14及圖24所示，經由接著材8，接 合（晶片焊接，晶片安裝）有半導體晶片2。於該接合步驟 中例如，將熱硬化性之接著材8塗布於佈線基板31上面 31a之各半導體裝置區域32之第他焊劑部…上，並於第1 阻焊劑部14a上形成晶片固定用之接著層，將半導體晶片2 載置^接著材8上，並藉由加熱等使接著材8硬化，並且經 由接著材8將|導體晶片2之冑面2e與第！阻焊劑部⑷進行 接合。於半導體晶片2之接合步驟中，如上所述，由於於 平面尺寸（面積）小於半導體晶片2之帛丄阻焊劑部^上經由 接著材8而接合有半導體晶片2,故而於半導體晶片2之背 面2c外周。卩2d之下方不會延伸（存在）有阻焊劑層14(第1阻 焊劑部14a以及第2阻焊劑部Mb)或接著材8。為此，當將 半導體晶片2接合於佈線基板31之各半導體裝置區域32上 時’將會於半導體晶片2之背面2。外周部2d與佈線基板3之 上面3a之間形成有空間21，且該空間21於高度方向上之尺 寸大致相當於第1阻焊劑部ua之厚度Tl與接著材8之 厚度τ2之總和(Hl=T| + T2)’故可使空間⑽高度方向上之 尺寸Hl相對較大。例如’若接著材8之厚度丁2為2〇至30叩 左右，第1阻焊劑部14a之厚度1為2〇至3〇 pm左右，則可 使空間21於高度方向上之尺寸A為4()㈣叫左右。 105491-971003.doc -27· 1374527 其次，如圖15以及圖25所示，實施打線接合步驟，並邊 由接合線4將半導體晶片2之各電極以及與此對應之佈線基 板31上所形成之連接端子15進行電性連接。即，經由複數 個接合線4將佈線基板31之上面31a之各半導體裝置區域32 上之複數個連接端子15與接合於該半導體裝置區域32上之 半導體晶片2之複數個電極2a進行電性連接。例如，使用 打線接合裝置，將接合線4之一端連接（第一次接合）於半導 體晶片2之電極2a之後，將接合線4之他端連接（第二次接 合）於佈線基板31之連接端子15。 於該打線接合步驟中，至於其他形態，如圖26之主要部 分剖面圖中所示般，首先於佈線基板31之連接端子15上形 成含有金（Au)等凸塊（突起電極，凸塊）35後，如圖27所 示，亦可將接合線4之一端連接於半導體晶片2之電極2a， 再將接合線4之他端連接於於佈線基板31之連接端子15上 所形成之凸塊35上。使連接端子15形成於與半導體晶片2 相對較近之位置上，或使用相對較厚之半導體晶片2等， 則即使接合線4與連接端子15所成之角度變陡（例如接近於 垂直），對接合線4之折曲應力變大，亦可藉由於連接端子 15上形成凸塊35，並將接合線4連接於該凸塊35上，而提 高接合線4與連接端子15(凸塊35)間之連接強度，由此可抑 制或防止接合線4自連接端子15(凸塊35)脫落。因此，可使 自連接端子15至半導體晶片2為止之距離縮小，由此可降 低半導體裝置1之平面尺寸。又’亦可使用厚度相對較厚 之半導體晶片2’故可擴大對半導體晶片2之選擇餘地。 105491-971003.doc -28- U74527 於打線接合步驟後，如圖16以及圖28所示，實施脫模步 驟（例如傳送脫模步驟）之樹脂密封，形成密封樹脂5a(密封 °P )’並藉由密封樹脂5a而封裝半導體晶片2以及接合線 4。於該脫模步驟中，實施以密封樹脂5a對佈線基板31上 面31a之複數個半導體裝置區域32進行一併密封之一並密 封。即，於佈線基板31上面31 a之複數個半導體裝置區域 32上以覆蓋半導體晶片2以及接合線4之方式形成密封樹脂 5a。為此，密封樹脂5a形成為覆蓋佈線基板3ι上面之 複數個半導體裝置區域32。密封樹脂5a含有例如熱硬化性 樹脂材料等樹脂材料等，亦可含有填充料等。例如，可使 用含有填充料之環氧樹脂等形成密封樹脂5a。 於該脫模步驟中，亦將用以形成密封樹脂5a之材料填充 於半導體晶片2之背面2c外周部2d之下方空間21中。於本 實施形態中，由於半導體晶片2之背面2c外周部2d之下方 空間21於尚度方向上之尺寸相對較大，故而於脫模步驟 中，於用以形成密封樹脂5a之材料中所含有之填充料等會 易於次入到半導體晶片2之背面2c外周部2d之下方空間21 中，由此可使填滿空間21(經過填充）之密封樹脂5a之成分 比與其他區域密封樹脂5a之成分比均一化，故而可進而提 高經過硬化之密封樹脂5a與半導體晶片2之密著性（接著強 度）。 其次，如圖17所示，將錫球6連接（接合）於佈線基板31 下面31b之焊盤16上。例如’可使佈線基板31之下面31b朝 向上方，並將複數個錫球6配置於佈線基板31下面31b之複 I05491-971003.doc -29- 1374527 數個輝·盤1 6上並以捏添丨哲 上並以烊劑等加以臨時固定 (焊錫回焊熱處理，熱處理）且將谭_ 了回坏處理 佈線基板31下面川之焊盤16接合。其後，/使錫球6與 實施清洗步驟，除去附著'、可根據需要 般，則接合有作為半導體裝置i外部端子之錫_等^此 於本實施形態t ’就接合作為半導體裝置丨外部端子 :“之情形加以說明、然而並非限定於此，亦可例如藉由 P刷法等而代㈣球6將焊錫供給至焊盤Μ上以形 體裝置！之外部端子（突起電極）。χ，將半導體裝置i作為 BGA(Ball GHd Array，球狀矩陣）形態之半導體裝置加以說 明’然而並非限定於此’亦可省略錫球6之形成，而將半 導體裝置1作為LGA(Land Grid Array ,柵格陣列）形態之 半導體裝置。X ’半導體裝置i外部端子（錫球6)之材質 可使用含鉛焊錫或不含鉛之無鉛焊錫，又，可藉由電鍍 (例如鍍金或鍍Pd等）形成半導體裝置1之外部端子（突起電 極）〇As shown in Figs. 14 and 24, the semiconductor wafer 2 is bonded (wafer soldered, wafer mounted) to the respective semiconductor device regions 32 of the upper surface 3a of the wiring substrate 31 prepared (manufactured) as described above. In the bonding step, for example, a thermosetting bonding material 8 is applied onto the other solder portion of each of the semiconductor device regions 32 on the upper surface 31a of the wiring substrate 31, and a wafer fixing portion is formed on the first solder resist portion 14a. Next, the semiconductor wafer 2 is placed on the bonding material 8, and the bonding material 8 is cured by heating or the like, and the germane surface 2e of the |conductor wafer 2 is transferred via the bonding material 8! The solder resist portion (4) is bonded. In the bonding step of the semiconductor wafer 2, as described above, since the semiconductor wafer 2 is bonded to the solder resist portion of the semiconductor wafer 2 via the bonding material 8 in the planar size (area), the semiconductor wafer 2 is bonded to the back surface of the semiconductor wafer 2. 2c outside the week. The solder resist layer 14 (the first solder resist portion 14a and the second solder resist portion Mb) or the bonding material 8 does not extend under the 卩 2d. For this reason, when the semiconductor wafer 2 is bonded to the respective semiconductor device regions 32 of the wiring substrate 31, it will be on the back surface 2 of the semiconductor wafer 2. A space 21 is formed between the outer peripheral portion 2d and the upper surface 3a of the wiring board 3, and the dimension of the space 21 in the height direction substantially corresponds to the sum of the thickness T1 of the first solder resist portion ua and the thickness τ2 of the bonding material 8 (Hl =T| + T2)' Therefore, the size H1 in the height direction of the space (10) can be made relatively large. For example, if the thickness 2 of the backing material 8 is about 2 〇 to 30 ,, and the thickness 1 of the first solder resist portion 14a is about 2 〇 to 3 〇 pm, the dimension A of the space 21 in the height direction can be made 4 () (four) called left and right. 105491-971003.doc -27· 1374527 Next, as shown in FIGS. 15 and 25, a wire bonding step is performed, and the electrodes of the semiconductor wafer 2 and the corresponding wiring substrate 31 are formed by the bonding wires 4. The connection terminal 15 is electrically connected. That is, the plurality of connection terminals 15 on the semiconductor device regions 32 of the upper surface 31a of the wiring substrate 31 are electrically connected to the plurality of electrodes 2a of the semiconductor wafer 2 bonded to the semiconductor device region 32 via a plurality of bonding wires 4. . For example, after the one end of the bonding wire 4 is connected (first bonding) to the electrode 2a of the semiconductor wafer 2 using a wire bonding device, the other end of the bonding wire 4 is connected (second bonding) to the connection terminal of the wiring substrate 31. 15. In the wire bonding step, as shown in the main portion cross-sectional view of FIG. 26, first, bumps (protruding electrodes, bumps) including gold (Au) are formed on the connection terminals 15 of the wiring substrate 31. After 35, as shown in FIG. 27, one end of the bonding wire 4 may be connected to the electrode 2a of the semiconductor wafer 2, and the other end of the bonding wire 4 may be connected to the bump formed on the connection terminal 15 of the wiring substrate 31. 35. When the connection terminal 15 is formed at a position relatively close to the semiconductor wafer 2, or a relatively thick semiconductor wafer 2 or the like is used, even if the angle formed by the bonding wire 4 and the connection terminal 15 becomes steep (for example, close to vertical), The bending stress of the bonding wire 4 becomes large, and the bonding wire 4 and the connection terminal 15 (bump 35) can be improved by forming the bump 35 on the connection terminal 15 and connecting the bonding wire 4 to the bump 35. The connection strength between them can thereby suppress or prevent the bonding wires 4 from coming off the connection terminals 15 (bumps 35). Therefore, the distance from the connection terminal 15 to the semiconductor wafer 2 can be reduced, whereby the planar size of the semiconductor device 1 can be reduced. Further, the semiconductor wafer 2' having a relatively thick thickness can be used, so that the selection of the semiconductor wafer 2 can be expanded. 105491-971003.doc -28- U74527 After the wire bonding step, as shown in FIG. 16 and FIG. 28, the resin sealing of the demolding step (for example, conveying the demolding step) is performed to form the sealing resin 5a (sealing °P)' The semiconductor wafer 2 and the bonding wires 4 are encapsulated by the sealing resin 5a. In the mold release step, one of the plurality of semiconductor device regions 32 of the upper surface 31a of the wiring substrate 31 is sealed with a sealing resin 5a and sealed. That is, the sealing resin 5a is formed on the plurality of semiconductor device regions 32 on the upper surface 31a of the wiring substrate 31 so as to cover the semiconductor wafer 2 and the bonding wires 4. To this end, the sealing resin 5a is formed to cover a plurality of semiconductor device regions 32 on the wiring substrate 3i. The sealing resin 5a contains a resin material such as a thermosetting resin material, and may contain a filler or the like. For example, the sealing resin 5a can be formed using an epoxy resin or the like containing a filler. In the demolding step, a material for forming the sealing resin 5a is also filled in the space 21 below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2. In the present embodiment, since the lower space 21 of the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 has a relatively large dimension in the direction of the width, it is contained in the material for forming the sealing resin 5a in the demolding step. The filler or the like can be easily introduced into the space 21 below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, whereby the composition ratio of the sealing resin 5a filling the space 21 (filled) can be made to the sealing resin 5a of the other regions. Since the composition ratio is uniform, the adhesion (adjacent strength) between the cured sealing resin 5a and the semiconductor wafer 2 can be further improved. Next, as shown in Fig. 17, the solder balls 6 are joined (bonded) to the pads 16 on the lower surface 31b of the wiring substrate 31. For example, 'the lower surface 31b of the wiring substrate 31 may be directed upward, and a plurality of solder balls 6 may be disposed on the lower surface 31b of the wiring substrate 31, I05491-971003.doc -29-1374527, and a plurality of phosphor disks 16 may be pinned. The 丨 上 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时 临时Thereafter, the solder ball 6 is subjected to a cleaning step to remove the adhesion, and if necessary, a tin which is an external terminal of the semiconductor device i is bonded, and the like is bonded to the outside of the semiconductor device in the present embodiment t'. Terminal: "The case is described, but it is not limited thereto, and the external terminal (protruding electrode) of the physical device can be supplied to the pad 例如 by the P brush method or the like, for example, by the P brush method or the like. The semiconductor device i is described as a semiconductor device in the form of a BGA (Ball GHd Array). However, the present invention is not limited thereto, and the formation of the solder ball 6 may be omitted, and the semiconductor device 1 may be used as an LGA (Land Grid Array). A semiconductor device in the form of a grid array. The material of the X 'semiconductor device i external terminal (tin ball 6) can be lead-free solder or lead-free solder without lead, and can be formed by electroplating (for example, gold plating or Pd plating). External terminal (protruding electrode) of the semiconductor device 1

其次，如圖18所示，進行標記，於密封樹脂53之表面付 與製品序號等標記。例如’可進行藉由雷射3 6進行標記之 雷射標記，亦可實施藉由油墨進行標記之油墨標記。又， 亦可將圖17之錫球6之連接步驟與圖18之標記步驟順序進 行調換’於進行圖18之標記步驟後，進行圖17之錫球6連 接步驟。 其次，如圖19所示，將密封樹脂5 a之上面貼付於密封固 定膠帶37上，並沿著切割區域（切割線）39藉由切割刀38等 105491-971003.doc • 30· 1374527 將佈線基板31以及形成於其上之密封樹脂5a切斷（切割）， 將各自之半導體裝置區域（CSP區域）切斷分離為各個（經過 單片化之）半導體裝置1(CSP)。即，將佈線基板31以及密 封樹脂5a切斷並分割為各個半導體裝置區域32。如此般， 可通過進行切斷.單片化，而製造如圖丨至圖7所示之半導 體裝置1。切斷並分離（分割）於各半導體裝置區域32中之佈 線基板3 1對應於佈線墓板3，而切斷並分離（分割）於各半導 體裝置區域32中之密封樹脂5a則對應於密封樹脂5。 圖29係如上述般所製造之半導體裝置！之端部附近區域 之其他主要部分剖面圖（部分放大刮面圖），且表示不同於 圖4之區域剖面。如上所述，由於使用電解電鍍法形成佈 線基板3(佈線基板31)之導體層12，故而於構成佈線基板3 之基材層11之上面11a周邊部（於基材層u之上面Ua端部與 連接端子15之間）存在有電鍍佈線34。於本實施形態中， 該電鍍佈線34上受到阻焊劑層14(第2阻焊劑部i4b)之覆 蓋，故電鍍佈線34與密封樹脂5並不接觸。 不同於本實施形態，於電鍍佈線34上並未形成有阻焊劑 層14之情形時，於連接端子15上形成有鍍金層後，於電鍍 佈線34上亦形成有鍍金層，故於形成密封樹脂5(密封樹脂 5a)後，將導致於上面形成有錄金層之電鑛佈線34與密封 樹脂5直接接觸。由於該情形時，密封樹脂5與電解鍍金層 之密著性低於阻焊劑層14與密封樹脂5之密著性，故而電 鍍佈線34與密封樹脂5之密著性將會下降。由於該密著性 較低之界面(電鍍佈線34與密封樹脂5之界面)經過單片化處 105491-971003.doc -31 - 1374527 理後將會於半導體裝置之側面上露出，故而將導致自界面 進入有濕氣(水分)之吸濕不良。藉由該吸濕不良而有可能 產生因密封樹脂5密著性下降而造成之剝離，或因濕氣而 造成之接合線4之生銹或氧化，由此導致半導體裝置之可 靠性下降。 於本實施形態甲’於使用電解電鍍法形成佈線基板3(佈 線基板31)之導體層12之情形時，將以阻焊劑層14(第2阻焊 劑部14b)覆蓋電鐘佈線34上，藉此可使電鍍佈線34與密封 樹脂5並不接觸，並且可使密著性較低之界面並不形成於 半導體裝置側®，因此可抑制來自+導體裝置側面之吸濕 不良，由此可提高半導體裝置之可靠性。 (實施形態2) 圖30係作為本發明其他實施形態之半導體裝置比之製造 步驟中之主要部分剖面圖，且表示有大致與上述實施形態 1之圖4相對應之區域。圖31以及圖32係本實施形態之打線 接合步驟之說明圓（主要部分剖面圖）。 本實施形態之半導體裝置lb之製造步驟，由於除打線接 合步驟以外與上述實施形態1大致相同故而於此省略其說 明，而就本實施形態半導體裝置113之製造步驟中之打線接 合步驟加以說明。 於上述實施形態1中’首先將接合線4之一端連接（第一 次接合）於半導體晶片2之電極2a ’再將接合線4之他端連 接於佈線基板31之連接端子15(第二次接合），而於本實施 形態中’首先將接合線4之一端連接（第一次接合）於佈線基 105491-971003.doc •32· 1374527 板31之連接端子i5，再將接合線4之他端連接（第二次接合） 於半導體晶片2之電極2a。 即，首先，如圖31所示，一面施加超音波一面將包含保 持於接合線4形成用之打線接合裝置之毛細管41的金（Au) 等之接合線4前端推壓至佈線基板31之連接端子15表面 上。隨後如圖32所示，將毛細管41提升至上方，並使之於 榼向上移動，一面施加超音波一面將接合線4推壓連接於 半導體晶片2之電極2a表面，並切斷接合線4。藉此，可經 由接合線4使佈線基板31之連接端子15與半導體晶片2之電 極2a電性連接。可藉由如此般實施打線接合，而製造如圖 30所示之半導體裝置lb。 圖33不同於本實施形態，其表示首先將接合線4之一端 連接（第一次接合）於半導體晶片2之電極2a，再將接合線4 之他端連接（第二次接合）於佈線基板31之連接端子15之情 形時之主要部分剖面圖。如圖33所示，首先將接合線4之 一端連接於半導體晶片2之電極2a情形時，於為進行第二 次接合而將毛細管41移動至連接端子15上時，接合線4可 位於毛細管41與半導體晶片2之間1此，若使佈線基板 之連接端子15過於接近半導體晶片2,則可能導致接合 線4與半導體晶片2接觸》 對此，於本實施形態中，如圖31以及圖32所示，首先將 接合線4之一端連接（第一次接合）於佈線基板31之連接端子 15，再將接合線4之他端連接（第二次接合）於半導體晶片2 之電極2a。即，可將連接端子15第—次接合於佈線基抑 105491-971003.doc -33· 1374527 後，將毛細管41提升至上方並使之於橫向上移動，使半導 體晶片2第二次接合於電極2a。為此，於為進行第二次接 合而使毛細管41移動至半導體晶片2之電極2a上時，接合 線4並不會位於毛細管41與半導體晶片2之間。因而，即使 佈線基板31之連接端子15接近於半導體晶片2，亦可防止 接合線4與半導體晶片2接觸。藉此，可提高半導體裝置之 可靠性。又，由於可使佈線基板31之連接端子15更加接近 於半導體晶片2，因此可使半導體裝置小型化（小面積化）。 又，於打線接合步驟中，較之第二次接合，第一次接合 者可縮小連接所需之電極面積。於本實施形態中，藉由首 先將接合線4之一端連接（第一次接合）於佈線基板31之連接 端子1 5，而可縮小連接端子丨5之面積，故可使第2阻焊劑 部14b之連接端子15露出用之開口部丨9變小。即，一面施 加超音波一面將保持於毛細管41中之接合線4前端推壓並 連接於佈線基板31之連接端子15表面（第一次接合），在將 毛細管41提升至上方，故而可使連接端子15變小因此可 使第2阻焊劑部14b之連接端子15露出用之開口部19變小。 例如，較好的是，使連接端子15之長度（連接端子15於延 伸方向上之長度）L, ’即第2阻焊劑部1仆之連接端子15露 出用之開口部19之長度L丨為120 μπι以下（Ljl20 μηι)，更 好的疋100 μηι以下（L丨各1〇〇 μπι)。藉此，可使半導體裝置 小型化（小面積化）。 又，更好的是’如圖31以及圖32之主要部分剖面圖所 不，預先於半導體晶片2之電極2a上形成含有金（Au)等凸 105491-971003.doc -34* 1374527 塊（突起電極，凸塊）42 ’並於進行第二次接合時，將接合 線4連接於半導體晶片2之電極23上之凸塊42。藉此，可提 高接合線4與半導體晶片2之電極2a之連接強度。又，於將 半導體晶片2第二次接合於電極2a時可降低給於半導體晶 片2之應力。 進而，由於可使接合線4與半導體晶片2(半導體晶片之 表面側端部2f)之距離較大，故而可使密封樹脂5向半導體 晶片2背面2c侧之流動性高於如圖33所示之打線接合之情 形。 (實施形態3) 圖34係作為本發明其他實施形態之半導體裝置lc之主要 部分剖面圖’圖35係其平面透視圖（上面圖）。圖34對應於 上述實施形態1之圖4 »又，圖3 5對應於上述實施形態1之 圖7 ’且表示透視密封樹脂5、半導體晶片2以及接合線4時 之半導體裝置lc之平面透視圖（上面圖），即用於半導體裝 置;lc之佈線基板3之上面圖》再者，於圖35中，用虛線表 示半導體晶片2之外形。又，圖35為平面圖，但為便於理 解，對自第1阻焊劑部14a，第2阻焊劑部14b，第3阻焊劑 部14c，以及第2阻焊劑部14b之開口部19所露出之連接端 子15付與影線。 本實施形態之半導體裝置lc中，由於形成於佈線基板3 上面3 a之阻焊劑層14以外之構成’大致與上述實施形態1 之半導體裝置1相同故而於此省略其說明，就於半導體裝 置lc上之佈線基板3上面3a所形成之阻焊劑層14加以說 105491-971003.doc -35- 1374527 明。 於上述實形態1中，佈線基板3上面3a之阻焊劑層14包 含：位於半導體晶片2下方之第！阻焊劑部14a ;位於佈線 基板3上面3a之外周部上之第2阻焊劑部141)，而於本實施 形態之半導體裝置1c中，佈線基板3上面3a之阻焊劑層 14，如圖34以及圖35所示，其含有：位於半導體晶片2下 方之第1阻焊劑部14a ;位於佈線基板3上面3a之外周部上 之第2阻焊劑部14b ;進而於第1阻焊劑部14a與第2阻焊劑 部1 4b之間以包圍第1阻焊劑部14a之方式而形成之第3阻焊 劑部14c。於第1阻焊劑部14a與第3阻焊劑部之間，存 在有並未形成有阻焊劑層14而露出有基材層1丨（以及含有 導體層12之柚引佈線）之區域（障壁區域）i8a，於第3阻焊劑 部14c與第2阻焊劑部14b之間，存在有並未形成阻焊劑層 14而露出有基材層ιι(以及含有導體層12之抽引佈線）區域 (障壁區域）18b。於第1阻焊劑部14a上經由接著材8接合（搭 載、連接、固定、配置）有半導體晶片2。第2阻焊劑部14b 含有用以露出連接端子15之開口部19。與上述實施形態1 相同，第1阻焊劑部14a之平面尺寸（面積），小於半導體晶 片2之平面尺寸（面積）。因此，當搭載有半導體晶片2時， 於半導體晶片2之背面2c外周部2d下方將不會延伸（存在）有 第1阻焊劑部1 4a。 如此般，於本實施形態中，於佈線基板3上面3 a形成有 如下者：於佈線基板3上面3a上經由接著材8接合有半導體 晶片2之第1阻焊劑部14a ;設置於第1阻焊劑部14a周圍（外 105491-971003.doc -36- 1374527 周）之第3阻焊劑部14c ;設置於第3阻焊劑部14c周圍（外周） 並自其開口部19露出連接端子15之第2阻焊劑部141)。於第 1阻焊劑部14a與第3阻焊劑部14c之間以及第3阻焊劑部i4c 與第2阻焊劑部14b之間，存在有並未形成阻焊劑層i4而露 出有基材層11之區域（障壁區域8a、l8b。因此，當將半 導體晶片2接合於佈線基板3上時，於第1阻焊劑部i4a與第 3阻焊劑部14c之間設置並無阻焊劑層14但露出有基材層】j 之區域（障壁區域）l8a,藉此可防止含有膏材等之接著材8 越過區域18a而擴散至第3阻焊劑部14c上，進而，即使含 有膏材等之接著材8越過區域18a而擴散至第3阻焊劑部14c 上’亦可藉由於第3阻焊劑部14c與第2阻焊劑部i朴之間設 置並無且f劑層14但露出有基材層丨丨之區域（障壁區 域）18b，而防止含有膏材等之接著材8越過區域i8b擴散至 第2阻焊劑部上。藉此，可更加確實防止接著材8擴散 至連接端子15上，由此可更加確實提高接合線4與連接端 子15間電性連接之可靠性。又，即使將流動性相對較高之 膏型接著材（接合材）用作接著材8，亦可防止含有膏材之接 著材8擴散至接合端子15上，因此可將較之晶粒接合膜價 格相對低廉之膏型接著材用作接著材8，因而有利於降低 半導體裝置之製造成本。 _ (實施形態4) 圖36係作為本發明其他實施形態之半導體裝置id之主要 部分剖面圖’並對應於上述實施形態1之圖4。 於上述實施形態！中，半導體裝置丨之佈線基板3上面“ I05491-971003.doc .37· 1374527 之第m焊劑部14a厚度與第2阻谭劑部⑽之厚度為大致相 同，而於本實施形態之半導體裝置比中，佈線基板3上面 3a之第】阻焊劑部14a之厚度T|則厚於第2阻焊劑部i4b之厚 度Τ3(ΊΊ>Τ3)。其他構成則與上述實施形態！大致相同故 而於此省略其說明。 於本實施形態中，如圖36所示，使平面尺寸小於半導體 晶月2且經由接著材8將半導體晶片2接合於其上之第丨阻焊 劑部14a之厚度Tl厚於設置於第！阻焊劑部14a周圍（外周）之 • 第2阻焊劑部14b之厚度丁3^>丁3卜如此之佈線基板3 ’例 如於基材層11之上面11a形成阻焊劑層14時，將阻焊劑層 進行2次塗布（複數塗布，複數印刷），故第2阻焊劑部Mb將 由第1層之阻焊劑層而形成，藉此俵之相對較薄，而第1阻 焊劑部14a由第1層以及第2層之阻焊劑層（之積層膜）而形 - 成，藉此使之相對較厚，由此可進行準備（製造）。 於本實施形態中，由於使第1阻焊劑部14a之厚度L厚於 第2阻焊劑部14b之厚度Τ3(Τι>Τ3)，故而較之第1阻焊劑部 _ 14a之厚度Τ丨與第2阻焊劑部14b之厚度Τ3相同之（τ丨=Τ3)情 形，當將半導體晶片2晶片焊接於佈線基板3上後，可使於 半導體晶片2之背面2c外周部2d與佈線基板3上面3a之間所 形成之空間21於高度方向上之尺寸H]更大。因此，於形成 密封樹脂5時，用以形成密封樹脂5之材料中所含有之填充 料等可藉由半導體晶片2之背面2c外周部2d之下方之空間 2 1而變得易於浸入，因而可使填充空間21之密封樹脂5之 成分比與其他區域密封樹脂5之成分比更加均一化。藉 105491-971003.doc -38- 1374527 此，可更加提高經過硬化之密封樹脂5與 著性(接著強度)，故而可更加提高半導體 性。 (實施形態5) 圖37係作為本發明其他實施形態之半導體裝置之平面透 視圖（上面圖），圖38係作為本發明更進一步之其他實施形 〜、之半導體裝置之平面透視圖（上面圖），且分別對應於上 述實施形態1之圖7。因此於圖37以及圖38中表示有透視密 封樹脂5，半導體晶片2以及接合線4時之半導體裝置之平 面透視圖（上面圖），即用於本實施形態半導體裝置之佈線 基板3之上面圖。又’於圖37以及圖38中，用虛線表示半 導體晶片2之外形。又，圖37以及圖38為平面圖，但為便 於理解，對第1阻焊劑部14a ’第2阻焊劑部14b以及自第2 阻焊劑部14b之開口部19所露出之連接端子15付與有影 線。 本實施形態之半導體裝置，由於除形成於佈線基板3上 面3a上之第2阻焊劑部14b之圖案形狀以外之構成，與上述 實施形態1之半導體裝置1大致相同故而於此省略其說明， 而就形成於本實施形態半導體裝置之佈線基板3上面3a的 第2阻焊劑部1 4b之圖案形狀加以說明。 於本實施形態中，於第2阻焊劑部14b内周部（與第1阻焊 劑部14a相對向之第2阻焊劑部14b之四邊，與半導體晶片2 之四邊相對向之第2阻焊劑部14b之四邊），形成有梳形（凹 凸狀）圖案。即，第2阻焊劑部14b含有形成於佈線基板3上 105491 ·971003.doc •39· 1374527 面3a之外周部上且具有用以露出連接端子15之開口㈣之 第1部分61 ;以及連接於第丨部分61，並自第丨部分61延伸 於接近第m焊劑部14a(半導體晶片2)方向之複數個第2部 分62。含有㈣圖案<第2阻焊劑部⑽之整體膜厚為大致 支句一〇 藉由第1之部分61與複數個第2部分62而形成第2阻焊劑 4 14b，並於第2阻焊劑部14b内周之四邊上設置梳形圖案 (阻焊劑圖案）’藉此，當藉由傳送脫模步驟等而形成密封 樹脂5時，將會易於自半導體晶片2之背面2c外周部2d與佈 線基板3上面3a間之空間21中排出空氣，故用以形成密封 樹脂5之材料之流動性會加強，因而可更加提高密封樹脂 對上述空間21之填充性。因此，可更加提高半導體晶片2 與密封樹脂5之密著性（接著強度），故而可更加提高半導體 裝置之可靠性。 又，如圖37所示’若第2阻焊劑部14b第2部分62並未延 伸至半導體晶片2下方為止，則當將半導體晶片2晶片焊接 於佈線基板3之上面3a時，可進一步擴大半導體晶片2之背 面2c外周部2d與佈線基板3上面3a之間所形成之空間21， 並當形成密封樹脂5時，可使填充料等易於浸入至半導體 晶片2之背面2c外周部2d之下方之空間21中。藉此，可使 填充空間2 1之密封樹脂5之成分比與其他區域密封樹脂5之 成分比更加均一。又，如圖38所示亦可使第2阻焊劑部14b 第2部分62延伸至半導體晶片2之下方為止，故於該情形 時，可使連接端子15進一步接近半導體晶片2側，由此將 105491-971003,doc •40- 1374527 有利於半導體裝置小型化（小面積化）。 (實施形態6) 圖39係作為本發明其他實施形態之半導體裝置le之端部 附近區域之主要部分剖面圖（部分放大剖面圖），其對應於 上述實施形態1之圖4。圖4〇係透視密封樹脂5時之半導體 裝置le之平面透視圖（上面圖），其對應於上述實施形態1之 圖6 ^圖41係透視密封樹脂5、半導體晶片2以及接合線4時 之半導體裝置le之平面透視圖（上面圖），即用於半導體裝 置le之佈線基板3之上面圖，且其對應於上述實施形態！之 圖7。圖42至圖44係模式性表示用於本實施形態之半導體 裝置le之製造的佈線基板31之製造步驟之一示例之平面圖 (上面圖），且其對應於上述實施形態1之圖21至圖23。再 者’於圖41中’用虛線表示半導體晶片2之外形。又，圖 41為平面圖，但為便於理解，而對第！阻焊劑部14a，第2 阻焊劑部14b以及自第2阻焊劑部14b所露出之連接端子15 付與有影線》 於上述實施形態1中’半導體裝置1之佈線基板3之上面 3a以及下面3b之導體層12，主要通過使用電解電鍍法而形 成’而於本實施形態中，半導體裝置le之佈線基板3之上 面3a以及下面3b之導體層12並不使用電解電鍍法，而是使 用無電解電鍵法而形成。又，於上述實施形態1中，於半 導體裝置1之佈線基板3上面3a之外周端部上形成有第2阻 焊劑部14b ’而於本實施形態之半導體裝置le中，如圖39 至圖41所示’於佈線基板3上面3a之連接端子15之更外周 10549l-971003.doc 41 1374527 側區域並未形成有第2阻焊劑部14b(阻焊劑層14)，而於佈 線基板3上面3a之外周端部中，佈線基板3之基材層11與密 封樹脂5處於密著（接觸）狀態。由於其他構成與上述實施形 態1大致相同，故而於此省略其說明。 首先，就用於本實施形態半導體裝置le之製造中的佈線 基板31之製造步驟加以說明。佈線基板31可例如以如下方 式進行製造。 於作為芯材之絕緣性基材層11之上面11 a以及下面上藉 由無電解電鍍（無電場電鍍）法而形成無電解鍍銅層，並藉 由蝕刻等而將該無電解鍍銅層圖案化。於上述實施形態1 中’於無電解鍍銅層上，形成有電解鍍銅層，而於本實施 形態中，預先形成較厚之無電解鍍銅層，而並非形成電解 鍍銅層。可藉由該無電解鍍銅層（銅層），而形成佈線基板 31 (佈線基板3)之導體層12。於圖42中，表示有通孔用導體 圖案33與連接端子15(用之導體圖案）於基材層11上面藉由 無電解鍍銅層（導體層12)而形成之狀態。連接端子15與導 體圖案33藉由含有形成於基材層11上面lla之無電解鍵銅 層（導體層12)之抽引佈線（省略圖示）而電性連接。又，雖 未進行圖示，但於基材層11之下面，藉由無電解鍍銅層 (導體層12)而形成有焊盤16。又，於本實施形態中，由於 並未使用有電解電鍍法，故而於基材層11之上面lla，並 未形成如上述實施形態1般之電鍍佈線（供電線）34。 其次，如圖43所示，於基材層11開口部形成有（通孔、 通道、貫通礼）17。開口部17形成於通孔用導體圖案33之 105491-971003.doc • 42· 1374527 内側》 其次，藉由無電解電鍍法而於開口部17側壁上形成無電 解鍍銅層。藉由於該基材層11側壁上所形成之無電解鍍銅 層，而形成有開口部17側壁上之上述導體層12。隨後如圖 44所示，使用印刷法等以填充開口部17内之方式於基材層 11之上面11a以及下面上形成阻焊劑層14。藉此，於基材 層11之上面1 la，形成有第i阻焊劑部14a與第2阻焊劑部 14b。於基材層11之上面lia，連接端子15自阻焊劑層14之 開口部19a露出，而於基材層u之下面，焊盤16自阻焊劑 層14之開口部露出。用以露出連接端子15之開口部19a形 成於第2阻焊劑部14b上’且以橫切第2阻焊劑部1朴開口部 19a之中央之方式形成有切割區域39。其次，於基材層11 之上面11a以及下面上之無電解鍵銅層之露出部（即連接端 子15以及焊盤16)上’藉由無電解電鍍法而依次形成有無 電解鍍鎳層、無電解鍍鈀層以及鍍金層。其後，可根據需 要對基材層11進行外形加工（切斷）而形成佈線基板31。 可使用以如此方式而製造之佈線基板3丨，製造本實施形 態之半導體裝置le’但由於該製造步驟大致與上述實施形 態1相同，故而於此省略其說明。 於本實施形態中，如上述般，使用無電解電鍍法而並非 電解電鑛法’形成佈線基板3(佈線基板31)之導體層12。 即’並不使用電解電鑛法，而使用無電解電錄法形成佈線 基板3之連接端子15或焊盤16。由於為形成導體層12而並 未使用電解電鍍法，故而於佈線基板3之上面3a(佈線基板 105491-97I003.doc -43- 1374527 31上面31 a)，並未形成有如上述實施形態1般之電鍍佈線 (供電線）34。又，於本實施形態中，如上所述’因使切割 區域39橫切用以露出連接端子15之開口部19a中央，故於 佈線基板3上面3a之連接端子15之更外周側區域中並未形 成有第2阻焊劑部14b。即，於佈線基板3之上面3a中，第2 阻焊劑部14b(阻焊劑層14)並未自連接端子15延伸至佈線基 板3之端部。因此’於佈線基板3上面3 a之外周端部露出有 佈線基板3之基材層U ’且所露出之基材層丨丨可與密封樹 月曰5抵著。於本實施形態中’由於於佈線基板3之上面3a之 外周端部並未存在有電鍍佈線’而基材層u與密封樹脂5 為密著狀態，故而密著性較低之界面不會形成於半導體裝 置之側面，由此可提高半導體裝置之可靠性。 。又由於於佈線基板3上面3a之連接端子15之更外周側 區域中並未形成有第2阻焊劑部⑽，故而於對連接端子15 進行打線接合時，可防止毛細管（對應於上述毛細管叫接 觸於第2阻焊劑部14b。因此， 了構疋進仃對連接端子15之 打線接合，故可進_ at. ie -¾. , 知：问連接知子15與接合線4電性連 接之可靠性。又，亦可縮小連 .._ 饮响卞15之面積’故而有利 於實現半導體裝置小型化 m. ^ λ 償化）又，亦可易於進行 將複數個接合線4連接至一個連接 如雙倍焊接或三倍焊接卜 《複數煤接（例 (實施形態7) 圖45係作為本發明其他實施形雄之 部分剖面圖’且其對應 :導體裝置】f之主要 述實施形態6之圖39。 105491-971003.doc • 44 - 於上述實施形態6之半導體裝置lel}7，半導體裝置卜之 佈線基板3上面3a以及下面3b之導體層⑽使用無電解電 鍍法而並非電解電鍍法所形成者，而於本實施形態之半導 體裝置if中，與上述實施形態i之半導體裝置1相同，主要 使用電解紐法（或電解電鍍法以及無電場f鍍法之組合） 形成半導體裝置1之佈線基板3上面33以及下面化之導體層 12。然而，不同於上述實施形態丨之半導體裝置丨，本實施 形態之半導體裝置If並非將電鍍佈線（供電線）34形成於基 材層11之上面11a上，而是使其形成於基材層u之下面Iib 上。本實施形態之半導體裝置If其他構成以及製造步驟大 致與上述半導體裝置le相同。因此，透視密封樹脂5時之 半導體裝置If之平面透視圖（上面圖）與上述實施形態6之圖 40相同，而透視密封樹脂5、半導體晶片2以及接合線4時 之半導體裝置If之平面透視圖（上面圖），即用於半導體裝 置If中之佈線基板3之上面圖與上述實施形態6之圖41相 同。即’於本實施形態之半導體裝置lf中亦含有與上述實 施形態ό之半導體裝置le相同之阻焊劑層第1阻焊劑部 14a以及第2阻焊劑部14b)之圖案形狀。由此，與上述實施 形態6之半導體裝置le相同，於本實施形態之半導體裝置 If中’於佈線基板3上面3a之連接端子15之更外周側區域 中並未形成有第2阻焊劑部14b(阻焊劑層14)，且於佈線基 板3之上面3a之外周端部上，佈線基板3之基材層11與密封 樹脂5處於密著（接觸）狀態。 於本實施形態中，由於與上述實施形態6相同，於佈線 105491-971003.doc •45· 1374527 基板3上面3a之連接端子15之更外周側區域中亦並未形成 有第2阻焊劑部14b，故而可於對連接端子。進行打線接合 時防止毛細管（對應於上述毛細管41)接觸於第2阻焊劑部 14b。因此，可穩定進行對連接端子15之打線接合，故而 可提咼連接端子15與接合線4電性連接之可靠性。又，亦 可使連接端子15之面積縮小，故而有利於實現半導體裝置 小型化（小面積化）。又，亦可易於進行將複數個接合線4連 接至一個連接端子15中之複數焊接（例如雙倍焊接或三倍 焊接）。 又，於本實施形態中，主要使用電解電鍍法形成佈線基 板3之上面3a以及下面3b之導體層12，但並未將用於電解 電鍍時之電鍍佈線（供電線）34形成於基材層u之上面Ua 上，而是將其形成於基材層n之下面ub上。因此，於佈 線基板3之上面3a(佈線基板31上面31a)上，並未形成有電 鍍佈線（供電線）34。又，於本實施形態，亦如上述實施形 態6所述，因使切割區域39橫切用以露出連接端子15之開 口。卩19a中央，故而於佈線基板3上面3a之連接端子Η之更 外周側區域中不會形成有第2阻焊劑部14b。即，於半導體 裝置If之佈線基板3之上面3a中，第2阻焊劑部14b(阻焊劑 層14)並未自連接端子15延伸至佈線基板3之端部。因此， 於佈線基板3上面3a之外周端部中，露出有佈線基板3之基 材層11，並所露出之基材層n可與密封樹脂5進行密著。 而於本實施形態中，由於於佈線基板3之上面3&外周端部 中，並未存在有電鍍佈線，且基材層u與密封樹脂5密 105491-971003.doc -46- 1374527 著，故而密著性較低之界面不會形成於半導體裝置側面， 因此可提高半導體裝置之可靠性。 (實施形態8) 圖46係作為本發明其他實施形態之半導體裝置lg之平面 透視圖（上面圖）’圖47係其剖面圖。㈣對應於上述實施 形態1之圖6，且表示有透視密封樹脂5時之半導體裝置。 之平面透視圖(上面圖）。圖47對應於上述實㈣態】之圖 3 ’且圖46之B-B線剖面大致對應於圖47。 於上述實施形態1之半導體裝置丨中，於佈線基板3上搭 載有一個半導體晶片2,而於本實施形態之半導體裝置。 中，於佈線基板3上搭載有複數個半導體晶片2。於此就搭 載有2個半導體晶片2之例示加以說明，但並非限定於此， 亦可於佈線基板3上搭載2個以上半導體晶片2而製造半導 體裝置1 g ^ 於本實施形態中，於佈線基板3之上面3a形成有：第1阻 焊劑部14a，其經由接著材8將半導體晶片2接合於佈線基 板3之上面3a上；第2阻焊劑部14b，其設置於第”且焊劑部 14a之周圍（外周），並自其開口部19露出連接端子15，但數 量與搭載於佈線基板3上之半導體晶片2數相同之第1阻焊 劑部14a形成於佈線基板3之上面3a。例如，如圖46以及圖 47般當將2個半導體晶片2搭載於佈線基板3上之情形時，2 個第1阻焊劑部1 4a形成於佈線基板3之上面3a，並經由接 著材8而於各第1阻焊劑部14a上接合半導體晶片2。複數個 半導體晶片2之複數個電極2 a ’經由複數個接合線4而電性 I05491-971003.doc •47- 1374527 連接於佈線基板3之複數個連接端子丨5上。而其他構成則 大致與上述實施形態1相同。 於本實施形態中，由於於分別接合半導體晶片2之第”且 焊劑部14a與第2阻焊劑部14b之間，亦存在有並未形成阻 焊劑層14但露出有基材層n之區域（障壁區域）18 ,故而當 將半導體晶片2接合於佈線基板3上時，可防止含有膏材等 之接著材8越過區域18而擴散至第2阻焊劑部Mb上。藉 此，可防止接著材8擴散至連接端子15上，因此可提高接 合線4與連接端子1 5間電性連接之可靠性。 又，於本實施形態中，各半導體晶片2亦經由接著材8而 接合於平面尺寸（面積）小於該半導體晶片之第1阻焊劑部 1鈍上。因此，當將各半導體晶片2晶片焊接於佈線基板3 之上面3a時’於各半導體晶片2之背面2c外周部2d下方不 會延伸（存在）有第1阻焊劑部l4a以及接著材8，而於各半導 體晶片2之背面2c外周部2d與佈線基板3之上面3a之間形成 有二間2 1。因此，當形成密封樹脂5時，由於亦將用以形 成密封樹脂5之材料填充於各半導體晶片2之背面2c外周部 2d與佈線基板3之上面3a間之空間21，而經過硬化之密封 樹脂5覆蓋各半導體晶片2之表面2b，側面k，以及背面& 之外周部2d ’由此可提高各半導體晶片2與密封樹脂5之密 著性（接著強度），從而可提高半導體裝置lg之可靠性。 又’當形成密封樹脂5時，於用於形成密封樹脂5之材料中 含有之填充料等’易於浸入各半導體晶片2之背面2e外周 2d之下方空間21 ’由此可使填充空間21之密封樹脂5之 105491-971003.doc •48· 1374527 成分比，與其他區域密封樹脂5之成分比均勻化。藉此， 可提高經過硬化之密封樹脂5與各半導體晶片2之密著性 (接著強度），由此可提高半導體裝置1§之可靠性。 (實施形態9) 圖48係作為本發明其他實施形態之半導體裝置^之平面 透視圖（上面圖）。圖49以及圖50係其剖面圖。圖48對應於 上述實施形態1之圖6，且表示有透視密封樹脂5時之半導 體裝置ih之平面透視圖(上面圖）。又，圖49與圖5〇係不同 之剖面。 於上述實施形態1之半導體裝置丨中，於佈線基板3上搭 載有一個半導體晶片2，而於本實施形態之半導體裝置化 中於佈線基板3上搭載有經過積層之複數個半導體晶片 2於此就將2個半導體晶片2進行積層並搭載於佈線基板3 上之例不加以說明，但並非限定於此，可以將2個以上半 導體晶片2進行積層並搭載於佈線基板3上之方式製造半導 體裝置lh。 於本實把形態中，如圖至圖5〇所示，於佈線基板3上 面3a之第1阻焊劑部丨4a上經由接著材8而搭載（接合）半導體 晶片2，進而經由接著材71將其他半導體晶片2，即半導體 晶片7〇搭載（接合）於半導體晶片2之表面2b上》即，於佈線 基板3之上面3a上積層有半導體晶片2以及半導體晶片7〇。 上層側半導體晶片70之平面尺寸（面積）小於下層側半導體 曰曰片2之平面尺寸（面積）。下層側半導體晶片2之複數個電 極2a ’經由複數個接合線4而電性連接於佈線基板3之複數 105491-971003.doc •49 1374527 個連接端子1 5。上層側半導體晶片7〇之祓數個電極7〇a， 經由接合線4而電性連接於半導體晶片2之複數個電極2&及 /或佈線基板3之複數個連接端子15上。而其他構成則大致 與上述實施形態1相同。 於本實施形態中，於接合下層側半導體晶片2之第1阻焊 劑部14a與第2阻焊劑部14b之間’亦存在有並未形成有阻 焊劑層14而露出有基材層11之區域（障壁區域）18，故而於 將半導體晶片2晶片焊接於佈線基板3上時，可防止含有膏 材等之接著材8越過區域18而擴散至第2阻焊劑部141?上。 藉此，可防止接著材8擴散至連接端子15上，由此可提高 接合線4與連接端子丨5間電性連接之可靠性。 “又’於本實施形態'中，下層側半導體晶片2，亦經由接 著材8接合於平面尺寸（面積）小於該半導體晶片2之第1阻焊 劑部14a上。因此，當將下層側半導體晶片2晶片焊接於佈 線基板3之上面3a時，第！阻焊劑部14a以及接著材8不會延 伸（存在）於下層側半導體晶片2之背面2c外周部^之下方， 而於下層側半導體晶片2之背面2e外周部2d與佈線基板3之 上面3a間形成有空間21。因此，於形成密封樹脂$時由 於亦將用以形成密封樹脂5之材料填充於下層側半導體晶 片2之背面2c外周部2d與佈線基板3之上面“間之空間Μ， 且經過硬化之密封樹脂5覆蓋下層側半導體晶片7之表面 2b、側面2e及背面2c外周部2d與上層側半導體晶月表面 以及側面，故而可提高半導體晶片2、7〇與密封樹脂5之密 者性（接著強度），並可提高半導體裝置以之可靠性。又， 10549I-97I003.doc -50- 1374527 當形成密封樹脂5時’用以形成密封樹脂5之材料中所含有 之填充劑等，易於浸入至下層側半導體晶片2之背面。外 周部2d下方之空間21中，故可使填充空間21之密封樹脂5 之成分比與其他區域密封樹脂5之成分比均一化。藉此可 進而提高經過硬化之密封樹脂5與各半導體晶片2之密著性 (接著強度）’因此可提高半導體裝置化之可靠性。 又，於本實施形態中，可藉由將複數個半導體晶片2進 行積層’於此可藉由將其他半導體晶片7〇積層於半導體晶 片2上’而實現半導體裝置小型化（低面積化）。 以上，基於其他實施形態具體說明由本發明者所完成之 發明，但本發明並非限定於上述實施形態者，毋庸置言於 不脫離其精神之範圍内可進行各種變更。 又，本發明可適用於佈線基板上搭載有半導體晶片之各 種半導體封裝形態之半導體裝置，但若適用csp(ChipNext, as shown in Fig. 18, marking is performed, and a mark such as a product number is attached to the surface of the sealing resin 53. For example, a laser mark marked by a laser 36 can be performed, and an ink mark marked by an ink can also be performed. Further, the step of connecting the solder balls 6 of Fig. 17 and the step of marking the steps of Fig. 18 may be reversed. After the marking step of Fig. 18 is performed, the solder ball 6 connecting step of Fig. 17 is performed. Next, as shown in Fig. 19, the upper surface of the sealing resin 5a is attached to the sealing fixing tape 37, and is routed along the cutting area (cutting line) 39 by a cutter blade 38, etc. 105491-971003.doc • 30· 1374527 The substrate 31 and the sealing resin 5a formed thereon are cut (cut), and the respective semiconductor device regions (CSP regions) are cut and separated into individual (singulated) semiconductor devices 1 (CSP). In other words, the wiring board 31 and the sealing resin 5a are cut and divided into the respective semiconductor device regions 32. In this manner, the semiconductor device 1 shown in Fig. 7 can be manufactured by performing dicing and singulation. The wiring substrate 31 cut and separated (divided) in each semiconductor device region 32 corresponds to the wiring tomb 3, and the sealing resin 5a which is cut and separated (divided) in each semiconductor device region 32 corresponds to the sealing resin. 5. Figure 29 is a semiconductor device manufactured as described above! A cross-sectional view of another main portion of the region near the end portion (partially enlarged scraping view), and shows a cross-section of the region different from that of Fig. 4. As described above, since the conductor layer 12 of the wiring substrate 3 (wiring substrate 31) is formed by electrolytic plating, the peripheral portion 11a of the base material layer 11 constituting the wiring substrate 3 (the Ua end portion on the upper surface of the base material layer u) There is a plating wiring 34 between the connection terminal 15 and the connection terminal 15 . In the present embodiment, since the plating wiring 34 is covered by the solder resist layer 14 (the second solder resist portion i4b), the plating wiring 34 does not come into contact with the sealing resin 5. Unlike the present embodiment, when the solder resist layer 14 is not formed on the plating wiring 34, a gold plating layer is formed on the connection terminal 15, and a gold plating layer is formed on the plating wiring 34, so that a sealing resin is formed. After 5 (sealing resin 5a), the electric ore wiring 34 on which the gold plating layer is formed is brought into direct contact with the sealing resin 5. In this case, the adhesion between the sealing resin 5 and the electrolytic gold plating layer is lower than the adhesion between the solder resist layer 14 and the sealing resin 5, so that the adhesion between the plating wiring 34 and the sealing resin 5 is lowered. Since the interface with lower adhesion (the interface between the plating wiring 34 and the sealing resin 5) passes through the singulation portion 105491-971003.doc -31 - 1374527, it will be exposed on the side of the semiconductor device, and thus will result from The interface enters moisture (moisture) and has poor moisture absorption. Due to the poor moisture absorption, peeling due to a decrease in the sealing property of the sealing resin 5 or rust or oxidation of the bonding wire 4 due to moisture may occur, thereby deteriorating the reliability of the semiconductor device. In the case where the conductor layer 12 of the wiring board 3 (wiring board 31) is formed by electrolytic plating in the present embodiment, the electric resistance layer 14 is covered with the solder resist layer 14 (second solder resist portion 14b). This makes it possible to prevent the plating wiring 34 from coming into contact with the sealing resin 5, and it is possible to prevent the interface having a low adhesion from being formed on the semiconductor device side®, thereby suppressing moisture absorption from the side surface of the +conductor device, thereby improving Reliability of semiconductor devices. (Embodiment 2) FIG. 30 is a cross-sectional view showing a principal part of a semiconductor device according to another embodiment of the present invention, and shows a region substantially corresponding to FIG. 4 of the above-described first embodiment. Fig. 31 and Fig. 32 are explanatory circles (main part sectional views) of the wire bonding step of the embodiment. The manufacturing process of the semiconductor device 1b of the present embodiment is substantially the same as that of the above-described first embodiment except for the wire bonding step, and the description thereof will be omitted. The wire bonding step in the manufacturing process of the semiconductor device 113 of the present embodiment will be described. In the first embodiment, 'firstly, one end of the bonding wire 4 is connected (first bonding) to the electrode 2a' of the semiconductor wafer 2, and the other end of the bonding wire 4 is connected to the connection terminal 15 of the wiring substrate 31 (second time) In the present embodiment, 'firstly, one end of the bonding wire 4 is connected (first bonding) to the connection terminal i5 of the wiring substrate 105491-971003.doc • 32· 1374527 plate 31, and the bonding wire 4 is again The terminal is connected (second bonding) to the electrode 2a of the semiconductor wafer 2. In other words, as shown in FIG. 31, the tip end of the bonding wire 4 including gold (Au) or the like which is held by the capillary 41 of the wire bonding apparatus for forming the bonding wire 4 is pressed to the connection of the wiring substrate 31 while applying ultrasonic waves. On the surface of the terminal 15. Subsequently, as shown in Fig. 32, the capillary 41 is lifted upward, and the crucible is moved upward, and the bonding wire 4 is pressed and attached to the surface of the electrode 2a of the semiconductor wafer 2 while the ultrasonic wave is applied, and the bonding wire 4 is cut. Thereby, the connection terminal 15 of the wiring substrate 31 and the electrode 2a of the semiconductor wafer 2 can be electrically connected via the bonding wire 4. The semiconductor device 1b shown in Fig. 30 can be manufactured by performing wire bonding as described above. 33 is different from this embodiment in that it is first connected (one first bonding) to one end of the bonding wire 4 to the electrode 2a of the semiconductor wafer 2, and then the other end of the bonding wire 4 is connected (second bonding) to the wiring substrate. A cross-sectional view of the main part in the case of the connection terminal 15 of 31. As shown in FIG. 33, when one end of the bonding wire 4 is first connected to the electrode 2a of the semiconductor wafer 2, the bonding wire 4 may be located in the capillary 41 when the capillary 41 is moved to the connection terminal 15 for the second bonding. When the connection terminal 15 of the wiring board is brought too close to the semiconductor wafer 2, the bonding wire 4 may be in contact with the semiconductor wafer 2, and in this embodiment, as shown in FIG. 31 and FIG. 32. As shown, first, one end of the bonding wire 4 is connected (first bonding) to the connection terminal 15 of the wiring substrate 31, and the other end of the bonding wire 4 is connected (second bonding) to the electrode 2a of the semiconductor wafer 2. That is, after the connection terminal 15 is first bonded to the wiring substrate 105491-971003.doc -33·1374527, the capillary 41 is lifted upward and moved in the lateral direction, so that the semiconductor wafer 2 is bonded to the electrode for the second time. 2a. For this reason, when the capillary 41 is moved to the electrode 2a of the semiconductor wafer 2 for the second bonding, the bonding wire 4 is not located between the capillary 41 and the semiconductor wafer 2. Therefore, even if the connection terminal 15 of the wiring substrate 31 is close to the semiconductor wafer 2, the bonding wire 4 can be prevented from coming into contact with the semiconductor wafer 2. Thereby, the reliability of the semiconductor device can be improved. Moreover, since the connection terminal 15 of the wiring board 31 can be brought closer to the semiconductor wafer 2, the semiconductor device can be downsized (small area). Further, in the wire bonding step, the first bonding person can reduce the electrode area required for the connection as compared with the second bonding. In the present embodiment, by first connecting one end of the bonding wire 4 (first bonding) to the connection terminal 15 of the wiring board 31, the area of the connection terminal 丨5 can be reduced, so that the second solder resist portion can be obtained. The opening portion 露出9 for exposing the connection terminal 15 of 14b becomes small. In other words, while the ultrasonic wave is applied, the tip end of the bonding wire 4 held in the capillary 41 is pressed and connected to the surface of the connection terminal 15 of the wiring substrate 31 (first bonding), and the capillary 41 is lifted upward, so that the connection can be made. When the terminal 15 is made smaller, the opening portion 19 for exposing the connection terminal 15 of the second solder resist portion 14b can be made small. For example, it is preferable that the length of the connection terminal 15 (the length of the connection terminal 15 in the extending direction) L, 'that is, the length L丨 of the opening portion 19 for exposing the connection terminal 15 of the second solder resist portion 1 is 120 μπι or less (Ljl20 μηι), better 疋100 μηι or less (L丨1〇〇μπι). Thereby, the semiconductor device can be downsized (small area). Further, it is more preferable that the main portion of the cross-sectional view of Fig. 31 and Fig. 32 is formed in advance on the electrode 2a of the semiconductor wafer 2 to form a bump containing gold (Au) 105491-971003.doc -34* 1374527 (protrusion). The electrode, bump 42' and the bonding wire 4 are connected to the bump 42 on the electrode 23 of the semiconductor wafer 2 during the second bonding. Thereby, the connection strength between the bonding wire 4 and the electrode 2a of the semiconductor wafer 2 can be improved. Further, the stress applied to the semiconductor wafer 2 can be reduced when the semiconductor wafer 2 is bonded to the electrode 2a a second time. Further, since the distance between the bonding wire 4 and the semiconductor wafer 2 (the surface side end portion 2f of the semiconductor wafer) can be made large, the fluidity of the sealing resin 5 toward the back surface 2c side of the semiconductor wafer 2 can be made higher than that shown in FIG. The case of wire bonding. (Embodiment 3) Fig. 34 is a cross-sectional view showing a principal part of a semiconductor device 1c according to another embodiment of the present invention. Fig. 35 is a plan perspective view (top view). Fig. 34 corresponds to Fig. 4 of the above-described first embodiment. Further, Fig. 35 corresponds to Fig. 7' of the above-described first embodiment, and shows a plan perspective view of the semiconductor device 1c when the see-through sealing resin 5, the semiconductor wafer 2, and the bonding wires 4 are formed. (Top view), that is, the upper surface of the wiring substrate 3 for the semiconductor device; lc. Further, in Fig. 35, the outer shape of the semiconductor wafer 2 is indicated by a broken line. 35 is a plan view, but for the sake of understanding, the connection from the first solder resist portion 14a, the second solder resist portion 14b, the third solder resist portion 14c, and the opening portion 19 of the second solder resist portion 14b is exposed. Terminal 15 is given a hatch. In the semiconductor device 1c of the present embodiment, the configuration other than the solder resist layer 14 formed on the upper surface 3a of the wiring board 3 is substantially the same as that of the semiconductor device 1 of the above-described first embodiment, and thus the description thereof is omitted here, and the semiconductor device lc is omitted. The solder resist layer 14 formed on the upper surface 3a of the wiring substrate 3 is referred to as 105491-971003.doc -35-1374527. In the above-described first embodiment, the solder resist layer 14 on the upper surface 3a of the wiring board 3 includes: the lower portion of the semiconductor wafer 2! The solder resist portion 14a; the second solder resist portion 141) located on the outer peripheral portion of the upper surface 3a of the wiring board 3, and in the semiconductor device 1c of the present embodiment, the solder resist layer 14 on the upper surface 3a of the wiring substrate 3 is as shown in FIG. As shown in FIG. 35, the first solder resist portion 14a located under the semiconductor wafer 2, the second solder resist portion 14b located on the outer peripheral portion of the upper surface 3a of the wiring board 3, and the first solder resist portion 14a and the second portion are provided. The third solder resist portion 14c is formed between the solder resist portions 14b so as to surround the first solder resist portion 14a. Between the first solder resist portion 14a and the third solder resist portion, there is a region where the solder resist layer 14 is not formed and the base material layer 1 (and the grapefruit wiring including the conductor layer 12) is exposed (barrier region) In the case of i8a, between the third solder resist portion 14c and the second solder resist portion 14b, a region where the base material layer (and the lead wiring including the conductor layer 12) is not exposed is formed without forming the solder resist layer 14 (barrier) Area) 18b. The semiconductor wafer 2 is bonded (joined, connected, fixed, and disposed) to the first solder resist portion 14a via the bonding material 8. The second solder resist portion 14b includes an opening 19 for exposing the connection terminal 15. Similarly to the first embodiment, the planar size (area) of the first solder resist portion 14a is smaller than the planar size (area) of the semiconductor wafer 2. Therefore, when the semiconductor wafer 2 is mounted, the first solder resist portion 14a does not extend under the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2. In the present embodiment, the first solder resist portion 14a of the semiconductor wafer 2 is bonded to the upper surface 3a of the wiring board 3 via the bonding material 8 on the upper surface 3a of the wiring board 3; The third solder resist portion 14c around the flux portion 14a (outside 105491-971003.doc - 36 - 1374527 weeks); the second solder resist portion 14c (outer periphery) is provided, and the second terminal of the connection terminal 15 is exposed from the opening portion 19 Solder resist portion 141). Between the first solder resist portion 14a and the third solder resist portion 14c and between the third solder resist portion i4c and the second solder resist portion 14b, the base material layer 11 is exposed without forming the solder resist layer i4. In the region (the barrier regions 8a and 18b), when the semiconductor wafer 2 is bonded to the wiring substrate 3, the solder resist layer 14 is not provided between the first solder resist portion i4a and the third solder resist portion 14c but the substrate is exposed. In the region of the layer j (the barrier region) 18a, it is possible to prevent the bonding material 8 containing the paste or the like from spreading over the region 18a and diffusing to the third solder resist portion 14c, and further, even if the bonding material 8 containing the paste or the like crosses the region 18a and diffused to the third solder resist portion 14c' may be provided by the third solder resist portion 14c and the second solder resist portion i, and the portion of the layer 14 is exposed but the substrate layer is exposed. (Baffle region) 18b prevents the adhesive material 8 containing the paste material from diffusing over the second solder resist portion over the region i8b. Thereby, it is possible to more reliably prevent the adhesive material 8 from diffusing onto the connection terminal 15, thereby making it more reliable Improve the reliability of the electrical connection between the bonding wire 4 and the connection terminal 15. Further, even if the flow A relatively high-quality paste-type backing material (joining material) is used as the backing material 8, and the adhesive material 8 containing the paste material is prevented from diffusing to the bonding terminal 15, so that the paste which is relatively inexpensive compared to the crystal grain bonding film can be used. The type of the secondary material is used as the adhesive material 8, and it is advantageous to reduce the manufacturing cost of the semiconductor device. _ (Embodiment 4) FIG. 36 is a cross-sectional view of a main portion of a semiconductor device id according to another embodiment of the present invention, and corresponds to the above embodiment. Fig. 4 is a view showing the thickness of the mth solder portion 14a of the upper surface of the wiring board 3 of the semiconductor device "I05491-971003.doc.37·1374527" and the thickness of the second resistive agent portion (10). In the semiconductor device ratio of the present embodiment, the thickness T| of the solder resist portion 14a of the upper surface 3a of the wiring board 3 is thicker than the thickness Τ3 of the second solder resist portion i4b (ΊΊ>Τ3). The above-described embodiment is substantially the same, and the description thereof is omitted here. In the present embodiment, as shown in FIG. 36, the third substrate having the planar size smaller than the semiconductor crystal 2 and the semiconductor wafer 2 bonded thereto via the bonding material 8 is formed. The thickness T1 of the flux portion 14a is thicker than the thickness of the second solder resist portion 14b provided around the outer periphery of the solder resist portion 14a (outer periphery), and the wiring substrate 3' such as the substrate layer 11 When the solder resist layer 14 is formed on the upper surface 11a, the solder resist layer is applied twice (multiple coating, plural printing), so that the second solder resist portion Mb is formed of the solder resist layer of the first layer, whereby the solder resist layer is relatively Thin, and the first solder resist portion 14a is formed by the first layer and the second layer of the solder resist layer (the buildup film), thereby making it relatively thick, whereby preparation (manufacturing) can be performed. In the present embodiment, since the thickness L of the first solder resist portion 14a is thicker than the thickness Τ3 of the second solder resist portion 14b (Τι>3), the thickness of the first solder resist portion _ 14a is smaller than that of the first solder resist portion 14a. When the thickness of the solder resist portion 14b is the same as that of (3丨=Τ3), after the semiconductor wafer 2 is soldered to the wiring substrate 3, the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3 can be formed. The space 21 formed between the heights H] is larger in the height direction. Therefore, when the sealing resin 5 is formed, the filler or the like contained in the material for forming the sealing resin 5 can be easily immersed by the space 2 1 below the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2, and thus can be easily immersed. The component ratio of the sealing resin 5 of the filling space 21 is made more uniform than the component ratio of the sealing resin 5 of the other regions. By the use of 105491-971003.doc -38- 1374527, the hardness of the cured sealing resin 5 can be further improved, and the semiconductor property can be further improved. (Embodiment 5) Fig. 37 is a plan perspective view (top view) of a semiconductor device according to another embodiment of the present invention, and Fig. 38 is a plan perspective view of a semiconductor device as another embodiment of the present invention (above And corresponding to Fig. 7 of the above-described first embodiment. Therefore, in FIG. 37 and FIG. 38, a plan view (top view) of the semiconductor device in which the see-through sealing resin 5, the semiconductor wafer 2, and the bonding wires 4 are formed, that is, the upper surface of the wiring substrate 3 used in the semiconductor device of the present embodiment is shown. . Further, in Figs. 37 and 38, the outer shape of the semiconductor wafer 2 is indicated by a broken line. 37 and 38 are plan views. However, for the sake of understanding, the first solder resist portion 14a' the second solder resist portion 14b and the connection terminal 15 exposed from the opening 19 of the second solder resist portion 14b are provided. Shadow line. In the semiconductor device of the present embodiment, the configuration of the second solder resist portion 14b formed on the upper surface 3a of the wiring board 3 is substantially the same as that of the semiconductor device 1 of the first embodiment, and thus the description thereof is omitted. The pattern shape of the second solder resist portion 14b formed on the upper surface 3a of the wiring board 3 of the semiconductor device of the present embodiment will be described. In the present embodiment, the second solder resist portion is formed on the inner peripheral portion of the second solder resist portion 14b (the fourth solder resist portion 14b facing the first solder resist portion 14a and the second solder resist portion facing the four sides of the semiconductor wafer 2). Four sides of 14b) are formed with a comb-shaped (concave-convex) pattern. In other words, the second solder resist portion 14b includes a first portion 61 formed on the outer peripheral portion of the surface 3a of the wiring substrate 3, 105491 · 971003.doc • 39 · 1374527, and having an opening (4) for exposing the connection terminal 15; The second portion 61 extends from the second portion 61 to a plurality of second portions 62 in the direction of the m-th flux portion 14a (semiconductor wafer 2). Containing (four) patterns <The second solder resist portion (10) has a film thickness of substantially the same, and the second solder resist 4 14b is formed by the first portion 61 and the plurality of second portions 62, and is formed in the second solder resist portion 14b. A comb pattern (solder resist pattern) is provided on the four sides of the circumference. Thus, when the sealing resin 5 is formed by the transfer demolding step or the like, it is easy to be applied from the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2 and the wiring substrate 3 Since the air is discharged from the space 21 between the 3a, the fluidity of the material for forming the sealing resin 5 is enhanced, so that the filling property of the sealing resin to the space 21 can be further improved. Therefore, the adhesion (adhesive strength) between the semiconductor wafer 2 and the sealing resin 5 can be further improved, so that the reliability of the semiconductor device can be further improved. Further, as shown in FIG. 37, when the second portion 62 of the second solder resist portion 14b does not extend below the semiconductor wafer 2, when the semiconductor wafer 2 is soldered to the upper surface 3a of the wiring substrate 3, the semiconductor can be further enlarged. The space 21 formed between the outer peripheral portion 2d of the back surface 2c of the wafer 2 and the upper surface 3a of the wiring substrate 3, and when the sealing resin 5 is formed, the filler or the like can be easily immersed under the outer peripheral portion 2d of the back surface 2c of the semiconductor wafer 2. In space 21. Thereby, the composition ratio of the sealing resin 5 in the filling space 21 can be made more uniform than the composition ratio of the sealing resin 5 in the other regions. Further, as shown in FIG. 38, the second portion 62 of the second solder resist portion 14b may be extended below the semiconductor wafer 2. Therefore, in this case, the connection terminal 15 can be further brought closer to the side of the semiconductor wafer 2, thereby 105491-971003, doc • 40- 1374527 Conducive to miniaturization (small area) of semiconductor devices. (Embodiment 6) FIG. 39 is a cross-sectional view (partially enlarged cross-sectional view) of a main portion in the vicinity of an end portion of a semiconductor device le according to another embodiment of the present invention, and corresponds to FIG. 4 of the first embodiment. 4 is a plan perspective view (top view) of the semiconductor device le when the resin is seen through the sealing resin 5, which corresponds to FIG. 6 of the above-described first embodiment. FIG. 41 is a perspective view of the sealing resin 5, the semiconductor wafer 2, and the bonding wires 4. A plan view (top view) of the semiconductor device le, that is, a top view of the wiring substrate 3 for the semiconductor device le, corresponds to the above embodiment! Figure 7. 42 to 44 are plan views (top views) schematically showing an example of a manufacturing procedure of the wiring substrate 31 used in the manufacture of the semiconductor device le of the present embodiment, and correspond to FIG. 21 to FIG. twenty three. Further, the shape of the semiconductor wafer 2 is indicated by a broken line in Fig. 41. Further, Fig. 41 is a plan view, but for ease of understanding, the opposite! The solder resist portion 14a, the second solder resist portion 14b, and the connection terminal 15 exposed from the second solder resist portion 14b are given a hatching. The upper surface 3a and the lower surface of the wiring substrate 3 of the semiconductor device 1 in the first embodiment. The conductor layer 12 of 3b is mainly formed by electrolytic plating. In the present embodiment, the conductor layer 12 of the upper surface 3a and the lower surface 3b of the wiring board 3 of the semiconductor device le is not subjected to electrolytic plating, but is used without Formed by electrolytic bond method. Further, in the above-described first embodiment, the second solder resist portion 14b' is formed on the outer peripheral end portion of the upper surface 3a of the wiring board 3 of the semiconductor device 1, and in the semiconductor device le of the present embodiment, as shown in FIGS. 39 to 41. The second solder resist portion 14b (solder resist layer 14) is not formed on the side of the outer peripheral portion 10549l-971003.doc 41 1374527 of the connection terminal 15 on the upper surface 3a of the wiring substrate 3, and the upper surface of the wiring substrate 3 is 3a. In the outer peripheral end portion, the base material layer 11 of the wiring board 3 and the sealing resin 5 are in a state of being in contact (contact). Since the other configuration is substantially the same as that of the above-described embodiment 1, the description thereof is omitted here. First, the manufacturing steps of the wiring board 31 used in the manufacture of the semiconductor device le of the present embodiment will be described. The wiring substrate 31 can be manufactured, for example, in the following manner. An electroless copper plating layer is formed on the upper surface 11 a of the insulating base material layer 11 as a core material and on the lower surface by electroless plating (no electric field plating), and the electroless copper plating layer is formed by etching or the like. Patterned. In the first embodiment, the electrolytic copper plating layer is formed on the electroless copper plating layer. In the present embodiment, the thick electroless copper plating layer is formed in advance, and the electrolytic copper plating layer is not formed. The conductor layer 12 of the wiring substrate 31 (wiring substrate 3) can be formed by the electroless copper plating layer (copper layer). Fig. 42 shows a state in which the via hole conductor pattern 33 and the connection terminal 15 (conductor pattern used) are formed on the base material layer 11 by an electroless copper plating layer (conductor layer 12). The connection terminal 15 and the conductor pattern 33 are electrically connected by an extraction wiring (not shown) including an electroless copper layer (conductor layer 12) formed on the upper surface 11a of the base material layer 11. Further, although not shown, a pad 16 is formed on the lower surface of the base material layer 11 by an electroless copper plating layer (conductor layer 12). Further, in the present embodiment, since the electrolytic plating method is not used, the plating wiring (power supply line) 34 as in the first embodiment described above is not formed on the upper surface 11a of the base material layer 11. Next, as shown in FIG. 43, a through hole (channel, passage, pass) 17 is formed in the opening of the base material layer 11. The opening portion 17 is formed on the inner side of the through-hole conductor pattern 33 105491-971003.doc • 42·1374527. Next, an electroless copper plating layer is formed on the side wall of the opening portion 17 by electroless plating. The conductor layer 12 on the side wall of the opening 17 is formed by the electroless copper plating layer formed on the side wall of the base material layer 11. Subsequently, as shown in Fig. 44, a solder resist layer 14 is formed on the upper surface 11a of the substrate layer 11 and on the lower surface by a printing method or the like to fill the inside of the opening portion 17. Thereby, the i-th solder resist portion 14a and the second solder resist portion 14b are formed on the upper surface 1 la of the base material layer 11. On the upper surface lia of the base material layer 11, the connection terminal 15 is exposed from the opening 19a of the solder resist layer 14, and the pad 16 is exposed from the opening of the solder resist layer 14 under the substrate layer u. The opening portion 19a for exposing the connection terminal 15 is formed on the second solder resist portion 14b, and the dicing region 39 is formed so as to traverse the center of the second solder resist portion 1 opening portion 19a. Next, on the upper surface 11a of the base material layer 11 and the exposed portions of the electroless bond copper layer on the lower surface (i.e., the connection terminal 15 and the pad 16), an electroless nickel plating layer is sequentially formed by electroless plating. Electrolytic palladium layer and gold plating layer. Thereafter, the base material layer 11 can be subjected to outer shape processing (cutting) as needed to form the wiring substrate 31. The wiring device 3 manufactured in this manner can be used to manufacture the semiconductor device le' of the present embodiment. However, since the manufacturing steps are substantially the same as those of the above-described embodiment 1, the description thereof will be omitted. In the present embodiment, as described above, the conductor layer 12 of the wiring board 3 (wiring board 31) is formed by electroless plating instead of electrolytic electrowinning. Namely, the connection terminal 15 or the pad 16 of the wiring substrate 3 is formed by electroless plating without using the electrolytic ore method. Since the electrolytic plating method is not used to form the conductor layer 12, the upper surface 3a of the wiring board 3 (the upper surface 31a of the wiring substrate 105491-97I003.doc -43 - 1374527 31) is not formed as in the above-described first embodiment. Plating wiring (power supply line) 34. Further, in the present embodiment, as described above, the cutting region 39 is transversely cut to expose the center of the opening 19a of the connection terminal 15, so that it is not in the outer peripheral side region of the connection terminal 15 on the upper surface 3a of the wiring board 3. The second solder resist portion 14b is formed. That is, in the upper surface 3a of the wiring board 3, the second solder resist portion 14b (solder resist layer 14) does not extend from the connection terminal 15 to the end portion of the wiring board 3. Therefore, the base material layer U' of the wiring board 3 is exposed at the outer peripheral end portion of the upper surface 3a of the wiring board 3, and the exposed base material layer 抵 can be pressed against the sealing tree. In the present embodiment, the substrate layer u and the sealing resin 5 are in a closed state because the plating wiring is not present at the peripheral end portion of the upper surface 3a of the wiring board 3, so that the interface having low adhesion is not formed. On the side of the semiconductor device, the reliability of the semiconductor device can be improved. . Further, since the second solder resist portion (10) is not formed in the outer peripheral side region of the connection terminal 15 on the upper surface 3a of the wiring board 3, the capillary can be prevented when the connection terminal 15 is wire-bonded (corresponding to the capillary contact In the second solder resist portion 14b. Therefore, the bonding of the structure to the connection terminal 15 is performed, so that it can be entered into the _at. ie -3⁄4., and the reliability of the connection between the connector 15 and the bonding wire 4 is ensured. Moreover, it is also possible to reduce the area of the . . . ' ' ' ' ' ' ' ' ' ' 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Double welding or triple welding "Multiple coal joints (Example 7) FIG. 45 is a partial cross-sectional view of another embodiment of the present invention and corresponds to: conductor device] f. FIG. 39 of the principal embodiment 6 105491-971003.doc • 44 - In the semiconductor device le7} of the above-described sixth embodiment, the conductor layer (10) on the upper surface 3a and the lower surface 3b of the wiring board 3 of the semiconductor device is formed by electroless plating instead of electrolytic plating. And in this In the semiconductor device if, in the same manner as the semiconductor device 1 of the above-described embodiment i, the upper surface 33 and the lower surface of the wiring substrate 3 of the semiconductor device 1 are mainly formed by an electrolytic method (or a combination of electrolytic plating and no electric field f plating). The conductor layer 12 is different from the semiconductor device of the above-described embodiment, and the semiconductor device If of the present embodiment does not form the plating wiring (power supply line) 34 on the upper surface 11a of the base material layer 11, but It is formed on the lower surface Iib of the base material layer u. The other configuration and manufacturing steps of the semiconductor device If in the present embodiment are substantially the same as those of the above-described semiconductor device le. Therefore, a plan view of the semiconductor device If when the resin 5 is seen through is sealed (above) The same as the above-described FIG. 40 of Embodiment 6, the perspective view (top view) of the semiconductor device If when the sealing resin 5, the semiconductor wafer 2, and the bonding wires 4 are seen, that is, the upper surface of the wiring substrate 3 in the semiconductor device If The figure is the same as that of Fig. 41 of the above-described sixth embodiment. That is, the semiconductor device lf of the present embodiment also includes the above-described embodiment. The pattern of the first solder resist layer 14a and the second solder resist portion 14b) of the solder resist layer of the semiconductor device le is the same. As a result, in the semiconductor device If of the present embodiment, the second solder resist portion 14b is not formed in the outer peripheral side region of the connection terminal 15 of the upper surface 3a of the wiring board 3 in the same manner as the semiconductor device of the sixth embodiment. (The solder resist layer 14), and the base material layer 11 of the wiring board 3 and the sealing resin 5 are in a state of being in contact (contact) on the outer peripheral end portion of the upper surface 3a of the wiring board 3. In the present embodiment, as in the sixth embodiment, the second solder resist portion 14b is not formed in the outer peripheral side region of the connection terminal 15 of the upper surface 3a of the substrate 3 on the wiring 105491-971003.doc •45·1374527. Therefore, it is possible to connect the terminals. When the wire bonding is performed, the capillary (corresponding to the capillary 41) is prevented from coming into contact with the second solder resist portion 14b. Therefore, the wire bonding of the connection terminal 15 can be stably performed, so that the reliability of electrically connecting the connection terminal 15 and the bonding wire 4 can be improved. Further, since the area of the connection terminal 15 can be reduced, it is advantageous to reduce the size (small area) of the semiconductor device. Further, it is also possible to easily perform a plurality of welding (e.g., double welding or triple welding) in which a plurality of bonding wires 4 are connected to one connecting terminal 15. Further, in the present embodiment, the conductor layer 12 of the upper surface 3a and the lower surface 3b of the wiring board 3 is mainly formed by electrolytic plating, but the plating wiring (power supply line) 34 for electrolytic plating is not formed on the substrate layer. On the upper Ua of u, it is formed on the lower ub of the substrate layer n. Therefore, an electroplated wiring (power supply line) 34 is not formed on the upper surface 3a (the upper surface 31a of the wiring substrate 31) of the wiring board 3. Further, in the present embodiment, as described in the above-described embodiment 6, the cutting region 39 is transversely cut to expose the opening of the connection terminal 15. Since the center of the crucible 19a is formed, the second solder resist portion 14b is not formed in the outer peripheral side region of the connection terminal 3 of the upper surface 3a of the wiring board 3. In other words, in the upper surface 3a of the wiring board 3 of the semiconductor device If, the second solder resist portion 14b (solder resist layer 14) does not extend from the connection terminal 15 to the end portion of the wiring board 3. Therefore, the base material layer 11 of the wiring board 3 is exposed at the outer peripheral end portion of the upper surface 3a of the wiring board 3, and the exposed base material layer n can be adhered to the sealing resin 5. In the present embodiment, since the plating wiring is not present in the outer peripheral end portion of the upper surface 3& of the wiring board 3, and the base material layer u and the sealing resin 5 are densely 105491-971003.doc -46-1374527, The interface with low adhesion is not formed on the side of the semiconductor device, so the reliability of the semiconductor device can be improved. (Embodiment 8) Fig. 46 is a plan perspective view (top view) of a semiconductor device 1g according to another embodiment of the present invention. Fig. 47 is a cross-sectional view thereof. (4) Corresponding to Fig. 6 of the above-described first embodiment, and showing a semiconductor device in which the sealing resin 5 is seen. Plane perspective view (above). Fig. 47 corresponds to Fig. 3' of the above-described real (fourth) state, and a cross section taken along line B-B of Fig. 46 substantially corresponds to Fig. 47. In the semiconductor device of the first embodiment, a semiconductor wafer 2 is mounted on the wiring board 3, and the semiconductor device of the embodiment is used. A plurality of semiconductor wafers 2 are mounted on the wiring board 3. Here, an example in which two semiconductor wafers 2 are mounted will be described. However, the present invention is not limited thereto, and two or more semiconductor wafers 2 may be mounted on the wiring board 3 to manufacture a semiconductor device 1 g ^ in the present embodiment. The upper surface 3a of the substrate 3 is formed with a first solder resist portion 14a that bonds the semiconductor wafer 2 to the upper surface 3a of the wiring substrate 3 via the bonding material 8, and a second solder resist portion 14b that is provided on the first and solder portion 14a. In the periphery (outer circumference), the connection terminal 15 is exposed from the opening portion 19, but the first solder resist portion 14a having the same number as the number of the semiconductor wafers 2 mounted on the wiring board 3 is formed on the upper surface 3a of the wiring board 3. For example, When two semiconductor wafers 2 are mounted on the wiring board 3 as shown in FIG. 46 and FIG. 47, the two first solder resist portions 14a are formed on the upper surface 3a of the wiring board 3, and are respectively formed via the bonding material 8. The semiconductor wafer 2 is bonded to the first solder resist portion 14a. The plurality of electrodes 2a' of the plurality of semiconductor wafers 2 are connected to the plurality of wiring substrates 3 via a plurality of bonding wires 4 and electrically I05491-971003.doc • 47-1374527 Connect terminal 丨5. The other configuration is substantially the same as that of the first embodiment. In the present embodiment, the solder resist layer is not formed between the solder portion 14a and the second solder resist portion 14b. 14. However, when the semiconductor wafer 2 is bonded to the wiring board 3, the bonding material 8 containing the paste or the like is prevented from spreading over the region 18 and diffusing to the second solder resist. On the Mb. Thereby, the bonding of the bonding material 8 to the connection terminal 15 can be prevented, so that the reliability of the electrical connection between the bonding wire 4 and the connection terminal 15 can be improved. Further, in the present embodiment, each of the semiconductor wafers 2 is also bonded to the first solder resist portion 1 having a planar size (area) smaller than the semiconductor wafer via the bonding material 8 to be blunt. Therefore, when the semiconductor wafer 2 is soldered to the upper surface 3a of the wiring board 3, the first solder resist portion 14a and the bonding material 8 do not extend (be present) under the outer peripheral portion 2d of the back surface 2c of each semiconductor wafer 2. Two spaces 21 are formed between the outer peripheral portion 2d of the back surface 2c of each semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3. Therefore, when the sealing resin 5 is formed, the material for forming the sealing resin 5 is filled in the space 21 between the outer peripheral portion 2d of the back surface 2c of each semiconductor wafer 2 and the upper surface 3a of the wiring substrate 3, and the cured sealing resin is used. 5 covering the surface 2b, the side surface k, and the back surface & outer peripheral portion 2d' of each of the semiconductor wafers 2, thereby improving the adhesion (adhesive strength) of each of the semiconductor wafers 2 and the sealing resin 5, thereby improving the semiconductor device lg reliability. Further, when the sealing resin 5 is formed, the filler or the like contained in the material for forming the sealing resin 5 is easily immersed in the lower space 21' of the outer periphery 2d of the back surface 2e of each of the semiconductor wafers 2, thereby sealing the filling space 21. Resin 5 105491-971003.doc • 48· 1374527 The composition ratio is uniform with the composition ratio of the sealing resin 5 in other regions. Thereby, the adhesion (adhesive strength) between the cured sealing resin 5 and each of the semiconductor wafers 2 can be improved, whereby the reliability of the semiconductor device 1 can be improved. (Embodiment 9) Fig. 48 is a plan perspective view (top view) of a semiconductor device according to another embodiment of the present invention. 49 and 50 are cross-sectional views thereof. Fig. 48 corresponds to Fig. 6 of the above-described first embodiment, and shows a plan perspective view (top view) of the semiconductor device ih with the see-through sealing resin 5. Further, Fig. 49 and Fig. 5 are different cross sections. In the semiconductor device of the first embodiment, one semiconductor wafer 2 is mounted on the wiring board 3, and in the semiconductor device of the embodiment, a plurality of laminated semiconductor wafers 2 are mounted on the wiring board 3 In the example in which the two semiconductor wafers 2 are laminated and mounted on the wiring board 3, the present invention is not limited thereto, and the semiconductor device can be manufactured by laminating two or more semiconductor wafers 2 and mounting them on the wiring board 3. Lh. In the present embodiment, as shown in FIG. 5A, the semiconductor wafer 2 is mounted (bonded) to the first solder resist portion 4a of the upper surface 3a of the wiring board 3 via the bonding material 8, and further via the bonding material 71. The other semiconductor wafer 2, that is, the semiconductor wafer 7 is mounted (joined) on the surface 2b of the semiconductor wafer 2, that is, the semiconductor wafer 2 and the semiconductor wafer 7 are laminated on the upper surface 3a of the wiring substrate 3. The planar size (area) of the upper-side semiconductor wafer 70 is smaller than the planar size (area) of the lower-side semiconductor wafer 2. The plurality of electrodes 2a' of the lower-side semiconductor wafer 2 are electrically connected to the plurality of wiring boards 3 via a plurality of bonding wires 4, 105491-971003.doc • 49 1374527 connection terminals 15 . The plurality of electrodes 7〇a of the upper semiconductor wafer 7 are electrically connected to the plurality of electrodes 2& and/or the plurality of connection terminals 15 of the wiring substrate 3 via the bonding wires 4. The other configuration is substantially the same as that of the first embodiment. In the present embodiment, the region between the first solder resist portion 14a and the second solder resist portion 14b of the lower-side semiconductor wafer 2 is also formed, and the substrate layer 11 is exposed without forming the solder resist layer 14. (Block area) 18, when the semiconductor wafer 2 is wafer-bonded to the wiring board 3, it is possible to prevent the bonding material 8 containing the paste or the like from passing over the region 18 and diffusing to the second solder resist portion 141. Thereby, it is possible to prevent the adhesive material 8 from being diffused onto the connection terminal 15, whereby the reliability of electrical connection between the bonding wire 4 and the connection terminal 5 can be improved. In the present embodiment, the lower-side semiconductor wafer 2 is also bonded to the first solder resist portion 14a having a planar size (area) smaller than the semiconductor wafer 2 via the bonding material 8. Therefore, when the lower-side semiconductor wafer is to be used When the wafer is soldered to the upper surface 3a of the wiring board 3, the first solder resist portion 14a and the bonding material 8 are not extended (present) under the outer peripheral portion 2b of the lower-side semiconductor wafer 2, and the lower-side semiconductor wafer 2 is formed. A space 21 is formed between the outer peripheral portion 2d of the back surface 2e and the upper surface 3a of the wiring board 3. Therefore, when the sealing resin $ is formed, the material for forming the sealing resin 5 is also filled in the outer peripheral portion of the back surface 2c of the lower-side semiconductor wafer 2. 2d and the space between the upper surface of the wiring board 3, and the cured sealing resin 5 covers the surface 2b of the lower-side semiconductor wafer 7, the side surface 2e and the back surface 2c outer peripheral portion 2d, and the upper-layer semiconductor crystal moon surface and the side surface. The compactness (adequate strength) of the semiconductor wafers 2, 7 and the sealing resin 5 is improved, and the reliability of the semiconductor device can be improved. Further, when a sealing resin 5 is formed, the filler or the like contained in the material for forming the sealing resin 5 is easily immersed in the back surface of the lower-side semiconductor wafer 2. In the space 21 below the outer peripheral portion 2d, the component ratio of the sealing resin 5 in the filling space 21 can be made uniform to the component ratio of the sealing resin 5 in the other region. Thereby, the adhesion (adhesive strength) of the cured sealing resin 5 to each of the semiconductor wafers 2 can be further improved, so that the reliability of semiconductor device formation can be improved. Further, in the present embodiment, it is possible to reduce the size (lower area) of the semiconductor device by stacking a plurality of semiconductor wafers 2 by stacking the other semiconductor wafers 7 on the semiconductor wafer 2. The invention made by the inventors of the present invention has been described in detail with reference to the accompanying drawings. However, the invention is not limited thereto, and various modifications may be made without departing from the spirit and scope of the invention. Further, the present invention can be applied to a semiconductor device in various semiconductor package forms in which a semiconductor wafer is mounted on a wiring board, but if csp (Chip is applied)

Package)般之小型半導體封裝形態之半導體裝置則效果 更為顯著。 又，於上述實施形態1至9中，於佈線基板3上面3a之阻 焊劑層14之第1阻焊劑部14a與第2阻焊劑部Mb之間，設有 並未形成有阻焊劑層14而露出有基材層丨丨之區域（障壁區 域）18，但亦可設置阻焊劑層14之凹部（槽部）而代替露出有 基材層11之區域18 »即，於區域1 8中，亦可以薄於第i以 及第2阻焊劑部Ma、14b之方式殘存（存在）阻焊劑層η，且 該情形亦包含於本發明中。如此般，亦於區域18中較薄 殘存有阻焊劑層14，並於佈線基板3上面3a之阻焊劑層Μ I0549I-97I003.doc 51 1374527The semiconductor device in the form of a small semiconductor package is more effective. Further, in the above-described first to ninth embodiments, the solder resist layer 14 is not formed between the first solder resist portion 14a and the second solder resist portion Mb of the solder resist layer 14 on the upper surface 3a of the wiring board 3 The region (barrier region) 18 of the substrate layer is exposed, but the recess (groove portion) of the solder resist layer 14 may be provided instead of the region 18 of the substrate layer 11 exposed, that is, in the region 18, The solder resist layer η may remain (present) in a manner thinner than the i-th and second solder resist portions Ma, 14b, and this case is also included in the present invention. In this manner, the solder resist layer 14 remains on the thinner region 18, and the solder resist layer on the upper surface of the wiring substrate 3 is ΜI0549I-97I003.doc 51 1374527

中，藉由凹凸而設有第1阻焊劑部14a(凸部）、第2阻焊劑部 14b(凸部）’及該等間之凹部（與上述區域18相對應之位置 凹部）之情形時，亦可獲得大致與上述實施形態丨至9同樣 之效果。其中，如上述實施形態1至9般，由於於第丨阻焊 劑部14a與第2阻焊劑部14b間之區域18中露出有基材層u 之情形者，較之於區域18較薄殘存有阻焊劑層丨4之情形 者，可進一步加深形成於第丨阻焊劑部14a與第2阻焊劑部 14b間之凹部（槽部）深度，故而於將半導體晶片2晶片焊接 於佈線基板3上後，可進一步確實防止接著材8擴散至第2 阻焊劑部14b上或連接端子15上’因而可使提高接合線續 連接端子15間電性連接之可靠性之效果增大。 [產業上之可利用性] 本發明可適用於佈線基板上搭載有半導體晶片之半導體 裝置以及其之製造技術。 【圖式簡單說明】In the case where the first solder resist portion 14a (convex portion), the second solder resist portion 14b (convex portion)', and the recesses between the portions (the recesses corresponding to the region 18) are provided by the unevenness Also, effects similar to those of the above-described embodiments 丨 to 9 can be obtained. In the case of the above-described first to ninth embodiments, the substrate layer u is exposed in the region 18 between the second solder resist portion 14a and the second solder resist portion 14b, and is thinner than the region 18. In the case of the solder resist layer 4, the depth of the recess (groove portion) formed between the second solder resist portion 14a and the second solder resist portion 14b can be further deepened, so that after the semiconductor wafer 2 is soldered to the wiring substrate 3, Further, it is possible to surely prevent the adhesive material 8 from being diffused onto the second solder resist portion 14b or the connection terminal 15, so that the effect of improving the reliability of the electrical connection between the bonding wires continued to connect the terminals 15 can be increased. [Industrial Applicability] The present invention is applicable to a semiconductor device in which a semiconductor wafer is mounted on a wiring substrate and a manufacturing technique therefor. [Simple description of the map]

圖1係本發明一實施形態之半導體裝置之上面圖。 圖2係圖1之半導體裝置之下面圖。 圖3係圖1之半導體裝置之剖面圖。 圖4係圖i之半導體裝置之主要部分剖面圖。 圖5係圖1之半導體裝置之側面圖。 圖 圖6係透視密封樹脂時之圖！中的半導體裝置之平面透視 以及接合線時之圖1中 圖7係透視密封樹脂、半導體晶片 的半導體裝置之平面透視圖。 105491-971003.doc •52- 1374527 圖8係第1比較例之半導體裝置之主要部分剖面圖。 圖9係第2比較例之半導體裝置之主要部分剖面圖。 圖10係第3比較例之半導體裝置之主要部分剖面圖。 圖11係本發明之其他實施形態之半導體裝置之主要部、 剖面圖。 圖12係圖11之半導體裝置之平面透視圖。 圖13係作為本發明一實施形態之半導體裝置之製造牛 中之剖面圖。 /驟 圖14係繼續圖13之半導體裝置製造步驟中之剖面圖 圖15係繼續圖14之半導體裝置製造步驟中之剖面圖 圖16係繼續圖15之半導體裝置製造步驟中之剖面圖 圖17係繼續圖16之半導體裝置製造步驟中之剖面圖。 圖18係繼續圖17之半導體裝置製造步驟中之剖面圖。 圖19係繼續圖18之半導體裝置製造步驟中之剖面圖。 圖20係繼續圖19之半導體裝置製造步驟中之剖面圖。 圖21係表示佈線基板製造步驟之平面圖。 圖22係繼續圖21之佈線基板製造步驟中之平面圖。 圖23係繼續圖22之佈線基板製造步驟中之平面圖。 圖24係作為本發明一實施形態之半導體裝置製造步驟中 之主要部分剖面圖。 圖25係作為本發明一實施形態之半導體裝置製造步驟中 之平面圖。 圖26係打線接合步驟之說明圖。 圖27係打線接合步驟之說明圖。 105491-971003.doc -53- 1374527 圖28係作為本發明—實施形態之半導體裝置製造步驟中 之主要部分剖面圖 圖29係作為本發明一實施形態之半導體裝置之其他主要 部分剖面圖。 圖30係作為本發明其他實施形態之半導體裝置之主要部 分剖面圖。 圖3 1係打線接合步驟之說明圖。 圖32係打線接合步驟之說明圖。 圖33係打線接合步驟之說明圖。 圖34係作為本發明其他實施形態之半導體裝置之主要部 分剖面圖。 圖35係圖34之半導體裝置之平面透視圖。 圖36係作為本發明其他實施形態之半導體裝置之主要部 分剖面圖。 圖37係作為本發明其他實施形態之半導體裝置之平面透 視圖。 圖3 8係作為本發明其他實施形態之半導體裝置之平面透 視圖。 圖39係作為本發明其他實施形態之半導體裝置之主要部 分剖面圖。 圖40係圖39之半導體裝置之平面透視圖。 圖41係圖39之半導體裝置之平面透視圖。 圖42係表示用於圖39之半導體裝置製造中的佈線基板製 造步驟之平面圖。 105491-971003.doc •54· 1374527 圖43係繼續圖42之佈線基板製造步驟中之平面圖。 圖44係繼續圖43之佈線基板製造步驟中之平面圖。 圖45係作為本發明其他實施形態之半導體裝置之主要部 分剖面圖。 圖46係作為本發明其他實施形態之半導體裝置之平面透 視圖® 圖47係圖46之半導體裝置之剖面圖。 圖48係作為本發明其他實施形態之半導體裝置之平面透 視圖。 圖49係圖48之半導體裝置之剖面圖。 圖50係圖48之半導體裝置之其他剖面圖。 【主要元件符號說明】 1 半 導 體 裝 置 la 半 導 體 裝 置 lb 半 導 體 裝 置 1 c 半 導 體 裝 置 Id 半 導 體 裝 置 1 e 半 導 體 裝 置 If 半 導 體 裝 置 ig 半 導 體 裝 置 lh 半 導 體 裝 置 2 半 導 體 晶 片 2a 電 極 2b 表 面 105491-971003.doc -55- 1374527BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a semiconductor device according to an embodiment of the present invention. 2 is a bottom view of the semiconductor device of FIG. 1. 3 is a cross-sectional view of the semiconductor device of FIG. 1. Figure 4 is a cross-sectional view showing the main part of the semiconductor device of Figure i. Figure 5 is a side elevational view of the semiconductor device of Figure 1. Figure Figure 6 is a perspective view of the sealing resin! The plan view of the semiconductor device and the bonding line are shown in Fig. 1. Fig. 7 is a plan perspective view of the semiconductor device of the sealing resin and the semiconductor wafer. 105491-971003.doc • 52- 1374527 Fig. 8 is a cross-sectional view showing the main part of the semiconductor device of the first comparative example. Fig. 9 is a cross-sectional view showing the main part of a semiconductor device of a second comparative example. Fig. 10 is a cross-sectional view showing the main part of a semiconductor device of a third comparative example. Fig. 11 is a main part and a cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Figure 12 is a plan perspective view of the semiconductor device of Figure 11. Fig. 13 is a cross-sectional view showing the manufacture of a semiconductor device according to an embodiment of the present invention. FIG. 15 is a cross-sectional view showing a semiconductor device manufacturing step in FIG. 13 and FIG. 16 is a cross-sectional view showing a semiconductor device manufacturing step in FIG. A cross-sectional view of the semiconductor device manufacturing step of Fig. 16 is continued. Figure 18 is a cross-sectional view showing the steps of manufacturing the semiconductor device of Figure 17; Figure 19 is a cross-sectional view showing the steps of manufacturing the semiconductor device of Figure 18; Figure 20 is a cross-sectional view showing the steps of manufacturing the semiconductor device of Figure 19; Fig. 21 is a plan view showing a manufacturing step of a wiring board. Fig. 22 is a plan view showing the steps of manufacturing the wiring substrate of Fig. 21; Fig. 23 is a plan view showing the steps of manufacturing the wiring substrate of Fig. 22; Fig. 24 is a cross-sectional view showing the principal part of a manufacturing process of a semiconductor device according to an embodiment of the present invention. Fig. 25 is a plan view showing a manufacturing step of a semiconductor device according to an embodiment of the present invention. Fig. 26 is an explanatory view of a wire bonding step. Figure 27 is an explanatory view of a wire bonding step. Fig. 28 is a cross-sectional view showing a principal part of a semiconductor device according to an embodiment of the present invention. Fig. 29 is a cross-sectional view showing another principal part of a semiconductor device according to an embodiment of the present invention. Fig. 30 is a cross-sectional view showing the main part of a semiconductor device according to another embodiment of the present invention. Figure 3 is an explanatory view of the wire bonding step. Figure 32 is an explanatory view of a wire bonding step. Figure 33 is an explanatory view of a wire bonding step. Figure 34 is a cross-sectional view showing the main part of a semiconductor device according to another embodiment of the present invention. Figure 35 is a plan perspective view of the semiconductor device of Figure 34. Figure 36 is a cross-sectional view showing the main part of a semiconductor device according to another embodiment of the present invention. Figure 37 is a plan perspective view of a semiconductor device as another embodiment of the present invention. Fig. 3 is a plan view showing a semiconductor device as another embodiment of the present invention. Figure 39 is a cross-sectional view showing the main part of a semiconductor device according to another embodiment of the present invention. Figure 40 is a plan perspective view of the semiconductor device of Figure 39. Figure 41 is a plan perspective view of the semiconductor device of Figure 39. Figure 42 is a plan view showing the steps of manufacturing the wiring substrate used in the manufacture of the semiconductor device of Figure 39. 105491-971003.doc • 54· 1374527 FIG. 43 is a plan view showing a step of manufacturing the wiring substrate of FIG. 42. Fig. 44 is a plan view showing the steps of manufacturing the wiring substrate of Fig. 43; Fig. 45 is a cross-sectional view showing the main part of a semiconductor device according to another embodiment of the present invention. Figure 46 is a plan view of a semiconductor device as another embodiment of the present invention. Figure 47 is a cross-sectional view of the semiconductor device of Figure 46. Fig. 48 is a plan perspective view showing a semiconductor device according to another embodiment of the present invention. Figure 49 is a cross-sectional view of the semiconductor device of Figure 48. Figure 50 is another cross-sectional view of the semiconductor device of Figure 48. [Main component symbol description] 1 semiconductor device la semiconductor device 1b semiconductor device 1 c semiconductor device Id semiconductor device 1 e semiconductor device If semiconductor device ig semiconductor device lh semiconductor device 2 semiconductor wafer 2a electrode 2b surface 105491-971003.doc -55- 1374527

2c 背面 2d 外周部 2e 侧面 2f 端部 3 佈線基板 3 a 上面 3b 下面 4 接合線 5 密封樹脂 5a 密封樹脂 6 錫球 8 接著材 11 基材層 11a 上面 lib 下面 12 導體層 14 阻焊劑層 14a 第1阻焊劑部 14b 第2阻焊劑部 14c 第3阻焊劑部 15 連接端子 16 焊盤 17 開口部 18 區域 105491-971003.doc -56 13745272c Back surface 2d Outer peripheral portion 2e Side surface 2f End portion 3 Wiring substrate 3 a Upper surface 3b Lower surface 4 Bonding wire 5 Sealing resin 5a Sealing resin 6 Tin ball 8 Substrate 11 Substrate layer 11a Upper lib Lower 12 Conductor layer 14 Solder resist layer 14a 1 solder resist portion 14b second solder resist portion 14c third solder resist portion 15 connection terminal 16 pad 17 opening portion 18 region 105491-971003.doc -56 1374527

18a 區域 18b 區域 19 開口部 19a 開口部 20a 開口部 20b 後退部 21 空間 31 佈線基板 32 半導體裝置區域 33 導體圖案 34 電鍍佈線 35 凸塊 36 雷射 41 毛細管 61 第1部分 62 第2部分 70 半導體晶片 70a 電極 71 接著材 101 半導體裝置 103 佈線基板 103a 上面 114 阻焊劑層 201 半導體裝置 105491-971003.doc -57- 1374527 203 佈線基板 203a 上面 214 阻焊劑層 214a 第1阻焊劑部 214b 第2阻焊劑部 218 區域 221 空間 301 半導體裝置 105491-971003.doc -5818a region 18b region 19 opening portion 19a opening portion 20a opening portion 20b retreating portion 21 space 31 wiring substrate 32 semiconductor device region 33 conductor pattern 34 plating wiring 35 bump 36 laser 41 capillary 61 first portion 62 second portion 70 semiconductor wafer 70a electrode 71 Next material 101 Semiconductor device 103 Wiring substrate 103a Upper surface 114 Solder resist layer 201 Semiconductor device 105491-971003.doc -57- 1374527 203 Wiring substrate 203a Upper surface 214 Solder resist layer 214a First solder resist portion 214b Second solder resist portion 218 Area 221 Space 301 Semiconductor device 105491-971003.doc -58

Claims (1)

十、申請專利範圍： 1' 一種半導體裝置之製造方法，其特徵在於包含以下步 驟： 準備佈線基板，該佈線基板包含；基材層，其平面形 狀為四角形所構成；複數佈線，設於前述基材層之主 面，複數連接端子，沿前述基材層之各邊配置，並與前 述複數佈線之每一者一體地形成；絕緣膜，其以露出前 述基材層之周緣部及前述複數連接端子之方式覆蓋前述 複數佈線；及開σ部，形成於前述絕緣膜中較前述複數 連接端子更内侧之區域，並使前述複數佈線之每—者之 一部份及前述基材層之一部份露出； 準備半導體晶片，該半導體晶片具有形成有複數電極 之主面以及與前述主面對向之背面； 經由供給於前述絕緣膜中較前述開口部更内側之區域 的膏狀接著材，以前述半導體晶片之背面與前述佈線基 板之主面對向之方式，將前述半導體晶片搭載於前㈣ 線基板之主面上； 將前述半導體晶片之複數電極塾與前述佈線基板之複 數連接端子經由複數接合線—電性連接. 將前述羊導體晶片、前述複數接合線'及前述佈線基 板之主面以樹脂密封。 2·如請求項1之半導體裝置之製造方法，其中 前述複數接合線之連接係使用毛細管所進行 3.如請求項1之半導體裝置之製造方法，其中丁 105491-971003.doc 1374527 性==晶片：端部與前述絕緣臈之開口部平面 板之主面上/ ’將别述丰導體晶片搭載於前述佈線基 (如請求項3之半導體裳置之製造方法，盆令 以將前述半導體晶片主面 、 及前述半導體晶片之背面二丰導體晶片之側面、 式密封。 。卩伤以前述樹脂覆蓋之方 5’如=求項3之半導體裝置之製造方法，其中 則相口部係沿前述半導體晶片之端 6·如請求項3之半導體裝置之製造方法，” 前述開口部之平面形狀形成為環狀Γ 7.如請求項3之半導韓裝置之製造方法， =半導體晶片之平面形狀為四角形所構成； 别述半導體晶片係以前述 線基板各邊與前述佈 上. 戰於别述佈線基板之主面 !述開口部係沿前述半導體晶片之各邊所形成； 别述開口部之角部朝前述佈線基板之角部後退。 8.如2求項7之半導體裝置之製造方法，其中 ^開口部之各邊之各自—部份朝前述佈線基板之各 邊後退。 9. 平面形狀為四角形所 之主面；複數連接端 一種半導體裝置，其特徵在於包含 佈線基板，其包含：基材層，其 構成；複數佈線，設於前述基材層 105491-971003.doc 1374527 子’沿前述基材層之各邊配置，並與前述複數佈線之每 一者一體地形成；絕緣膜’其以露出前述基材層之周緣 部及前述複數連接端子之方式覆蓋前述複數佈線；及開 口部’形成於前述絕緣膜中較前述複數連接端子更内側 之區域’並使前述複㈣線之每—者之_部份及前述基 材層之一部份露出； 膏狀接著材，供給於前述絕緣膜中較前述開口部更内 側之區域； 半導體晶片，其具有形成有複數電極之主面以及與前 述主面對向之背面，且以前述背面與前述佈線基板：主 面對向之方式，經由前述接著材搭載於前述佈線基板之 主面上； 複數接合線，將前述半導體晶片之複數電極墊與前述 佈線基板之複數連接端子—電性連接； 二密封樹脂，將前述半導體晶片、前述複數接合線、及 前述佈線基板之主面密封。 io.如請求項9之半導體裝置，其中 前述開口部形成於前述絕緣膜中與前述半導體晶片之 端部平面性地重疊之區域。 u.如請求項1〇之半導體裝置，其中 則述密封樹脂係以將前述半導體晶片主面、前述半導 體晶片之側面、及前述半導體晶片之背面之—部份覆蓋 之方式所形成。 12.如請求項10之半導體裝置，其中 >05491-971003^00 13. 前述開口部係沿前述半導體 B曰片之端部形成。 如Μ求項10之半導體裝置，其中 前述開口部之平面形狀形成為環狀。 14. 如請求項10之半導體裝置，其中 月1J述半導體晶片之平面形壯i m & 十面办狀為四角形所構成； 前述半導體晶片係以前述半導體晶片之各邊與前述佈 線基板之各邊並排之方式搭載於前述佈線基板之主面 L ： 2述開口部係沿前述半導體晶片之各邊所形成； 月J述開口。p之角部朝前述佈線基板之角部後退。 15. 如請求項14之半導體裝置，其中 前述開口冑之各邊之各自—部份朝冑述佈，線基板之各 邊後退。 16. 一種半導體裝置，其特徵在於包括： Ο)佈線基板，其包含：基材層，其平面形狀為四角 形所構成，複數佈線，設於前述基材層之主面；複數連 接知子’沿前述基材層之各邊配置；絕緣膜，其以使前 述複數連接端子自前述絕緣膜露出之方式覆蓋前述複數 佈線；及凹部，形成於前述絕緣膜； (b) 膏狀接著材’供給於較前述凹部平面性地更内側 之前述絕緣膜； (c) 半導體晶片，具有主面、與前述主面為相反側之 背面、及形成於前述主面之複數電極墊，並以前述半導 體晶片之周緣部與前述凹部平面性地重疊之方式，經由 105491-971003.doc 1374527 月IJ述接著材搭載於前述佈線基板之前述主面上； (d) 複數接合線，將前述半導體晶片之前述複數電極 墊/、别述佈線基板之前述複數連接端子--電性連接； (e) 也封樹脂’將前述半導體晶片、前述複數接合 線、及前述佈線基板之主面密封； 刚述複數連接端子分別與前述複數佈線—體地形成； 月IJ述凹部係較前述複數連接端子平面性地更内側配 置；X. Patent application scope: 1′ A manufacturing method of a semiconductor device, comprising the steps of: preparing a wiring substrate, wherein the wiring substrate comprises; a substrate layer having a planar shape of a quadrangle; and a plurality of wirings disposed on the base a main surface of the material layer, a plurality of connection terminals disposed along each side of the substrate layer, and integrally formed with each of the plurality of wirings; and an insulating film exposing a peripheral portion of the substrate layer and the plurality of connections a terminal covering the plurality of wirings; and an opening σ portion formed in a region of the insulating film that is further inside than the plurality of connection terminals, and one of each of the plurality of wirings and one of the substrate layers a semiconductor wafer having a main surface on which a plurality of electrodes are formed and a back surface facing the main surface; and a paste-like material supplied through a region of the insulating film that is further inside than the opening portion, The semiconductor wafer is mounted on the front (four) line so that the back surface of the semiconductor wafer faces the main surface of the wiring board a main surface of the substrate; a plurality of connection terminals of the semiconductor wafer and a plurality of connection terminals of the wiring substrate are electrically connected via a plurality of bonding wires. The main surface of the sheep conductor wafer, the plurality of bonding wires, and the wiring substrate are Resin sealed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the connection of the plurality of bonding wires is performed using a capillary tube. 3. The method for manufacturing a semiconductor device according to claim 1, wherein D. 105491-971003.doc 1374527 property == wafer : the end surface and the main surface of the opening flat plate of the insulating / / 'The semiconductor wafer is mounted on the wiring substrate (the manufacturing method of the semiconductor device of claim 3, the pot is to make the semiconductor wafer main a side surface of the semiconductor wafer, and a side surface of the semiconductor wafer, and a method of manufacturing a semiconductor device in which the resin is covered by the resin 5', wherein the phase portion is along the semiconductor The method of manufacturing the semiconductor device according to claim 3, wherein the planar shape of the opening portion is formed in a ring shape. 7. The manufacturing method of the semiconductor device of claim 3, wherein the planar shape of the semiconductor wafer is A semiconductor chip is formed on each side of the wire substrate and the cloth. The main surface of the wiring substrate is described. The corners of the opening are retracted toward the corners of the wiring board. The method of manufacturing the semiconductor device of claim 7, wherein each of the sides of the opening portion is partially The sides of the wiring board are retracted. 9. The planar shape is a main surface of a quadrangular shape; the plurality of terminals are a semiconductor device, comprising: a wiring substrate comprising: a substrate layer; the plurality of wires are disposed on the base The material layer 105491-971003.doc 1374527 is disposed along each side of the substrate layer and integrally formed with each of the plurality of wirings; the insulating film is formed to expose a peripheral portion of the substrate layer and the plurality of connections a terminal covering the plurality of wirings; and an opening portion 'formed in a region of the insulating film that is further inside than the plurality of connection terminals' and each of the plurality of (four) wires and a portion of the substrate layer a paste-like adhesive material supplied to a region of the insulating film that is further inside than the opening portion; a semiconductor wafer having a main surface on which a plurality of electrodes are formed and a back surface facing the main surface, wherein the back surface and the wiring substrate face each other, and are mounted on a main surface of the wiring board via the bonding material; and a plurality of bonding wires to form a plurality of electrodes of the semiconductor wafer The pad is electrically connected to the plurality of connection terminals of the wiring board; and the second sealing resin seals the semiconductor wafer, the plurality of bonding wires, and the main surface of the wiring substrate. The semiconductor device according to claim 9, wherein the opening The portion of the insulating film that is planarly overlapped with the end portion of the semiconductor wafer. The semiconductor device of claim 1 wherein the sealing resin is used to bond the main surface of the semiconductor wafer to the semiconductor wafer. The side surface and the back side of the semiconductor wafer are formed in a manner of partial coverage. 12. The semiconductor device of claim 10, wherein >05491-971003^00 13. The opening portion is formed along an end portion of the semiconductor B piece. The semiconductor device according to claim 10, wherein the planar shape of the opening portion is formed in a ring shape. 14. The semiconductor device of claim 10, wherein the semiconductor wafer has a planar shape and a tetrahedron shape; the semiconductor wafer is formed by each side of the semiconductor wafer and each side of the wiring substrate The main surface L of the wiring board is mounted side by side: the opening is formed along each side of the semiconductor wafer; The corner portion of p retreats toward the corner of the wiring board. 15. The semiconductor device of claim 14, wherein each of the sides of the opening — is partially splayed, and each side of the line substrate is retracted. A semiconductor device, comprising: a wiring substrate comprising: a substrate layer having a planar shape of a quadrangular shape; a plurality of wirings disposed on a main surface of the substrate layer; and a plurality of connections Arranging each side of the base material layer; the insulating film covering the plurality of wires so that the plurality of connection terminals are exposed from the insulating film; and the recessed portion formed on the insulating film; (b) the paste-like material is supplied to The recessed portion is planarly further inside the insulating film; (c) the semiconductor wafer has a main surface, a back surface opposite to the main surface, and a plurality of electrode pads formed on the main surface, and a periphery of the semiconductor wafer The portion is planarly overlapped with the concave portion, and the bonding material is mounted on the main surface of the wiring substrate via 105491-971003.doc 1374527 IJ; (d) a plurality of bonding wires, and the plurality of electrode pads of the semiconductor wafer /, the above-mentioned plurality of connection terminals of the wiring board - electrical connection; (e) also sealing resin 'the aforementioned semiconductor wafer, the plurality of bonding wires And the main surface of the wiring board is sealed; the plurality of connection terminals are formed separately from the plurality of wirings; and the recesses are arranged more planarly than the plurality of connection terminals; 别述凹部與前述連接端子之間之前述絕緣膜自前述佈 線基板之前述主面突出； 前述接著材包含膏狀材料； -前述凹部之—部份位於較前述半導體晶片平面性地更 外側； 前述密封樹脂之-部份與自前述接著材露出之前述半 導體晶片的前述背面接觸。The insulating film between the recess and the connection terminal protrudes from the main surface of the wiring substrate; the bonding material comprises a paste material; - the portion of the recess is located more planar than the semiconductor wafer; The portion of the sealing resin is in contact with the aforementioned back surface of the semiconductor wafer exposed from the foregoing bonding material. 17. 如請求項16之半導體裝置，其中 前述絕緣膜係以前述基材層之前述周緣部與前述複數 之每—者自前述絕緣膜露出之方式覆蓋前述複 數佈線。 18. 如請求項16之半導體裝置，其中 前述凹部係使前述複數佈線之 考之一部份與前述 基材層之一部份露出。 仍興則4 19. 如§青求項16之半導體裝置，其中 前述半導體晶片與前述密封樹 〈在者性向於前述接 105491-971003.doc 1374527-4 著材與前述密封樹脂之密著性。 20.如請求項】6之半導體裝置，其中 自前述接著材露出之前述半導體a 述半導體晶片之側面 '及前述半導曰之前述主面、前 係以前述密封樹脂覆蓋。 片之則述背面’ 21. 如請求項16之半導體裝置，其中 前述凹部係沿前述半導體晶片之端Α 22. 如請求項16之半導體裝置，其中 卩所形成。17. The semiconductor device according to claim 16, wherein the insulating film covers the plurality of wirings such that the peripheral portion of the base material layer and the plurality of the plurality of insulating layers are exposed from the insulating film. 18. The semiconductor device of claim 16, wherein the recess portion exposes a portion of the plurality of wirings and a portion of the substrate layer. Further, the semiconductor device of the invention of claim 16, wherein the semiconductor wafer and the sealing tree are in contact with the sealing resin in the above-mentioned connector 105491-971003.doc 1374527-4. The semiconductor device according to claim 6, wherein the side surface of the semiconductor wafer from which the bonding material is exposed and the main surface of the semiconductor wafer are covered with the sealing resin. The semiconductor device of claim 16, wherein the recess is along the end of the semiconductor wafer 22. The semiconductor device of claim 16 wherein the recess is formed. 前述凹部之平面形狀形成為環狀。 23. 如請求項16之半導體裝置，其中 刖述半導體晶片之平面形妝 _ 巾狀為四角形所構成. 月，J述半導體晶片係以前述半導 ， 续其舡體曰日片之各邊與前述佈 上. 勒*於别逃佈線基板之主面 前述凹部係沿前述半導體晶片之各邊所形成； 前述凹部之㈣朝前料線基板之角部後退。 24.如請求項16之半導體裝置，其中 前述凹部之各邊之各自一部份朝前述佈線基板之各邊 後退。 105491-971003.doc 1374527 七、指定代表圖：The planar shape of the concave portion is formed in a ring shape. 23. The semiconductor device of claim 16, wherein the planar wafer-shaped shape of the semiconductor wafer is formed by a quadrangle. The semiconductor wafer of the semiconductor wafer is formed by the aforementioned semi-conducting, and the sides of the crucible The concave portion is formed along each side of the semiconductor wafer on the main surface of the wiring substrate, and the fourth portion of the concave portion is retreated toward the corner of the front feed line substrate. The semiconductor device of claim 16, wherein each of the sides of the concave portion retreats toward each side of the wiring substrate. 105491-971003.doc 1374527 VII. Designated representative map: (一) 本案指定代表圖為：第（4 ) (二) 本代表圖之元件符號簡單說明 1 半導體裝置 2 半導體晶片 2a 電極 2b 表面 2c 背面 2d 外周部 2e 側面 2f 端部 3 佈線基板 3a 上面 3b 下面 4 接合線 5 密封樹脂 6 錫球 8 接著材 11 基材層 11a 上面 lib 下面 12 導體層 14 阻焊劑層 14a 第1阻焊劑層 105491-971003.doc 1374527 14b 第2阻焊劑層 15 連接端子 16 焊盤 17, 19 開口部 18 區域 21 空間 τ,, τ2 厚度 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式 (無） 105491-971003.doc(1) The representative representative of the case is: (4) (2) The symbol of the representative figure is briefly described. 1 Semiconductor device 2 Semiconductor wafer 2a Electrode 2b Surface 2c Back surface 2d Outer peripheral portion 2e Side surface 2f End portion 3 Wiring substrate 3a Upper surface 3b Next 4 bonding wires 5 sealing resin 6 solder balls 8 subsequent material 11 substrate layer 11a upper lib lower 12 conductor layer 14 solder resist layer 14a first solder resist layer 105491-971003.doc 1374527 14b second solder resist layer 15 connection terminal 16 Pad 17, 19 Opening 18 Area 21 Space τ,, τ2 Thickness 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention (none) 105491-971003.doc
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US20060091523A1 (en) 2006-05-04
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