1364815 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體元件隔離結構，尤指—種半 導體元件隔離結構之形成方法，用以避免接觸窗蝕刻停止 層中產生隙縫，因而可防止後續形成之接觸插塞短路。 【先前技術】 傳統用於隔離半導體元件之場氧化層（field 〇xide， FOX)結構疋由區域碎氧化法（丨ocal 〇xidati〇n of silicon， LOCOS)來形成，但利用區域矽氧化法之隔離技術所形成之 隔離結構具有場氧化層的水平成長、場換雜離子的水平擴 散、小尺寸場氡化層的薄化效應、以及鳥嘴侵蝕等的缺點， 因而發展出淺溝渠隔離結構(shallow trench isolation structure，STI structure)，以適用於深次微米積體電路的製 造。淺溝渠隔離結構係先在半導體基底中形成溝渠，再填 入絕緣材料並平坦化來製作用以隔離的絕緣區域，所以不 會有區域石夕氧化法特有的鳥嘴現象發生，並且具有小尺寸 隔離線寬、明確之主動區劃分、均勻的隔離區深度、尺寸 可調整（scalable)，以及絕佳的隔離區平坦架構等的優點， 因此成為目前較為理想之隔離技術，而被廣泛的運用在 0.25微米技術的積體電路製造上。 請參考第1圖與第2圖，第1圖為習知半導體元件，例如 1364815 動態隨赫取記憶體（DRAM)，佈狀上視4圖，第2 圖為第1圖中沿AA切線之半導體元件隔離結構的剖面示 意圖。如第1圖所示，於形成記憶胞(mem〇rycell)之各電晶 體時，基底1〇〇上會先形成至少一淺溝渠隔離結構1〇2，: 定義出複數個主動區刚1且各個主動區刚均係藉由淺 溝渠隔離結構H)2來隔離其他鄰近之主動區1()4。然後形成 複數㈣極結獅6橫跨於各㈣㈣績淺雜隔離結構 102上’再於各閘極結構106之周圍側壁形成間隙壁 (SP隨，。之後，進行1對準金屬耗(seif aHgned sUicide，Salicide)製程，以形成相對應之金屬石夕化物層 (silicide iay…於各閘極結構i 〇6與各主動區丨〇4上。 然而，於習知製造半導體元件的過程中，會進行多次 的姓刻及清洗製程，例如：為了移除各電晶體之頂蓋層與 硬罩幕層所進行賴刻製程、間隙壁形成之_與其後所 進行的清洗製程、主動區中之㈣蝴極形成之後所進行的 清洗製程、金屬耗物層形成之前所進行的預清洗製程、 以及最後移除未反應完全之金屬層的_製程等。而在進 行這些射m«清洗製料，料㈣縣之淺溝渠隔 離結構102造成傷害，並於各閘極結構1〇6間之淺溝渠隔離 結構102之表面產生凹陷（recess) u〇，如第2圖所示，其 深度可達數百埃（angstrom，人）以上。由於該！生 等向性姓刻製程對淺溝渠隔離結構102會產生^且积的 7 1364815 • 侵蝕，更容易造成凹陷110之擴大，其中又以形成金屬矽化 物層之前所進行的預清洗製程與形成金屬矽化物層於主動 區104上之後的蝕刻製程所造成之影響為最鉅。此凹陷n〇 之擴大甚至延伸至間隙壁108下方，更嚴重者甚至延伸至閘 極結構106下方’進而導致元件漏電流。 另外，由於元件尺度微縮以提升金氧半場效電晶體 • (metal-oxide-semiconductor field-effect transistor，MOSFET) 特性表現的方式也正遭遇到微影製程技術瓶頸、昂貴花費 等因素之影響’故現行半導體製程也大量利用應變石夕通道 (strained-Si channel)技術，例如具有壓縮/伸張應力之接觸 窗蝕刻停止層（contact etch stop layer，CESL)，來提升載子 遷移率進而改善元件的驅動電流。請參考第3圖，第3圖為 於第2圖之半導體元件隔離結構上形成接觸窗蝕刻停止 之剖面示意圖。如第3圖所示，於後續形成接觸窗蝕刻停止 • 層112的製程中，由於淺溝渠隔離結構1〇2之表面存在凹^ 110，並且各閘極結構106之間過於密集，使得用於、積接 觸窗蝕刻停止層112之化學氣相沉積法容易產生突懸 (overhang)，所以覆蓋於基底1〇〇上且同時填入凹陷丨1〇中 接觸窗餘刻停止層112不僅會於凹陷11 〇之闊口位置產生办 懸，甚至突懸之部份會接合在一起而產生隙縫(seam)或= 洞（void)l 14。 1364815 - 接著，於後續製程中，接觸窗蝕刻停止層上會覆蓋一 層間介電層（inter-layer dielectric layer，ILD layer)，然後於 各電晶體之閘極電極、源極/波極換雜區上分別形成相對應 之接觸窗，再填入鎢金屬而形成鎢接觸插塞（contact plug)。由於淺溝渠隔離結構上之接觸窗姓刻停止層具有隙 縫或孔洞，再加上在進行鶴的化學氣相沉積時，鶴金屬的 填洞能力很強，因此於形成鎢接觸插塞的過程中，鎢金屬 $ 亦會填入接觸窗蝕刻停止層之隙縫或孔洞，以致於-兩-枏'鄰 之鎢接觸插塞產生橋接現象，互相短路，造成積體電路無 法正常運作。 【發明内容】 本發明之主要目的之一在於提供一種半導體元件隔離 結構之形成方法與其形成之半導體元件隔離結構，以避免 因接觸窗蝕刻停止層產生隙縫而所造成相鄰之接觸插塞短 籲路之現象。 根據本發明之申請專利範圍，係提供一種半導體元件 隔離結構之形成方法，其包含有下列步驟：首先，提供一 基底，該基底中具有至少一淺溝渠隔離結構。接著，進行 一金屬矽化製程，且該金屬矽化製程會於該淺溝渠隔離結 構表面形成一凹陷。之後，形成一覆蓋層覆蓋該基底並填 入該凹陷，接著進行一蝕刻製程，以去除位於該凹陷外之 1364815 该覆蓋層，最後，形成一 填滿該凹陷 成接觸固钱刻停止層覆蓋該基底並 =本^之申料利簡，储供— ^結構’其包含有一基底、至少一 渠隔離結構、至少^ ^中之淺溝 面、— 再又罝於5亥夂溝渠隔離結構表 覆盍層、以及—接觸窗蝕刻停止層。其中 結構間之該淺溝準隔 /、 社構之用円表面具有一凹陷。該等閘極 、，，口構之周圍側壁均且右 U間隙壁’且該凹陷具有一延伸邻 位於該等間隙壁下方。唁覆 乙伸。ρ 覆盍層係填充於該凹陷之該延伸 且該接觸窗_停止層覆蓋該等閘極結構與該淺溝 木隔離結構並填滿該凹陷。 屬石夕之半導體元件隔離結構之形成方法係於完成金 淺溝準提供一覆蓋層’以填補任二閉極結構間之 ^結構之凹陷，使後續形成之接觸窗钮刻停止声 付以提南其階梯覆蓋率(卿coverage)而能完整覆蓋基底 且填滿凹陷’而不具有隙縫與孔洞。因此，本發明之半導 體元件隔離結構可有效防止相鄰之接觸插塞產生橋接之現 象。 【實施方式] 請參考第4圖至第9圖，第4圖為本發明—較佳實施 1364815 例之半導體元件，例如動態隨機存取記憶體（DRAM)之 記憶胞(memory cell) ’佈局的上視示意圖，第$圖至第9 圖為本發明一較佳實施例沿著第4圖中bb，線之半導體元 件隔離結構之形成方法示意圖。如第4圖與第5圖所示， 首先，提供一基底200，例如一矽晶圓或一矽覆絕緣基底 等。基底200包含有至少一淺溝渠隔離結構2〇2以及複數 條設置於淺溝渠隔離結構202與基底2〇〇上之閘極結構 204，其中淺清渠隔離結構202係定義出複數個主動區 206，並且淺/冓渠隔離結構202係用來隔離各主動區206。 另外，各閘極結構204之周圍側壁分別形成有一間隙壁 208。及溝^隔滩結構202、閘極結構204與間隙壁208之 形成方法為於此技術領域具有通常知識者所熟知，故於此 不再贅述。 接著，進行一自對準金屬矽化(salicide)製程，以於閘 極結構2 04上形成金屬矽化物層2丨〇或於未被閘極結構2 與間隙壁208覆蓋之主動區屬上形成相對應之金屬石幻 物層（圖未示）。其中’㈣準金射化製程包含有針重^ 底200表面進行一預清洗製程，然後於基底2〇〇上 : 屬層以及遮蓋層（圖未示）並進行快速熱退火f程(raPid ’ thermal annealing，RTA)以形成金屬矽化物層21〇，再 -触刻製程移除遮蓋層以及未反應之金屬層。 用 11 1364815 如第5圖所示，值得注意的是，在形成淺溝渠隔離会士 構202之後到形成金屬石夕化物層210的過程中，所進行的 諸如移除各電晶體之頂蓋層與硬罩幕層所進行的蝕刻製 程、間隙壁208形成之蝕刻與其後所進行的清洗製程、主 動區206甲之源極/汲極形成之後所進行的清洗製程、金屬 矽化物層210形成之前所進行的預清洗製程、以及最後移 除未反應完全之金屬層的蝕刻製程等皆可能會對裸露之淺 溝渠隔離結構202造成傷害，使未被各閘極結構204與各 間隙壁208覆蓋之淺溝渠隔離結構202的表面形成複數個 凹陷212。特別是，對淺溝渠隔離結構202的效能影響較 鉅者為形成金屬石夕化物層210之前的預清洗製程以及去除 閘極結構204或主動區206上未反應完全之金屬層的餘刻 製程。而且，形成於任二相鄰閘極結構204間之淺溝渠隔 離結構202中的凹陷212具有一延伸部213位於間隙壁2〇8 下方，使間隙壁208底側產生底切（undercut)之情況。 如第6圖所示，接下來，進行一沉積製程，例如：化 學氣相沉積（chemical vapor deposition，CVD)製程，以形成 —覆蓋層（cap film)214覆蓋基底200，且同時於凹陷212 表面形成覆蓋層214，用以填補位於間隙壁208下方之凹 陷212，尤其是實質填補凹陷212的延伸部213，以修整凹 陷212表面輪廓，進而避免於後續填充凹陷212的過程中 產生隙縫與孔洞。其中’覆蓋層214之材料可為氧化物， 1364815 - 例如：氧化矽（Si02)，或氮化物，例如：氮化矽，等之絕緣 ' 材料為主，但覆蓋層214之材料仍可依據實際需求或製程 效率而定。此外，覆蓋層214可另包含有一氧化層，作為 後續蝕刻製程之蝕刻停止層，亦即於形成覆蓋層214的主 材料層之前，例如氮化物，本較佳實施例可先形成一氧化 層覆蓋於基底200上，然後再形成覆蓋層214的主材料層， 以避免於後續蝕刻製程中，為了移除凹陷212外之覆蓋層 I 214的主材料層，而傷害到閘極結構204或主動區206上 之金屬矽化物層210。此外，覆蓋層214亦可為多層結構， 由複數個氧化物層、氮化物層或上述之組合所構成。 然後，如第7圖所示，進行一蝕刻製程，以去除位於 凹陷212外之覆蓋層214，亦即僅有部分之覆蓋層214在 蝕刻製程後餘留於凹陷212内，用以填補位於間隙壁208 下方之凹陷212的延伸部213並修整凹陷212表面輪廓。 ® 此蝕刻製程可為非等向性蝕刻製程，例如：電漿蝕刻，使 位於凹陷212之側壁具有較多覆蓋層214之殘留，以有助 於後續沉積製程之進行。值得注意的是，根據不同之蝕刻 條件，剩餘之覆蓋層214可不只位於凹陷212之延伸部213 與凹陷212之側壁，其另可有部分之殘餘覆蓋層214位於 凹陷212之底部，如第8圖所示，且以覆蓋層214可填補 整個凹陷212内之延伸部213與底部為較佳。此外，於此 蝕刻製程之後，可選擇性進行電漿清洗與溶液清洗，用以 13 1364815 清除基底200上之污染物。 最後，如第9圖所示，進行非現場(ex-situ)之一沉積製 程’例如：化學氣相沉積製程，以形成一接觸窗蝕刻停止 層（contact etch stop layer，CESL)216 覆蓋基底 200 且沿著 覆蓋層214填滿凹陷212，其中非現場為於不同機台中進 行’亦即形成覆蓋層214與形成接觸窗蝕刻停止層216係 於不同機台中進行。值得注意的是，由於在形成接觸窗蝕 刻停止層216之前’本較佳實施例係先於凹陷212之側壁、 延伸部213或底部填補覆蓋層214來修整凹陷212表面輪 廓，故可使接續填入凹陷212之接觸窗蝕刻停止層216不 致於產生孔洞或隙縫之情況，因而能有效避免後續製程中 鎢金屬填入接觸窗蝕刻停止層216之隙縫或孔洞，導致相 之接觸插基產生橋接現象。由於接觸窗触刻停止層216 同時具有糾Ά止層之功用與提供電晶體通道區（ehannel) 又應力a之功用，因此其材料以可作為钱刻停止層與具 :可提供壓縮/伸張應力之特性為主 ，例如本實施例之接觸 1刻彳T止層216係以氮化妙為例，但不限於此。接著， σ、、擇熟化製程，例如：採用紫外光照射製程或 =熱製程等方式實施，使接觸窗關停止廣 216能具有 s .心 以提升通道區内載子之遷移率進而改善元件 的驅動電然後，再於接觸窗餘刻停止層216上方覆蓋 層間；I電層218，並進行接觸插塞製程。另外，由於形 14 1364815 •成覆蓋層2i4之步驟與形成接觸窗蝕刻停止層216之步驟 係於不同之機台中進行，覆蓋層214之材料可不同於接觸 窗钱刻停止層216之材料，例如：覆蓋層214為氧化物， 接觸該刻停止層216則為氮化石夕，接觸窗姓刻停止層216 之應力會大於覆蓋層214之應力。此外，為了讓接觸窗姓 刻#•止層216對通道區之晶格排列產生較強之影響，接觸 窗敍刻停止層216之位置需越接近通道區越佳，所以在本 φ實施例中，位於閘極結構204以及主動區2〇6上方之覆蓋 層214於蝕刻製程中需盡量清除乾淨以使接續形成之接 觸窗蝕刻停止層216可直接覆蓋於閘極結構2〇4與主動區 206.上，進而藉由接觸窗蝕刻停止層216所提供之應力拉 大或縮小主動區206中閘極結構204下方之基底200.來改 變通道區之晶格排列，以提升通道區之載子遷移率與元件 之驅動電流。 值得注意的是，本發明形成覆蓋層214之步驟與形成接 觸窗蝕刻停止層216之步驟並不限於前述實施例於不同機 台中依序進行的方式’其亦可於同—機台.叫之不同反 應室（chamber)中依序形成或於同—機台之同一反應室中依 序形成。當形成覆蓋層214之步驟與形成接觸窗㈣停止^ 216之步驟於同-機台之不同反應室中進行時，雖卿^ 者所使用之沉積製程因同-機台而必須相同，但由於在不 同反應室中進行’所以形成覆蓋層214與接觸窗餘刻停止居 15 1364815 216之材料可以不相同，而且覆蓋層2丨4亦可不需如接觸窗 餘刻停止層216需進行熟化製程之步驟。另外，當形成 層214之步驟與形成接觸窗蝕刻停止層216之步驟於同— 台之同一反應室中形成時，形成兩者所使用之沉積製程= 為相同且皆可選擇性進行熟化製程，並且為避免反應=之 污染，覆蓋層214與接觸窗蝕刻停止層216之材料可為=之 同，因此可視覆蓋層214為接觸窗蝕刻停止層216之—邛 分，並且覆蓋層214之應力4於接觸.窗蚀刻停止層aw之應 力’對通道區可產生相同之應力。換句話說，當形成覆蓋 層214之步驟與形成接觸窗钱刻停止層216之步驟於同一反 應至中形成時，形成覆蓋層214、進行餘刻製程以及形成接 觸窗餘刻停止層216可為一沉積/餘刻/沉積 (Deposition/Etch/Deposition)之製程，亦即本實施例可利用 傳統形成接觸窗蝕刻停止層216之沉積製程來形成覆蓋層 214、部分蝕刻、形成接觸窗蝕刻停止層216。例如，高密 度電毁化學氣相沉積（high density plasma chemical vapor deposition，HDPCVD)即同時具有化學氣相沉積與物理濺 钱的特性，因此於高密度電漿化學氣相沉積製程中，在沉 積覆蓋層214之後’隨即藉由電漿轟擊或調整其物理濺蝕之 速率及化學氣相沉積之速率，來將部份位於凹陷212外之覆 蓋層214蝕刻掉，再直接將接觸窗蝕刻停止層216沉積至凹 陷212中。 丄 此外，接觸窗餘刻停止層216更可為多層（multl_la㈣ ί構，而且每—層均可具有不同之應力值。亦即形成接觸 由钱刻停止層216之步驟可包含多個單階段沉積製程，並可 於各单階段沉積製程之後，皆分別進行—次熟化製程，使 每一層之接觸窗餘刻停止層216皆具有高應力狀態，進而能 讓此多層結構之接觸窗钱刻停止層216可具有較佳之應力 狀態。 如第4圖與第9圖所示，利用上述之半導體元件隔離 結構之形成方法製作出一半導體元件隔離結構，其包含有 -基底200、至少一淺溝渠隔離結構2〇2、複數條間極結構 2〇4、複數個間隙壁雇、一覆蓋層214以及一接觸窗關 停止層216。其中，淺溝渠離結構2〇2設置於基底2〇〇中 且定義出複數個主動區206。各閘極結構2〇4係橫跨於淺 溝渠隔離結構202與主動區206上，並且各間隙壁分 別設置於各閘極結構204之周圍側壁上。任二相鄰閘極結 構204間之淺溝渠隔離結構2〇2的表面具有一凹陷212， 且凹陷212更具有一延伸部213設置於間隙壁2〇8下方。 值的注意的是，覆蓋層214係填充於凹陷212之延伸部213 中，並且接觸窗蝕刻停止層216覆蓋於閘極結構2〇4與淺 溝k隔離結構202上且沿著凹陷212中之覆蓋層214填滿 凹陷212且覆蓋覆蓋層214。藉由覆蓋層214預先填補於 使間隙壁208產生底切現象之凹陷212的延伸部213中， 17 1364815 因此後續形成之接觸窗蝕刻停止層216得以提高其階梯覆 蓋率而能完整覆蓋基底200且填滿凹陷212，而不產生隙 缝或孔洞。但本發明之半導體元件隔離結構並不限於覆蓋 層214僅填充於凹陷212之延伸部213中，如第8圖所示， 半導體元件隔離結構可另包含有覆蓋層214設置於凹陷 212之底部。 綜上所述，本發明之半導體元件隔離結構之形成方法 係於完成金屬矽化製程之後，隨即提供一覆蓋層，以填補 任二相鄰閘極結構間之淺溝渠隔離結構因清洗製程或蝕刻 製程所產生之凹陷，.並修整凹陷表面輪廓，使後續形成之 接觸窗蝕刻停止層得以提高其階梯覆蓋率而能完整覆蓋基 底且填滿凹陷，而不產生隙縫或孔洞。因此，本發明之半 導體元件隔離結構可有效防止相鄰之接觸插塞產生橋接之 現象。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖為習知半導體元件佈局之上視示意圖。 第2圖為第1圖中沿AA’線之剖面示意圖。 第3圖為於第2圖之結構上形成接觸窗蝕刻停止層之剖面 18 丄 丄 示意圖。 第4圖為本發明一 意圖。 較佳實施例之半導體元件佈局的上視示 第5圖至第9圖為本發明 線之半導體元件隔離結 一較佳實施例沿著第4 構之形成方法示意圖。 圖中 BB， 【主要元件符號說明】 100基底 104主動區 108間隙壁 112接觸窗钮刻停止層 200基底 204閘極結構 208間隙壁 212 凹陷 214覆蓋層 218層間介電層 102 .淺溝渠隔離結構 106閘極結構 110凹陷 114孔洞 202淺溝渠隔離結構 206主動區 210金屬矽化物層 213延伸部 216接觸窗蝕刻停止層1364815 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device isolation structure, and more particularly to a method for forming a semiconductor device isolation structure, in order to avoid occurrence of a gap in a contact window etch stop layer, thereby preventing The subsequently formed contact plug is shorted. [Prior Art] The field oxide layer (FOX) structure conventionally used for isolating semiconductor devices is formed by 丨ocal 〇xidati〇n of silicon (LOCOS), but using a region 矽 oxidation method. The isolation structure formed by the isolation technology has the disadvantages of the horizontal growth of the field oxide layer, the horizontal diffusion of the field-changing ions, the thinning effect of the small-scale field deuteration layer, and the bird's beak erosion, thus developing a shallow trench isolation structure ( The shallow trench isolation structure (STI structure) is suitable for the fabrication of deep sub-micron integrated circuits. The shallow trench isolation structure first forms a trench in the semiconductor substrate, and then fills the insulating material and planarizes to form an insulating region for isolation, so that there is no bird's mouth phenomenon unique to the region, and has a small size. The isolation line width, the clear active area division, the uniform isolation area depth, the scalable size, and the excellent isolation area flat structure, etc., have become the ideal isolation technology, and are widely used in The integrated circuit of 0.25 micron technology is manufactured. Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a conventional semiconductor device, for example, 1364815 dynamic with memory (DRAM), cloth top view 4, and FIG. 2 is tangent to AA in FIG. A schematic cross-sectional view of a semiconductor device isolation structure. As shown in FIG. 1, when forming each transistor of a memory cell, at least one shallow trench isolation structure 1〇2 is formed on the substrate 1〇〇, and a plurality of active regions are defined as 1 Each active zone is isolated by the shallow trench isolation structure H) 2 to isolate other adjacent active zones 1 () 4 . Then, a plurality of (four) pole lions 6 are formed across each of the (four) (four) shallow hybrid isolation structures 102 and a spacer is formed on the surrounding sidewalls of the gate structures 106 (SP follows, after that, 1 alignment metal consumption is performed (seif aHgned) sUicide, Salicide) process to form a corresponding metallization layer (silicide iay ... on each gate structure i 〇 6 and each active region 丨〇 4. However, in the process of manufacturing semiconductor components, Performing multiple engraving and cleaning processes, for example, in order to remove the top and bottom layers of each transistor, the etching process and the formation of the spacers are followed by the cleaning process and the active area. (4) The cleaning process performed after the formation of the butterfly pole, the pre-cleaning process performed before the formation of the metal consumable layer, and the final removal of the unreacted metal layer, etc., while performing these injections «cleaning materials, (4) The shallow trench isolation structure 102 of the county causes damage, and a depression u〇 is formed on the surface of the shallow trench isolation structure 102 between the gate structures 1 and 6, as shown in Fig. 2, the depth is up to several Angstrom (angstrom, Above. Because of this! The isotropic process of engraving is applied to the shallow trench isolation structure 102, which will produce 7 1364815 • erosion, which is more likely to cause the expansion of the depression 110, which is performed before the formation of the metal telluride layer. The effect of the pre-cleaning process and the etching process after forming the metal telluride layer on the active region 104 is greatest. The expansion of the recesses even extends below the spacers 108, and more particularly even to the gate structures 106. The lower part, which leads to leakage current of the component. In addition, due to the size reduction of the component to enhance the performance of the metal-oxide-semiconductor field-effect transistor (MOSFET), the lithography process bottleneck is also encountered. The impact of factors such as expensive costs, so the current semiconductor process also makes extensive use of strained-Si channel technology, such as contact etch stop layer (CESL) with compression/extension stress to enhance the load. The sub-mobility further improves the drive current of the device. Please refer to Figure 3, and Figure 3 shows the semiconductor device in Figure 2. A cross-sectional view of the contact window etch stop is formed on the structure. As shown in FIG. 3, in the subsequent process of forming the contact etch stop layer 112, there is a recess 110 on the surface of the shallow trench isolation structure 1 〇 2, and each The gate structures 106 are too dense, so that the chemical vapor deposition method for the contact window etch stop layer 112 is prone to overhang, so that it covers the substrate 1 while filling the recesses. The middle contact window residual stop layer 112 not only creates a suspension at the wide opening position of the recess 11 but also the protruding portions are joined together to create a seam or a void 14 . 1364815 - Next, in the subsequent process, the contact etch stop layer is covered with an inter-layer dielectric layer (ILD layer), and then the gate electrode and source/wave of each transistor are replaced. Corresponding contact windows are formed on the regions, and tungsten metal is filled in to form a tungsten contact plug. Since the contact layer on the shallow trench isolation structure has a gap or a hole in the stop layer, and the chemical vapor deposition of the crane is carried out, the hole filling ability of the crane metal is strong, so in the process of forming the tungsten contact plug. Tungsten metal $ will also fill the gaps or holes in the contact window etch stop layer, so that the -two-枏's adjacent tungsten contact plugs will bridge and short-circuit each other, causing the integrated circuit to fail to operate normally. SUMMARY OF THE INVENTION One of the main objects of the present invention is to provide a method for forming a semiconductor device isolation structure and a semiconductor device isolation structure formed thereof, so as to avoid short contact between adjacent contact plugs caused by gaps in the contact window etch stop layer. The phenomenon of the road. According to the scope of the invention, there is provided a method of forming a semiconductor device isolation structure comprising the steps of: first, providing a substrate having at least one shallow trench isolation structure therein. Next, a metal deuteration process is performed, and the metal deuteration process forms a depression on the surface of the shallow trench isolation structure. Thereafter, a cover layer is formed to cover the substrate and fill the recess, and then an etching process is performed to remove the cover layer located at 1364815 outside the recess. Finally, a recess is formed to fill the recess to cover the solid layer. Basement = the application of this ^ is simplified, the storage - ^ structure 'contains a base, at least one canal isolation structure, at least ^ shallow shallow groove surface, and then 罝 5 5 5 5 5 5 5 5 5 The germanium layer, and the contact window etch stop layer. The shallow groove of the structure between the structures has a depression on the surface of the structure. The gates and the surrounding sidewalls of the mouth are both right U-walls and the recesses have an extension adjacent to the spacers.唁 乙 伸. The ρ cladding layer fills the extension of the recess and the contact window stop layer covers the gate structures and the shallow trench isolation structure and fills the recess. The method for forming the isolation structure of the semiconductor component of Shi Xi is to provide a cover layer to complete the structure of the structure between the two closed-pole structures, so that the subsequent contact window button is stopped and the sound is lifted. South has a step coverage (clear coverage) and can completely cover the substrate and fill the recesses without the slits and holes. Therefore, the semiconductor element isolation structure of the present invention can effectively prevent the occurrence of bridging of adjacent contact plugs. [Embodiment] Please refer to FIG. 4 to FIG. 9 , and FIG. 4 is a diagram of a memory cell of a semiconductor device of the invention, for example, a dynamic random access memory (DRAM). FIG. 1 to FIG. 9 are schematic diagrams showing a method of forming a semiconductor device isolation structure along line bb in FIG. 4 according to a preferred embodiment of the present invention. As shown in Figs. 4 and 5, first, a substrate 200 such as a germanium wafer or a germanium insulating substrate is provided. The substrate 200 includes at least one shallow trench isolation structure 2〇2 and a plurality of gate structures 204 disposed on the shallow trench isolation structure 202 and the substrate 2, wherein the shallow trench isolation structure 202 defines a plurality of active regions 206. And the shallow/drain isolation structure 202 is used to isolate each active region 206. In addition, a spacer 208 is formed on each of the surrounding sidewalls of each of the gate structures 204. The method of forming the trench structure 202, the gate structure 204, and the spacers 208 is well known to those skilled in the art and will not be described herein. Next, a self-aligned metal salicide process is performed to form a metal telluride layer 2 on the gate structure 206 or to form a phase on the active region that is not covered by the gate structure 2 and the spacer 208. Corresponding metal stone illusion layer (not shown). The '(4) quasi-gold radiochemical process includes a surface of the bottom 200 to perform a pre-cleaning process, and then on the substrate 2: a layer and a cover layer (not shown) and a rapid thermal annealing f process (raPid ' Thermal annealing (RTA) to form a metal telluride layer 21, and then a touch-etching process to remove the mask layer and the unreacted metal layer. 11 1364815 As shown in Fig. 5, it is worth noting that during the formation of the shallow trench isolation barrier 202 to the formation of the metallic lithium layer 210, the removal of the cap layer of each transistor is performed. The etching process performed by the hard mask layer, the etching formed by the spacer 208, the cleaning process performed thereafter, the cleaning process performed after the source/drain formation of the active region 206, and the formation of the metal telluride layer 210 are performed. The pre-cleaning process performed, and the etch process that ultimately removes the unreacted metal layer, may cause damage to the exposed shallow trench isolation structure 202, such that it is not covered by the gate structures 204 and the spacers 208. A plurality of recesses 212 are formed on the surface of the shallow trench isolation structure 202. In particular, the effect on the efficiency of the shallow trench isolation structure 202 is greater than the pre-cleaning process prior to the formation of the metallization layer 210 and the removal of the unreacted metal layer on the gate structure 204 or active region 206. Moreover, the recess 212 formed in the shallow trench isolation structure 202 between any two adjacent gate structures 204 has an extension portion 213 located below the spacer 2〇8 to cause undercut of the bottom side of the spacer 208. . As shown in FIG. 6, next, a deposition process, such as a chemical vapor deposition (CVD) process, is performed to form a cap film 214 covering the substrate 200, and simultaneously on the surface of the recess 212. A cover layer 214 is formed to fill the recess 212 below the spacer 208, and in particular to substantially fill the extension 213 of the recess 212 to trim the surface profile of the recess 212, thereby avoiding the creation of slots and holes during subsequent filling of the recess 212. Wherein the material of the capping layer 214 may be an oxide, 1364815 - for example: yttrium oxide (SiO 2 ), or a nitride such as tantalum nitride, etc., but the material of the cap layer 214 may still be practical. Depending on the efficiency of the demand or process. In addition, the cap layer 214 may further comprise an oxide layer as an etch stop layer for the subsequent etching process, that is, before forming the main material layer of the cap layer 214, such as nitride, the preferred embodiment may first form an oxide layer. On the substrate 200, the main material layer of the capping layer 214 is then formed to avoid damage to the gate structure 204 or the active region in order to remove the main material layer of the capping layer I 214 outside the recess 212 during the subsequent etching process. A metal telluride layer 210 on 206. In addition, the cover layer 214 may also have a multi-layer structure composed of a plurality of oxide layers, nitride layers, or a combination thereof. Then, as shown in FIG. 7, an etching process is performed to remove the cap layer 214 located outside the recess 212, that is, only a portion of the cap layer 214 remains in the recess 212 after the etching process to fill the gap. The extension 213 of the recess 212 below the wall 208 and trims the surface profile of the recess 212. ® This etch process can be an anisotropic etch process, such as plasma etch, to leave a portion of the sidewalls of the recess 212 with more of the cap layer 214 to aid in the subsequent deposition process. It should be noted that, depending on different etching conditions, the remaining cover layer 214 may be located not only on the sidewalls of the recess 213 and the recess 212 of the recess 212, but also a portion of the residual cover layer 214 may be located at the bottom of the recess 212, such as the eighth. As shown, it is preferred that the cover layer 214 fill the extensions 213 and the bottom of the entire recess 212. In addition, after the etching process, plasma cleaning and solution cleaning may be selectively performed to remove contaminants on the substrate 200 by 13 1364815. Finally, as shown in FIG. 9, an ex-situ deposition process, such as a chemical vapor deposition process, is performed to form a contact etch stop layer (CESL) 216 covering the substrate 200. And the recess 212 is filled along the cover layer 214, wherein the off-site is performed in different machines, that is, the formation of the cover layer 214 and the formation of the contact window etch stop layer 216 are performed in different machines. It should be noted that since the preferred embodiment prior to forming the contact etch stop layer 216, the surface profile of the recess 212 is trimmed prior to the sidewalls of the recess 212, the extension 213 or the bottom fill overlay 214, so that the fill can be filled. The contact etch stop layer 216 entering the recess 212 does not cause holes or slits, thereby effectively preventing the tungsten metal from filling the gap or hole of the contact etch stop layer 216 in the subsequent process, resulting in bridging of the contact plug of the phase. . Since the contact window etch stop layer 216 has both the function of the stagnation stop layer and the function of providing the transistor channel and the stress a, the material can be used as a stop layer and the device can provide compression/extension stress. The characteristics are mainly, for example, the contact 1 彳T stop layer 216 of the present embodiment is exemplified by nitriding, but is not limited thereto. Then, the σ, and the aging process, for example, using an ultraviolet light irradiation process or a = hot process, etc., so that the contact window is closed, the 216 can be used to improve the mobility of the carrier in the channel region and thereby improve the components. The driving power is then applied to the interlayer stop layer 216 over the contact window to cover the interlayer; the I electrical layer 218, and the contact plug process is performed. In addition, since the step of forming the cover layer 2i4 and the step of forming the contact window etch stop layer 216 are performed in different machines, the material of the cover layer 214 may be different from the material of the contact window stop layer 216, for example, The cover layer 214 is an oxide, and the stop layer 216 is nitrided at the moment of contact, and the stress of the stop layer 216 of the contact window is greater than the stress of the cover layer 214. In addition, in order to make the contact window surname • 层 216 have a strong influence on the lattice arrangement of the channel region, the position of the contact window swatch stop layer 216 needs to be closer to the channel region, so in the φ embodiment The cap layer 214 located above the gate structure 204 and the active region 2〇6 needs to be cleaned as much as possible during the etching process so that the contact window etch stop layer 216 formed successively can directly cover the gate structure 2〇4 and the active region 206. Further, by changing the stress provided by the contact etch stop layer 216 to enlarge or reduce the substrate 200 under the gate structure 204 in the active region 206, the lattice arrangement of the channel region is changed to enhance the carrier migration in the channel region. Rate and component drive current. It should be noted that the step of forming the cover layer 214 and the step of forming the contact etch stop layer 216 of the present invention are not limited to the manner in which the foregoing embodiments are sequentially performed in different machines. Formed sequentially in different chambers or sequentially in the same reaction chamber of the same machine. When the step of forming the cap layer 214 and the step of forming the contact window (4) stop ^ 216 are performed in different reaction chambers of the same machine, although the deposition process used by the device must be the same due to the same machine, In the different reaction chambers, the material forming the cover layer 214 and the contact window may be different. The cover layer 2丨4 may also need to be subjected to the aging process as the contact window is stopped. step. In addition, when the step of forming the layer 214 and the step of forming the contact etch stop layer 216 are formed in the same reaction chamber of the same stage, the deposition process for forming both is the same and both can be selectively performed. In order to avoid the reaction=contamination, the material of the cover layer 214 and the contact etch stop layer 216 may be the same, so that the visible cover layer 214 is the contact etch stop layer 216, and the stress of the cover layer 214 is 4 The stress on the contact etch stop layer aw can produce the same stress on the channel region. In other words, when the step of forming the cap layer 214 and the step of forming the contact window stop layer 216 are formed in the same reaction to the middle, the forming of the cap layer 214, the process of performing the engraving process, and the formation of the contact window stop layer 216 may be A deposition/deposition/deposition process, that is, the deposition process of the conventional contact window etch stop layer 216 can be used to form the cap layer 214, partially etch, and form a contact etch stop layer. 216. For example, high-density plasma chemical vapor deposition (HDPCVD) has the characteristics of chemical vapor deposition and physical splashing. Therefore, in high-density plasma chemical vapor deposition process, deposition coverage After layer 214, the portion of the cap layer 214 located outside of the recess 212 is etched away by plasma bombardment or by adjusting the rate of physical sputter and the rate of chemical vapor deposition, and the contact window etch stop layer 216 is directly applied. Deposited into the recess 212. In addition, the contact window stop layer 216 may be a plurality of layers (multl_la(4) structure, and each layer may have different stress values. That is, the step of forming the contact stop layer 216 may include multiple single-stage depositions. The process, and after each single-stage deposition process, respectively, the secondary curing process is performed, so that the contact window stop layer 216 of each layer has a high stress state, thereby enabling the contact window of the multilayer structure to stop the layer. 216 may have a better stress state. As shown in FIGS. 4 and 9, a semiconductor device isolation structure is formed by the above-described method for forming a semiconductor device isolation structure, which includes a substrate 200 and at least one shallow trench isolation structure. 2〇2, a plurality of interpole structures 2〇4, a plurality of spacers, a cover layer 214, and a contact window stop layer 216. The shallow trench structure 2〇2 is disposed in the substrate 2〇〇 and defined A plurality of active regions 206 are formed. The gate structures 2〇4 are spanned over the shallow trench isolation structures 202 and the active regions 206, and the spacers are respectively disposed on the surrounding sidewalls of the gate structures 204. The surface of the shallow trench isolation structure 2〇2 between any two adjacent gate structures 204 has a recess 212, and the recess 212 has an extension portion 213 disposed under the spacer 2〇8. Note that the cover layer 214 is filled in the extension 213 of the recess 212, and the contact etch stop layer 216 covers the gate structure 2〇4 and the shallow trench k isolation structure 202 and fills the recess 212 along the cover layer 214 in the recess 212 and Covering the cover layer 214. The cover layer 214 is pre-filled in the extension portion 213 of the recess 212 which causes the undercut 208 to cause undercut, 17 1364815. Therefore, the subsequently formed contact etch stop layer 216 can improve its step coverage and can The substrate 200 is completely covered and filled with the recesses 212 without creating slits or holes. However, the semiconductor device isolation structure of the present invention is not limited to the cover layer 214 being only filled in the extension portion 213 of the recess 212, as shown in FIG. The component isolation structure may further include a cover layer 214 disposed at the bottom of the recess 212. In summary, the method for forming the semiconductor device isolation structure of the present invention is after completing the metal deuteration process, and then Providing a cover layer to fill the depression caused by the cleaning process or the etching process of the shallow trench isolation structure between any two adjacent gate structures, and trimming the surface profile of the recess, so that the subsequently formed contact window etch stop layer can be improved The step coverage can completely cover the substrate and fill the recess without generating slits or holes. Therefore, the semiconductor device isolation structure of the present invention can effectively prevent the adjacent contact plug from bridging. The above is only the present invention. The preferred embodiments of the present invention are intended to be within the scope of the present invention. The first embodiment is a schematic view of a conventional semiconductor device layout. Fig. 2 is a schematic cross-sectional view taken along line AA' in Fig. 1. Fig. 3 is a schematic view showing a section 18 丄 形成 of the contact etch stop layer formed on the structure of Fig. 2. Figure 4 is an illustration of the present invention. The top view of the semiconductor device layout of the preferred embodiment is shown in Figs. 5 to 9 is a schematic view showing a method of forming a semiconductor device isolation junction according to a fourth embodiment of the present invention. BB, [Major component symbol description] 100 substrate 104 active region 108 spacer 112 contact window button stop layer 200 substrate 204 gate structure 208 spacer 212 recess 214 cover layer 218 interlayer dielectric layer 102. shallow trench isolation structure 106 gate structure 110 recess 114 hole 202 shallow trench isolation structure 206 active region 210 metal telluride layer 213 extension portion 216 contact window etching stop layer