TWI511286B - An soi transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto - Google Patents

Description

SOI transistor with reduced length drain and source regions and adjacent dielectric materials

In general, the present invention relates to forming integrated circuits, and more particularly to forming a stressed channel region by using a stress source, a stressed overlayer, and the like. The transistor is reinforced to the charge carrier mobility in the channel region of the MOS transistor.

In general, there are a number of process technologies currently employed in the field of semiconductor fabrication, where complex circuits, such as microprocessors, memory chips, etc., due to operational speed and/or power consumption and/or cost effectiveness The superior features of CMOS technology are currently the most promising approach. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, namely N-channel transistors and P-channel transistors, are formed on a substrate comprising a crystalline semiconductor layer. Regardless of the NMOS transistor or PMOS transistor, the MOS transistor includes a so-called PN junction, which is a highly doped drain and source region and is disposed in the drain region and The interface between the source regions is opposite or weakly doped channel regions.

The conductivity of the channel region (i.e., the drive current capability of the conductive channel) is controlled by a gate electrode formed adjacent to the channel region and separated from the channel region by a thin insulating layer. After the conductive path is formed, the conductivity of the channel region depends on the dopant concentration, the mobility of most charge carriers, and the direction of the transistor width due to the application of an appropriate control voltage to the gate electrode. For a given extension of the channel zone, The distance between the drain and the source region (which is also referred to as the channel length). Therefore, after applying the control voltage to the gate electrode, combined with the ability to rapidly generate a conductive path under the insulating layer, the total conductivity of the channel region substantially determines the performance of the MOS transistor. Therefore, reducing the channel length is the main design criterion for achieving an increased operating speed and a packing density of the integrated circuit.

However, the continued shrinking of the transistor size involves a number of problems associated with it that must be resolved so as not to unduly offset the benefits obtained by steadily reducing the channel length of the MOS transistor. A major problem in this regard is to provide low sheet resistivity and low contact resistivity in any contact between the source and drain regions and the source and drain regions. Maintain channel controllability. For example, reducing the channel length may require increasing the capacitive coupling between the gate electrode and the channel region, which may require reducing the thickness of the gate insulating layer. At present, the thickness of the gate insulating layer based on cerium oxide is in the range of 1 to 2 nm, and in view of the fact that the leakage current generally increases exponentially when the thickness of the gate dielectric is reduced, it is less desirable to reduce the thickness.

The continued size reduction of the critical dimensions (i.e., the gate length of the transistor) requires adaptation and possible new development of highly complex process techniques with respect to the above mentioned problems. It has been proposed to improve the efficacy of the transistor by increasing the charge carrier mobility in a channel region for a given channel length, thereby enhancing the channel conductivity of the transistor element, thereby providing the possibility of achieving an improvement in performance. Promote to the future of technology nodes while avoiding or at least Many of the above problems are postponed, such as the size scaling of the gate dielectric. An effective mechanism for increasing the charge carrier mobility is to modify the lattice structure in the channel region, for example by generating tensile stress or compressive stress near the channel region. A corresponding strain is generated in the channel region that causes a modified mobility rate for the electron and the hole, respectively. For example, for a standard germanium substrate, a tensile strain in the channel region increases the mobility of the electrons, and the increased mobility of the electrons can then be directly converted to a correspondingly increased conductivity, and thus the drive is increased. Current and operating speed. On the other hand, the compressive strain in the channel region increases the mobility of the hole, thereby providing the possibility of enhancing the performance of the P-type transistor. The introduction of stress or strain engineering into the fabrication of integrated circuits is a promising approach to further device generations, so for example, strained strains can be considered as "new" types of semiconductor materials, which makes it unnecessary to be expensive In the case of semiconductor materials, fast and powerful semiconductor devices are fabricated while still using many widely accepted fabrication techniques.

According to a promising method, stress can be generated by, for example, layers located adjacent to a transistor, a spacer element, etc., to induce a desired strain in the channel region. However, the process of generating strain in the channel region by applying a specific external stress may suffer from the problem that the external stress is not effectively converted into strain in the channel region. Thus, while providing significant advantages, the efficiency of the stress transfer mechanism may depend on the process and device specifications, and because the overlay may be significantly offset from the channel region, for a widely accepted standard transistor design May cause reduced performance The gain, thus reducing the resulting strain in the channel region. Therefore, recessed transistor architectures have been proposed to enhance lateral stress transfer.

Referring to Figures 1a through 1g, a conventional strategy for forming a recessed transistor architecture will now be described in more detail to explain the main advantages of the device architecture, and also to the silicon-on-insulator, in particular. SOI) problem.

FIG. 1a schematically illustrates an upper view of a semiconductor device 100 including a transistor element 150. The transistor element 150 typically includes a drain and source region 151 and a gate electrode 152 that may have been formed on the sidewalls of its individual sidewall spacers 153. Moreover, individual contacts 157 may extend substantially perpendicular to the pattern plane of Figure 1a to establish electrical connection of the drain and source regions 151 to respective higher wiring layers (not shown). Moreover, the individual dielectric materials used to passivate material 150 may not be shown in FIG. 1a so as not to unduly obscure the individual structures of transistor element 150.

Fig. 1b is a schematic cross-sectional view showing the semiconductor device 100 along the line 1b-1b of Fig. 1a. First, a substantially flat configuration is shown in Figure 1b to illustrate the advantages of the recessed transistor configuration, and will be explained in more detail with reference to Figures 1c through 1d. In FIG. 1b, the semiconductor device 100 includes a substrate 101, which is a bulk substrate, and a semiconductor layer 102 is included on the upper portion of the substrate 101. Thus, the transistor element 150 can represent a base transistor in which the drain and source regions 151 and corresponding channel regions 155 are electrically coupled to the substrate 101. Moreover, in this stage of fabrication, individual metal telluride regions 154 may also be formed on gate electrode 152 and on the drain and source. In the polar region 151, the corresponding lateral offset to the gate electrode 152 can be substantially defined by the spacer structure 153. For the sake of convenience, the metal telluride region 154 is not shown in Figure 1a.

Furthermore, a strain-inducing dielectric layer 103 (e.g., a tantalum nitride layer) is formed over the transistor element 150 to induce a desired type of strain in the channel region 155. Typically, the dielectric layer 103 can represent a portion of the interlayer dielectric material that is disposed to encapsulate the transistor 150 prior to forming individual wiring layers or metallization layers (not shown) that are provided to the semiconductor device The required electrical connection of individual circuit components in 100. When transistor 150 represents an N-channel transistor, the tensile strain in channel region 155 can significantly enhance the electron mobility therebetween, thereby providing enhanced transistor performance. In this case, the dielectric material of layer 103 can provide a high intrinsic tensile stress to mechanically transfer stress into channel region 155.

It will be appreciated that a high efficiency strain inducing mechanism can be used for P-channel transistors, such as providing buried germanium/germanium materials in individual drain and source regions 151, resulting in significant transistor improvements to PMOS transistors, However, in this case, a high compressive stress may be additionally provided to a suitable stressed dielectric material, such as layer 103, to further enhance the overall transistor performance. It is known that tantalum nitride can provide high intrinsic stress, wherein high intrinsic stress is obtained according to a widely accepted deposition technique of plasma assisted chemical vapor deposition (PECVD), in which extremely high compression values can be obtained, and individual The tensile strain is less significant. As a result, in the following, it can be assumed that the transistor 150 can represent an N-channel transistor whose performance is further improved to reduce the performance gain of the P-channel transistor and the N-channel transistor by strain engineering techniques. Unbalanced. For example, individual mechanical transfer of stress enhancement to the channel region 155 can be enhanced by recessing the drain and source regions 151 to provide an increased "direct" stress component that substantially acts laterally on the channel region 155.

Figure 1c schematically shows a semiconductor device 100 comprising a transistor 150 having recessed drain and source regions 151. That is, the drain and source regions 151 include a surface portion 151R that is significantly lower relative to the channel region 155 when compared to the substantially planar configuration as shown in Figure 1b. The height level. Thus, the stressed material of layer 103 can act in a substantial lateral direction, as previously described. In addition, the recessed architecture provides increased surface area of the metal telluride region 154 in the drain and source regions 151 because additional sidewalls of the recessed drain and source regions 151 may be obtained during corresponding deuteration. The area is 151s. As such, the overall series resistance of the transistor 150 can be reduced as compared to the planar configuration shown in FIG. 1b.

For this reason, the corresponding fabrication sequence for forming the transistor element 150 as shown in FIG. 1b can be suitably modified to introduce additional process steps for forming corresponding recesses in the drain and source regions 151. The transistor structure as shown in Figure 1c. For example, a widely accepted process technique can be used to form the transistor 150 shown in FIG. 1c in a state where the drain and source regions 151 are to be formed in the semiconductor layer 102. During the corresponding process sequence, the implantation sequence can be suitably designed to achieve the desired depth of the drain and source regions 151 to account for the desired degree of recession to be formed therein. From the description given above, it can be understood that due to the increased efficiency of stress transfer and the amount of metal telluride added in zone 154, The increased depth of face 151R may result in increased performance gain. Thus, in a base transistor configuration as shown in FIG. 1c, a conventionally tailored process technique can be used to achieve a desired recess depth for the drain and source regions 151, which can be appropriately designed. The etching process is formed. Other transistor elements, such as P-channel transistors or any other transistor that does not require a recessed configuration, may be suitably covered by a corresponding etch mask during the corresponding etch process. Thereafter, further processing can be continued in accordance with widely accepted techniques, for example, by forming a metal halide region and depositing a dielectric layer 103 in accordance with appropriate deposition parameters to achieve the desired high degree of intrinsic stress. Thereafter, an interlayer dielectric material 104 such as hafnium oxide can be deposited according to widely accepted techniques.

Fig. 1d schematically shows the transistor 150 according to Fig. 1c shown in the cross-sectional view indicated by the Id-Id line in Fig. 1a. Thus, contacts 157, which may be comprised of any suitable electrically conductive material, such as tungsten, copper, silver, or any other material and alloy, may extend through interlayer dielectric material 104 and force layer 103 to metal halide region 154. Contact 157 can be formed in accordance with an anisotropic etch process, wherein layer 103 can be effectively used as an etch stop material for first patterning the material 104. Thereafter, layer 103 can be opened and the resulting opening can then be filled with the desired conductive material. Thus, in terms of strain and series resistance, significant advantages can be obtained by the configuration of the recesses, wherein the respective performance gains are substantially determined by the depth of the individual drain and source regions 151. The depth is substantially limited by the location of the PN junction of the drain and source regions 151 because the metal telluride region 154 must not extend beyond the individual PN junctions. Thus, in the matrix structure, individual electricity can be modified. The crystal is designed to achieve the desired depth of the drain and source regions 151 by appropriately designing individual dopant profiles without shorting individual PN junctions.

Referring to Figures 1e through 1g, other advantages of the recessed transistor configuration will be shown. In Figure 1e, semiconductor device 100 includes adjacent transistor elements 150A, 150B in accordance with a planar configuration, wherein each transistor 150A, 150B may substantially correspond to the transistor shown in Figure 1d. In this configuration, the contacts 157 can be positioned between the two transistors 150A, 150B, wherein the metal telluride region 154 can provide sufficient drive current capability to avoid undue increase in series resistance because it can be avoided The significant current in the metal telluride region 154 is congested, but the conductivity of the junction 157 may be significantly higher than the conductivity of the metal telluride in the region 154, and the conductivity of the metal telluride is more buckling. The conductivity of the source region 151 is significantly higher.

Figure 1f schematically shows a further application of the semiconductor device 100 in which the corresponding spacing between adjacent transistors 150A, 150B can be significantly reduced, resulting in a significant reduction in the lateral extension of the metal telluride region 154 and the contact 157. proportion. In the example shown in Figure 1f, this ratio may even become closer to 1, resulting in significant current congestion within the metal telluride material, which may undesirably reduce the semiconductor device 100 due to increased current congestion at portion 137A. Overall performance.

Figure 1g schematically shows a semiconductor device 100 similar to Figure 1f, however where a recessed drain and source stack are used, as previously described with reference to Figures 1c and 1d. Obviously, due to the increased interface between area 157A between junction 157 and metal telluride region 154, it can be avoided or At least the improperly increased series resistance is reduced, thereby also making it advantageous to have the recessed drain and source structures in a semiconductor device that requires a reduced spacing between adjacent transistor elements.

In principle, the recessed transistor structure can also facilitate the SOI device environment, however, wherein the depth of the recessed SOI structure is initiated by a semiconductor layer formed over a buried insulating layer. Thickness is limited. Thus, it has been proposed to etch a recess close to the buried insulating layer but still retain sufficient enthalpy required for subsequent deuteration processes. That is, in order to maintain the integrity of the telluride, the residual layer is maintained, and the thickness of the residual layer is substantially determined by the thickness of the telluride required to obtain the desired low gate resistance in the gate electrode. For example, in modern SOI transistors with recessed drain/source configurations, a minimum thickness of about 20 mm may be required to provide process uniformity and telluride integrity. Therefore, there is still room for improvement in the performance of SOI transistors having recessed drain/source structures.

The present disclosure is directed to various methods and apparatus that can avoid or at least reduce the effects of one or more of the problems discussed above.

In order to provide a basic understanding of certain aspects of the invention, the following simplified summary is presented. This Summary is not an extensive overview of the invention, and is not intended to identify key or critical elements of the invention or the scope of the invention. The sole purpose of the invention is to .

In general, the subject matter disclosed herein relates to SOI transistors by providing a reduced "tap and source length" SOI transistor. Techniques for enhancing the efficacy of a transistor by increasing the stress transfer mechanism and/or reducing the series resistance in the crystal, thereby providing the possibility of forming a strain inducing material laterally adjacent to the drain and source regions under the buried insulating layer. As a result, the strain inducing material can act laterally along substantially the entire depth of the adjacent drain and source regions, thereby significantly increasing the overall strain in the individual channel regions. In some aspects, a portion of the buried insulating layer can be exposed to a high degree of compatibility with other process technologies to form a recessed drain/source structure, thereby not unnecessarily adding additional Process complexity. In other aspects, individual process steps can be introduced at any suitable stage of manufacture so as not to unduly affect the overall process sequence and transistor characteristics.

An exemplary semiconductor device disclosed herein includes a transistor formed over a buried insulating layer, wherein the transistor includes a drain and a source region in a semiconductor material formed over the buried insulating layer. The semiconductor device further includes a strain inducing layer formed over the transistor, wherein the strain inducing layer substantially extends to the buried insulating layer adjacent to the drain and source regions.

In one exemplary method disclosed herein, the recess is laterally offset from the gate electrode structure of the transistor to be formed in the germanium-containing semiconductor layer, the germanium-containing semiconductor layer being formed on the buried insulating layer. The method further includes performing a heat treatment in the hydrogen-containing environment to initiate a material flow in the recess to substantially expose a portion of the buried insulating layer.

In another exemplary method disclosed herein, the recess is formed by offsetting a gate electrode of a field effect transistor, wherein the gate electrode is over a semiconductor layer formed over the buried insulating layer, wherein the recess Substantially extend to the Embed the insulation layer. The method further includes forming a drain region and a source region adjacent to the gate electrode, and forming a dielectric strain inducing layer over the field effect transistor and in the recess.

Various illustrative embodiments of the invention are described below. For the sake of clarity, this specification does not describe all of the features of the actual implementation. Of course, it should be understood that in the development of any such actual embodiment, a number of implementation-specific decisions must be made in order to achieve the inventor's specific objectives, such as system-dependent changes that vary from embodiment to embodiment. And business-related restrictions. Moreover, it should be appreciated that such development work can be complex and time consuming, however, it will still be a routine undertaking for those of ordinary skill in the art having the benefit of the teachings of the present invention. .

The invention will now be described with reference to the accompanying figures. The various structures, systems, and devices are illustrated in the drawings for purposes of illustration only and are not intended to be However, the accompanying drawings are included to illustrate and explain exemplary embodiments of the present disclosure. The vocabulary and words in this article should be understood and interpreted in a sense that is familiar to the artist. The terms and vocabulary used consistently throughout this document do not imply a particular definition, and a particular definition is a definition that is different from the ordinary customary definitions that are familiar to the skilled person. If a term or vocabulary has a specific definition, that is, it is not intended to be familiar to those skilled in the art, the specification will provide its definition directly and unambiguously.

In general, the subject matter disclosed herein solves the limited thickness and formation of recessed bucks and layers of active semiconductor layers in SOI transistors. The source region combines the problems caused by the effective metal halide region. For this purpose, aspects of the subject matter disclosed herein are related to fabrication techniques in which a recess can be formed adjacent to the drain and source regions, which recess can extend substantially completely down to the buried insulating layer. At the same time, sufficient process margin is still provided during subsequent metal halide processing. As a result, after the formation of the metal telluride region, the corresponding strain-inducing dielectric material can be deposited over the substantially exposed portion of the buried insulating layer, as compared to conventional recessed drain/sources in SOI devices. The architecture significantly enhances the total stress transfer mechanism. Moreover, because of the further device scaling, the overall conductivity from the individual contact portions in the entry channel region can be enhanced and thus the spacing between adjacent transistor elements can be reduced, as compared to conventional designs as previously described. Does not unduly reduce total transistor performance. Because the entire effective depth of the active semiconductor layer in the SOI fabric can be utilized in the stress transfer mechanism, it can be based on the internal stress of the corresponding dielectric material to be filled in the recess formed adjacent to the drain and source regions. Achieve an appropriate adjustment of the total strain in individual SOI transistors. As a result, it can be provided for adjusting individual strains according to a single process step, i.e., deposition of a stressed dielectric material that can be readily provided to achieve a desired degree of strain in various device regions. The wide bandwidth of the feature.

In some aspects, the principles disclosed herein can be applied in a highly selective manner to provide significant performance gains in the selected transistor device while substantially not affecting other transistor devices. For example, the techniques disclosed herein can be advantageously applied to N-channel transistors to provide strainers by stressing dielectric materials based on individual SOI transistors. The high performance gain gained by the process technology. In this case, the imbalance between the N-channel transistor and the P-channel transistor with respect to the strain-inducing mechanism can be at least partially compensated by applying these techniques only to the N-channel transistor. In other exemplary embodiments, the techniques disclosed herein may be advantageously applied to P-channel transistors and N-channel transistors that provide the possibility of obtaining enhanced transistor performance based on a single strain-initiating mechanism while providing enhancement The series conductivity is as described above. In still other aspects, the techniques disclosed herein may advantageously incorporate additional strain inducing sources, such as semiconductor alloys disposed in the drain and source regions and/or channel regions.

As such, the subject matter disclosed herein should not be construed as limited to a single type of transistor, but in the exemplary embodiments disclosed herein may be an N-channel transistor of SOI.

Figure 2a schematically shows a cross-sectional view of a semiconductor device 200 comprising a substrate 201, which may represent any carrier material used to form a transistor device in accordance with the SOI configuration. For example, substrate 201 can represent a germanium substrate as is typically used in SOI devices. Furthermore, a buried insulating layer 205 including any suitable material (such as cerium oxide, tantalum nitride, etc.) is formed over the substrate 201, and the silicon-based semiconductor layer 202 and the substrate 201 are provided. Separate. The germanium-based semiconductor layer 202 can be represented by any suitable germanium-based material in a substantially crystalline structure, wherein the germanium-based material can be understood to include a semiconductor material having an effective amount of germanium (e.g., about 50 volume percent or more), and can also occur Other species, such as isoelectronic species, such as germanium, carbon, and the like, as well as dopants for adjusting the conductivity of the semiconductor layer 202. Semiconductor layer 202 and The buried insulating layer 205 below defines an SOI fabric, wherein it should be understood that the corresponding SOI fabric may not necessarily extend across the entire substrate 201, but may be locally limited to individual device areas, and in the individual device area The advantageous properties of the desired SOI transistor can be obtained. For example, transistor 250 can be represented by circuit components in functional blocks that require high operating speeds that can be provided by transistor 250 due to parasitic capacitance, enhanced performance SOI transistors, and the like. Among other device areas, when individual substrate transistors are considered to be preferred device operations, such as when considering static memory area or the like, the substrate structure can be provided, for example, by omitting the buried insulating layer 205.

In the illustrated embodiment, the transistor 250 can include individual drain and source regions 251 defined by a suitable lateral dopant profile that can also extend down to buried insulation. Layer 205. The channel region 255 is formed with a gate electrode structure 252 between the drain and source regions 251 and is separated from the channel region 255 by a gate insulating layer 256. In complex applications, the gate length of the gate electrode 252, that is, the horizontal extension in Figure 2a, can be about 50 nm and significantly less, such as 30 nm and less. The gate electrode 252 can be covered by a sidewall spacer structure 253, which can comprise any suitable material, such as tantalum nitride, hafnium oxide, or the like. For example, the spacer structure 253 can include one or more individual spacer elements that can be separated from each other by a separate liner material having a high etch selectivity with respect to the spacer material. In other cases, structure 253 can be formed from a substantially homogeneous material composition. Furthermore, for example, with a spacer structure A cap layer 259 of substantially the same material (e.g., tantalum nitride) may be formed on top of the gate electrode 252, wherein a separate substrate material 258, such as hafnium oxide or the like, may be provided.

The semiconductor device 200 as shown in Fig. 2a can be formed in accordance with the following processes. After providing (at least partially) the substrate 201 on which the buried insulating layer 205 and the semiconductor layer 202 have been formed, individual active regions may be defined in the layer 202, corresponding to a transistor area requiring a specific conductivity or other The area of the semiconductor. For this purpose, a suitable isolation structure (not shown) can be formed, after which the desired dopant concentration can be introduced to set the transistor characteristics, such as conductivity type, threshold voltage, and the like. Next, the gate electrode 252 and the gate insulating layer 256 can be formed according to widely accepted techniques in which complex oxidation and/or deposition techniques can be used for the material of the gate insulating layer 256, followed by deposition of a suitable gate electrode material. The gate electrode material may include individual cap materials, anti-reflecting coating (ARC) materials, and the like, as needed. For example, materials for cap layer 259 and substrate 258 can be formed prior to patterning the gate electrode material. Patterning can be performed according to complex lithography and etching techniques, while in other cases, gate electrode 252 can be formed at a later stage by forming a place holder structure, and The placeholder structure is removed at a later stage. For example, in some transistors, a strain inducing mechanism can be implemented, such as in the form of a semiconductor alloy of any suitable composition, to facilitate modification of the crystalline structure in at least a portion of the individual active regions. For example, if a compressive strain may be desired in a certain type of transistor (such as a P-channel transistor), individual recesses may be formed. The recesses can be refilled with epitaxially grown semiconductor materials such as ruthenium/iridium.

In the following, it can be assumed that the transistor 250 can represent an N-channel transistor that can receive the appropriate type of strain in the channel region 255 by the corresponding stressed dielectric material still to be formed, without providing Additional strain inducing sources. Thus, after patterning the gate electrode 252, it is possible to bond the substrate 258 (which may have a thickness in the range of about 2 to 5 nanometers) and the cap layer 259 (the cap layer 259 may have about 2 to 5 nm) A range of thicknesses can be performed while performing an individual implantation process, such as a halo implantation, a source/dip extension implant, and the like. For this purpose, a spacer structure 253 can be obtained by forming one or more additional spacer elements and then forming a suitable offset spacer, if desired. During the individual steps used to form the spacer elements, individual implantation processes can be formed to ultimately achieve the desired lateral doping profile of the drain and source regions 251.

Figure 2b schematically shows the semiconductor device 200 when exposed to an etch environment of the etch process 210. During the etch process 210, a recess 210R having a predetermined depth 210D may be formed in the drain and source regions 251, which may take into account subsequent modifications of the extent to which the drain and source regions are tapered in respect of being formed therein. The choice is based on the needs of the device, which will be explained later. For example, in some exemplary embodiments, the etch process 210 can be designed to exhibit a high degree of compatibility with the etch process used to form the recessed drain and source structures in the SOI device to maintain The desired thickness of layer 202 is as previously described. Therefore, in this case, it can be made Use a widely accepted process recipe. In one embodiment, the etch process 210 can be designed to simultaneously etch the material of the spacer structure 253 and the cap layer 259, wherein the etched front surface can be reliably terminated to the substrate 258, thereby when the gate electrode 252 is comprised of polysilicon Substantially avoiding improper damage to the gate electrode 252. In other exemplary embodiments, the etch process 210 can include a selective etch process to remove the material of the layer 202 and a subsequent selective etch step to remove portions of the cap layer 259 and structure 253. Individual selective etching formulations, such as tantalum, tantalum nitride, and hafnium oxide, are widely accepted in the art. When the other areas of the semiconductor device 200 do not need to accommodate the respective recesses 210R, the etching process 210 can be performed in accordance with a suitably designed etch mask (not shown). For example, if an individual transistor element that can include an additional strain inducing source (such as a buried semiconductor alloy, etc.) has been formed, the corresponding transistor does not need to further enhance the strain transfer mechanism provided by the covering force layer, and Therefore, the corresponding transistor can be covered by a resist mask or the like. In other exemplary embodiments, the recess 210R may be adjusted when the corresponding last desired strain amount can be adjusted by the amount of intrinsic stress of the corresponding dielectric material to be filled into the recess 210R in a later manufacturing stage. Formed in other types of transistors, such as P-channel transistors.

Figure 2c is a schematic representation of the semiconductor device 200 at a further manufacturing stage. Here, the device is subjected to a heat treatment 211 in the presence of a hydrogen atmosphere to initiate the material flow of any non-passivated bismuth-based material (i.e., the ruthenium material in layer 202), which is non-passivated. Bismuth based materials may not be temperature-resistant Material (such as spacer structure 253) is covered. The heat treatment may be carried out at a temperature ranging from 750 to 1000 ° C, or from 800 to 950 ° C, over a period of seconds to minutes, such as a period of from about 30 seconds to 5 minutes. During this "high temperature hydrogen bake", the bismuth based material will move to reduce its surface area as indicated by arrow 211A. In some exemplary embodiments, the heat treatment 211 may be performed in a state in which the transistor 250 has performed an individual annealing process for activating the dopant and curing the crystallization damage, while in other exemplary embodiments, the heat treatment 211 may be used. As a first step of re-crystallizing the damaged area in the drain and source regions 251, the corresponding dopant atoms are activated to some extent. It will be appreciated that material stream 211A can be substantially confined to the exposed ruthenium area, where the total exposed surface area can be reduced each. For example, in a substantially flat exposed enamel-containing region that may be subjected to heat treatment 211, only reduced material flow may be observed, or in other embodiments, individual exposed portions may be coated with a suitable material, such as dioxide. Covered by tantalum, tantalum nitride, etc.

Fig. 2d schematically shows the semiconductor device 200 after the heat treatment 211. As shown, material flow 211A may result in the removal of material previously covering layer 202 of buried insulating layer 205, and may accumulate adjacent to the reduced total surface area of the drain and source regions including recess 210R. Gate electrode structure. Thus, due to the previous heat treatment 211, the previously recessed drain and source regions 251 may include additional portions 251A having substantially trapezoidal edges 251S. As a result, the individual portions 205A of the buried insulating layer 205 can be substantially exposed during the heat treatment 211, thereby also reducing the effective "long" of the drain and source regions 251 at a level corresponding to the buried insulating layer 205. Degree 251 L. Since the corresponding dopant atoms in the ruthenium-based material may have also been transferred to the additional portion 251A, the desired high dopant concentration may still be maintained over the entire drain and source regions 251 having a reduced length. Furthermore, portion 251A is now available for subsequent deuteration processes and can provide sufficient processing margin to avoid improper shorting of individual PN junctions, substantially independent of the degree of deuteration required by gate electrode 252. In order to reduce its resistance. Further, by appropriately adjusting the depth 210D of the recess 210R (Fig. 2b), the amount of the bismuth-based material in the drain and source regions 251 can be adjusted, thereby providing an appropriate adjustment of the additional portion. The possibility of 251A size, and thus the offset from the edge 251S of the individual PN junctions. Therefore, individual deuteration processes may not cause improper germanium growth in the drain and source regions 251, which Inadequate telluride creates the risk of shorting the PN junction.

Figure 2e is a schematic representation of the semiconductor device 200 at a further stage of fabrication. Individual metal telluride regions 254 are formed in gate electrode 252 and additional portion 251S in accordance with the need for reduced gate resistance, as previously described. For the corresponding deuteration process, a widely accepted process technique can be used in which non-reactive metals (e.g., nickel, platinum, cobalt, etc.) that can be used to form the metal telluride region 254 can be self-irritating (e.g., buried insulating layer). Portion 205A of 205 and spacer 253) are effectively removed. If it is desired to further reduce the series resistance, and/or even further enhance the stress transfer, the width of the spacer structure 253 can be reduced by performing a separate selective etching process in accordance with the widely accepted etching recipe. In this case, depending on the extent of the spacer removal, the offset to the channel region 255 can be reduced. At the same time, the risk of shorting the PN junction in the lower portion of the drain and source regions 251 due to the additional portion 251A can still be avoided.

After the metal halide region 254 is formed, the stressed dielectric material 203 can be provided in accordance with widely accepted techniques. For example, in the illustrated embodiment, layer 203 can include a high tensile stress dielectric material to create individual tensile strains in channel region 255. Since the highly stressed layer 203 can be formed along the entire depth of the drain and source regions 251, and can be in contact with the buried insulating layer 205, that is, a portion 205A of the significantly enhanced stress transfer mechanism can be achieved. In some exemplary embodiments (not shown), another etch process can be performed in device 200 as shown in FIG. 2d to selectively remove from exposed portion 205A of the buried insulating layer in accordance with a selective etch process. material. In this case, the highly stressed material of layer 203 may even extend beyond the drain and source regions 251, thereby further enhancing the overall strain inducing mechanism. During the corresponding etching process, if the material of the isolation structure is substantially composed of the same material as the buried insulating layer 205, the material of the isolation structure may also be removed, because the corresponding material may be subsequently used by the material of the layer 203. Instead, the above practices are acceptable.

Figure 2f schematically shows a cross-sectional view of the semiconductor device 200 along a plane provided with individual contacts 253, similar to the cross-sectional view shown by lines 1d-1d in Figure 1a. Due to the generally tapered shape of the individual edges 251S, it is apparent that the contacts 257 can form an increased interface area with the edges 251S of the metal telluride regions 254 in the drain and source regions 251. Even for the slightly misaligned contacts 257, a significant overlap between the contacts 257 and the individual metal halide regions 254 can be obtained to facilitate Significant current crowding, as previously described with reference to the conventional organization. Thus, junction 257 can be bonded to metal germanide region 254 in drain and source regions 251, thereby forming an angle defined substantially to the extent that the drain and source regions 251 are tapered. For example, the corresponding angle can range from about 20 to 60 degrees.

The 2g diagram schematically shows the advantages of the semiconductor device 200 having a recessed drain/source configuration transistor as described with reference to Figures 1b and 1c, for example. It is apparent that due to the additional height 230, that is, the difference between the thickness of the initial layer 202 and the recess 203A of the conventional transistor shown on the left hand side, the height difference can be used to transfer from the force layer 202 to form the drain. The lateral stress transfer of the semiconductor material with source region 251 and channel region 255 can enhance the corresponding total transistor performance compared to device 100. Furthermore, the entire sidewall area down to the edge 251S of the buried insulating layer 205 can be used for current flow, thereby effectively reducing the series resistance in the transistor 250.

Figure 2h schematically shows the semiconductor device 200 when including closely spaced transistors 250A, 250B, each of which may have substantially the same configuration as the transistor 250 described above. As shown, the contacts 257 can encounter respective increased sidewall areas of the edges 251S such that current can flow from the contacts 257 into the metal halide region 254 down to the buried insulating layer 205, thereby even being closely spaced apart. In the case where contacts are provided between the crystals, any problems with current congestion are also significantly alleviated.

Referring to Figures 3a through 3d, another illustrative embodiment will now be described in which the exposed portions of the buried insulating layer can occur at an earlier stage of fabrication.

Figure 3a schematically shows a semiconductor device 300 comprising a transistor 350 in an early stage of fabrication. The transistor 350 may include a substrate 301 including a buried insulating layer 305 having a germanium-based semiconductor layer 302 formed thereon. Furthermore, the gate electrode 352 may be formed over the semiconductor layer 302 and may be separated from the semiconductor layer 302 by the gate insulating layer 356. With regard to the components currently described, the same criteria as previously described with reference to devices 100 and 200 can be applied. Moreover, in this stage of fabrication, the gate electrode 352 can be covered by a suitably designed sidewall spacer structure 353 and cap layer 359, wherein a corresponding substrate 358 can be provided if desired. It should be appreciated that in some exemplary embodiments, semiconductor device 300 may include other transistor areas in which recesses may have to be formed to incorporate individual semiconductor alloys, such as ruthenium/iridium, and the like. Thus, the respective sidewall spacers 353 and cap layer 359 can also be provided in other transistor areas. The spacer 353 can be formed in accordance with the widely accepted spacer fabrication technique (i.e., by depositing a suitable material, such as tantalum nitride) in a conformally manner, possibly in combination with a suitable substrate material (not shown) And the material is anisotropically etched to obtain the final spacer 353. The cap layer 359 can be formed in accordance with the process techniques described above with reference to the cap layer 259.

Device 300 can then be subjected to an etch process 310 to remove material from the exposed portions of semiconductor layer 302. For this purpose, widely accepted etching formulations can be used with this technology.

FIG. 3b schematically shows the semiconductor device 300 after the etching process 310 and after removing the spacer structure 353 and the cap layer 359. Therefore, individual A recess 310R can be formed in layer 302, wherein the size and volume of recess 310R can correspond to the size and volume required for other transistor types, such as P-channel transistors, which can accommodate corresponding 矽/锗 material. In other cases, the size of the recess 310R and, in particular, the offset to the gate electrode 352 can be selected in accordance with the desired specifications of the last desired drain and source length.

Figure 3c is a schematic illustration of a semiconductor device 300 in a further fabrication stage in which individual offset spacers 353A can be formed on the sidewalls of the gate electrode 352, which has the purpose of defining individual gates for subsequent use. And the width required to implant the source extension process. Spacer 353A can be formed according to widely accepted techniques, such as by depositing a suitable material, such as ruthenium dioxide or the like. Furthermore, device 300 can be subjected to heat treatment 311 in the presence of hydrogen, as previously described, to reconfigure the semiconductor material in layer 302, thereby initiating correspondence due to the tendency of the material to reduce its surface area. Material flow, as explained above. As a result, the process 311 can result in a substantially exposed portion 305A of the buried insulating layer 305, thereby effectively reducing the length of the drain and source regions still to be formed. As such, the heat treatment 311 may not substantially affect the finally obtained dopant distribution because the respective PN junctions may be formed after the heat treatment 311. Corresponding implant processes can be performed in accordance with appropriate dopant species to define respective extension regions in the material of layer 302.

Figure 3d schematically shows the semiconductor device 300 in a further manufacturing stage. As shown, respective extensions 351E can be formed in layer 302 as previously described. Furthermore, a spacer junction comprising substrate 353C can be provided Structure 353B. The spacer 353B of the bonding substrate 353C may be formed according to a widely accepted technique, that is, the material 353C may be deposited according to any suitable deposition technique, such as chemical vapor deposition (CVD) in the form of cerium oxide, etc., to provide High etch selectivity for the material of spacer 353B. Thereafter, the spacer material can be deposited in a highly conformal manner, and then an anisotropic etch process can be performed to obtain the respective spacer elements. It will be appreciated that due to the sloped surface 351S, the corresponding material removal during the anisotropic etch process may be less effective than the substantially horizontal surface portion. As a result, individual etching processes may perform some degree of over-etch time to completely remove material from surface portion 351S. In this case, the height of the spacer 353B can be reduced, but this does not substantially adversely affect the further process. In other exemplary embodiments, subsequent to the anisotropic etch process, a short highly selective isotropic etch process can be performed to substantially completely remove any material remaining in the slanted sidewall portions 351S. For example, a corresponding isotropic etch process can be performed in accordance with the corresponding etch mask, which can cover other device areas that may not accept an isotropic etch process. The corresponding etch mask can then also define individual drain and source regions 351 for subsequent ion implantation 312 based on widely accepted implant parameters. Thereafter, further processing can be continued as previously described, and also by the respective annealing cycles to activate the dopants in the drain and source regions 351 and to cure the lattice damage. Thereafter, a separate cleaning process can be performed to prepare an exposed surface portion for the metal telluride process. As a result, an advantageous transistor structure that reduces the length of the drain and the source can be provided according to the heat treatment 311 at an early manufacturing stage, thereby substantially avoiding the Any undue influence of the diffusion of the dopant without substantially causing undue process complexity. It will be appreciated that the corresponding process for forming the recess 310R can advantageously be combined with recesses formed in other device areas, such as P-channel transistors, thereby enhancing process uniformity during the corresponding etching process. If a subsequent selective epitaxial growth process can be performed in other device areas, a corresponding growth mask can be formed in the recess 310, such as according to a suitably selected material layer, such as hafnium oxide and tantalum nitride. The material layer can be selectively formed in the transistor 350 by oxidation, deposition, or the like.

Referring to Figures 4a through 4b, another illustrative embodiment will now be described in which the drain and source structures can be modified in accordance with an etch process to expose a portion of the buried insulating layer.

Figure 4a schematically shows a semiconductor device 400 comprising a transistor 450 having substantially the same organization as the transistor 250 shown in Figure 2a. Accordingly, the device may include a substrate 401, a buried insulating layer 405, and a semiconductor layer 402. The transistor 450 can include a gate electrode 452 formed over the gate insulating layer 456 that separates the gate electrode from the channel region 455 surrounded by individual drain and source regions 451. A sidewall spacer structure 453, which may comprise a suitable substrate material, may be formed on the sidewalls of the gate electrode 452, which may be covered by bonding the etch stop layer 458 and the cap layer 459. The components described so far can be formed according to the same process as explained above.

Next, a spacer layer 440 can be formed prior to recessing the drain and source regions 451, wherein the thickness of the spacer layer 440 can be selected to obtain The desired offset of the PN junction in the pole and source regions 451. The spacer layer 440 can be formed of any suitable material and, in some exemplary embodiments, can be comprised of a material having substantially the same etch rate as the spacer 453 and cap layer 459 materials. Next, an anisotropic etch process can be performed that removes the material of the spacer layer 440 and the material that encapsulates the gate electrode 452 while also removing the material of the semiconductor layer 402. For example, an anisotropic etch process can be performed in which the respective processing parameters and etch components can be suitably adapted at a stage prior to the etch process to obtain enhanced isotropic components during the etch process. Thus, during the etching process that is performed, a substantially tapered shape corresponding to the recess can be obtained. The etching process can be continued until a portion of the buried insulating layer 405 is exposed.

Figure 4b is a schematic representation of the semiconductor device 400 after the corresponding etch sequence. Therefore, due to the isotropic composition of the previous etching process, the recess 410R extending down to the buried insulating layer 405 can be formed by the inclined sidewall portions adjacent to the drain and source regions 451. Furthermore, the width of the spacer 453 may also have been reduced in the isotropic phase of the previous etching process. However, the corresponding substrate material can reliably prevent exposure of the gate electrode 452 and can also provide the desired offset for subsequent deuteration processes. Thus, according to the configuration shown in Figure 4b, further processing can be continued by forming individual metal germanide regions and forming strained dielectric material in recess 410R, as previously described.

As a result, the subject matter disclosed herein provides a technique and individual semiconductor devices obtained by this technique in which recesses are recessed prior to formation of individual metal telluride regions and strained dielectric materials. The pole and source regions are substantially down to the buried insulating layer, and the transistor characteristics of the SOI device can be significantly enhanced. In some aspects, this may be based on a heat treatment in a hydrogen-containing environment at a suitable temperature to initiate a flow of material due to the tendency of the material to reduce its surface. Thus, it is possible to provide a tapered drain and source region having a reduced effective length, whereby the material is substantially completely removed from the buried insulating layer such that the corresponding stressed material can advantageously act on the entire depth thereof. On the pole and source areas. Thus, enhanced resistance transfer and reduced series resistance can be obtained even for highly scaled semiconductor devices including closely spaced transistor elements. The technique of "reducing the effective gate length" can be used for N-channel transistors and P-channel transistors, wherein, in some exemplary embodiments, the techniques disclosed herein may be advantageously applied to N-channel transistors for use. An additional strain inducing source of this type of transistor is effective to effectively reduce the performance gain imbalance between the P-channel transistor and the N-channel transistor. The corresponding process steps used to initiate the material flow can be incorporated at any suitable stage without unduly affecting the overall process sequence. In still other embodiments, removing material from the drain and source regions to expose a portion of the buried insulating layer can be accomplished in accordance with an etch process that can be performed at any suitable stage of fabrication, such as after completion. After the pole and source regions, without unduly affecting the overall process sequence.

The specific embodiments disclosed above are intended to be illustrative only, as the invention may be For example, the process steps set forth above can be performed in a different order. Again, the architecture shown here or The design details are not intended to be limiting, except as described in the appended claims. Therefore, it is apparent that the particular embodiments disclosed above and all such variations are contemplated within the spirit and scope of the invention. Thus, the Applicants of the present invention are as set forth in the appended claims.

100‧‧‧Semiconductor device

101‧‧‧Substrate

102‧‧‧Semiconductor layer

103‧‧‧Dielectric layer, layer

Section 137A‧‧‧

150‧‧‧Optoelectronic components, transistors

150A, 150B‧‧‧Optoelectronic components, transistors

151‧‧‧Bungee and source areas

151R‧‧‧Surface part

151S‧‧‧Additional sidewall area

152‧‧‧gate electrode

153‧‧‧ Sidewall spacers, spacer structure

154‧‧‧Metal Telluride Zone

155‧‧‧Channel area

157‧‧‧Contacts

157A‧‧‧ area

200‧‧‧Semiconductor device

201‧‧‧Substrate

202‧‧‧Semiconductor layer

203‧‧‧Dielectric materials, layers

205‧‧‧ buried insulation

205A‧‧‧ part of the buried insulation

210‧‧‧ etching process

210D‧‧‧Deep

210R‧‧‧ recess

211‧‧‧ heat treatment

211A‧‧‧Arrow, material flow

230‧‧‧ Height

232‧‧‧gate insulation

250, 250A, 250B‧‧‧ transistors

251‧‧‧Bungee and source regions

251A‧‧‧Additional part

251L‧‧‧effective "length"

251S‧‧‧ edge, extra part

252‧‧ ‧ gate electrode structure, gate electrode

253‧‧‧ Sidewall spacer structure

254‧‧‧Metal Telluride Zone

255‧‧‧Channel area

256‧‧‧ gate insulation

257‧‧‧Contacts

258‧‧‧substrate

259‧‧‧ cover

300‧‧‧Semiconductor device

301‧‧‧Substrate

302‧‧‧矽-based semiconductor layer

305‧‧‧ buried insulation

305A‧‧‧ exposed parts

310‧‧‧ etching process

310R‧‧‧ recess

311‧‧‧ heat treatment

312‧‧‧Ion implantation

350‧‧‧Optoelectronics

351‧‧‧Bungee and source areas

351E‧‧‧Extension

351S‧‧‧Slanted, sloping side wall section

352‧‧‧gate electrode

353‧‧‧ sidewall spacer structure

353A‧‧‧Offset spacer

353B‧‧‧ spacer structure containing substrate

353C‧‧‧Substrate

356‧‧‧ gate insulation

358‧‧‧Substrate

359‧‧‧ cover

400‧‧‧Semiconductor device

401‧‧‧Substrate

402‧‧‧Semiconductor layer

405‧‧‧ buried insulation

410R‧‧‧ recess

440‧‧‧ spacer layer

450‧‧‧Optoelectronics

451‧‧‧Bungee and source areas

452‧‧ ‧ gate electrode

453‧‧‧ sidewall spacer structure

455‧‧‧Channel area

456‧‧‧gate insulation

458‧‧‧etch stop layer

459‧‧‧ cover

The invention may be understood by the following description in conjunction with the accompanying drawings, wherein the same reference numerals represent the same elements, wherein: FIG. 1a schematically shows a top view of a conventional semiconductor device including a transistor; FIGS. 1b to 1c Illustratively showing a cross-sectional view of the transistor of the device of FIG. 1a in a substantially planar and concave drain/source configuration in a substrate structure; FIG. 1d schematically shows a cross section of the transistor shown in FIG. 1c. Figure 1e to 1f schematically show a base transistor element having a moderate width spacing and a narrow spacing between adjacent elements having a substantially planar source/drain configuration; Figure 1g schematically shows a narrow spacing therebetween a transistor element in which the recessed drain/source structure provides enhanced conductive characteristics; FIGS. 2a through 2f schematically illustrate the formation of a buried portion having substantial extension down to the SOI device during various stages of fabrication in accordance with an exemplary embodiment A cross-sectional view of the reduced length of the recess of the insulating layer and the transistor element of the source region; FIG. 2g schematically shows a recessed drain/source composition in accordance with an exemplary embodiment of the present invention Conventional SOI transistors, and reduced bungee And a source length transistor; FIG. 2h schematically shows a cross-sectional view of a semiconductor device including a transistor having a reduced interval therebetween in accordance with an exemplary embodiment; and FIGS. 3a through 3d schematically illustrate in accordance with another exemplary embodiment A cross-sectional view of a SOI transistor during various stages of fabrication, wherein a recess is formed in accordance with high temperature hydrogen bake at an early stage of fabrication; and 4a through 4b schematically show an SOI transistor used in accordance with yet another illustrative embodiment A cross-sectional view of the process sequence exposed to portions of the buried insulating layer in the drain and source regions.

While the subject matter disclosed herein is susceptible to various modifications and alternatives, the specific embodiments are shown by way of example in the drawings. It should be understood, however, that the description of the specific embodiments of the invention are not intended to Modifications, equivalences, and replacements.

200‧‧‧Semiconductor device

250A, 250B‧‧‧O crystal

252‧‧ ‧ gate electrode structure, gate electrode

254‧‧‧Metal Telluride Zone

257‧‧‧Contacts

Claims (19)

A semiconductor device comprising: a transistor formed over a buried insulating layer, the transistor comprising a drain and a source region in a semiconductor material formed on the buried insulating layer; and the drain and source a metal telluride region at the edge of the region, the metal halide region extending substantially to the buried insulating layer; and a strain inducing layer formed over the transistor and the metal halide region, the strain inducing layer substantially extending to The buried insulating layer adjacent to the drain and source regions. The semiconductor device of claim 1, wherein the semiconductor device comprises a contact filled with a conductive material, and a portion of the contact extends to the buried insulating layer. The semiconductor device of claim 1, wherein the semiconductor material has a dimension in the longitudinal direction of the transistor that is the largest at the buried insulating layer. The semiconductor device of claim 1, wherein the transistor represents an N-channel transistor. A method of fabricating a semiconductor device, comprising: forming a recess laterally offset from a gate electrode structure of a transistor in a germanium-containing semiconductor layer formed on a buried insulating layer; performing heat treatment in a hydrogen-containing environment to induce A stream of material in the recess to substantially expose a portion of the buried insulating layer. The method of claim 5, wherein the heat treatment is performed at a temperature ranging from about 750 degrees Celsius to 1000 degrees Celsius. The method of claim 5, further comprising forming a drain and a source region adjacent to the gate electrode structure prior to performing the heat treatment. The method of claim 7, further comprising forming a drain and a source region adjacent to the gate electrode structure after performing the heat treatment. The method of claim 7, further comprising forming a metal halide on the edge regions of the drain and source regions after performing the heat treatment, the metal halide extending to the buried insulating layer. The method of claim 9, wherein the method comprises forming a strain inducing layer over the transistor, the strain inducing layer extending into the recess. The method of claim 10, wherein the strain inducing layer is formed to induce tensile strain. The method of claim 5, further comprising providing a cap layer over the gate electrode prior to forming the recess. The method of claim 12, wherein forming the recess comprises etching the semiconductor layer and the cap layer in a common etching process. The method of claim 8, wherein forming the recess comprises masking the gate electrode structure and etching the semiconductor material to a predetermined depth. The method of claim 14, further comprising removing a portion of the material for masking the gate electrode structure and performing the heat treatment. A method of fabricating a semiconductor device, comprising: forming a recess offset from a gate electrode of a field effect transistor, the gate electrode being over a semiconductor layer formed over a buried insulating layer, the recess extending to the buried Insulating layer; Forming a drain region and a source region adjacent to the gate electrode; performing a heat treatment for inducing a material flow in the recess to expose a portion of the buried insulating layer; and over the field effect transistor A dielectric strain inducing layer is formed in the recess. The method of claim 16, wherein forming the recess comprises etching the semiconductor layer to a predetermined depth and performing a heat treatment in a hydrogen-containing environment to expose a portion of the buried insulating layer. The method of claim 16, wherein the recess is formed by etching the semiconductor layer to expose a portion of the buried insulating layer. The method of claim 18, wherein etching the semiconductor layer comprises performing an etching process including an isotropic etching step to obtain a tapered recess.