US10734531B2 - Two-dimensional electrostrictive field effect transistor (2D-EFET) - Google Patents
Two-dimensional electrostrictive field effect transistor (2D-EFET) Download PDFInfo
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- US10734531B2 US10734531B2 US15/945,207 US201815945207A US10734531B2 US 10734531 B2 US10734531 B2 US 10734531B2 US 201815945207 A US201815945207 A US 201815945207A US 10734531 B2 US10734531 B2 US 10734531B2
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Definitions
- the present invention is related to a device and method for manufacturing a two-dimensional electrostrictive field effect transistor having a substrate, a gate, a source, a drain, and a channel disposed between the source and the drain.
- the channel is a two-dimensional layered material.
- the gate has a column of an electrostrictive or piezoelectric or ferroelectric material, wherein an electrical input to the gate produces an elongation of the column that applies a force or stress on the channel and reduces the bandgap of the two-dimensional material.
- the change in the bandgap of the two dimensional material changes its conductivity such that the two-dimensional electrostrictive field effect transistor operates with subthreshold slope which is less than 60 mV/decade.
- MOSFET metal oxide semiconductor field effect transistor
- CMOS complementary metal oxide semiconductor
- tunneling FETs are the most matured candidates, which have experimentally demonstrated SS less than 60 mV/decade.
- the greatest challenge for tunneling FETs are their low ON state current densities limited by the large tunneling barriers.
- Piezoelectric strain modulated Si FinFETs are also promising but suffer from the limitation of the bulk nature of Si at the scaling limits.
- SS slope should be as abrupt as possible (ideally zero) to meet the low power requirement whereas the ON current should be as high as possible to increase the device's speed. Therefore, it would be desirable to overcome the above-discussed limitations and to provide a better solution.
- Certain embodiments of the present invention provide a disruptive device concept, which meets both low power and high performance criterion for post-CMOS computing and at the same time, enables aggressive channel length scaling.
- This device hereafter refer to as a two-dimensional electrostrictive field effect transistor or 2D-EFET, allows a sub-60 mV/decade subthreshold swing and a considerably higher ON current compared to any state of the art FETs. Additionally, by the virtue of its ultra-thin body nature and electrostatic integrity, the 2D-EFET enjoys scaling beyond 10 nm technology node. The 2D-EFET works on the principle of voltage induced strain transduction.
- Certain embodiments of the present invention provide a two-dimensional electrostrictive field effect transistor (2D-EFET) having a substrate, a gate, a source, a drain, and a channel disposed between the source and the drain.
- the channel is a two-dimensional layered material.
- the gate has a column of an electrostrictive or piezoelectric or ferroelectric material, wherein an electrical input to the gate produces an elongation of the column that applies a force or mechanical stress on the channel and reduces the bandgap of the two-dimensional material.
- Some embodiments of the 2D-EFET may further have a capping wherein the substrate, the gate, the source, the drain, and the channel are embedded.
- the consecutive layers of two-dimensional material may include a semiconductor MX 2 wherein M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn) and X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn)
- X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- the electrostrictive or piezoelectric or ferroelectric column may elongate and thereby transduce a compressive force on the channel.
- the channel transitions from an insulator or large bandgap semiconductor to a metal or smaller bandgap semiconductor.
- the channel may have a plurality of consecutive layers of the two-dimensional layered material.
- the 2D-EFET may have a capping, a substrate embedded inside the capping, a source embedded inside the capping, a drain embedded inside the capping, and a channel embedded inside the capping between the source and the drain.
- the channel is a two-dimensional layered material.
- the consecutive layers of the two-dimensional material may include a semiconductor MX 2 wherein M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn) and X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- the electrostrictive or piezoelectric or ferroelectric column may elongate and thereby transduce a compressive force on the channel.
- the channel transitions from an insulator or large bandgap semiconductor to a metal or smaller bandgap semiconductor.
- the channel may have a plurality of consecutive layers of the two-dimensional layered material.
- the channel may exhibit an insulator to metal transition or a large bandgap semiconductor to small bandgap semiconductor transition and vice versa in response to the application or removal of electrical voltage to the gate, such that the transistor exhibits a subthreshold swing of less than 60 mV/decade.
- Some embodiments of the two-dimensional electrostrictive field effect transistor according to the present invention may also have a dielectric formed on the gate such that the source, the drain, and the channel are disposed on the dielectric.
- This embodiment also has a back gate disposed on the substrate and the gate is formed on the back gate.
- Yet other embodiments of the 2D-FET according to the present invention may also have another gate with another column of an electrostrictive or piezoelectric or ferroelectric material.
- the electrical input to the another gate produces an elongation of the another column.
- the channel has a first surface and a second surface.
- the column of the gate is configured to apply the force on the first surface of the channel and the another gate is disposed such that the elongation of the another column applies another force on the second surface of the channel and reduces the bandgap of the two-dimensional layered material.
- Certain embodiments of the present invention provide a method of manufacturing a two-dimensional electrostrictive field effect transistor (2D-EFET) that has the steps of forming a substrate, forming a source, forming a drain, and forming a channel from two or more consecutive layers of two-dimensional material and disposing the channel between the source and the drain.
- the method also has a step of forming a gate proximate a channel and the gate may comprise a column of an electrostrictive or piezoelectric or ferroelectric material, wherein applying an electrical input to the gate produces an elongation of the column that applies a force on the channel and reduces the bandgap of the two-dimensional channel material.
- Some embodiments of the method may have the steps of providing a capping, and embedding the substrate, the gate, the source, the drain and the channel on the substrate.
- Another embodiment of the method may include steps of forming a dielectric between the gate and the channel and forming a back gate between the substrate and the gate.
- the column may be disposed between the back gate and the gate.
- Yet another embodiment of the method may have additional steps of forming a second gate, wherein the channel is disposed between the gate and the second gate.
- the second gate has a second column of an electrostrictive or piezoelectric or ferroelectric material. The second gate produces an elongation of the second column that applies a force or mechanical stress on the channel and reduces the bandgap of the two-dimensional layered material.
- FIG. 1 a is a cross-sectional block diagram of a 2D-EFET in an OFF state according to one embodiment of the present invention
- FIG. 1 b is a cross-sectional block diagram of a 2D-EFET in an ON state according to one embodiment of the present invention
- FIG. 1 c is a cross-section of a 2D channel with a plurality of cascaded consecutive layers of two-dimensional material
- FIG. 2 a is a graphical representation of strain (S) versus electric field ( ⁇ e ) characteristics of an electrostrictive material such as lead magnesium niobate-lead titanate (PMN-PT);
- FIG. 2 b is a graphical representation of bandgap (E G ) versus out-of-plane stress (P) characteristics of a 2D material (MoS 2 );
- FIG. 2 c is a cross-sectional block diagram of a 2D-EFET and its equivalent capacitive circuit network
- FIG. 2 d is a schematic showing band movement in a 2D-EFET in response to an applied gate bias (V GS );
- FIG. 3 g is a list of line styles corresponding to various values of ⁇ in FIGS. 3 a -3 f and FIGS. 4 a - 4 b;
- FIG. 4 c is a graphical representation of subthreshold swing (SS) as a function of ⁇ for different values of interface traps capacitance C IT ;
- FIG. 4 e is a graphical representation of room temperature output characteristics (I Ds versus V Ds ) for a 2D-EFET for different values of V GS ;
- FIG. 4 g is a list of line styles corresponding to various values of interface traps capacitance C IT in FIG. 4 c;
- FIG. 4 h is a list of line styles corresponding to various values of V DD in FIG. 4 f;
- FIG. 5 is a flow diagram depicting example operations that may be performed in accordance with a method of producing a 2D-EFET consistent with the present disclosure
- FIG. 6 is a cross-sectional block diagram of a 2D-EFET according to another embodiment of the present invention.
- FIG. 7 a shows simulated 2D-EFET characteristics of Total surface potential ⁇ T versus VG for different values of the strain transfer coefficient ⁇ ;
- FIG. 7 b shows simulated 2D-EFET characteristics of I D versus V G characteristics showing a sub 60 mV/dec subthreshold slope
- FIG. 7 c shows simulated 2D-EFET characteristics of subthreshold slope as a function of the strain transfer coefficient ⁇ ;
- FIG. 7 d shows simulated 2D-EFET characteristics of I D vs. V D characteristics showing saturation and dramatically increased ON currents
- FIG. 8 is a cross-sectional block diagram of a 2D-EFET according to another embodiment of the present invention.
- the present disclosure generally relates to 2D-EFETs that include a channel with bandgap characteristics altered by an application or removal of an electrical input.
- a two dimensional electrostrictive field effect transistor (2D-EFET) system and method according to the present invention may take a variety of forms.
- Various examples of the present invention are shown in the Figures. However, the present invention is not limited to the illustrated embodiments. Reference will now be made in detail to some embodiments of the present invention, examples of which are illustrated in the accompanying figures.
- a 2D-EFET consists of a source, a drain, and a channel disposed between the source and the drain.
- the channel consists of a two-dimensional (2D) material that has a large bandgap in an OFF state.
- the 2D-EFET also has a high-k insulating gate in the form of a layer of electrostrictive or piezoelectric or ferroelectric material deposited on the channel. When an electrical input is applied to the gate, the electrostrictive or piezoelectric or ferroelectric material expands and transduces an out-of-plane stress on the 2D channel.
- the out-of-plane stress due to expansion monotonically reduces the channel's bandgap to zero allowing current conduction between the source and the drain, and thus, switching 2D-EFET to an ON state.
- the 2D-EFET offers a steep subthreshold swing (SS) below 60 mV/decade owing to an internal-feedback mechanism giving rise to voltage amplification and provides significantly higher ON-state current density compared to any existing state of the art charge based device.
- SS subthreshold swing
- Two-dimensional (2D) layered semiconductors have an ultra-thin body that allows aggressive channel length scaling and hence high performance.
- the bandgap of multilayer Transition Metal Dichalcogenides (TMDs: a class of 2D materials) like MoS 2 , WSe 2 etc. can be dynamically reduced to zero by applying an out-of-plane stress.
- TMDs transition Metal Dichalcogenides
- the scalability of the 2D materials is combined with the stress induced dynamic bandgap engineering to form a device referred to herein as a Two Dimensional Electrostrictive Field Effect Transistor or 2D-EFET.
- FIG. 1 a is a cross-sectional block diagram of one embodiment of a Two-Dimensional Electrostrictive Field Effect Transistor, or 2D-EFET 10 , in the OFF state
- FIG. 1 b is a cross-sectional block diagram of a 2D-EFET 10 in an ON state.
- the 2D-EFET 10 includes a source 120 , a drain 130 , and a channel 160 .
- Channel 160 has a large bandgap E G in the OFF state.
- Channel 160 may be formed by transition metal dichalcogenide (TMD) two dimensional layers 140 that are bound to each other by van der Waals (vdW) attraction.
- TMD transition metal dichalcogenide
- vdW van der Waals
- the two-dimensional material 140 may consist of a semiconductor MX 2 , wherein M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn) and X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn)
- X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- the 2D-EFET 10 also consists of a substrate 110 and gate 150 . Source 120 , drain 130 , and channel 160 are disposed on the substrate 110 .
- Gate 150 includes a column of electrostrictive material that is deposited on channel 160 .
- the gate includes a contact or upper element 152 .
- the 2D-EFET operates with a large bandgap and prevents current conduction between the source 120 and drain 130 whereas in an ON state, it operates with a smaller or zero bandgap and allows current conduction.
- the electrostrictive material behaves like a high-k insulating gate oxide but undergoes a longitudinal expansion when an electric field is applied across it. Electrostrictive materials exhibit a dimensional change upon application of an electric field due to the energy increase associated with the polarization induced by the electric field in the material.
- this is a form of elastic deformation of an electrostrictive material induced by an electric field.
- This dimensional change transduces an out-of-plane stress on the 2D channel material and monotonically reduces its bandgap to zero.
- the electrostrictive material of gate 150 has a length L 1 when the V GS (Voltage Gate to Source) is zero.
- V GS Voltage Gate to Source
- the stress produced by the expansion of electrostrictive material 150 from L 1 to L 2 is transferred to channel 160 resulting in its compression.
- This compression brings the consecutive layers 140 of channel 160 closer and reduces the bandgap E G .
- Reduced bandgap E G allows current conduction between source 120 and drain 130 , and the 2D-EFET switches to its ON state.
- the 2D-EFET offers a steep subthreshold swing (SS) below 60 mV/decade owing to an internal-feedback mechanism giving rise to voltage amplification and provides a significantly higher ON-state current density compared to any existing charge based device.
- SS subthreshold swing
- the amount of deformation of the electrostrictive material may vary depending on the composition of the electrostrictive material and/or the gate electrical input V GS .
- the amount of elongation of the electrostrictive material is such that the channel 160 with a large bandgap (as shown in FIG. 1 a ) transitions into channel 160 that has a small bandgap (as shown in FIG. 1 b ).
- the amount of elongation of the electrostrictive material is such that the bandgap of the channel 160 substantially reduces to zero and thereby exhibit characteristics of a metal in the ON state.
- channel 160 of some embodiments of the present disclosure may have a plurality of cascaded consecutive layers 140 of the two-dimensional material in 2D-EFET 10 .
- FIG. 2 a is a graphical representation of strain (S) versus electric field ( ⁇ ) characteristics (equation 1) of an electrostrictive material
- FIG. 2 b is a graphical representation of bandgap (E G ) versus out-of-plane stress (P) characteristics (equation 2) of a 2D material based on the phenomenological models.
- S ⁇ (1)
- E G E G0 ⁇ P (2)
- the ⁇ parameter for the 2D-EFET determines the efficiency of strain transduction and hence improvement in the subthreshold swings (SS).
- SS subthreshold swings
- FIG. 2 c is a cross-sectional block diagram of a 2D-EFET and its equivalent capacitive network model, where V GS is the applied external gate bias, ⁇ S is the electrostatic surface potential, and C E , C CH and C IT are respectively the capacitances associated with the electrostrictive material, the 2D channel material and the interface traps.
- FIG. 2 d is a schematic showing the position of the energy bands inside the 2D channel material corresponding to the OFF and ON state of the device during its operation.
- ⁇ S is the usual electrostatic component
- ⁇ E is the electrostrictive component.
- the electrostrictive component ⁇ E arises due to a reduction in the bandgap of the 2D material 160 in response to the out-of-plane stress transduced by the electrostrictive material 150 . This gives rise to internal voltage amplification, which is responsible for a steep subthreshold swing (SS) that is less than 60 mV/decade in 2D-EFETs. Note that the additional band movement ⁇ E appears due to the decrease in the bandgap of the channel material 160 through an electrostrictive transduction.
- SS subthreshold swing
- FIGS. 3 a -3 f are channel potential maps of the electrostatic potential ( ⁇ S ), electrostrictive potential ( ⁇ E ) and the total channel potential ( ⁇ T ) as a function of the external gate bias (V GS ) obtained by solving equations 4 through 6 self-consistently with equation 7.
- Equation 7 D(E) denotes the 2D density of states derived from the parabolic energy dispersion relationship, m*is the carrier effective mass, h is the Planck's constant, and f S (E) and f D (E) are the Fermi function for the source and drain contact electrodes, respectively.
- equation 8 represents the subthreshold swing (SS), wherein k B is the Boltzmann constant, q is the electronic charge, and T is the temperature.
- the feedback mechanism begins between the electrostatic and electrostrictive potentials since r ⁇ 1 owing to the finite channel capacitance (C CH ).
- C CH finite channel capacitance
- This leads to an internal voltage amplification ( ⁇ T >V GS ) in the ON state, wherein the dotted line represents ⁇ T V GS .
- this amplification is not conducive for the sub-60 mV/decade subthreshold swing (SS).
- the total channel potential ⁇ T increases monotonically according to FIG. 3 c .
- none of these scenarios are conducive for achieving the sub-60 mV/decade subthreshold swing (SS) since the internal voltage amplification ( ⁇ T > ⁇ S ) takes place only in the ON state of the device operation.
- the ⁇ values used to obtain the corresponding ⁇ values are 0.0, 0.2, 0.4, and 0.6, respectively.
- the ⁇ values used to obtain the corresponding ⁇ values are 0.0, 0.2, 0.4, and 0.6, respectively.
- FIGS. 4 a and 4 b show the transfer characteristics of the 2D-EFET obtained by solving equations 4 through 7 self consistently with the ballistic Landauer formalism (equation 9).
- I 1 and I 2 are the current due to electron injection from the drain and the source contacts, respectively and v(E) is the carrier velocity.
- SS sub-60 mV/decade subthreshold swing
- FIG. 4 c shows an average subthreshold swing (SS) (over 4 decades) as a function of ⁇ for different values of C IT . It should be noted that the sub-60 mV/decade subthreshold swing (SS) is obtained if and only if C IT >0 and ⁇ >1.
- FIG. 4 d shows the dynamic bandgap change as a function of the applied gate bias
- FIG. 4 g is a list of line styles corresponding to various values of C IT in FIG. 4 c
- FIG. 4 h is a list of line styles corresponding to various values of V DD in FIG. 4 f .
- the rectangular boxes in FIGS. 4 d and 4 e correlate the length of the saturation region with the dynamic bandgap of the 2D-EFET.
- FIG. 4 f shows the ON current (I ON ) and ON to OFF current ratio (I ON /I OFF ) for the 2D-EFET as a function of the flat band voltage (V FB ) for different supply voltages (V DD ). Ballistic Landauer formalism was used to compute the current versus voltage characteristics.
- the channel length (L G ) scalability of the 2D-EFET is determined through the band bending length ⁇ (equation 10), which is derived by solving 2D Poisson's equation similar to the conventional planar FETs.
- FIG. 5 is a flow diagram of example operations that may be performed in connection with a method of making a 2D-EFET consistent with the present disclosure. It should be understood that the method steps shown are illustrated in a particular order for the sake of clarity, but that in practice they may be performed in any order depending on the geometry and configuration of the 2D-EFET being formed.
- method 500 begins at the block 501 .
- a substrate is provided or formed, and at block 503 a source and a drain may be formed on a substrate, which may be made of metal or another suitable material.
- the formation of the source may be performed using any suitable semiconductor manufacturing technique, including various forms of deposition (e.g. thermal evaporation, electron beam evaporation, sputtering, chemical vapor deposition, physical vapor deposition, atomic layer deposition, electrodeposition, electroless deposition, etc.), as may be known in the art.
- a channel may be formed between the source and the drain. Formation of the channel may involve depositing or otherwise forming layers of a two-dimensional material.
- a prefabricated channel may be deposited between the source and the drain using any suitable semiconductor manufacturing process.
- Some embodiments may have a plurality of consecutive layers of the two-dimensional material.
- FIG. 1 c shows an example of the two-dimensional material with a plurality of consecutive layers. The nature and manner of forming additional layers of the two-dimensional material is the same as discussed above, and for the sake of brevity will not be reiterated.
- depositing or growing suitable semiconductor materials using any suitable semiconductor manufacturing process may form the source 120 and the drain 130 .
- Such materials may be intrinsic semiconductors, or may be doped during or after their initiation formation to become an extrinsic p or n type semiconductors, as desired.
- the method may proceed to block 505 , wherein a gate may be formed proximate the channel.
- the gate may consist of a column of an electrostrictive material that elongates upon application of an electrical input to the gate. Elongation of the column applies a force on the channel, which in turn reduces the bandgap between the consecutive layers of two-dimensional material.
- the method may proceed to block 506 and end.
- FIG. 6 is a cross-sectional block diagram of a 2D-EFET according to another embodiment of the present invention.
- the embodiment 600 shown in the FIG. 6 has four terminals i.e. source 610 , drain 620 , gate 630 , back gate 640 , and a capping layer 690 .
- the 2D-EFET 600 may be manufactured by depositing a layer of the back gate 640 on a substrate 650 . Consecutive layers of a gate 630 , and a dielectric 670 may be deposited on the back gate 640 .
- the gate 630 includes a column of electrostrictive material 660 that is deposited on the back gate 640 .
- the source 610 , drain 620 , and at least one layer of 2D material 680 may be provided on the dielectric layer 670 .
- the 2D material 680 comprises a first surface 605 toward the capping layer 690 and a second surface 615 toward the dielectric 670 .
- the resulting assembly of the electrostrictive material 660 , gate 630 , dielectric 670 , source 610 , drain 620 , and at least one layer of 2D material 680 may be enclosed and/or encapsulated by the capping layer 690 on the back gate 640 .
- electrostrictive materials exhibit a dimensional change upon application of an electric field due to the energy increase associated with the polarization induced by the electric field in the material.
- this is a form of elastic deformation of an electrostrictive material induced by an electric field.
- the resulting assembly ensures that due to the dimensional change of the electrostrictive material 660 , a distance M between the first surface 605 and the back gate 640 does not change. It should be noted that the resulting assembly might be encapsulated/restrained in other ways.
- the dimensional change of the electrostrictive material 660 transduces an out-of-plane stress on the 2D material 680 and monotonically reduces the bandgap of the 2D material 680 to zero.
- the four terminal 2D-EFET 600 separates the band gap modulation function from the field effect function.
- the amount of deformation of the electrostrictive material 660 may vary depending on the composition of the electrostrictive material and/or the terminal voltage(s). In some embodiments, the amount of elongation of the electrostrictive material is such that the 2D material 680 with a large bandgap transitions into 2D material 680 that has a small bandgap. In other embodiments, the amount of elongation of the electrostrictive material 660 is such that the bandgap of the 2D material 680 substantially reduces to zero and thereby exhibit characteristics of a metal in the ON state. Similar to as shown in FIG. 1 c , the 2D material 680 of some embodiments of the present disclosure may have a plurality of cascaded consecutive 2D material layers 680 of the two-dimensional material in 2D-EFET 600 .
- Electrostrictive materials whether grown by sol-gel, epitaxy, sputter or pulsed laser deposition, generally require high processing temperatures which can adversely affect the 2D semiconductor properties. For at least this reason, it is advantageous to integrate the 2D material after the electrostrictive material deposition.
- the four terminal operation of the 2D-EFET 600 potentially offers additional circuit functionality, allowing for complete and independent characterization of the FET and bandgap modulation behavior. When voltages are applied to the source 610 , drain 620 , gate 630 , and back gate 640 , the FET and band gap modulation behavior can be individually activated.
- the structure of the 2D-EFET 600 also removes the interface trap density requirement of the 2D-EFET 10 shown in FIGS. 1 a and 1 b.
- ⁇ E ( ⁇ ) ⁇ ( ⁇ ⁇ ⁇ C 33 , 2 ⁇ D ⁇ 1 t 2 ⁇ D ) ⁇ ( d 33 ) ⁇ V G ( 11 )
- ⁇ is the strain transfer coefficient or the fraction of the electrostrictive material displacement transferred into the 2D material
- ⁇ is the bandgap coefficient (meV in bandgap reduction per GPa of applied stress)
- C 33 is the 2D material out of plane compliance
- t 2D is the channel thickness
- d 33 is the piezo electric coefficient
- V G is the applied gate voltage. From the self-consistent calculations, FIG. 7 a shows that in the switching regime, the total band movement exceeds the applied gate voltage, hence internal voltage amplification.
- FIGS. 7 b and 7 c show the I D ⁇ V G characteristics, and subthreshold slope characteristics for an increase in the values of ⁇ .
- the 2D-EFET 600 device saturates similarly to a traditional MOSFET but with dramatically increased ON currents as shown in FIG. 7 d .
- FIG. 8 is a cross-sectional block diagram of a 2D-EFET according to another embodiment of the present invention.
- the embodiment 800 shown in the FIG. 8 has four terminals i.e. source 818 , drain 810 , first gate 814 , second gate 804 , and a capping layer 802 .
- the 2D-FET 800 may be manufactured by depositing a layer of the first gate 814 on a substrate 816 . Consecutive layers of a 2D-material 808 , and the second gate 804 may be deposited on the first gate 814 .
- the first gate 814 and the second gate 804 respectively include columns of electrostrictive material 812 , and electrostrictive material 806 that are deposited toward the 2D-material 808 .
- the source 818 and drain 810 are connected to the columns of electrostrictive material 812 and 806 toward an opposing side away from the first gate 814 and second gate 804 , respectively.
- the resulting assembly of electrostrictive material 806 , electrostrictive material 812 , first gate 814 , second gate 804 , source 818 , drain 810 , and at least one layer of 2D material 808 may be enclosed and capsuled by the capping layer 802 on top of the substrate 816 .
- electrostrictive materials exhibit a dimensional change upon application of an electric field due to the energy increase associated with the polarization induced by the electric field in the material.
- this is a form of elastic deformation of an electrostrictive material induced by an electric field.
- the resulting assembly ensures that due to the dimensional change of the electrostrictive materials 806 , 812 , a distance N between the first gate 814 and the second gate 804 does not change. It should be noted that the resulting assembly might be encapsulated/restrained in other ways.
- the longitudinal expansion of the electrostrictive materials 806 , 812 transduces an out-of-plane stress on the 2D material 808 from both sides and monotonically reduces the bandgap of the 2D material 808 to zero.
- Applying a gate voltage V GS modulates the band position similar to the 2D-EFET 10 shown in FIGS. 1 a and 1 b . This voltage also produces a significant electric field in the electrostrictive materials 806 , 812 , therefore actuating them and compressing the 2D material 808 .
- the amount of deformation of the electrostrictive materials 806 , 812 may vary depending on the composition of the electrostrictive material and/or the terminal voltage(s). In some embodiments, the amount of elongation of the electrostrictive material is such that the 2D material 808 with a large bandgap transitions into 2D material 808 that has a small bandgap. In other embodiments, the amount of elongation of the electrostrictive materials 806 , 812 is such that the bandgap of the 2D material 808 substantially reduces to zero and thereby exhibit characteristics of a metal in the ON state. Similar to as shown in FIG. 1 c , the 2D material 808 of some embodiments of the present disclosure may have a plurality of cascaded consecutive 2D material layers 808 of the two-dimensional material in 2D-EFET 800 .
- the 2D material 140 of FIGS. 1 b , 1 c, 2D material 680 of FIG. 6 , 2D material 808 of FIG. 8 or any other 2D material used in an embodiment of a 2d-EFET according to the present disclosure or an embodiment manufactured according to the method of the present disclosure may consist of a semiconductor MX 2 , wherein M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn) and X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- M is a transition metal atom like Molybdenum (Mo), Tungsten (W) or Tin (Sn)
- X is a chalcogen atom of Sulphur (S), Selenium (Se) or Tellurium (Te).
- the 2D material in the embodiments of this disclosure have a variable bandgap.
- the 2D material is configured in the 2D-EFET
- the sequence of depositing or creating one layer next to another layer of the 2D-EFET may vary depending on the manufacturing technique or process.
- 2D-EFET a novel and disruptive device concept called 2D-EFET is proposed based on strain transduction and dynamic bandgap engineering in the 2D material, which provides a solution for the post silicon, ultra-low power, high performance, and aggressively scalable device technology.
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Abstract
Description
S=λξ (1)
E G =E G0 −αP (2)
λ=√{square root over (t 2D t Eε2D/εE)} (10)
where, η is the strain transfer coefficient or the fraction of the electrostrictive material displacement transferred into the 2D material, α is the bandgap coefficient (meV in bandgap reduction per GPa of applied stress), C33 is the 2D material out of plane compliance, t2D is the channel thickness, d33 is the piezo electric coefficient, and VG is the applied gate voltage. From the self-consistent calculations,
- 1 Dennard, R. H., Rideout, V., Bassous, E. & LeBlanc, A. Design of ion-implanted MOSFET's with very small physical dimensions. Solid-State Circuits, IEEE Journal of 9, 256-268 (1974).
- 2 Frank, D. J. et al. Device scaling limits of Si MOSFET's and their application dependencies. Proceedings of the IEEE 89, 259-288 (2001).
- 3 Haensch, W. et al. Silicon CMOS devices beyond scaling. IBM Journal of Research and
Development 50, 339-361 (2006). - 4 Avouris, P., Chen, Z. & Perebeinos, V. Carbon-based electronics.
Nature nanotechnology 2, 605-615 (2007). - 5 Franklin, A. D. & Chen, Z. Length scaling of carbon nanotube transistors.
Nature nanotechnology 5, 858-862 (2010). - 6 Appenzeller, J. et al. Toward nanowire electronics. Electron Devices, IEEE Transactions on 55, 2827-2845 (2008).
- 7 Li, Y., Qian, F., Xiang, J. & Lieber, C. M. Nanowire electronic and optoelectronic devices.
Materials today 9, 18-27 (2006). - 8 Das, S., Robinson, J. A., Dubey, M., Terrones, H. & Terrones, M. Beyond graphene: Progress in novel two-dimensional materials and van der waals solids. Annual Review of Materials Research 45, 1-27 (2015).
- 9 Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V. & Kis, A. Single-Layer MoS2 Transistors.
Nature Nanotechnology 6, 147-150 (2011). - 10 Das, S., Chen, H.-Y., Penumatcha, A. V. & Appenzeller, J. High performance multilayer MoS2 transistors with scandium contacts.
Nano letters 13, 100-105 (2012). - 11 Das, S. & Appenzeller, J. WSe2 field effect transistors with enhanced ambipolar characteristics. Applied Physics Letters 103, 103501 (2013).
- 12 Das, S., Demarteau, M. & Roelofs, A. Ambipolar phosphorene field effect transistor.
ACS nano 8, 11730-11738 (2014). - 13 Butler, S. Z. et al. Progress, challenges, and opportunities in two-dimensional materials beyond graphene.
ACS nano 7, 2898-2926 (2013). - 14 Meric, I. et al. Current saturation in zero-bandgap, top-gated graphene field-effect transistors.
Nature nanotechnology 3, 654-659 (2008). - 15 Lu, H. & Seabaugh, A. Tunnel field-effect transistors: state-of-the-art. Electron Devices Society, IEEE Journal of the 2, 44-49 (2014).
- 16 Das, S., Prakash, A., Salazar, R. & Appenzeller, J. Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.
ACS nano 8, 1681-1689 (2014). - 17 van Hemert, T. & Hueting, R. J. Piezoelectric strain modulation in FETs. IEEE transactions on
electron devices 60, 3265-3270 (2013). - 18 Salahuddin, S. & Datta, S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices.
Nano letters 8, 405-410 (2008). - 19 Bourianoff, G. I., Gargini, P. A. & Nikonov, D. E. Research directions in beyond CMOS computing. Solid-
State Electronics 51, 1426-1431 (2007). - 20 Behin-Aein, B., Datta, D., Salahuddin, S. & Datta, S. Proposal for an all-spin logic device with built-in memory.
Nature Nanotechnology 5, 266-270 (2010). - 21 Banerjee, S. K., Register, L. F., Tutuc, E., Reddy, D. & MacDonald, A. H. Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device. IEEE
Electron Device Letters 30, 158-160 (2009). - 22 Nayak, A. P. et al. Pressure-induced semiconducting to metallic transition in multilayered molybdenum disulphide. Nature communications 5 (2014).
- 23 Kumar, A. & Ahluwalia, P. Semiconductor to metal transition in bilayer transition metals dichalcogenides MX2 (M=Mo, W; X═S, Se, Te). Modelling and Simulation in Materials Science and
Engineering 21, 065015 (2013). - 24 Coondoo, I., Panwar, N. & Kholkin, A. Lead-free piezoelectrics: Current status and perspectives. Journal of
Advanced Dielectrics 3, 1330002 (2013). - 25 Pham, K.-N. et al. Giant strain in Nb-doped Bi 0.5 (Na 0.82 K 0.18) 0.5
TiO 3 lead-free electromechanical ceramics. Materials Letters 64, 2219-2222 (2010). - 26 Hussain, A., Ahn, C. W., Lee, J. S., Ullah, A. & Kim, I. W. Large electric-field-induced strain in Zr-modified lead-free Bi 0.5 (Na 0.78 K 0.22) 0.5
TiO 3 piezoelectric ceramics. Sensors and Actuators A: Physical 158, 84-89 (2010). - 27 Lundstrom, M. & Guo, J. Nanoscale transistors: device physics, modeling and simulation. (Springer Science & Business Media, 2006).
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10658470B2 (en) * | 2017-11-14 | 2020-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device with doped phosphorene and method for doping phosphorene |
US10541132B2 (en) * | 2018-06-11 | 2020-01-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming semiconductor structures with two-dimensional materials |
US20190378977A1 (en) * | 2018-06-12 | 2019-12-12 | University Of Rochester | Ferroelectric strain based phase-change device |
CN110034181A (en) * | 2019-03-04 | 2019-07-19 | 上海华力集成电路制造有限公司 | A kind of iron/piezoelectricity field-effect tube and its preparation method |
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US11121214B2 (en) * | 2019-08-22 | 2021-09-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain contact with 2-D material |
US11581430B2 (en) * | 2019-08-22 | 2023-02-14 | Globalfoundries U.S. Inc. | Planar transistor device comprising at least one layer of a two-dimensional (2D) material and methods for making such transistor devices |
US11152508B2 (en) * | 2019-08-23 | 2021-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including two-dimensional material layer |
US11636324B2 (en) | 2019-09-11 | 2023-04-25 | The Penn State Research Foundation | Gaussian synapses for probabilistic neural networks |
CN111463289B (en) * | 2020-04-13 | 2023-09-29 | 国家纳米科学中心 | Field effect transistor and preparation method and application thereof |
EP3913356A1 (en) * | 2020-05-18 | 2021-11-24 | Imec VZW | A method for measuring the trap density in a 2-dimensional semiconductor material |
US20210408227A1 (en) * | 2020-06-26 | 2021-12-30 | Intel Corporation | Transition metal dichalcogenide nanowires and methods of fabrication |
US11296224B1 (en) * | 2021-06-16 | 2022-04-05 | Purdue Research Foundation | Non-volatile polarization induced strain coupled 2D FET memory |
KR102557596B1 (en) * | 2021-08-10 | 2023-07-19 | 고려대학교 산학협력단 | Modulation-doped high-mobility atomic-layer semiconductor devices and method of manufacturing the same |
KR20230037346A (en) * | 2021-09-09 | 2023-03-16 | 삼성전자주식회사 | Semiconductor device |
CN114709257B (en) * | 2022-03-01 | 2023-04-21 | 电子科技大学 | Field effect transistor device based on two-dimensional interlayer sliding ferroelectric semiconductor and preparation method thereof |
WO2024063826A2 (en) * | 2022-07-05 | 2024-03-28 | The Penn State Research Foundation | An ultra-steep slope and high-performance strain effect transistor |
KR102678554B1 (en) * | 2023-03-14 | 2024-06-25 | 연세대학교 산학협력단 | Ternary mosfet device and ternary cmos device having the same |
Citations (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633120A (en) | 1983-10-19 | 1986-12-30 | Nec Corporation | Electrostriction transducer comprising electrostriction layers of axially varied thicknesses |
US5255972A (en) | 1991-01-30 | 1993-10-26 | Nec Corporation | Electrostrictive effect element and the process of manufacturing the same |
US6570437B2 (en) | 2001-03-09 | 2003-05-27 | International Business Machines Corporation | Bandgap reference voltage circuit |
US20080231248A1 (en) | 2007-03-16 | 2008-09-25 | Kenneth Wai Ming Hung | Fast start-up circuit bandgap reference voltage generator |
US7432542B2 (en) | 2005-05-31 | 2008-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same |
US20090014804A1 (en) * | 2006-03-29 | 2009-01-15 | Fujitsu Limited | Misfet, semiconductor device having the misfet and method of manufacturing the same |
US20090101986A1 (en) | 2007-10-19 | 2009-04-23 | Seiko Epson Corporation | Semiconductor device and electronic apparatus |
US20100140589A1 (en) | 2008-12-04 | 2010-06-10 | Ecole Polytechnique Federale De Lausanne (Epfl) | Ferroelectric tunnel fet switch and memory |
US7871877B2 (en) | 2007-05-31 | 2011-01-18 | Globalfoundries Inc. | Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region |
US7999326B2 (en) | 2007-10-31 | 2011-08-16 | Advanced Micro Devices, Inc. | Tensile strain source using silicon/germanium in globally strained silicon |
US8030148B2 (en) | 2008-08-29 | 2011-10-04 | Advanced Micro Devices, Inc. | Structured strained substrate for forming strained transistors with reduced thickness of active layer |
US20110266927A1 (en) | 2010-04-30 | 2011-11-03 | Hon Hai Precision Industry Co., Ltd. | Carbon nanotube based electrostrictive composite and electrostrictive element using the same |
US8062952B2 (en) | 2009-05-29 | 2011-11-22 | Global Foundries Inc. | Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors |
US20110317486A1 (en) | 2010-06-25 | 2011-12-29 | Imec | Methods for Operating a Semiconductor Device |
US20120019284A1 (en) | 2010-07-26 | 2012-01-26 | Infineon Technologies Austria Ag | Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor |
US8329531B2 (en) | 2010-02-26 | 2012-12-11 | Globalfoundries Inc. | Strain memorization in strained SOI substrates of semiconductor devices |
US8772878B2 (en) | 2008-07-31 | 2014-07-08 | Globalfoundries Inc. | Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material |
US8884379B2 (en) | 2009-02-27 | 2014-11-11 | Globalfoundries Inc. | Strain engineering in semiconductor devices by using a piezoelectric material |
US20160126341A1 (en) | 2010-02-10 | 2016-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response |
US9450073B2 (en) | 2007-03-30 | 2016-09-20 | Advanced Micro Devices, Inc. | SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto |
US20170040331A1 (en) * | 2015-08-07 | 2017-02-09 | Imec Vzw | Ferroelectric memory device and fabrication method thereof |
US20170069738A1 (en) * | 2014-03-28 | 2017-03-09 | Uygar E. Avci | Tunneling field effect transistors with a variable bandgap channel |
US20170162702A1 (en) * | 2015-12-04 | 2017-06-08 | The Regents Of The University Of California | 3d transistor having a gate stack including a ferroelectric film |
US20170162250A1 (en) * | 2015-12-03 | 2017-06-08 | Namlab Ggmbh | Multilevel Ferroelectric Memory Cell for an Integrated Circuit |
US20170249983A1 (en) * | 2014-08-19 | 2017-08-31 | Ji Hoon Park | Non-volatile ferroelectric memory cells with multilevel operation |
US20170345831A1 (en) * | 2016-05-25 | 2017-11-30 | Micron Technology, Inc. | Ferroelectric Devices and Methods of Forming Ferroelectric Devices |
US20180277683A1 (en) * | 2017-03-21 | 2018-09-27 | International Business Machines Corporation | Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit |
US20180315852A1 (en) * | 2017-05-01 | 2018-11-01 | The Regents Of The University Of California | Strain gated transistors and method |
US20180322912A1 (en) * | 2017-05-03 | 2018-11-08 | Globalfoundries Inc. | Non-volatile transistor element including a buried ferroelectric material based storage mechanism |
US20180323188A1 (en) * | 2017-05-03 | 2018-11-08 | International Business Machines Corporation | Indirect readout fet |
-
2018
- 2018-04-04 US US15/945,207 patent/US10734531B2/en active Active
-
2020
- 2020-06-30 US US16/916,454 patent/US10964824B2/en active Active
Patent Citations (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4633120A (en) | 1983-10-19 | 1986-12-30 | Nec Corporation | Electrostriction transducer comprising electrostriction layers of axially varied thicknesses |
US5255972A (en) | 1991-01-30 | 1993-10-26 | Nec Corporation | Electrostrictive effect element and the process of manufacturing the same |
US6570437B2 (en) | 2001-03-09 | 2003-05-27 | International Business Machines Corporation | Bandgap reference voltage circuit |
US7432542B2 (en) | 2005-05-31 | 2008-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same |
US20090014804A1 (en) * | 2006-03-29 | 2009-01-15 | Fujitsu Limited | Misfet, semiconductor device having the misfet and method of manufacturing the same |
US20080231248A1 (en) | 2007-03-16 | 2008-09-25 | Kenneth Wai Ming Hung | Fast start-up circuit bandgap reference voltage generator |
US9450073B2 (en) | 2007-03-30 | 2016-09-20 | Advanced Micro Devices, Inc. | SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto |
US7871877B2 (en) | 2007-05-31 | 2011-01-18 | Globalfoundries Inc. | Technique for strain engineering in silicon-based transistors by using implantation techniques for forming a strain-inducing layer under the channel region |
US8035164B2 (en) | 2007-10-19 | 2011-10-11 | Seiko Epson Corporation | Semiconductor device and electronic apparatus |
US20090101986A1 (en) | 2007-10-19 | 2009-04-23 | Seiko Epson Corporation | Semiconductor device and electronic apparatus |
US7999326B2 (en) | 2007-10-31 | 2011-08-16 | Advanced Micro Devices, Inc. | Tensile strain source using silicon/germanium in globally strained silicon |
US8772878B2 (en) | 2008-07-31 | 2014-07-08 | Globalfoundries Inc. | Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material |
US8030148B2 (en) | 2008-08-29 | 2011-10-04 | Advanced Micro Devices, Inc. | Structured strained substrate for forming strained transistors with reduced thickness of active layer |
US20100140589A1 (en) | 2008-12-04 | 2010-06-10 | Ecole Polytechnique Federale De Lausanne (Epfl) | Ferroelectric tunnel fet switch and memory |
US8884379B2 (en) | 2009-02-27 | 2014-11-11 | Globalfoundries Inc. | Strain engineering in semiconductor devices by using a piezoelectric material |
US9263582B2 (en) | 2009-02-27 | 2016-02-16 | Globalfoundries Inc. | Strain engineering in semiconductor devices by using a piezoelectric material |
US8062952B2 (en) | 2009-05-29 | 2011-11-22 | Global Foundries Inc. | Strain transformation in biaxially strained SOI substrates for performance enhancement of P-channel and N-channel transistors |
US20160126341A1 (en) | 2010-02-10 | 2016-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field Effect Transistor with Conduction Band Electron Channel and Uni-Terminal Response |
US8329531B2 (en) | 2010-02-26 | 2012-12-11 | Globalfoundries Inc. | Strain memorization in strained SOI substrates of semiconductor devices |
US20110266927A1 (en) | 2010-04-30 | 2011-11-03 | Hon Hai Precision Industry Co., Ltd. | Carbon nanotube based electrostrictive composite and electrostrictive element using the same |
US20110317486A1 (en) | 2010-06-25 | 2011-12-29 | Imec | Methods for Operating a Semiconductor Device |
US20120019284A1 (en) | 2010-07-26 | 2012-01-26 | Infineon Technologies Austria Ag | Normally-Off Field Effect Transistor, a Manufacturing Method Therefor and a Method for Programming a Power Field Effect Transistor |
US20170069738A1 (en) * | 2014-03-28 | 2017-03-09 | Uygar E. Avci | Tunneling field effect transistors with a variable bandgap channel |
US20170249983A1 (en) * | 2014-08-19 | 2017-08-31 | Ji Hoon Park | Non-volatile ferroelectric memory cells with multilevel operation |
US20170040331A1 (en) * | 2015-08-07 | 2017-02-09 | Imec Vzw | Ferroelectric memory device and fabrication method thereof |
US20170162250A1 (en) * | 2015-12-03 | 2017-06-08 | Namlab Ggmbh | Multilevel Ferroelectric Memory Cell for an Integrated Circuit |
US20170162702A1 (en) * | 2015-12-04 | 2017-06-08 | The Regents Of The University Of California | 3d transistor having a gate stack including a ferroelectric film |
US20170345831A1 (en) * | 2016-05-25 | 2017-11-30 | Micron Technology, Inc. | Ferroelectric Devices and Methods of Forming Ferroelectric Devices |
US20180277683A1 (en) * | 2017-03-21 | 2018-09-27 | International Business Machines Corporation | Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit |
US20180315852A1 (en) * | 2017-05-01 | 2018-11-01 | The Regents Of The University Of California | Strain gated transistors and method |
US20180322912A1 (en) * | 2017-05-03 | 2018-11-08 | Globalfoundries Inc. | Non-volatile transistor element including a buried ferroelectric material based storage mechanism |
US20180323188A1 (en) * | 2017-05-03 | 2018-11-08 | International Business Machines Corporation | Indirect readout fet |
Non-Patent Citations (3)
Title |
---|
Agarwal et al., A Nanoscale Piezoelectric Transformer for Low-Voltage Transistors, ASC Publications, Nono Lett. 2014, 14, 6263-6268. |
Chhowalla et al., Two-dimensional semiconductors for transistors, Nature Reviews, Materials, vol. 1, Nov. 2016. |
Transition metal dichalcogenide monolayers, https://en.wikipedia.org/wiki/Transition_metal_dichalcogenide_monolayers#cite_note-FET-3 (last accessed Apr. 19, 2017). |
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