CN109979995A - A kind of novel grid extraction and injection field-effect transistor structure - Google Patents
A kind of novel grid extraction and injection field-effect transistor structure Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The present invention proposes that a kind of novel grid extracts and inject field-effect transistor structure, is related to microelectric technique and semiconductor technology.The present invention can reduce the power consumption of integrated circuit, suitable for super large-scale integration, it is characterized in that being provided with top gate medium floor in channel semiconductor area, source, drain electrode and top-gated pole are set on top gate medium layer, channel semiconductor area is arranged with backgate dielectric layer, and backgate dielectric layer is arranged with back grid.Advantage of the invention is that can all transistors on entire chip be carried out with whole regulation, reach the carrier number for controlling the channel semiconductor area of all devices, reduce the purpose of IC power consumption, furthermore also particular device can individually be regulated and controled, this is more applicable in for solving the power problems of super large-scale integration.
Description
Technical field
The present invention relates to microelectric techniques and semiconductor technology.
Background technique
With the CMOS integrated circuit that silicon is semiconductor material, its development follows always Moore's Law in decades.On the one hand,
Process is constantly scaled, at present 7nm technique oneself through realize volume production[1], it is in exploitation 5nm[2]Or even 3nm work
The stage of skill technology[3]；On the other hand, the substrate thickness of silicon integrated circuit is also increasingly thinned, and gradually sends out to two-dimensional semiconductor direction
Exhibition.Two-dimensional material, also referred to as monolayer material are by the former molecular crystalline material of single layer, from University of Manchester in 2004
Geim experiment group be successfully separated after obtaining monoatomic layer graphene, two-dimensional material is suggested for the first time and starts to cause scientific circles
Extensive concern；It is each to lead due to the excellent properties that monoatomic layer graphene is shown in electricity, mechanics, calorifics and optics aspect
The numerous and confused input research of the researcher in domain is using graphene as in " gold rush " of the two-dimensional material of representative[4]。
Since the band gap of graphene is zero, can not effectively turn off brilliant by the graphene field effect of planar technology manufacture
Body pipe (GFET)[5-7].Professor Li Ping thinks that the number of carrier in two-dimensional semiconductor material is that far smaller than conventional three-dimensional is partly led
Body material, thus theoretically by semi-insulated gate dielectric material from grid by nearly all current-carrying in channel semiconductor area
Son be it is feasible, then, Li Ping professor et al. is prepared for the grapheme transistor of aluminium autoxidation gate medium, and successfully has turned off
It, and on-off ratio has reached unprecedented 5 × 107, therefore, Li Ping professor et al. propose grid extract/inject field-effect
The concept of transistor[8]。
It is born from Moore's Law[9]Start, in decades, silicon integrated circuit follows always scaled principle[10], silicon
The power consumption of integrated circuit is with operating voltage VddReduction and linearly reduce[11].And with the increasingly reduction of silicon device size, mole
Law can not continue the rhythm for leading electronic equipment to develop, have excellent migration by the two-dimensional material of representative of graphene
Rate is expected to support the development of More Moore, and makes a breakthrough in the direction More than Moore[12].Li Ping professor et al. mentions
Grid out extracts/injects the mechanism of channel carrier, so that by the value of regulation grid voltage to control MOSFET channel
The number of middle carrier is possibly realized, it means that the I of MOSFET can be made by changing grid voltagedsAt the reduction of the order of magnitude, thus real
The super low-power consumption application of existing device, this has great meaning for solving the power problems that current super large-scale integration faces
Justice.
Before this patent proposition, traditional MOSFET do not have gate electrode electric current grid is extracted/inject field-effect, cannot
Size by controlling grid current reduces the carrier number n in channel semiconductor material, thus power consumption is high, can only be by pressing
The principle of scale smaller reduces its power consumption.Although the grid that Li Ping professor et al. proposes extracts and injection field effect transistor energy
It enough realizes the low-power consumption application of device, but is directed to single tube, grid extraction and injection can only be carried out to a MOSFET[13],
And the new construction that this patent is proposed can carry out whole regulation to all transistors on entire chip, reach all devices of control
The carrier number in the channel semiconductor area of part, reduces the purpose of IC power consumption, furthermore can also carry out to particular device
Individually regulation, this is more applicable in for solving the power problems of super large-scale integration.
Bibliography:
[1]R.Xie,et al.“A 7nm FinFET technology featuring EUV patterning and
dual strained high mobility channels.”IEDM,p47,2016
[2]ED Kurniawan,et al,Effect of fin shape of tapered FinFETs on the
device performance in 5-nm node CMOS technology,Microelectronics Reliability,
Aug.2017
[3]Thirunavukkarasu V,Jhan Y R,Liu Y B,et al.Performance of
Inversion,Accumulation,and Junctionless Mode n-Type and p-Type Bulk Silicon
FinFETs With 3-nm Gate Length[J].IEEE Electron Device Letters,2015,36(7):645-
647.
[4]A.K.Geim,K.S.Novoselov.“The rise of graphene”.Nature Material,
2007,6(3):183-191
[5]F.Schwierz,et al.,Graphene transistors:status,prospects,and
problems[J].Peoceeding of the IEEE.2013,101:1567-1584.
[6]K.S.Novoselov,et al.A roadmap for graphene.Nature,2012,490:192-
200.
[7]Lei Liao,et al.,High-speed graphene transistors with a self-
aligned nanowire gate,NATURE|Vol 467|16September 2010。
[8] Ping Li, R.Z.Zeng, Y.B.Liao, Q.W.Zhang, J.H.Zhou, A Novel Graphene
Metal Semi-Insulator Semiconductor Transistor and Its New Super-Low Power
Mechanism [J], Scientific Reports, 2019.3.6,9:3542.
[9]Moore,Gordon E."Cramming more components onto integrated
circuits".Electronics.Retrieved 2016-07-01.
[10]Thompson S,Packan P,Bohr M.MOS scaling:transistor challenges for
the 21stcentury.Intel Technology Journal,1998；pp 1-18.
[11]Anantha P.Chandrakasan,Samuel Sheng,and Robert W.Brodersen,Low-
Power Cmos digital design[J].IEEE J Sol Sta Cire.1992,27(4)
[12] Tian He, novel micro nanometer electronic device research Beijing [D] based on graphene: Tsinghua University, 2015
[13] Li Ping, Liao Yongbo, Zeng Rongzhou, Zhang Qingwei, Li Xia grid extract and inject field effect transistor and its channel
Carrier control method [P] .CN201810771577.2019.1.8.
Summary of the invention
The technical problems to be solved by the present invention are: providing the novel grid of one kind extracts and injects field effect transistor knot
Structure, realization control the channel carrier number of all devices on chip or in same substrate, to realize integrated electricity
Road power consumption and realizes the raising of the operating voltage of device and integrated circuit at the significant decrease of the order of magnitude, and device and integrated
The power consumption of circuit is still more low in energy consumption than traditional device and integrated circuit.This is because P=I*V, when I can significantly reduce, V
It can properly increase.
The present invention solve the technical problem the technical solution adopted is that: pass through top-gated pole extraction/injection and control single device
The number of part semiconductor channel area carrier, or all device semiconductor channel region current-carrying of monolith chip are controlled by back grid
The number of son.It is provided with top gate medium floor in channel semiconductor area, source, drain electrode and top-gated are set on top gate medium layer
Pole, channel semiconductor area are arranged with backgate dielectric layer, and backgate dielectric layer is arranged with back grid, it is characterised in that:
The top gate medium layer and backgate dielectric layer are that resistance value is 103~1016The semi-insulating dielectric material of Ω；
The material in the channel semiconductor area is two-dimensional semiconductor material or standard two of the thickness less than 10 atomic layer level thickness
Tie up semiconductor material.
The material of the top gate medium layer and backgate dielectric layer is perhaps two kinds or two of one of following thin-film materials
Kind or more combination:
SIPOS, aluminium oxide, amorphous silicon, polysilicon, Amorphous GaN, polycrystalline Si C, Amorphous SiC, polycrystal GaN, amorphous Buddha's warrior attendant
Stone, polycrystalline diamond, amorphous GaAs, polycrystalline GaAs.Wherein aluminium oxide is self-alumina.
Further, the material in the channel semiconductor area is intrinsic semiconductor, and the source electrode and drain electrode is metal electrode；
It is Ohmic contact between the channel semiconductor area and metal electrode when device is opened；In device shutdown, the channel half
It is Schottky contacts between conductor region and metal electrode.
The channel semiconductor area includes two the first conductivity regions and second conductivity regions, and one first is led
Electric class area is set between source electrode and the second conductivity regions, another first conductivity regions is set to drain electrode and second and leads
Between electric class area；
The material of first conductivity regions is N-type semiconductor, and the material of the second conductivity regions is P-type semiconductor；
Alternatively, the material of the first conductivity regions is P-type semiconductor, the material of the second conductivity regions is N-type semiconductor；
Alternatively, the material of the first conductivity regions is N-type semiconductor, the material of the second conductivity regions is N-type semiconductor；Alternatively, the
The material of one conductivity regions is P-type semiconductor, and the material of the second conductivity regions is P-type semiconductor.
Alternatively, the channel semiconductor area include two the first conductivity regions and second conductivity regions, one
First conductivity regions are set between source electrode and the second conductivity regions, another first conductivity regions be set to drain electrode and
Between second conductivity regions；
The material of first conductivity regions is heavily-doped semiconductor, and the material of the second conductivity regions is to be lightly doped partly to lead
Body；Alternatively, the material of the first conductivity regions is heavily-doped semiconductor, the material of the second conductivity regions is intrinsic semiconductor.
A kind of novel grid of the invention extracts and injection field-effect transistor structure, provides a kind of new semiconductor channel
The control method of area's carrier quantity, which is characterized in that include the following steps:
1) apply the first back gate voltage, complete to all device channel semiconductor regions carry on entire chip or in same substrate
Flow the extraction of son；
2) apply the second back gate voltage, complete to all device channel semiconductor regions carry on entire chip or in same substrate
Stream reinjects, by controlling the amplitude of voltage, the quantity of control injection carrier, to realize that whole super low-power consumption is answered
With.
3) or apply top-gated voltage, completion reinjects particular device channel semiconductor area carrier, passes through control electricity
The amplitude of pressure, the quantity of control injection carrier, to realize the super low-power consumption application of particular device.
The beneficial effects of the present invention are:
1) power consumption of device and integrated circuit is significantly reduced at the order of magnitude；Since device operation current Ids is dropped at the order of magnitude
Low, device work Vds=Vgs can not be reduced, and be still able to achieve the low-power consumption of device and circuit, brought device and circuit as a result,
The improvement of the simulated performances such as signal-to-noise ratio and anti-interference ability；
2) because carrier number is reduced, the collision scattering between carrier is reduced, and device operating frequencies is caused to improve；
3) traditional concept of insulation gate medium must be used by breaking through silicon field-effect transistor, it will so that silicon MOSFET element function
Consuming into the order of magnitude significantly reduces；
4) present invention can be used for logic switch, memory, programming device, low level signal amplification etc., highly effective can drop
The power consumption of low circuit, the working frequency or switching speed for improving circuit；
5) structure of the invention can be using back-gate electrode to the channel half of all devices on entire chip or same substrate
Conductor region carrier number carries out whole regulation, also can use top-gated electrode and is individually regulated and controled to particular device, for solution
Certainly the power problems of super large-scale integration are more applicable in.
Detailed description of the invention
Fig. 1 is the schematic diagram of transistor arrangement of the invention, is demonstrated by its basic structure.
Fig. 2 is the schematic diagram of transistor of the invention when not adding back gate voltage.
Fig. 3 is the schematic diagram that transistor of the invention extracts channel carrier by backgate, is demonstrated by under negative voltage, is carried
The case where stream is extracted from back grid.
Fig. 4 is transistor of the invention by schematic diagram of the backgate to Channeling implantation carrier, is demonstrated by under positive voltage,
The case where carrier is injected into channel semiconductor area from back grid.
Fig. 5 is transistor of the invention by schematic diagram of the top-gated to Channeling implantation carrier, is demonstrated by lower positive electricity
Pressure, carrier are injected into the situation in channel semiconductor area from top-gated pole.
Fig. 6 is transistor of the invention by schematic diagram of the top-gated to Channeling implantation carrier, is demonstrated by when positive grid voltage reaches
When certain value, more carriers are injected into the situation in channel semiconductor area.
Fig. 7 is the schematic diagram that transistor of the invention extracts channel carrier by top-gated, is demonstrated by lower negative voltage
Under, the case where carrier is extracted from back-gate electrode.
Fig. 8 is the schematic diagram that transistor of the invention extracts channel carrier by top-gated, is demonstrated by and reaches in minus gate voltage
When certain value, situation that the carrier in channel semiconductor area has almost been extracted completely.
Fig. 9 be the present invention combine existing Smart-cut technology one is the schematic diagrames of embodiment.
Each figure grade: 101 back grid metal layers, 102 backgate dielectric layers, 103 drain semiconductor areas, 104 drain metal layers,
105 top gate medium layers, 106 top gate metal layers, 107 semiconductor channel areas, 108 source metals, 109 source semiconductor areas,
110 basal layers, 111 realize the heavily doped region of Ohmic contact.
Specific embodiment
A kind of novel grid extracts and injection field-effect transistor structure, is provided with top gate medium in channel semiconductor area
Layer, source, drain electrode and top-gated pole are set on top gate medium layer, and channel semiconductor area is arranged with backgate dielectric layer, and backgate is situated between
Matter layer is arranged with back grid, it is characterised in that:
The top gate medium layer and backgate dielectric layer are that resistance value is 103~1016The semi-insulating dielectric material of Ω；
The material in the channel semiconductor area is two-dimensional semiconductor material or standard two of the thickness less than 10 atomic layer level thickness
Tie up semiconductor material.
The material of the top gate medium layer and backgate dielectric layer is perhaps two kinds or two of one of following thin-film materials
Kind or more combination:
SIPOS, aluminium oxide, amorphous silicon, polysilicon, Amorphous GaN, polycrystalline Si C, Amorphous SiC, polycrystal GaN, amorphous Buddha's warrior attendant
Stone, polycrystalline diamond, amorphous GaAs, polycrystalline GaAs.Wherein aluminium oxide is self-alumina.
Such as: the combination of amorphous silicon and polycrystalline Si C,
Such as: the combination of Amorphous SiC, polycrystal GaN, amorphous diamond, amorphous GaAs, polycrystalline GaAs.
The material in the channel semiconductor area is intrinsic semiconductor, and the source electrode and drain electrode is metal electrode；It is opened in device
Qi Shi is Ohmic contact between the channel semiconductor area and metal electrode；Device shutdown when, the channel semiconductor area with
It is Schottky contacts between metal electrode.
Referring to Fig. 1-8.
Embodiment 1: novel grid extracts and injection field-effect transistor structure example.
A kind of novel grid extracts and injection field-effect transistor structure, less than 10 atoms of channel semiconductor area thickness
Thickness degree is provided with top gate medium floor in channel semiconductor area, source, drain electrode and top-gated pole is arranged on top gate medium layer,
Channel semiconductor area is arranged with backgate dielectric layer, and backgate dielectric layer is arranged with back grid.The top gate medium layer and backgate
The material of dielectric layer is self-alumina, dielectric constant 7.5, resistance value 109~1012Ω.Channel semiconductor area is P-
Injection, source-drain area are P+ injection.In order to realize grid extraction/injection control channel carrier function, back grid first adds negative
Voltage, since semiconductor channel area is very thin, carrier therein can have been extracted almost, and then top-gated adds positive electricity to press to ditch
Road injects carrier, and negative voltage is added then to extract channel carrier, and the amplitude by controlling voltage can control thorough cut road and partly lead
The number of body area carrier.
Embodiment 2: switching device.
The switching device that the present embodiment system is configured to using the transistor junction of embodiment 1.Pass through the big of control grid current
The small carrier number n made in channel semiconductor material reduces at the order of magnitude, according to Ids=qvnS, and device power consumption P=Ids 2R, into
Row switching circuit or digital logic applications, so that the power consumption of device or circuit be made to significantly reduce.
Embodiment 3: amplifying device.
The amplifying device that the present embodiment system is configured to using the transistor junction of embodiment 1.Pass through the big of control grid current
The small carrier number n made in channel semiconductor material reduces at the order of magnitude, makes device work in the state of less carrier, carries out
Analog signal amplification, to realize high-gain, high speed, high frequency and well full etc. characteristics.
Embodiment 4: memory device.
The non-volatile semiconductor memory that the present embodiment system is configured to using the transistor junction of embodiment 1.I.e. by device
Part grid applies sufficiently high positive voltage (or negative voltage), turns off device, hereafter, as long as no longer applying minus gate voltage (or positive electricity
Pressure), device is by long-time or is held permanently in IdsThe OFF state for being zero, to realize the storage to information.
Referring to Fig. 9.
Embodiment 5: in conjunction with the embodiment of prior art.
A kind of novel grid extracts and injection field-effect transistor structure, less than 10 atoms of channel semiconductor area thickness
Thickness degree is provided with top gate medium floor in channel semiconductor area, source, drain electrode and top-gated pole is arranged on top gate medium layer,
Channel semiconductor area is arranged with backgate dielectric layer, and in conjunction with existing Smart-cut technology, backgate dielectric layer is arranged with thick silicon
Layer and back-gate electrode.The material of the top gate medium layer and backgate dielectric layer is self-alumina, dielectric constant 7.5, electricity
Resistance value is 109~1012Ω.Channel semiconductor area and thick silicon layer are P- injection, the ohmic contact regions for having P+ to inject under thick silicon layer, source
Drain region is also P+ injection.In order to realize grid extraction/injection control channel carrier function, back grid first adds negative voltage,
Since semiconductor channel area is very thin, carrier therein can have been extracted almost, and then top-gated adds positive electricity to press to channel note
Enter carrier, negative voltage is added then to extract channel carrier, the amplitude by controlling voltage can control thorough cut road semiconductor region
The number of carrier.
Claims (8)
1. a kind of novel grid extracts and injection field-effect transistor structure, top gate medium is provided in channel semiconductor area
Layer, source, drain electrode and top-gated pole are set on top gate medium layer, and channel semiconductor area is arranged with backgate dielectric layer, and backgate is situated between
Matter layer is arranged with back grid, which is characterized in that
The top gate medium layer and backgate dielectric layer are that resistance value is 103~1016The semi-insulating dielectric material of Ω；
The material in the channel semiconductor area is the quasi- two dimension half of two-dimensional semiconductor material or thickness less than 10 atomic layer level thickness
Conductor material.
2. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that the top-gated
The material of dielectric layer and backgate dielectric layer is perhaps two kinds or the two or more combination of one of following thin-film materials:
It is SIPOS, aluminium oxide, amorphous silicon, polysilicon, Amorphous GaN, polycrystalline Si C, Amorphous SiC, polycrystal GaN, amorphous diamond, more
Diamond, amorphous GaAs, polycrystalline GaAs.
3. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that the channel
The material of semiconductor region are as follows:
One of following two-dimensional semiconductor materials: graphene, MoS2、MoSe2、WSe2。
4. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that described quasi- two
Tie up semiconductor material are as follows:
Following semiconductors one of of the thickness less than 10 atomic layer level thickness: silicon, GaAs, gallium nitride, SiC, diamond.
5. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that the channel
The material of semiconductor region is intrinsic semiconductor, and the source electrode and drain electrode is metal electrode.
6. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that the channel
Semiconductor region includes two the first conductivity regions and second conductivity regions, and first conductivity regions are set to source
Between pole and the second conductivity regions, another first conductivity regions is set between drain electrode and the second conductivity regions；
The material of first conductivity regions is N-type semiconductor, and the material of the second conductivity regions is P-type semiconductor；
Alternatively, the material of the first conductivity regions is P-type semiconductor, the material of the second conductivity regions is N-type semiconductor；Or
Person, the material of the first conductivity regions are N-type semiconductor, and the material of the second conductivity regions is N-type semiconductor；Alternatively, first
The material of conductivity regions is P-type semiconductor, and the material of the second conductivity regions is P-type semiconductor.
7. novel grid as described in claim 1 extracts and injection field-effect transistor structure, which is characterized in that the channel
Semiconductor region includes two the first conductivity regions and second conductivity regions, and first conductivity regions are set to source
Between pole and the second conductivity regions, another first conductivity regions is set between drain electrode and the second conductivity regions；
The material of first conductivity regions is heavily-doped semiconductor, and the material of the second conductivity regions is that semiconductor is lightly doped；Or
Person, the material of the first conductivity regions are heavily-doped semiconductor, and the material of the second conductivity regions is intrinsic semiconductor.
8. novel grid as described in claim 1 extracts and injection field-effect transistor structure, provides and a kind of new partly lead
The control method of bulk channel area carrier quantity, which is characterized in that include the following steps:
1) apply the first back gate voltage, complete to all device channel semiconductor region carriers on entire chip or in same substrate
Extraction；
2) apply the second back gate voltage, complete to all device channel semiconductor region carriers on entire chip or in same substrate
Reinject, pass through control voltage amplitude, control injection carrier quantity, to realize whole super low-power consumption application；
3) or apply top-gated voltage, completion reinjects particular device channel semiconductor area carrier, passes through control voltage
Amplitude, the quantity of control injection carrier, to realize the super low-power consumption application of particular device.
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