CN109979995A - A kind of novel grid extraction and injection field-effect transistor structure - Google Patents

Abstract

The present invention proposes that a kind of novel grid extracts and inject field-effect transistor structure, is related to microelectric technique and semiconductor technology.The present invention can reduce the power consumption of integrated circuit, suitable for super large-scale integration, it is characterized in that being provided with top gate medium floor in channel semiconductor area, source, drain electrode and top-gated pole are set on top gate medium layer, channel semiconductor area is arranged with backgate dielectric layer, and backgate dielectric layer is arranged with back grid.Advantage of the invention is that can all transistors on entire chip be carried out with whole regulation, reach the carrier number for controlling the channel semiconductor area of all devices, reduce the purpose of IC power consumption, furthermore also particular device can individually be regulated and controled, this is more applicable in for solving the power problems of super large-scale integration.

Description

A Novel Gate Extraction and Injection Field Effect Transistor Structure

technical field

The present invention relates to microelectronics technology and semiconductor technology.

Background technique

The development of CMOS integrated circuits using silicon as a semiconductor material has been following Moore's Law for decades. On the one hand, the size of the process is constantly being scaled down. At present, the 7nm process has achieved mass production ^[1] , and it is in the stage of developing 5nm ^[2] and even 3nm process technology ^[3] ; on the other hand, the lining of silicon integrated circuits The thickness of the bottom is also getting thinner, and it is gradually developing towards the direction of two-dimensional semiconductor. Two-dimensional materials, also known as single-layer materials, are crystalline materials composed of single-layer atoms. Since the successful isolation of single-atom layer graphene by Geim's experimental group at the University of Manchester in 2004, two-dimensional materials were first proposed and began to cause problems. Widespread attention from the scientific community; due to the excellent properties of single-atom-layer graphene in electrical, mechanical, thermal and optical aspects, researchers in various fields have invested in the "gold rush" of two-dimensional materials represented by graphene in ^[4] .

Graphene field effect transistors (GFETs) fabricated by planar processes cannot be efficiently turned off due to the zero band gap of graphene ^[5-7] . Professor Li Ping believes that the number of carriers in two-dimensional semiconductor materials is much smaller than that of traditional three-dimensional semiconductor materials, so theoretically, almost all carriers in the channel semiconductor region are removed from the gate through the semi-insulating gate dielectric material. It is feasible. Subsequently, Professor Li Ping et al. prepared a graphene transistor with aluminum self-oxide gate dielectric, and successfully turned it off, and the on-off ratio reached an unprecedented 5 × 10 ⁷ . Therefore, Professor Li Ping et al. The concept of gate extraction/injection field effect transistor ^[8] .

Since the birth of Moore's Law ^[9] , for decades, silicon integrated circuits have been following the principle of scaling down ^[10] , and the power consumption of silicon integrated circuits decreases linearly with the decrease of operating voltage _Vdd ^[11] . With the decreasing size of silicon devices, Moore's Law can no longer continue to lead the development of electronic devices. Two-dimensional materials represented by graphene have excellent mobility, which is expected to support the development of More Moore. A breakthrough was made in the direction ^[12] . The mechanism of gate extraction/injection of channel carriers proposed by Prof. Li Ping and others makes it possible to control the number of carriers in the MOSFET channel by adjusting the value of the gate voltage, which means that changing the gate voltage can make the MOSFET The I _ds of the device is reduced by an order of magnitude, thereby realizing the ultra-low power consumption application of the device, which is of great significance for solving the power consumption problem faced by the current VLSI.

Before this patent is proposed, the traditional MOSFET has no gate electrode current to the gate extraction/injection field effect, and cannot reduce the number of carriers n in the channel semiconductor material by controlling the gate current, so the power consumption is high, Only through the principle of scaling down, its power consumption can be reduced. Although the gate extraction and injection field effect transistor proposed by Professor Li Ping et al. can realize the low power consumption application of the device, it is aimed at a single transistor and can only perform gate extraction and injection for one MOSFET ^[13] , while this patent The proposed new structure can control all transistors on the entire chip as a whole, so as to control the number of carriers in the channel semiconductor region of all devices and reduce the power consumption of the integrated circuit. In addition, individual devices can also be individually controlled. , which is more suitable for solving the power consumption problem of VLSI.

references:

[1] R.Xie, et al. “A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels.” IEDM, p47, 2016

[2] ED Kurniawan, et al, Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology, Microelectronics Reliability, Aug. 2017

[3] Thirunavukkarasu V, Jhan Y R, Liu Y B, et al. Performance of Inversion, Accumulation, and Junctionless Mode n-Type and p-Type Bulk Silicon FinFETs With 3-nm Gate Length [J]. IEEE Electron Device Letters, 2015, 36 (7): 645-647.

[4]A.K.Geim,K.S.Novoselov.“The rise of graphene”.Nature Material,2007,6(3):183-191

[5]F.Schwierz,et al.,Graphene transistors:status,prospects,andproblems[J].Peoceeding of the IEEE.2013,101:1567-1584.

[6]K.S.Novoselov,et al.A roadmap for graphene.Nature,2012,490:192-200.

[7] Lei Liao, et al., High-speed graphene transistors with a self-aligned nanowire gate, NATURE|Vol 467|16September 2010.

[8] Ping Li, R.Z.Zeng, Y.B.Liao, Q.W.Zhang, J.H.Zhou, A Novel GrapheneMetal Semi-Insulator Semiconductor Transistor and Its New Super-Low PowerMechanism[J], Scientific Reports, 2019.3.6, 9:3542.

[9] Moore, Gordon E. "Cramming more components onto integrated circuits". Electronics. Retrieved 2016-07-01.

[10] Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21 ^st century. Intel Technology Journal, 1998; pp 1-18.

[11] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, Low-Power Cmos digital design [J]. IEEE J Sol Sta Cire. 1992, 27(4)

[12] Tian He, Research on novel micro-nano electronic devices based on graphene [D]. Beijing: Tsinghua University, 2015

[13] Li Ping, Liao Yongbo, Zeng Rongzhou, Zhang Qingwei, Li Xia. Gate extraction and injection field effect transistor and its channel carrier control method [P].CN201810771577.2019.1.8.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a novel gate extraction and injection field effect transistor structure, which can control the number of channel carriers of all devices on the chip or on the same substrate, thereby realizing the integrated circuit function. Significant reductions in power consumption by orders of magnitude, as well as increases in operating voltages of devices and integrated circuits are achieved, while the power consumption of devices and integrated circuits is still lower than that of conventional devices and integrated circuits. This is because, P=I*V, when I can be significantly reduced, V can be appropriately increased.

The technical solution adopted by the present invention to solve the technical problem is: controlling the number of carriers in the semiconductor channel region of a single device by extracting/injecting the top gate, or controlling the current carrying of all devices in the semiconductor channel region of the entire chip through the back gate number of children. A top gate dielectric layer is provided on the channel semiconductor region, a source electrode, a drain electrode and a top gate electrode are provided on the top gate dielectric layer, a back gate dielectric layer is provided under the channel semiconductor region, and a back gate dielectric layer is provided under the back gate dielectric layer gate, characterized by:

The top gate dielectric layer and the back gate dielectric layer are both semi-insulating dielectric materials with a resistance value of 10 ³ to 10 ¹⁶ Ω;

The material of the channel semiconductor region is a two-dimensional semiconductor material or a quasi-two-dimensional semiconductor material with a thickness of less than 10 atomic layers.

The top gate dielectric layer and the back gate dielectric layer are made of one of the following thin film materials, or two, or a combination of two or more:

SIPOS, Alumina, Amorphous Silicon, Polycrystalline Silicon, Amorphous SiC, Polycrystalline SiC, Amorphous GaN, Polycrystalline GaN, Amorphous Diamond, Polycrystalline Diamond, Amorphous GaAs, Polycrystalline GaAs. The alumina is self-alumina.

Further, the material of the channel semiconductor region is an intrinsic semiconductor, the source electrode and the drain electrode are metal electrodes; when the device is turned on, the channel semiconductor region and the metal electrode are in ohmic contact; when the device is turned off When the channel semiconductor region and the metal electrode are in Schottky contact.

The channel semiconductor region includes two regions of the first conductivity type and one region of the second conductivity type, one region of the first conductivity type is arranged between the source electrode and the region of the second conductivity type, and another region of the first conductivity type is arranged between the source electrode and the second conductivity type region. between the drain and the second conductivity type region;

The material of the first conductive type region is N-type semiconductor, and the material of the second conductive type region is P-type semiconductor;

Alternatively, the material of the first conductivity type region is a P-type semiconductor, and the material of the second conductivity type region is an N-type semiconductor; or, the material of the first conductivity type region is an N-type semiconductor, and the material of the second conductivity type region is an N-type semiconductor or, the material of the first conductivity type region is P-type semiconductor, and the material of the second conductivity type region is P-type semiconductor.

Alternatively, the channel semiconductor region includes two regions of the first conductivity type and one region of the second conductivity type, one region of the first conductivity type is disposed between the source electrode and the region of the second conductivity type, and the other region of the first conductivity type arranged between the drain electrode and the second conductive type region;

The material of the first conductivity type region is a heavily doped semiconductor, and the material of the second conductivity type region is a lightly doped semiconductor; or, the material of the first conductivity type region is a heavily doped semiconductor, and the material of the second conductivity type region is this Levy semiconductors.

A novel gate extraction and injection field effect transistor structure of the present invention provides a novel method for controlling the number of carriers in a semiconductor channel region, which is characterized by comprising the following steps:

1) applying the first back gate voltage to complete the extraction of carriers from all device channel semiconductor regions on the entire chip or on the same substrate;

2) Apply the second back gate voltage to complete the re-injection of carriers in the channel semiconductor regions of all devices on the entire chip or on the same substrate. By controlling the amplitude of the voltage, the number of injected carriers is controlled, thereby realizing the overall super low power applications.

3) Or apply a top gate voltage to complete the re-injection of carriers to the channel semiconductor region of individual devices, and control the magnitude of the voltage to control the number of injected carriers, thereby realizing ultra-low power consumption applications of individual devices.

The beneficial effects of the present invention are:

1) The power consumption of the device and the integrated circuit is significantly reduced by orders of magnitude; since the device operating current Ids is reduced by an order of magnitude, the device operating Vds=Vgs may not be reduced, and the low power consumption of the device and circuit can still be achieved, thus bringing the device and circuit. Improved analog performance such as signal-to-noise ratio and anti-jamming capability;

2) Due to the reduction in the number of carriers, the collision scattering between carriers is reduced, resulting in an increase in the operating frequency of the device;

3) Breaking through the traditional concept that silicon field effect transistors must use insulating gate dielectrics, which will significantly reduce the power consumption of silicon MOSFET devices by orders of magnitude;

4) The present invention can be used in logic switches, memories, programmable devices, small signal amplification, etc., and can effectively reduce the power consumption of the circuit and improve the operating frequency or switching speed of the circuit;

5) The structure of the present invention can use the back gate electrode to control the number of carriers in the channel semiconductor region of the entire chip or all devices on the same substrate as a whole, and can also use the top gate electrode to control individual devices individually. The power consumption problem of large-scale integrated circuits is more applicable.

Description of drawings

FIG. 1 is a schematic diagram of the transistor structure of the present invention, showing its basic structure.

FIG. 2 is a schematic diagram of the transistor of the present invention when no back gate voltage is applied.

FIG. 3 is a schematic diagram of the transistor of the present invention extracting channel carriers through the back gate, showing the case where the carriers are extracted from the back gate under a negative voltage.

FIG. 4 is a schematic diagram of injecting carriers into the channel through the back gate of the transistor of the present invention, showing the situation in which carriers are injected from the back gate into the channel semiconductor region under a positive voltage.

FIG. 5 is a schematic diagram of injecting carriers into the channel through the top gate of the transistor of the present invention, showing the situation in which carriers are injected from the top gate into the channel semiconductor region under a relatively low positive voltage.

6 is a schematic diagram of injecting carriers into the channel through the top gate of the transistor of the present invention, showing that when the positive gate voltage reaches a certain value, more carriers are injected into the channel semiconductor region.

FIG. 7 is a schematic diagram of the transistor of the present invention extracting channel carriers through the top gate, showing the case where carriers are extracted from the back gate electrode at a relatively low negative voltage.

8 is a schematic diagram of the transistor of the present invention extracting channel carriers through the top gate, which shows that when the negative gate voltage reaches a certain value, the carriers in the channel semiconductor region are almost completely extracted.

FIG. 9 is a schematic diagram of an embodiment of the present invention combined with the existing Smart-cut technology.

Each figure number: 101 back gate metal layer, 102 back gate dielectric layer, 103 drain semiconductor region, 104 drain metal layer, 105 top gate dielectric layer, 106 top gate metal layer, 107 semiconductor channel region, 108 source Electrode metal layer, 109 source semiconductor region, 110 base layer, 111 heavily doped region for realizing ohmic contact.

Detailed ways

A novel gate extraction and injection field effect transistor structure is provided with a top gate dielectric layer on the channel semiconductor region, a source electrode, a drain electrode and a top gate electrode are provided on the top gate dielectric layer, and a top gate dielectric layer is provided under the channel semiconductor region. The back gate dielectric layer is provided with a back gate under the back gate dielectric layer, and is characterized in that:

The top gate dielectric layer and the back gate dielectric layer are both semi-insulating dielectric materials with a resistance value of 10 ³ to 10 ¹⁶ Ω;

The material of the channel semiconductor region is a two-dimensional semiconductor material or a quasi-two-dimensional semiconductor material with a thickness of less than 10 atomic layers.

The top gate dielectric layer and the back gate dielectric layer are made of one of the following thin film materials, or two, or a combination of two or more:

SIPOS, Alumina, Amorphous Silicon, Polycrystalline Silicon, Amorphous SiC, Polycrystalline SiC, Amorphous GaN, Polycrystalline GaN, Amorphous Diamond, Polycrystalline Diamond, Amorphous GaAs, Polycrystalline GaAs. The alumina is self-alumina.

For example: the combination of amorphous silicon and polycrystalline SiC,

For example: combination of amorphous GaN, polycrystalline GaN, amorphous diamond, amorphous GaAs, polycrystalline GaAs.

The material of the channel semiconductor region is an intrinsic semiconductor, and the source electrode and the drain electrode are metal electrodes; when the device is turned on, the channel semiconductor region and the metal electrode are in ohmic contact; when the device is turned off, the A Schottky contact is formed between the channel semiconductor region and the metal electrode.

See Figures 1-8.

Example 1: Example of a novel gate extraction and injection field effect transistor structure.

A novel gate extraction and injection field effect transistor structure, the thickness of the channel semiconductor region is less than 10 atomic layers, a top gate dielectric layer is arranged on the channel semiconductor region, and a source electrode and a drain electrode are arranged on the top gate dielectric layer. A back gate dielectric layer is arranged under the channel semiconductor region, and a back gate is arranged under the back gate dielectric layer. The material of the top gate dielectric layer and the back gate dielectric layer is self-alumina, the dielectric constant thereof is 7.5, and the resistance value thereof is 10 ⁹ -10 ¹² Ω. The channel semiconductor region is P- implanted, and the source and drain regions are P+ implanted. In order to realize the function of gate extraction/injection of control channel carriers, firstly, a negative voltage is applied to the back gate. Since the semiconductor channel region is very thin, the carriers in it will be almost completely extracted, and then a positive voltage is applied to the top gate. The carriers are injected into the channel, and the negative voltage is applied to extract the channel carriers, and the number of carriers in the semiconductor region of the channel can be controlled by controlling the amplitude of the voltage.

Example 2: Switching device.

This embodiment is a switching device formed by using the transistor structure of Embodiment 1. By controlling the magnitude of the gate current, the number of carriers n in the channel semiconductor material is reduced by an order of magnitude, according to I _ds = qvnS, and the device power consumption P = I _ds ² R, to perform switching circuits or digital logic applications, thereby The power consumption of the device or circuit is significantly reduced.

Example 3: Amplification device.

This embodiment is an amplifier device formed by using the transistor structure of the first embodiment. By controlling the size of the gate current, the number of carriers in the channel semiconductor material is reduced by an order of magnitude, so that the device works in a state of fewer carriers, and the analog signal is amplified, so as to achieve high gain, high speed and high frequency. and good saturation characteristics.

Example 4: Memory device.

This embodiment is a non-volatile semiconductor memory formed by using the transistor structure of the first embodiment. That is, by applying a high enough positive voltage (or negative voltage) to the gate of the device, the device is turned off, after which, as long as the negative gate voltage (or positive voltage) is no longer applied, the device will remain at zero I _ds for a long time or permanently off state, so as to realize the storage of information.

See Figure 9.

Embodiment 5: An embodiment combined with an existing process.

A novel gate extraction and injection field effect transistor structure, the thickness of the channel semiconductor region is less than 10 atomic layers, a top gate dielectric layer is arranged on the channel semiconductor region, and a source electrode and a drain electrode are arranged on the top gate dielectric layer. A back gate dielectric layer is provided under the channel semiconductor region, and a thick silicon layer and a back gate electrode are provided under the back gate dielectric layer in combination with the existing Smart-cut technology. The material of the top gate dielectric layer and the back gate dielectric layer is self-alumina, the dielectric constant thereof is 7.5, and the resistance value thereof is 10 ⁹ -10 ¹² Ω. The channel semiconductor region and the thick silicon layer are implanted with P-, and there is an ohmic contact region with P+ implantation under the thick silicon layer, and the source and drain regions are also implanted with P+. In order to realize the function of gate extraction/injection to control channel carriers, a negative voltage is first applied to the back gate. Since the semiconductor channel region is very thin, the carriers in it will be almost completely extracted, and then a positive voltage is applied to the top gate. The carriers are injected into the channel, and the negative voltage is applied to extract the channel carriers, and the number of carriers in the semiconductor region of the channel can be controlled by controlling the amplitude of the voltage.

Claims (8)

1. A novel gate extraction and injection field effect transistor structure, a top gate dielectric layer is provided on the channel semiconductor region, a source electrode, a drain electrode and a top gate electrode are provided on the top gate dielectric layer, and the channel semiconductor region is provided with a source electrode, a drain electrode and a top gate electrode. A back gate dielectric layer is arranged under the back gate dielectric layer, and a back gate is arranged under the back gate dielectric layer, which is characterized in that: The top gate dielectric layer and the back gate dielectric layer are both semi-insulating dielectric materials with a resistance value of 10 ³ to 10 ¹⁶ Ω; The material of the channel semiconductor region is a two-dimensional semiconductor material or a quasi-two-dimensional semiconductor material with a thickness of less than 10 atomic layers. 2. The novel gate extraction and injection field effect transistor structure according to claim 1, wherein the top gate dielectric layer and the back gate dielectric layer are made of one of the following thin film materials, or both, or A combination of two or more: SIPOS, Alumina, Amorphous Silicon, Polycrystalline Silicon, Amorphous SiC, Polycrystalline SiC, Amorphous GaN, Polycrystalline GaN, Amorphous Diamond, Polycrystalline Diamond, Amorphous GaAs, Polycrystalline GaAs. 3. novel gate extraction and injection field effect transistor structure as claimed in claim 1, is characterized in that, the material of described channel semiconductor region is: One of the following two-dimensional semiconductor materials: graphene, MoS ₂ , MoSe ₂ , WSe ₂ . 4. The novel gate extraction and injection field effect transistor structure of claim 1, wherein the quasi-two-dimensional semiconductor material is: One of the following semiconductors with a thickness of less than 10 atomic layers: silicon, gallium arsenide, gallium nitride, SiC, diamond. 5 . The novel gate extraction and injection field effect transistor structure according to claim 1 , wherein the material of the channel semiconductor region is an intrinsic semiconductor, and the source electrode and the drain electrode are metal electrodes. 6 . 6. The novel gate extraction and injection field effect transistor structure of claim 1, wherein the channel semiconductor region comprises two regions of the first conductivity type and one region of the second conductivity type, and one region of the first conductivity type The type region is arranged between the source electrode and the second conductivity type region, and another first conductivity type region is arranged between the drain electrode and the second conductivity type region; The material of the first conductive type region is N-type semiconductor, and the material of the second conductive type region is P-type semiconductor; Alternatively, the material of the first conductivity type region is a P-type semiconductor, and the material of the second conductivity type region is an N-type semiconductor; or, the material of the first conductivity type region is an N-type semiconductor, and the material of the second conductivity type region is an N-type semiconductor or, the material of the first conductivity type region is P-type semiconductor, and the material of the second conductivity type region is P-type semiconductor. 7. The novel gate extraction and implantation field effect transistor structure of claim 1, wherein the channel semiconductor region comprises two regions of the first conductivity type and one region of the second conductivity type, and one region of the first conductivity type The type region is arranged between the source electrode and the second conductivity type region, and another first conductivity type region is arranged between the drain electrode and the second conductivity type region; The material of the first conductivity type region is a heavily doped semiconductor, and the material of the second conductivity type region is a lightly doped semiconductor; or, the material of the first conductivity type region is a heavily doped semiconductor, and the material of the second conductivity type region is this Levy semiconductors. 8. The novel gate extraction and injection field effect transistor structure as claimed in claim 1 provides a new method for controlling the number of carriers in the semiconductor channel region, characterized in that it comprises the following steps: 1) applying the first back gate voltage to complete the extraction of carriers from all device channel semiconductor regions on the entire chip or on the same substrate; 2) Apply the second back gate voltage to complete the re-injection of carriers in the channel semiconductor regions of all devices on the entire chip or on the same substrate. By controlling the amplitude of the voltage, the number of injected carriers is controlled, thereby realizing the overall super low-power applications; 3) Or apply a top gate voltage to complete the re-injection of carriers to the channel semiconductor region of individual devices, and control the magnitude of the voltage to control the number of injected carriers, thereby realizing ultra-low power consumption applications of individual devices.