九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電鍍方法及半導體基板，詳言之，係 關於一種電性接觸墊之電鍍方法及具有電性接觸墊之半導 體基板。 【先前技術】 參考圖1至圖13，顯示習知電性接觸墊之電鍍方法。首 先’參考圖1 ’提供一基板1 ’該基板1具有一第一表面 11、一第二表面12、一第一導電層13及一第二導電層14, 該第一導電層13係位於該第一表面η，該第二導電層14係 位於第二表面12。該第一導電層13及該第二導電層14之材 質係為銅。接著，參考圖2’形成一貫穿孔15，該貫穿孔 15係貫穿該基板1。接著，參考圖3,形成一金屬層16，該 金屬層16之材質係為銅，該金屬層16包括一第一金屬層 161、一第二金屬層162及一側壁金屬層163，該第一金屬 層161係位於該第一導電層13上，該第二金屬層ι62係位於 該第二導電層14上，該側壁金屬層163係位於該貫穿孔15 之側壁。 接著，參考圖4’圖案化該第一金屬層ι61及該第一導電 層13 ’以形成至少一電性接觸墊17及至少一連接線18(如 圖5之俯視圖所示），該電性接觸墊17係供打線之用，該連 接線18係用以電氣連接該電性接觸墊丨7至一預設位置。接 著’參考圖6，形成一絕緣材19於該貫穿孔15内。接著， 參考圖7’形成一第一保護層21於該基板1之該第一表面η • Ί · 130743.doc 1360191 及該第二表面12上，以覆蓋該第一金屬層ι61及該第二金 屬層162’部分該第一金屬層161及部分該第二金屬層i62 係顯露於該第一保護層21之外。 接著，參考圖8，形成一電鑛層，該電鍵層之材質係為 鎳/金。該電鍍層包括一第一電鍍層221及一第二電鍍層 222，該第一電鍍層221係位於該第一金屬層161上，該第 一電鍵層222係位於該第二金屬層162上。接著，來考圖 9’移除該第一保護層21。接著，參考圖10，形成一第二 保護層23於該基板1之該第一表面11上，以覆蓋該第一金 屬層161及該第一電鍍層221，且形成一第三保護層24於該 基板1之該第二表面12上’以覆蓋該第二金屬層162，部分 該第二金屬層162係顯露於該第三保護層24之外。 接著’參考圖11，圖案化該第二金屬層162及該第二導 電層14。接者’參考圖12’移除該第二保護層23及該第三 保護層24 ^最後，參考圖13，形成一防焊層25於該基板1 之該第一表面11及該第二表面12，以覆蓋該第一金屬層 161及該第二金屬層162’並顯露該第一電鍍層221及該第 二電鍍層222，以得到一具有電性接觸墊17之半導體基板 2 ° 該習知電性接觸墊17之電鍍方法之缺點如下。由於該習 知電性接觸墊17之電鍍方法係於該基材1之該第二表面12 上先形成該第二電鍍層222，再圖案化該第二金屬層162及 該第二導電層14，最後再形成該防焊層25，然而在圖案化 之後’該第二電鍍層222之二側會形成突出部A(圖13)，由 130743.doc « 1360191 於該第二電鍍層222和該防焊層25之結合力不足，因此於 該防焊層25與該第二電鑛層222之突出部A接觸的地方容易 產生剝落的現象’進而影響產品良率及外觀。此外，該連 接線18全部鍍上鎳/金，如此會形成不必要的浪費。 因此’有必要提供一種創新且具進步性的電性接觸墊之 電鍍方法及具有電性接觸墊之半導體基板，以解決上述問 題。 【發明内容】 本發明提供一種電性接觸墊之電鍍方法，包括以下步 驟：（a)提供一基板’該基板具有一第一表面、一第二表 面、一第一導電層及一第二導電層，該第一導電層係位於 該第一表面’該第二導電層係位於該第二表面；（b)形成一 貫穿孔，該貫穿孔係貫穿該基板；（c)形成一金屬層，該金 屬層包括一第一金屬層、一第二金屬層及一側壁金屬層， 該第一金屬層係位於該第一導電層上，該第二金屬層係位 於該第二導電層上，該侧壁金屬層係位於該貫穿孔之側 壁，（d)圖案化該第一金屬層、該第一導電層、該第二金屬 層及該第二導電層，以形成至少一電性接觸墊及至少—連 接線，（e)形成一第一防焊層（Solder Mask Layer)於該第二 金屬層上並填入該貫穿孔，且部分該第二金屬層係顯露於 該第一防焊層之外；（f)形成一第三導電層於該基板之第— 表面，且覆蓋該第一金屬層及位於該貫穿孔之一端之第一 防焊層；（g)移除該第三導電層之一第一部分，該第—部份 之面積涵蓋該電性接觸墊及部分該連接線；（h)形成一電錄 130743.doc 層於該電性接觸墊及顯露於該第一防焊層之外之該第二金 屬層；⑴移除剩餘之該第三導電層；及⑴形成一第二防焊 層於該基板之第一表面，且覆蓋該第一金屬層及位於該貫 穿孔之一端之第一防焊層，且該電性接觸墊係顯露於該第 二防焊層之外。 本發明另提供一種具有電性接觸墊之半導體基板，其包 括一基板、一金屬層、一第一防焊層、一電鍍層及一第二 防知層。該基板具有一第一表面、一第二表面、一第一導 電層、一第二導電層及一貫穿孔。該第一導電層係位於該 第一表面，該第二導電層係位於該第二表面，該貫穿孔係 貝穿該基板。 該金屬層包括一第一金屬層、一第二金屬層及一側壁金 屬層。該第一金屬層係位於該第一導電層上。該第二金屬 層係位於該第二導電層上，該側壁金屬層係位於該貫穿孔 之側壁，其中該第一金屬層、該第一導電層、該第二金屬 層及該第二導電層具有至少一電性接觸墊及至少一連接 線。 該第一防焊層位於該基板之第二表面上及該貫穿孔内， 覆蓋部分該第二金屬層之下表面，且該第一防焊層具有複 數個開口，該等開口定義出複數個第一電鍍區域。該電鍍 層包括一第一電鍍層及一第二電鍍層，該第一電鍍層位於 該等第一電鍍區域内之第二金屬層上，該第二電鍍層位於 該電性接觸墊上。該第二防焊層位於該基板之第一表面 上’覆蓋顯露於該第二電鍍層之外之第一金屬層及位於該 130743.doc -10- 貫穿孔之一端之第一防焊層，且該電性接觸墊係顯露於該 第二防焊層之外。 藉此’本發明係先圖案化該第二金屬層及該第二導電 層’再以該第一防焊層覆蓋，然後才形成該電鍍層，故該 電鍍層係形成於顯露於該第一防焊層之外之該第二金屬 層’使該第一防銲層之結合力良好，不會產生剝落之情 況’進而提升產品良率。此外，本發明只在該電性接觸墊 鍍上錄/金，故可以減少該電鍍層之用量，以降低成本。 【實施方式】 參考圖14至圖51 ’顯示本發明電性接觸墊之電鍍方法之 示意圖。首先’參考圖14之剖面圖及圖15之俯視圖，提供 一基板3，該基板3具有一第一表面31、一第二表面32、一 第一導電層33及一第二導電層34。該第一導電層33係位於 該第一表面31 ’該第二導電層34係位於該第二表面32。在 本實施例中，該第一導電層33及該第二導電層34之材質係 為銅。接著，參考圖16及圖17,形成一貫穿孔35,該貫穿 孔35係貫穿該基板3。接著，參考圖18及圖19，形成一金 屬層36，該金屬層36包括一第一金屬層36i、一第二金屬 潛362及一侧壁金屬層363。該第一金屬層361係位於該第 一導電層33上’該第二金屬層362係位於該第二導電層34 上，該側壁金屬層363係位於該貫穿孔35之側壁。在本實 施例中’該金屬層36之材質係為銅。 接著’圖案化該第一金屬層361、該第一導電層33、該 第二金屬層362及該第二導電層34，以形成至少—電性接 130743.doc -11 - 1360191 觸塾37及至少—連接線38(圖26及圖27)。在本實施例中， 該電性接觸㈣為-導電指，係、供打線之用，而在其他應 用中，該電性接觸塾37亦可為一打線鲜塾（B〇nding p叫或 一銲球墊（Solder Ball Pad)，該連接線38係用以電氣連接 該電性接觸塾37至-預設位置。在本發明中，圖案化該第 一金屬層36丨、該第一導電層33、該第二金屬層362及該第 二導電層34之方式包含但不限於以下所述之方法。 首先，參考圖20及圖21，形成一第一保護層39於該基板 3之該第一表面31，以覆蓋該第一金屬層361，且形成一第 一保5蒦層41於該基板3之該第二表面32，以覆蓋該第二金 屬層362。該第一保護層39及該第二保護層41係為一乾膜 (Dry Film)或一光阻層（Photo Resist Layer)。接著，參考圖 22及圖23，形成一第一圖案391於該第一保護層39，以暴 露出部分該第一金屬層361，且形成一第二圖案411於該第 一保護層41’以暴露出部分該第二金屬層362。接著，參 考圖24及圖25 ’#刻位於該第一圖案391内之該第一金屬 層361及該第一導電層33 ’且#刻位於該第二圖案411内之 該第一金屬層362及該第二導電層34。最後，參考圖26及 圖27 ’移除該第一保護層39及該第二保護層41，以形成該 電性接觸墊37及該連接線38 » 接著’參考圖28及圖29’形成一第一防焊層（s〇ider Mask Layer)42於該第二金屬層362上並填入該貫穿孔35， 且部分該第二金屬層3 62係顯露於該第一防焊層42之外。 在本實施例中，該第一防焊層42具有複數個開口顯露部分 130743.doc -12- 1360191 該第二金屬層362之下表面3621，該等開口定義出複數個 第一電鍍區域421。接著，參考圖30及圖31，形成一第三 導電層43於該基板3之第一表面31，且覆蓋該第—金屬層 361及位於該貫穿孔35之一端之第一防焊層42。在本實施 例中，該第三導電層43係利用濺鍍（Sputter)、物理蒸氣沉 積法（Physical Vapor Deposition，PVD)、化學氣相沉積法 (Chemical Vapor Deposition，CVD)或無電鍍法方式形成，[Technical Field] The present invention relates to a plating method and a semiconductor substrate, and more particularly to an electroplating method for an electrical contact pad and a semiconductor substrate having an electrical contact pad. [Prior Art] Referring to Figs. 1 to 13, a plating method of a conventional electrical contact pad is shown. First, a substrate 1 is provided with reference to FIG. 1 '. The substrate 1 has a first surface 11 , a second surface 12 , a first conductive layer 13 and a second conductive layer 14 . The first surface η, the second conductive layer 14 is located on the second surface 12. The material of the first conductive layer 13 and the second conductive layer 14 is copper. Next, a uniform through hole 15 is formed with reference to Fig. 2', and the through hole 15 penetrates through the substrate 1. Next, referring to FIG. 3, a metal layer 16 is formed. The metal layer 16 is made of copper. The metal layer 16 includes a first metal layer 161, a second metal layer 162, and a sidewall metal layer 163. The metal layer 161 is located on the first conductive layer 13, and the second metal layer ι62 is located on the second conductive layer 14, and the sidewall metal layer 163 is located on the sidewall of the through hole 15. Next, the first metal layer ι 61 and the first conductive layer 13 ′ are patterned with reference to FIG. 4 ′ to form at least one electrical contact pad 17 and at least one connecting line 18 (as shown in the top view of FIG. 5 ). The contact pad 17 is for wire bonding, and the connecting wire 18 is used for electrically connecting the electrical contact pad 7 to a predetermined position. Next, referring to Fig. 6, an insulating material 19 is formed in the through hole 15. Next, a first protective layer 21 is formed on the first surface η · 130130.doc 1360191 and the second surface 12 of the substrate 1 to cover the first metal layer ι 61 and the second The first metal layer 161 and a portion of the second metal layer i62 are exposed outside the first protective layer 21 in the metal layer 162' portion. Next, referring to Fig. 8, an electric ore layer is formed, which is made of nickel/gold. The plating layer includes a first plating layer 221 and a second plating layer 222. The first plating layer 221 is located on the first metal layer 161, and the first electrical bonding layer 222 is located on the second metal layer 162. Next, the first protective layer 21 is removed by referring to FIG. Next, referring to FIG. 10, a second protective layer 23 is formed on the first surface 11 of the substrate 1 to cover the first metal layer 161 and the first plating layer 221, and a third protective layer 24 is formed. The second surface 12 of the substrate 1 is disposed to cover the second metal layer 162, and a portion of the second metal layer 162 is exposed outside the third protective layer 24. Next, referring to FIG. 11, the second metal layer 162 and the second conductive layer 14 are patterned. Referring to FIG. 12, the second protective layer 23 and the third protective layer 24 are removed. Finally, referring to FIG. 13, a solder resist layer 25 is formed on the first surface 11 and the second surface of the substrate 1. 12, covering the first metal layer 161 and the second metal layer 162' and exposing the first plating layer 221 and the second plating layer 222 to obtain a semiconductor substrate having an electrical contact pad 17 The disadvantages of the electroplating method of the electropositive contact pad 17 are as follows. Since the plating method of the conventional electrical contact pad 17 is performed on the second surface 12 of the substrate 1 to form the second plating layer 222, the second metal layer 162 and the second conductive layer 14 are patterned. Finally, the solder resist layer 25 is formed, however, after the patterning, the protrusions A (Fig. 13) are formed on both sides of the second plating layer 222, by 130743.doc «1360191 on the second plating layer 222 and the Since the bonding force of the solder resist layer 25 is insufficient, the peeling phenomenon is likely to occur in the place where the solder resist layer 25 is in contact with the protruding portion A of the second electric ore layer 222, thereby affecting the product yield and appearance. In addition, the connection wires 18 are all plated with nickel/gold, which creates unnecessary waste. Therefore, it is necessary to provide an innovative and progressive electroless contact pad plating method and a semiconductor substrate having an electrical contact pad to solve the above problems. SUMMARY OF THE INVENTION The present invention provides a method for electroplating an electrical contact pad, comprising the steps of: (a) providing a substrate having a first surface, a second surface, a first conductive layer, and a second conductive layer. a layer, the first conductive layer is located on the first surface 'the second conductive layer is located on the second surface; (b) forming a uniform through hole, the through hole is penetrating the substrate; (c) forming a metal layer, The metal layer includes a first metal layer, a second metal layer and a sidewall metal layer, the first metal layer is located on the first conductive layer, and the second metal layer is located on the second conductive layer, the side The wall metal layer is located on the sidewall of the through hole, and (d) patterning the first metal layer, the first conductive layer, the second metal layer and the second conductive layer to form at least one electrical contact pad and at least a connecting line, (e) forming a first solder mask layer on the second metal layer and filling the through hole, and a portion of the second metal layer is exposed to the first solder resist layer (f) forming a third conductive layer on the substrate - And covering the first metal layer and the first solder resist layer at one end of the through hole; (g) removing the first portion of the third conductive layer, the area of the first portion covering the electrical contact a pad and a portion of the connecting wire; (h) forming an electric recording 130743.doc layer on the electrical contact pad and the second metal layer exposed outside the first solder resist layer; (1) removing the remaining third a conductive layer; and (1) forming a second solder resist layer on the first surface of the substrate, and covering the first metal layer and the first solder resist layer at one end of the through hole, and the electrical contact pad is exposed Outside the second solder mask. The invention further provides a semiconductor substrate having an electrical contact pad, comprising a substrate, a metal layer, a first solder resist layer, a plating layer and a second anti-knowledge layer. The substrate has a first surface, a second surface, a first conductive layer, a second conductive layer and a uniform via. The first conductive layer is located on the first surface, and the second conductive layer is located on the second surface, and the through hole is passed through the substrate. The metal layer includes a first metal layer, a second metal layer and a sidewall metal layer. The first metal layer is on the first conductive layer. The second metal layer is located on the second conductive layer, and the sidewall metal layer is located at a sidewall of the through hole, wherein the first metal layer, the first conductive layer, the second metal layer, and the second conductive layer And having at least one electrical contact pad and at least one connecting wire. The first solder resist layer is disposed on the second surface of the substrate and in the through hole, covering a portion of the lower surface of the second metal layer, and the first solder resist layer has a plurality of openings, and the openings define a plurality of openings The first plating area. The plating layer includes a first plating layer and a second plating layer, the first plating layer is on the second metal layer in the first plating region, and the second plating layer is on the electrical contact pad. The second solder resist layer is disposed on the first surface of the substrate to cover the first metal layer exposed outside the second plating layer and the first solder resist layer at one end of the 130743.doc -10- through hole. And the electrical contact pad is exposed outside the second solder mask. Thus, the present invention is characterized in that the second metal layer and the second conductive layer are patterned first and then covered with the first solder resist layer, and then the plating layer is formed, so that the plating layer is formed on the first The second metal layer 'beyond the solder resist layer makes the bonding force of the first solder resist layer good, and does not cause peeling off', thereby improving product yield. In addition, the present invention only records the gold/gold on the electrical contact pads, so that the amount of the plating layer can be reduced to reduce the cost. [Embodiment] A schematic view of a plating method of an electrical contact pad of the present invention is shown with reference to Figs. 14 to 51'. Referring first to the cross-sectional view of FIG. 14 and the top view of FIG. 15, a substrate 3 having a first surface 31, a second surface 32, a first conductive layer 33 and a second conductive layer 34 is provided. The first conductive layer 33 is located on the first surface 31' and the second conductive layer 34 is located on the second surface 32. In this embodiment, the material of the first conductive layer 33 and the second conductive layer 34 is copper. Next, referring to Fig. 16 and Fig. 17, a uniform through hole 35 is formed, and the through hole 35 penetrates through the substrate 3. Next, referring to Figures 18 and 19, a metal layer 36 is formed. The metal layer 36 includes a first metal layer 36i, a second metal potential 362, and a sidewall metal layer 363. The first metal layer 361 is located on the first conductive layer 33. The second metal layer 362 is located on the second conductive layer 34. The sidewall metal layer 363 is located on the sidewall of the through hole 35. In the present embodiment, the material of the metal layer 36 is copper. Then, the first metal layer 361, the first conductive layer 33, the second metal layer 362, and the second conductive layer 34 are patterned to form at least the electrical contacts 130743.doc -11 - 1360191 At least - the connection line 38 (Figs. 26 and 27). In this embodiment, the electrical contact (4) is a conductive finger, which is used for wire bonding, and in other applications, the electrical contact 塾37 can also be a wire 塾 塾 (B〇nding p or one a solder ball pad (Solder Ball Pad) for electrically connecting the electrical contact pad 37 to a predetermined position. In the present invention, the first metal layer 36 is patterned, the first conductive layer 33. The manner of the second metal layer 362 and the second conductive layer 34 includes, but is not limited to, the method described below. First, referring to FIG. 20 and FIG. 21, a first protective layer 39 is formed on the substrate 3. A surface 31 is formed to cover the first metal layer 361, and a first protective layer 41 is formed on the second surface 32 of the substrate 3 to cover the second metal layer 362. The first protective layer 39 and The second protective layer 41 is a dry film or a photo resist layer. Next, referring to FIG. 22 and FIG. 23, a first pattern 391 is formed on the first protective layer 39 to expose a portion of the first metal layer 361 is formed, and a second pattern 411 is formed on the first protective layer 41' to expose a portion of the second gold The layer 362. Next, referring to FIG. 24 and FIG. 25 '#, the first metal layer 361 and the first conductive layer 33' in the first pattern 391 and the first one in the second pattern 411 are engraved The metal layer 362 and the second conductive layer 34. Finally, the first protective layer 39 and the second protective layer 41 are removed by referring to FIG. 26 and FIG. 27 to form the electrical contact pad 37 and the connecting line 38 » Then, referring to FIG. 28 and FIG. 29, a first solder mask layer 42 is formed on the second metal layer 362 and filled in the through hole 35, and a part of the second metal layer 3 62 is formed. The first solder resist layer 42 has a plurality of open exposed portions 130743.doc -12 - 1360191, the second metal layer 362 lower surface 3621, which is exposed outside the first solder resist layer 42. The plurality of first plating regions 421 are defined by the openings. Next, referring to FIG. 30 and FIG. 31, a third conductive layer 43 is formed on the first surface 31 of the substrate 3, and covers the first metal layer 361 and is located therethrough. The first solder resist layer 42 at one end of the hole 35. In the embodiment, the third conductive layer 43 is made of sputtering or sputtering. Formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or electroless plating,
且其材質選自錫、銅、鉻、鈀、鎳、錫/鉛及其合金所組 成的族群其中之一。 接著’移除該第三導電層43之一第一部分，該第一部分 之面積43 1涵蓋該電性接觸墊37及部分該連接線38(圖“及 圖39)。在本實施例中，該第三導電層43之材質選自錫、 銅、鉻、鈀、鎳、錫/鉛及其合金所組成的族群其中之 一。在本發明中，移除該第三導電層43之該第一部分之方 式包含但不限於以下所述之方法。The material is selected from the group consisting of tin, copper, chromium, palladium, nickel, tin/lead and alloys thereof. Then, the first portion of the third conductive layer 43 is removed, and the area 43 1 of the first portion covers the electrical contact pad 37 and a portion of the connecting line 38 (FIG. "and FIG. 39". In this embodiment, the The material of the third conductive layer 43 is one selected from the group consisting of tin, copper, chromium, palladium, nickel, tin/lead and alloys thereof. In the present invention, the first portion of the third conductive layer 43 is removed. Ways include, but are not limited to, the methods described below.
首先，參考圖32及圖33，形成一第三保護層料於該基板 3之該第-表面31，以蓋該第三導電層43。在本實施例 中，該第三保護層44係為一乾膜或一光阻層。接著，參考 圖34及圖35,形成一第三圖案441於該第三保護層44,以 暴露出部分該第三導電層43，該第三圖案441係涵蓋該電 性接觸㈣及部分該連接線38。接著，參相％及圖^ 姓刻位於該第三圖案441内之該第三導電層 一 子电層43，亦即蝕刻 該第三導電層43之第一部分，該第— 丨刀之面積431涵蓋 該電性接觸墊37及部分該連接線38，因此兮带从& u此孩電性接觸墊37 130743.doc •13- 1360191 及部分該連接線38顯露於該第三導電層43之外β最後參 考圖38及圖39’移除該第三保護層44。 接著，形成一電鍍層於該電性接觸墊37及顯露於該第一 防焊層42之外之該第二金屬層362(圖46及圖4?)。在本實施 例中，該電鐘層之材質係為鎖/金。在本發明巾，形成該 電鐵層之方式包含但不限於以下所述之方法。 首先，參考圖40及圖41，形成—第四保護層#於該基板 3之該第一表面31，以覆蓋該第一金屬層361及該第三導電 層43。在本實施例中，該第四保護層牝係為一乾膜或一光 阻層接著’參考圖42及圖43，形成·_第四圖案於該第四 保護層46,以暴露出該電性接觸墊37，該第四圖案定義出 至少一第二電鍍區域461。該第四圖案之面積係小於該第 三圖案441(圖35)。接著，參考圖料及圖45,形成一電鑛 層’該電鍍層包括一第一電鍍層451及一第二電鍍層452， 其中該第一電鍍層451形成於該等第一電鍍區域421内之第 二金屬層362上，該第二電錢層452形成於該第二電錄區域 461内之電性接觸墊37上。最後，參考圖及圖π，移除 該第四保護層46。 接著，參考圖48及圖49，移除剩餘之該第三導電層43。 在本實轭例中，該第三導電層43係以蝕刻方式移除。最 後參考圖50及圖51，形成一第二防焊層47於該基板3之 該第一表面31，且覆蓋該第一金屬層361及位於該貫穿孔 35之一端之第-防焊層42，且該電性接觸墊37係顯露於該 第-防焊層47之外’以得到一具有電性接觸墊之半導體基 130743.doc •14· 1360191 板4。 藉此，本發明係先圖案化該第二金屬層362及該第二導 電層34,再以該第一防谭層42覆蓋，然後才形成該電鍍 層，故該電鍍層係形成於顯露於該第一防焊層42之外之該 第二金屬層362，使該第一防輝層42之結合力良好，不會 產生剝洛之情況，進而提升產品良率。此外，本發明只在 該電！生接觸墊37鍍上鎳/金，故可以減少該電鍍層之用 量，以降低成本。 再參考圖50，顯示本發明具有電性接觸墊之半導體基 板。該半導體基板4包括-基板3、一金屬|、一第_防焊 層42、一電鍍層及一第二防焊層47。該基板3具有一第— 表面31、一第二表面32、一第一導電層33、一第二導 34及一貫穿孔35。 /該第-導電層33係位於該第一表面3卜該第二導電層34 係位於該第二表面32，該貫穿孔35係貫穿該基板3。在本 鲁實施例中，該第-導電層33及該第二導電層34之材質係為 銅0 ‘ 該金屬層包括一第一金屬層361、一第二金屬層泊及一 側壁金屬層363。該第-金屬層361係位於該第—導電㈣ 上。該第二金屬層362係位於該第二導電層34上，該側壁 金屬層363儀位於該貫穿孔35之側壁，其中該第一金屬層 36卜該第-導電層33、該第二金屬層如及該第二導電^ 34具有至少-電性接觸塾37及至少—連接線（圖51)。在本 實施例中，該金屬層之材質係為銅，該電性接觸墊^為- 130743.doc •15· 1360191 導電指。而在其他應用中，該電性接觸墊37亦可為一打線 銲墊（Bonding Pad)或一銲球墊（Solcler Ball Pad)。 該第一防焊層42位於該基板3之第二表面32上及該貫穿 孔35内，覆蓋部分該第二金屬層362之下表面3621，且該 第一防焊層42具有複數個開口，該等開口定義出複數個第 一電鍍區域421。 該電鍍層包括一第一電鍍層451及一第二電鍍層452,該 第一電鍍層451位於該等第一電鍍區域421内之第二金屬層 362上，該第二電鑛層452位於該電性接觸墊37上。在本實 施例中，該電鍍層之材質係為鎳/金。 該第一防焊層47位於該基板3之第一表面31上，覆蓋顯 露於該第二電鍍層452之外之第一金屬層361及位於該貫穿 孔35之一端之第一防焊層42’且該電性接觸墊37係顯露於 該第二防焊層47之外。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此’習於此技術之人士對上述實施例進 行修改及變化仍不脫本發明之精神。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1至圖13顯示習知電性接觸墊之電鍍方法之示意圖； 圖14顯示本發明電性接觸墊之電鍍方法之基板之剖面 回 ♦ 圓， 圖15顯示本發明電性接觸墊之電鍍方法之基板之俯視 圖； 130743.doc -16- 1360191 圖丨6顯示本發明電性接觸墊之電鍍方法形成貫穿孔之剖 面圖； 圖17顯示本發明電性接觸墊之電鍍方法形成貫穿孔之俯 視圖； 圖18顯示本發明電性接觸墊之電鍍方法形成金屬層之剖 面圖； 圖19顯示本發明電性接觸墊之電鍍方法形成金屬層之俯 視圖； 圖20顯示本發明電性接觸墊之電鍍方法形成第一保護層 及第二保護層之剖面圖； 圖21顯示本發明電性接觸墊之電鍍方法形成第一保護層 及第二保護層之俯視圖； 圖22顯示本發明電性接觸墊之電鍍方法形成第一圖案及 第二圖案之剖面圖； 圖23顯示本發明電性接觸墊之電鍍方法形成第一圖案及 第二圖案之俯視圖； 圖24顯示本發明電性接觸墊之電鍍方法蝕刻部分第_金 屬層、第一導電層、第二金屬層及第二導電層之剖面圖； 圖25顯示本發明電性接觸墊之電鍍方法蝕刻部分第一金 屬層、第一導電層、第二金屬層及第二導電層之俯視圖； 圖26顯示本發明電性接觸墊之電鍍方法移除第一保護層 及第一保護層之剖面圖； 圖27顯示本發明電性接觸墊之電鍍方法移除第一保護層 及第二保護層之俯視圖； 130743.doc 17 1360191 圖28顯示本發明電性接觸塾之電鑛方法形成第—防焊層 之剖面圖； 圖29顯示本發明電性接觸墊之電鍍方法形成第一防焊層 之俯視圖； 圖30顯示本發明電性接觸墊之電鍍方法形成第三導電層 之剖面圖； 圖31顯示本發明電性接觸墊之電鍍方法形成第三導電層 之俯視圖； 圖32顯示本發明電性接觸墊之電鍍方法形成第三保護層 之剖面圖； 圖33顯示本發明電性接觸墊之電鍍方法形成第三保護層 之俯視圖； 圖34顯示本發明電性接觸墊之電鍍方法形成第三圖案之 剖面圖； 圖35顯示本發明電性接觸墊之電鍍方法形成第三圖案之 俯視圖； 圖36顯示本發明電性接觸墊之電鍍方法蝕刻部分第三^ 電層之剖面圖； 圖37顯示本發明電性接觸墊之電鍍方法蝕刻部分第三導 電層之俯視圖； 圖3 8顯示本發明電性接觸墊之電鍍方法移除第三保護層 之剖面圖； 圖39顯示本發明電性接觸墊之電鍍方法移除第三保護層 之俯視圖； I30743.doc 18 圖40顯示本發明電性接觸塾之電鍍方法形成第四保護層 之剖面圖； 圖41顯示本發明電性接觸墊之電鍍方法形成第四保護層 之俯視圖； 圖42顯示本發明電性接觸墊之電鍍方法形成第四圖案之 剖面圖； 圖43顯不本發明電性接觸墊之電鍍方法形成第四圖案之 俯視圖； 圖44顯示本發明電性接觸墊之電鍍方法形成電鍍層之剖 面圖； 圖45顯示本發明電性接觸墊之電鍍方法形成電鍍層之俯 視圖； 圖46顯示本發明電性接觸墊之電鍍方法移除第四保護層 之剖面圖； 圖47顯示本發明電性接觸墊之電鑛方法移除第四保護層 之俯視圖； 圖48顯示本發明電性接觸墊之電艘方法移除第三導電層 之剖面圖； 圖49顯示本發明電性接觸墊之電鍍方法移除第三導電層 之俯視圖； 圖50顯示本發明電性接觸墊之電鍍方法形成第二防焊層 之剖面圖；及 圖51顯示本發明電性接觸墊之電鍍方法形成第二防焊層 之俯視圖。 130743.doc -19- 1360191 【主要元件符號說明】 1 基板 2 習知具有電性接觸墊之半導體基板 3 基板 4 本發明具有電性接觸墊之半導體基板 11 第一表面 12 第二表面 13 第一導電層First, referring to Fig. 32 and Fig. 33, a third protective layer is formed on the first surface 31 of the substrate 3 to cover the third conductive layer 43. In this embodiment, the third protective layer 44 is a dry film or a photoresist layer. Next, referring to FIG. 34 and FIG. 35, a third pattern 441 is formed on the third protective layer 44 to expose a portion of the third conductive layer 43. The third pattern 441 covers the electrical contact (4) and a portion of the connection. Line 38. Then, the first phase and the last name of the third conductive layer are in the third pattern 441, that is, the first portion of the third conductive layer 43 is etched, and the area of the first file is 431. The electrical contact pad 37 and a portion of the connecting wire 38 are covered, so that the tape is exposed from the & u electrical contact pad 37 130743.doc • 13-1360191 and a portion of the connecting wire 38 is exposed to the third conductive layer 43 The outer beta finally removes the third protective layer 44 with reference to FIGS. 38 and 39'. Next, a plating layer is formed on the electrical contact pad 37 and the second metal layer 362 (FIG. 46 and FIG. 4) exposed outside the first solder resist layer 42. In this embodiment, the material of the electric clock layer is a lock/gold. In the present invention, the manner in which the electrical iron layer is formed includes, but is not limited to, the methods described below. First, referring to FIG. 40 and FIG. 41, a fourth protective layer # is formed on the first surface 31 of the substrate 3 to cover the first metal layer 361 and the third conductive layer 43. In this embodiment, the fourth protective layer is a dry film or a photoresist layer. Referring to FIG. 42 and FIG. 43, a fourth pattern is formed on the fourth protective layer 46 to expose the electrical property. Contact pad 37, the fourth pattern defines at least one second plating region 461. The area of the fourth pattern is smaller than the third pattern 441 (Fig. 35). Next, referring to the drawing and FIG. 45, an electric ore layer is formed. The plating layer includes a first plating layer 451 and a second plating layer 452, wherein the first plating layer 451 is formed in the first plating regions 421. On the second metal layer 362, the second power layer 452 is formed on the electrical contact pads 37 in the second lithography area 461. Finally, the fourth protective layer 46 is removed with reference to the figure and FIG. Next, referring to FIG. 48 and FIG. 49, the remaining third conductive layer 43 is removed. In the present embodiment, the third conductive layer 43 is removed by etching. Finally, referring to FIG. 50 and FIG. 51, a second solder resist layer 47 is formed on the first surface 31 of the substrate 3, and covers the first metal layer 361 and the first solder mask 42 at one end of the through hole 35. And the electrical contact pad 37 is exposed outside the first solder mask layer 47 to obtain a semiconductor substrate 130743.doc •14·1360191 plate 4 having an electrical contact pad. Therefore, in the present invention, the second metal layer 362 and the second conductive layer 34 are patterned first, and then covered by the first anti-tan layer 42 to form the plating layer, so that the plating layer is formed on the exposed layer. The second metal layer 362 outside the first solder resist layer 42 has a good bonding force of the first anti-glaze layer 42 and does not cause peeling, thereby improving product yield. In addition, the invention is only in the electricity! The green contact pad 37 is plated with nickel/gold, so that the amount of the plating layer can be reduced to reduce the cost. Referring again to Figure 50, a semiconductor substrate having an electrical contact pad of the present invention is shown. The semiconductor substrate 4 includes a substrate 3, a metal, a first solder resist layer 42, a plating layer, and a second solder resist layer 47. The substrate 3 has a first surface 31, a second surface 32, a first conductive layer 33, a second guide 34 and a uniform via 35. The first conductive layer 33 is located on the first surface 3 and the second conductive layer 34 is located on the second surface 32. The through hole 35 extends through the substrate 3. In the present embodiment, the first conductive layer 33 and the second conductive layer 34 are made of copper 0'. The metal layer includes a first metal layer 361, a second metal layer, and a sidewall metal layer 363. . The first metal layer 361 is located on the first conductive (four). The second metal layer 362 is located on the second conductive layer 34. The sidewall metal layer 363 is located at the sidewall of the through hole 35. The first metal layer 36 includes the first conductive layer 33 and the second metal layer. For example, the second conductive layer 34 has at least an electrical contact 37 and at least a connecting line (FIG. 51). In this embodiment, the material of the metal layer is copper, and the electrical contact pad is -130743.doc •15·1360191 conductive fingers. In other applications, the electrical contact pad 37 can also be a Bonding Pad or a Solcler Ball Pad. The first solder resist layer 42 is disposed on the second surface 32 of the substrate 3 and the through hole 35, covering a portion of the lower surface 3621 of the second metal layer 362, and the first solder resist layer 42 has a plurality of openings. The openings define a plurality of first plating regions 421. The plating layer includes a first plating layer 451 and a second plating layer 452. The first plating layer 451 is located on the second metal layer 362 in the first plating region 421, and the second electric ore layer 452 is located thereon. Electrical contact pad 37. In this embodiment, the material of the plating layer is nickel/gold. The first solder resist layer 47 is located on the first surface 31 of the substrate 3 and covers the first metal layer 361 exposed outside the second plating layer 452 and the first solder resist layer 42 at one end of the through hole 35. And the electrical contact pad 37 is exposed outside the second solder mask layer 47. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art will be able to modify and change the above-described embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 to FIG. 13 are schematic views showing a plating method of a conventional electrical contact pad; FIG. 14 is a cross-sectional view of a substrate of a plating method for an electrical contact pad of the present invention, and FIG. Top view of the substrate of the electroplating method of the contact pad; 130743.doc -16- 1360191 Figure 6 shows a cross-sectional view of the electroplating method of the electrical contact pad of the present invention, and FIG. 17 shows the electroplating method of the electrical contact pad of the present invention. FIG. 18 is a plan view showing a metal layer formed by the plating method of the electrical contact pad of the present invention; FIG. 19 is a plan view showing a metal layer formed by the plating method of the electrical contact pad of the present invention; FIG. 21 is a plan view showing the first protective layer and the second protective layer formed by the plating method of the electrical contact pad of the present invention; FIG. 22 shows the electric circuit of the present invention. The electroplating method of the contact pad forms a cross-sectional view of the first pattern and the second pattern; FIG. 23 shows the electroplating method of the electrical contact pad of the present invention to form the first pattern and the second FIG. 24 is a cross-sectional view showing an etching portion of the electroless contact pad of the present invention, a first metal layer, a first conductive layer, a second metal layer, and a second conductive layer; FIG. 25 shows an electrical contact pad of the present invention. The plating method etches a portion of the first metal layer, the first conductive layer, the second metal layer and the second conductive layer; FIG. 26 shows the plating method of the electrical contact pad of the present invention, the first protective layer and the first protective layer are removed FIG. 27 is a plan view showing the method of electroplating the electrical contact pad of the present invention with the first protective layer and the second protective layer removed; 130743.doc 17 1360191 FIG. 28 shows the formation of the electric ore method of the electrical contact crucible of the present invention. Figure 29 is a cross-sectional view showing the first solder resist layer formed by the electroplating method of the electrical contact pad of the present invention; and Figure 30 is a cross-sectional view showing the third conductive layer formed by the electroplating method of the electrical contact pad of the present invention; Figure 31 is a plan view showing the third conductive layer formed by the plating method of the electrical contact pad of the present invention; Figure 32 is a cross-sectional view showing the third protective layer formed by the plating method of the electrical contact pad of the present invention; The electroplating method of the electrical contact pad of the present invention forms a top view of the third protective layer; FIG. 34 shows a cross-sectional view of the electroplating method of the electrical contact pad of the present invention to form a third pattern; FIG. 35 shows the electroplating method of the electrical contact pad of the present invention. FIG. 36 is a cross-sectional view showing an etched portion of the third electrical layer of the method for electroplating the electrical contact pad of the present invention; FIG. 37 is a plan view showing an etching method of the third conductive layer of the method for electroplating the electrical contact pad of the present invention; Figure 3 is a cross-sectional view showing the electroplating method of the electrical contact pad of the present invention for removing the third protective layer; Figure 39 is a plan view showing the electroplating method of the electrical contact pad of the present invention for removing the third protective layer; I30743.doc 18 Figure 40 FIG. 41 is a plan view showing a fourth protective layer formed by the plating method of the electrical contact pad of the present invention; FIG. 41 is a plan view showing the fourth protective layer formed by the electroplating method of the electrical contact pad of the present invention; The method forms a cross-sectional view of the fourth pattern; FIG. 43 shows a top view of the electroplating method of the electrical contact pad of the present invention to form a fourth pattern; and FIG. 44 shows the electrical connection of the present invention. The plating method of the pad forms a cross-sectional view of the electroplated layer; FIG. 45 shows a top view of the electroplating method of the electroless contact pad of the present invention; FIG. 46 shows a cross-sectional view of the electroplating method of the electrical contact pad of the present invention for removing the fourth protective layer Figure 47 is a plan view showing the fourth protective layer removed by the electric ore method of the electrical contact pad of the present invention; Figure 48 is a cross-sectional view showing the third conductive layer removed by the electric boat method of the electrical contact pad of the present invention; FIG. 50 is a cross-sectional view showing a method of electroplating the electrical contact pad of the present invention to form a second solder resist layer; and FIG. 51 is a view showing the electrical contact pad of the present invention; The plating method forms a top view of the second solder resist layer. 130743.doc -19- 1360191 [Description of main component symbols] 1 substrate 2 conventional semiconductor substrate with electrical contact pads 3 substrate 4 semiconductor substrate 11 with electrical contact pads of the present invention first surface 12 second surface 13 first Conductive layer
14 第二導電層 15 貫穿孔 16 金屬層 17 電性接觸墊 18 連接線 19 絕緣材 21 第一保護層14 Second conductive layer 15 Through hole 16 Metal layer 17 Electrical contact pad 18 Connecting wire 19 Insulating material 21 First protective layer
23 第二保護層 24 第三保護層 25 防焊層 31 第一表面 32 第二表面 33 第一導電層 34 第二導電層 35 貫穿孔 3 6 金屬層 130743.doc •20- 1360191 37 電性接觸墊 38 連接線 39 第一保護層 41 第二保護層 42 第一防焊層 43 第三導電層 44 第三保護層 46 第四保護層 47 第二防焊層 161 第一金屬層 162 第二金屬層 163 側壁金屬層 221 第一電鍍層 222 第二電鍍層 361 第一金屬層 362 第二金屬層 363 側壁金屬層 391 第一圖案 411 第二圖案 421 第一電鍍區域 431 第一部分之面積 441 第三圖案 451 第一電鍍層 452 第二電鍍層 130743.doc •21 · 1360191 461 第二電鍍區域 3621 下表面23 second protective layer 24 third protective layer 25 solder resist layer 31 first surface 32 second surface 33 first conductive layer 34 second conductive layer 35 through hole 3 6 metal layer 130743.doc • 20- 1360191 37 electrical contact Pad 38 connection line 39 first protective layer 41 second protective layer 42 first solder resist layer 43 third conductive layer 44 third protective layer 46 fourth protective layer 47 second solder resist layer 161 first metal layer 162 second metal Layer 163 sidewall metal layer 221 first plating layer 222 second plating layer 361 first metal layer 362 second metal layer 363 sidewall metal layer 391 first pattern 411 second pattern 421 first plating region 431 area of the first portion 441 third Pattern 451 First plating layer 452 Second plating layer 130743.doc • 21 · 1360191 461 Second plating area 3621 Lower surface
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