1358880 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種補償電路，且特別是有關於一種 用於電流模式（current-mode)之DC/DC轉換器的斜率補償 電路》 【先前技術】 在一般電流模式（current-mode)的直流對直流（DC/DC) 轉換器中，通常會存在一斜率補償電路，用以改變參考電 壓與電流感應信號在交會之後其信號的斜率。此時，斜率 補償電路可輸出一斜率補償信號，並疊加於上述用來作為 控制參數的電流感應信號，藉以避免DC/DC轉換器中會有 開迴路不穩定性（open loop instability)或是次諸波振盪 (sub-harmonic oscillation)的問題。 以過去的作法而言，斜率補償信號係藉由將振盪器產 生的振盪信號作轉換，並將其疊加於電流感應信號而得。 然而’上述的振盪信號在產生時，通常是以一接地信號為 參考點；因此’一旦接地信號不穩定或是具有脈波雜訊 (glitch)的話，以上述方式獲得的斜率補償信號也將遭受影 響’而具有偏移以及失真的問題。如此一來，則更無法有 效地防止上述開迴路不穩定性或是次諧波振盪的問題，甚 至連整體DC/DC轉換器也可能無法正常地運作。 【發明内容】 6 本發明的目的是在提供一種斜率補償電路，用以解決 斜率補償信銳因不穩定的接地信號或是脈波雜訊所導致的 偏移以及失真問題。 本發明的另一目的是在提供一種DC/DC轉換器，用以 改善其中開迴路不穩定性或是次諧波振盪的問題。 依照本發明一實施例’提出一種斜率補償電路，包含 一第一差動對電路、一電流鏡單元、一第一操作電流產生 電路以及一轉導補償電路β第一差動對電路與一第一電流 源連接’並用以接收一對差動振盪信號而產生相對應於差 動振盪信號之一對差動電流。電流鏡單元與第一差動對電 路連接’並用以鏡像處理上述差動電流。第一操作電流產 生電路與電流鏡單元連接，並用以產生一第一操作電流， 其中第一操作電流包括上述差動電流。轉導補償電路係用 以穩定第一操作電流產生電路中之一靜態操作點，並接收 上述差動振盈信號而產生一輸出電流，其中輸出電流之值 是數倍於第一操作電流之值。 依照本發明另一實施例，提出一種DC/DC轉換器，包 含一控制電路、一切換開關以及一斜率補償電路。控制電 路係用以輸出一脈衝驅動信號。切換開關係藉由脈衝驅動 信號啟動’使得一電感經由一輸入電壓充電後產生一電感 電流。斜率補償電路係用以接收一對差動振盪信號而產生 一輸出電流，此輸出電流係疊加於接收電感電流之一電流 感應電路所輸出之一電流感應信號上，且疊加後之輸出電 流和電流感應信號係轉換為一回授信號以控制上述控制電 1358880 路。斜率補償電路包含一第一差動對電路、一電流鏡單元、 一第一操作電流產生電路以及一轉導補償電路。第—差動 對電路連接一第一電流源，並用以接收差動振盪信號而產 生相對應於差動振盪信號之一對差動電流。電流鏡單元連 接第一差動對電路，並用以鏡像處理上述差動電流。第一 操作電流產生電路連接電流鏡單元，並用以產生一第一操 作電流，其中第一操作電流包括上述差動電流。轉導補償 電路係用以穩定第一操作電流產生電路中之一靜態操作 點，並接收上述差動振盪信號而產生輸出電流，其中輸出 電流之值是數倍於第一操作電流之值。 根據本發明之技術内容，應用前述之斜率補償電路， 可不受接地信號的影響’並較先前作法提供更穩定的斜率 補償信號。如此一來，便可有效地避免DC/DC轉換器中開 迴路不穩定性或是次諧波振盪的問題，且DC/DC轉換器亦 可因此而完善地運作。 【實施方式】 第1圖係繪示依照本發明實施例之一種電流模式 (current-mode)之直流對直流（DC/DC)轉換器的主要電路方 塊圖。DC/DC轉換器100基本上包括電感L卜二極體D1、 控制電路102、切換開關104、電流感應電路106以及斜率 補償電路108。電感L1具有一第一端以及一第二端，其第 一端電性耦接於輪入電壓Vin，其第二端則電性耦接於切換 開關104及二極體D1的陽極。當切換開關104啟動時，電 8 1358880 感L1會由輸入電壓Vin進行充電，然後產生一電感電流 k，接著輸出電壓Vout再於二極體D1的陰極產生。此外， 電流感應電路106則是接收電感電流iL，並且輸出一電流 感應信號CS。 斜率補償電路108接收一對差動振盪信號VP和VN(缯· 示於第2圖），而產生一斜率補償信號SS疊加於電流感應 信號CS上，且疊加後的斜率補償信號SS和電流感應信號 CS再轉換為一回授信號FS，藉以對控制電路1〇2進行控 制。在一實施例中，斜率補償信號SS和電流感應信號CS 均是以電流的形式呈現’且兩電流疊加之後再轉換為一電 壓（即回授信號FS) ’對控制電路1 〇2進行控制。控制電路 102則可因此輸出以脈衝寬度調變（PWM)方式呈現的脈衝 驅動信號，藉以啟動切換開關104。 第2圖係繪示依照本發明實施例之一種斜率補償電路 的示意圖。斜率補償電路200包括一第一電流源202、一第 一差動對電路210、一電流鏡單元220、一第一操作電流產 生電路230以及一轉導補償電路280。第一差動對電路210 係電性連接於第一電流源202，並接收差動振盪信號VP和 VN ’藉以分別產生相對應於差動振盪信號vp和Vn的差 動電流il和i2。由於在此係使用差動振盪信號VP和VN 來作為輸入信號，因此當振盪信號具有脈波雜訊（glitch)或 偏移（offset)時，斜率補償電路200的輸入仍然可具有穩定 的狀態而較為準確》 電流鏡單元220係電性連接於第一差動對電路210,並 9 且對差動電流il和i2作鏡像處理（mirr〇ring)。第一操作電 流產生電路230則是電性連接於電流鏡單元22〇,並且根據 電流鏡單元220作鏡像處理之後的差動電流丨丨和i2，產生 一第一操作電流i3 ’使得第一操作電流i3基本上包括差動 電流11和12。換言之，電流鏡單元220係電性連接於第一 差動對電路210以及第一操作電流產生電路23〇之間，並 且對自第一差動對電路21〇流出的差動電流丨丨和口作鏡像 處理’使差動電流il和i2鏡像轉移至第一操作電流產生電 路 230。 轉導補償電路280係用以穩定第一操作電流產生電路 230中之一靜態操作點，或稱偏壓點，或簡稱Q-point(使裝 置以特定方式進行操作的直流電壓及/或電流），並且亦接收 差動振盈信號VP和VN而產生輪出信號（例如：其值是數 倍於第一操作電流i3的輸出電流i6)，以供與電流感應信號 CS疊加。 在本實施例中，轉導補償電路280更包括一第二電流 源204、一第二差動對電路24〇、一電流鏡25〇以及一第二 操作電流產生電路260 »第二電流源204係與第一電流源 202電性並聯相接’並可用以提供與第一電流源202相同或 不同的電流’或甚至是提供與第一電流源2〇2有倍數關係 的電流°在一實施例中，由第一電流源202所提供的電流， 其值是數倍於第二電流源204所提供的電流》 第二差動對電路240係與第二電流源204電性連接， 並接收差動振盛信號VP和VN，藉以產生相對應於差動振 1358880 盡信號VP和VN的差動電流i4。電流鏡250則是電性連接 於第二差動對電路24〇以及第二操作電流產生電路26〇之 間，並且對自第二差動對電路240流出的差動電流u作鏡 像處理’使差動電流i4鏡像轉移至第二操作電流產生電路 260。此外’第二操作電流產生電路26〇更與第一操作電流 產生電路230電性連接於節點QE’藉以與第二差動對電路 240和電流鏡250相互作用之後，穩定第一操作電流產生電 路230中的靜態操作點，並產生輸出電流i6。之後，輸出 電流i6再與電流感應信號CS疊加，並傳送至一假性 (dummy)負载 206。 簡單地來說’上述實施例是利用差動振盪信號VP和 VN輸入至斜率補償電路2〇〇中’所以當差動振盪信號 和VN其中一者有任何不穩定或是脈波雜訊的情形時，第 一操作電流產生電路23〇中的靜態操作點也可能因此不穩 定；亦即’節點QE的電壓可能會變動’使得第一操作電流 ι3不穩定。因此’第二差動對電路24〇、電流鏡25〇以及 第二操作電流產生電路26〇便是用來穩定第一操作電流產 生電路230中的靜態操作點，並且讓節點qe具有穩定的電 壓’使得第一操作電流i3可處於穩定的狀態，且輸出電流 i6亦可因此處於穩定的狀態。 在一實施例（如第2圖所示）中，第一差動對電路210 可更包括PMOS電晶體MP1和MP2。電晶體MP1的閘極 接收振盪信號VN’其源極與第一電流源202電性連接，其 没極則是與電流鏡單元220電性連接。電晶體MP1和MP2 11 1358880 在受到差動振盪信號VP和VN控制後，可因而開啟或關 閉，並分別據以產生差動電流il和i2。 第一電流源202可更包括PMOS電晶體MP6，其中電 晶體MP6的閘極和源極係與一高電壓源AVDD電性連接， 而其汲極則是與電晶體ΜP1和MP 2的源極電性連接於節點 MP6D。 再者，電流鏡單元220可更包括兩電流鏡222和224， 其中電流鏡222係與電晶體ΜΡ1電性連接，並對差動電流 il作鏡像處理，而電流鏡224則是與電晶體ΜΡ2電性連 接，並對差動電流i2作鏡像處理。在本實施例中，電流鏡 222可包括NMOS電晶體MN1和MN3，其中電晶體MN1 的閘極和汲極是與電晶體MP1的汲極電性連接，其源極是 與一低電壓源AVSS電性連接；此外，電晶體MN3的閘極 是與電晶體MN1的閘極電性連接，其汲極是與第一操作電 流產生電路230電性連接，其源極則是與低電壓源AVSS 電性連接。 另一方面，與電晶體MP2電性連接的電流鏡224則是 相似於與電晶體MP1電性連接的電流鏡222。在本實施例 中，電流鏡224可包括NMOS電晶體MN2和MN4，其中 電晶體MN2的閘極和汲極是與電晶體MP2的汲極電性連 接，其源極則是與低電壓源AVSS電性連接；此外，電晶 體MN4的閘極是與電晶體MP2的閘極，其汲極是與第一 操作電流產生電路230電性連接，其源極則是與低電壓源 AVSS電性連接。 12 1358880 另外，第一操作電流產生電路230可更包括PMOS電 晶體MP3和MP4，其中電晶體MP3的閘極和汲極是與電 晶體MN3的汲極電性連接，其源極則是與高電壓源AVDD 電性連接；而電晶體MP4的閘極是與電晶體MP3的閘極電 性連接，其汲極是與電晶體MN4的汲極電性連接於節點 QE，其源極則是與高電壓源AVDD電性連接《在另一實施 例中，第一操作電流產生電路230可以另一、電流鏡的形式 呈現》 如此一來，差動電流il便會自電晶體ΜΡ1，經由電晶 體MN1和MN3，鏡像轉移至電晶體MP3，而後再進一步 自電晶體MP3鏡像轉移至電晶體MP4;而差動電流i2則是 會自電晶體MP2，經由電晶體MN2和MN4，鏡像轉移至 電晶體MP4。因此，包括差動電流Π和i2的第一操作電流 i3便由此產生。 在轉導補償電路280中，第二差動對電路240可更包 括PMOS電晶體MP9和MP10，其中電晶體MP9的閘極接 收振盪信號VP，其源極是與第二電流源204電性連接，其 汲極則是與電流鏡250電性連接；而電晶體MP10的閘極 接收振盪信號VN，其源極是與第二電流源204電性連接， 其没極則是與電流鏡250電性連接。同樣地，電晶體MP9 和MP10在受到差動振盪信號VP和VN控制之後，可因而 開啟或關閉，並據以產生差動電流Η。 在一般類比積體電路的設計中，電晶體係以多指狀 (multi-finger)的方式來呈現；換言之，較大尺寸的電晶體係 13 1358880 由數個較小尺寸的電晶體並聯相接製成。在一實施例中， 第二差動對電路240中的電晶體MP9和MP10各具有寬度/ 長度（W/L)為8微米/2微米（以m)的比例，且第一差動對電 路210中的電晶體MP1和MP2各是以8個指狀結構 (finger)(M=8)來呈現，其中每一指狀結構均具有W/L為8 微米/2微米的比例。換句話說，電晶體MP1和MP2的尺寸 大小均是電晶體MP9和MP10的8倍。因此，在第一差動 對電路210的電路佈局中，實際上會存在8個PMOS電晶 體並聯相接而形成單一電晶體MP1或MP2，且每一個 PMOS電晶體均具有寬度為8微米而長度為2微米的尺寸。 第二電流源204可更包括PMOS電晶體MP11，其中電 晶體MP11的閘極是與電晶體MP6的閘極電性連接，其源 極是與高電壓源AVDD電性連接，其汲極則是與電晶體 MP9和MP10的源極電性連接》在一實施例中，第二電流 源204中的電晶體MP11係以5個指狀結構(M=5)來呈現， 其中每一指狀結構均具有W/L為20微米/1微米的比例； 而第一電流源202中的電晶體MP6則是以40個指狀結構 (M=40)來呈現，其中每一指狀結構亦均具有W/L為微 米/1微米的比例。亦即，電晶體MP6的尺寸大小是電晶體 MP11的8倍。 電流鏡250可更包括NMOS電晶體MN7和MN8，其 中電晶體MN8的閘極和汲極是相互連接，並與電晶體Mj>9 和MP10的汲極電性連接，其源極則是與低電源電壓AV% 電性連接。而電晶體MN7的閘極是與電晶體MN8的閘極 14 1358880 電性連接，其源極是與低電源電壓AVSS電性連接，其汲 極則是與第二操作電流產生電路260電性連接。 除此之外，第二操作電流產生電路260可包括電晶體 MP7和MP8，其中電晶體MP7的閘極和汲極相互連接，並 與電晶體MP4的汲極電性連接於節點QE，且與電晶體MN7 的汲極電性連接於節點PE，其源極則是與高電源電壓 AVDD電性連接。電晶體MP8的閘極是與電晶體MP7的汲 極電性連接，其源極是與高電源電壓AVDD電性連接，其 汲極則是與假性負載206電性連接。其中，假性負載206 可以一 PMOS電晶體MPCSR的形式呈現，且電晶體MPCSR 的閘極和汲極是與低電源電壓AVSS電性連接，其源極則 是與電晶體MP8的汲極電性連接。 如此一來，與差動電流i2相似的電流i4便可自電晶體 MP9和MP10，經由電晶體MN7和MN8，鏡像轉移至電晶 體MP7，藉以作為電流i5，且無論何時差動振盪信號VP 和VN係處於不穩定或具有脈波雜訊，節點QE和PE均可 操作於相同電壓而呈穩定狀態。此外，輸出電流i6亦可由 電流i5鏡像而得，且穩定地輸出而疊加於電流感應信號 CS。 由上述本發明之實施例可知，應用本發明之斜率補償 電路可不受接地信號的影響，並較先前作法提供更穩定的 輸出信號。如此一來，便可有效地避免DC/DC轉換器中開 迴路不穩定性或是次諧波振盪的問題，且DC/DC轉換器亦 可因此而完善地運作。 15 1358880 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何具有本發明所屬技術領域之通常知識者，在 不脫離本發明之精神和範圍内，當可作各種之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1圖係繪示依照本發明實施例之一種電流模式之直 流對直流轉換器的主要電路方塊圖。 第2圖係繪示依照本發明實施例之一種斜率補償電路 的示意圖。 主要元件符號說明】 100 ： DC/DC轉換器 104 ： 切換開關 108、 200 :斜率補償電路 204 ： 第二電流源 220 ： 電流鏡單元 240 : 第二差動對電路 230 ： 第一操作電流產生1 260 ： 第二操作電流產生11358880 IX. Description of the Invention: [Technical Field] The present invention relates to a compensation circuit, and more particularly to a slope compensation circuit for a current-mode DC/DC converter. Technology] In a current-mode DC-to-DC converter, there is usually a slope compensation circuit that changes the slope of the signal after the reference voltage and current sense signals meet. At this time, the slope compensation circuit can output a slope compensation signal and superimpose the current sensing signal used as a control parameter to avoid open loop instability or secondary in the DC/DC converter. The problem of sub-harmonic oscillation. In the past, the slope compensation signal is obtained by converting the oscillation signal generated by the oscillator and superimposing it on the current sensing signal. However, when the above-mentioned oscillating signal is generated, it is usually a grounding signal as a reference point; therefore, once the grounding signal is unstable or has glitch, the slope compensation signal obtained in the above manner will also suffer. Affects 'with offset and distortion problems. As a result, it is impossible to effectively prevent the above-mentioned open circuit instability or subharmonic oscillation, and even the overall DC/DC converter may not operate normally. SUMMARY OF THE INVENTION [6] It is an object of the present invention to provide a slope compensation circuit for solving the problem of offset and distortion caused by an unstable ground signal or pulse wave noise. Another object of the present invention is to provide a DC/DC converter for improving the problem of open loop instability or subharmonic oscillation therein. According to an embodiment of the present invention, a slope compensation circuit is provided, including a first differential pair circuit, a current mirror unit, a first operational current generating circuit, and a transduction compensation circuit β first differential pair circuit and a first A current source is coupled to 'and receives a pair of differential oscillating signals to generate a differential current corresponding to one of the differential oscillating signals. The current mirror unit is coupled to the first differential pair circuit and is used to mirror the differential current. The first operating current generating circuit is coupled to the current mirror unit and configured to generate a first operating current, wherein the first operating current comprises the differential current. The transduction compensation circuit is configured to stabilize a static operating point in the first operating current generating circuit, and receive the differential vibrating signal to generate an output current, wherein the value of the output current is several times the value of the first operating current . In accordance with another embodiment of the present invention, a DC/DC converter is provided that includes a control circuit, a switch, and a slope compensation circuit. The control circuit is used to output a pulse drive signal. The switching-on relationship is initiated by a pulse-driven signal to cause an inductor to be charged via an input voltage to generate an inductor current. The slope compensation circuit is configured to receive a pair of differential oscillation signals to generate an output current, which is superimposed on one of the current sensing signals outputted by the current sensing circuit of the receiving inductor current, and the superimposed output current and current The sensing signal is converted into a feedback signal to control the above control circuit 1358880. The slope compensation circuit includes a first differential pair circuit, a current mirror unit, a first operational current generating circuit, and a transduction compensation circuit. The first-differential pair connects the first current source to the circuit and receives the differential oscillating signal to generate a differential current corresponding to one of the differential oscillating signals. The current mirror unit is coupled to the first differential pair circuit and mirrored for the differential current. The first operational current generating circuit is coupled to the current mirror unit and configured to generate a first operational current, wherein the first operational current comprises the differential current. The transduction compensation circuit is configured to stabilize a static operating point in the first operational current generating circuit and receive the differential oscillating signal to generate an output current, wherein the value of the output current is several times the value of the first operating current. According to the technical content of the present invention, the aforementioned slope compensation circuit can be applied without being affected by the ground signal' and provides a more stable slope compensation signal than the prior art. In this way, the problem of open circuit instability or subharmonic oscillation in the DC/DC converter can be effectively avoided, and the DC/DC converter can also operate with perfection. [Embodiment] FIG. 1 is a main circuit block diagram of a current-mode DC-DC converter according to an embodiment of the present invention. The DC/DC converter 100 basically includes an inductor L diode D1, a control circuit 102, a changeover switch 104, a current sense circuit 106, and a slope compensation circuit 108. The inductor L1 has a first end and a second end. The first end is electrically coupled to the turn-in voltage Vin, and the second end is electrically coupled to the switch 104 and the anode of the diode D1. When the switch 104 is activated, the sense 8 L1 is charged by the input voltage Vin, and then an inductor current k is generated, and then the output voltage Vout is generated at the cathode of the diode D1. In addition, the current sensing circuit 106 receives the inductor current iL and outputs a current sensing signal CS. The slope compensation circuit 108 receives a pair of differential oscillation signals VP and VN (shown in FIG. 2), and generates a slope compensation signal SS superimposed on the current sensing signal CS, and the superimposed slope compensation signal SS and current sensing The signal CS is again converted into a feedback signal FS, whereby the control circuit 1〇2 is controlled. In one embodiment, both the slope compensation signal SS and the current sense signal CS are presented in the form of currents and the two currents are superimposed and then converted to a voltage (i.e., feedback signal FS)' to control the control circuit 〇2. Control circuit 102 can thus output a pulsed drive signal that is presented in a pulse width modulation (PWM) manner to initiate switching switch 104. Figure 2 is a schematic diagram showing a slope compensation circuit in accordance with an embodiment of the present invention. The slope compensation circuit 200 includes a first current source 202, a first differential pair circuit 210, a current mirror unit 220, a first operating current generating circuit 230, and a transconductance compensation circuit 280. The first differential pair circuit 210 is electrically connected to the first current source 202, and receives the differential oscillation signals VP and VN' to generate differential currents il and i2 corresponding to the differential oscillation signals vp and Vn, respectively. Since the differential oscillation signals VP and VN are used as input signals here, when the oscillation signal has pulse glitch or offset, the input of the slope compensation circuit 200 can still have a stable state. More accurately, the current mirror unit 220 is electrically connected to the first differential pair circuit 210, and mirrors the differential currents il and i2. The first operating current generating circuit 230 is electrically connected to the current mirror unit 22 and, according to the differential currents 丨丨 and i2 after the mirror processing of the current mirror unit 220, generates a first operating current i3 ′ such that the first operation Current i3 basically includes differential currents 11 and 12. In other words, the current mirror unit 220 is electrically connected between the first differential pair circuit 210 and the first operating current generating circuit 23A, and the differential current flowing from the first differential pair circuit 21〇 The mirroring process 'transfers the differential currents il and i2 to the first operational current generating circuit 230. The transduction compensation circuit 280 is configured to stabilize a static operating point, or bias point, or Q-point (a DC voltage and/or current that causes the device to operate in a specific manner) in the first operational current generating circuit 230. And also receiving the differential oscillation signals VP and VN to generate a turn-off signal (for example, the output current i6 whose value is several times the first operating current i3) for superposition with the current sensing signal CS. In this embodiment, the transduction compensation circuit 280 further includes a second current source 204, a second differential pair circuit 24A, a current mirror 25A, and a second operating current generating circuit 260 » a second current source 204. Is electrically connected in parallel with the first current source 202 and can be used to provide the same or different current as the first current source 202 or even provide a current having a multiple relationship with the first current source 2〇2. In the example, the current provided by the first current source 202 is multiplied by the current provided by the second current source 204. The second differential pair circuit 240 is electrically connected to the second current source 204 and receives The differential oscillating signals VP and VN are used to generate a differential current i4 corresponding to the differential oscillations 1358880 and the signal VP and VN. The current mirror 250 is electrically connected between the second differential pair circuit 24A and the second operating current generating circuit 26A, and mirrors the differential current u flowing from the second differential pair circuit 240. The differential current i4 is mirrored to the second operational current generating circuit 260. In addition, after the second operational current generating circuit 26 is electrically connected to the first operational current generating circuit 230 to the node QE′ to interact with the second differential pair circuit 240 and the current mirror 250, the first operational current generating circuit is stabilized. A static operating point in 230 and produces an output current i6. Thereafter, the output current i6 is superimposed with the current sense signal CS and transmitted to a dummy load 206. Simply speaking, the above embodiment uses the differential oscillation signals VP and VN to be input to the slope compensation circuit 2'. Therefore, when any one of the differential oscillation signal and the VN has any instability or pulse noise, At this time, the static operating point in the first operational current generating circuit 23A may also be unstable; that is, the voltage of the node QE may fluctuate such that the first operational current ι3 is unstable. Therefore, the 'second differential pair circuit 24', the current mirror 25A, and the second operating current generating circuit 26 are used to stabilize the static operating point in the first operating current generating circuit 230, and let the node qe have a stable voltage. 'Making the first operating current i3 to be in a stable state, and the output current i6 can therefore be in a stable state. In an embodiment (as shown in FIG. 2), the first differential pair circuit 210 may further include PMOS transistors MP1 and MP2. The gate of the transistor MP1 receives the oscillating signal VN', and its source is electrically connected to the first current source 202, and the pole is electrically connected to the current mirror unit 220. The transistors MP1 and MP2 11 1358880 can be turned on or off after being controlled by the differential oscillation signals VP and VN, and accordingly generate differential currents il and i2, respectively. The first current source 202 can further include a PMOS transistor MP6, wherein the gate and source of the transistor MP6 are electrically connected to a high voltage source AVDD, and the drain is connected to the source of the transistors 1P1 and MP2. Electrically connected to the node MP6D. Furthermore, the current mirror unit 220 can further include two current mirrors 222 and 224, wherein the current mirror 222 is electrically connected to the transistor ΜΡ1 and mirrors the differential current il, and the current mirror 224 is connected to the transistor ΜΡ2. Electrically connected and mirrored the differential current i2. In this embodiment, the current mirror 222 can include NMOS transistors MN1 and MN3, wherein the gate and the drain of the transistor MN1 are electrically connected to the drain of the transistor MP1, and the source thereof is connected to a low voltage source AVSS. In addition, the gate of the transistor MN3 is electrically connected to the gate of the transistor MN1, the drain of the transistor is electrically connected to the first operating current generating circuit 230, and the source thereof is connected to the low voltage source AVSS. Electrical connection. On the other hand, the current mirror 224 electrically connected to the transistor MP2 is similar to the current mirror 222 electrically connected to the transistor MP1. In this embodiment, the current mirror 224 may include NMOS transistors MN2 and MN4, wherein the gate and the drain of the transistor MN2 are electrically connected to the drain of the transistor MP2, and the source thereof is connected to the low voltage source AVSS. In addition, the gate of the transistor MN4 is connected to the gate of the transistor MP2, the drain of the transistor is electrically connected to the first operating current generating circuit 230, and the source thereof is electrically connected to the low voltage source AVSS. . 12 1358880 In addition, the first operating current generating circuit 230 may further include PMOS transistors MP3 and MP4, wherein the gate and the drain of the transistor MP3 are electrically connected to the gate of the transistor MN3, and the source thereof is high. The voltage source AVDD is electrically connected; the gate of the transistor MP4 is electrically connected to the gate of the transistor MP3, and the drain is electrically connected to the node QE of the gate of the transistor MN4, and the source thereof is The high voltage source AVDD is electrically connected. In another embodiment, the first operational current generating circuit 230 can be presented in the form of another current mirror. Thus, the differential current il will be from the transistor ,1 via the transistor. MN1 and MN3, the image is transferred to the transistor MP3, and then further transferred from the transistor MP3 image to the transistor MP4; and the differential current i2 is from the transistor MP2, through the transistors MN2 and MN4, mirror image transfer to the transistor MP4. Therefore, the first operating current i3 including the differential currents Π and i2 is thereby generated. In the transduction compensation circuit 280, the second differential pair circuit 240 may further include PMOS transistors MP9 and MP10, wherein the gate of the transistor MP9 receives the oscillating signal VP, and the source thereof is electrically connected to the second current source 204. The gate of the transistor MP10 receives the oscillating signal VN, the source of which is electrically connected to the second current source 204, and the pole of the transistor is electrically connected to the current mirror 250. Sexual connection. Similarly, the transistors MP9 and MP10 can be turned on or off after being controlled by the differential oscillation signals VP and VN, and accordingly a differential current 产生 is generated. In the design of a general analog integrated circuit, the electro-crystalline system is presented in a multi-finger manner; in other words, the larger-sized electro-crystalline system 13 1358880 is connected in parallel by several smaller-sized transistors. production. In one embodiment, the transistors MP9 and MP10 in the second differential pair circuit 240 each have a width/length (W/L) ratio of 8 microns/2 microns (in m), and the first differential pair circuit The transistors MP1 and MP2 in 210 are each represented by eight fingers (M=8), each of which has a ratio of W/L of 8 μm to 2 μm. In other words, the sizes of the transistors MP1 and MP2 are eight times that of the transistors MP9 and MP10. Therefore, in the circuit layout of the first differential pair circuit 210, there are actually eight PMOS transistors connected in parallel to form a single transistor MP1 or MP2, and each PMOS transistor has a width of 8 micrometers and a length. It is a 2 micron size. The second current source 204 may further include a PMOS transistor MP11, wherein the gate of the transistor MP11 is electrically connected to the gate of the transistor MP6, the source thereof is electrically connected to the high voltage source AVDD, and the drain is The source is electrically connected to the sources of the transistors MP9 and MP10. In one embodiment, the transistor MP11 in the second current source 204 is presented in five finger structures (M=5), wherein each finger structure Each has a ratio of W/L of 20 μm / 1 μm; and the transistor MP6 of the first current source 202 is represented by 40 finger structures (M=40), wherein each finger structure also has W/L is a ratio of micron / 1 micron. That is, the size of the transistor MP6 is eight times that of the transistor MP11. The current mirror 250 may further include NMOS transistors MN7 and MN8, wherein the gate and the drain of the transistor MN8 are connected to each other and electrically connected to the gates of the transistors Mj > 9 and MP10, and the source is low and low. The power supply voltage is AV% electrically connected. The gate of the transistor MN7 is electrically connected to the gate 14 1358880 of the transistor MN8, the source thereof is electrically connected to the low power supply voltage AVSS, and the drain thereof is electrically connected to the second operating current generating circuit 260. . In addition, the second operating current generating circuit 260 may include transistors MP7 and MP8, wherein the gate and the drain of the transistor MP7 are connected to each other, and are electrically connected to the node QE of the gate of the transistor MP4, and The drain of the transistor MN7 is electrically connected to the node PE, and the source thereof is electrically connected to the high power supply voltage AVDD. The gate of the transistor MP8 is electrically connected to the anode of the transistor MP7, the source of which is electrically connected to the high power supply voltage AVDD, and the drain of which is electrically connected to the dummy load 206. The dummy load 206 can be presented in the form of a PMOS transistor MPCSR, and the gate and the drain of the transistor MPCSR are electrically connected to the low power supply voltage AVSS, and the source is electrically connected to the gate of the transistor MP8. connection. In this way, the current i4 similar to the differential current i2 can be mirrored from the transistors MP9 and MP10, via the transistors MN7 and MN8, to the transistor MP7, thereby acting as the current i5, and whenever the differential oscillating signal VP and The VN system is unstable or has pulse wave noise, and both the nodes QE and PE can operate at the same voltage and are in a stable state. Further, the output current i6 can also be obtained by mirroring the current i5, and is stably outputted and superimposed on the current sensing signal CS. It will be apparent from the above-described embodiments of the present invention that the slope compensation circuit to which the present invention is applied is not affected by the ground signal and provides a more stable output signal than the prior art. In this way, the problem of open circuit instability or subharmonic oscillation in the DC/DC converter can be effectively avoided, and the DC/DC converter can also operate with perfection. The present invention has been disclosed in the above embodiments, and is not intended to limit the invention, and any one of ordinary skill in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the main circuit of a current mode DC-DC converter in accordance with an embodiment of the present invention. Figure 2 is a schematic diagram showing a slope compensation circuit in accordance with an embodiment of the present invention. Main component symbol description] 100: DC/DC converter 104: diverter switch 108, 200: slope compensation circuit 204: second current source 220: current mirror unit 240: second differential pair circuit 230: first operational current generation 1 260: The second operating current is generated 1
102 :控制電路 106 :電流感應電路 202 :第一電流源 210 :第一差動對電路 222、224、250 :電流鏡 28〇 :轉導補償電路 路 路102: control circuit 106: current sensing circuit 202: first current source 210: first differential pair circuit 222, 224, 250: current mirror 28〇: transduction compensation circuit circuit