JP2007159077A - Oscillation circuit - Google Patents

Oscillation circuit Download PDF

Info

Publication number
JP2007159077A
JP2007159077A JP2005380816A JP2005380816A JP2007159077A JP 2007159077 A JP2007159077 A JP 2007159077A JP 2005380816 A JP2005380816 A JP 2005380816A JP 2005380816 A JP2005380816 A JP 2005380816A JP 2007159077 A JP2007159077 A JP 2007159077A
Authority
JP
Japan
Prior art keywords
circuit
oscillation
capacitor
transistor
inverter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005380816A
Other languages
Japanese (ja)
Inventor
Naoki Saito
Masatoshi Sato
正敏 佐藤
直紀 斉藤
Original Assignee
Seiko Npc Corp
セイコーNpc株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Npc Corp, セイコーNpc株式会社 filed Critical Seiko Npc Corp
Priority to JP2005380816A priority Critical patent/JP2007159077A/en
Publication of JP2007159077A publication Critical patent/JP2007159077A/en
Withdrawn legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit which reduces variation in oscillation characteristics and is capable of stable oscillation from a low voltage. <P>SOLUTION: An oscillation circuit includes: an inverter circuit; a feedback resistor connected in parallel to the inverter circuit; a first capacitor connected between one terminal of the feedback resistor and a power source; and a second capacitor connected between another terminal of the feedback resistor and the power source, and generates an oscillation output by connecting a crystal vibrator in parallel to the inverter circuit. In this oscillation circuit, the inverter circuit includes: a PchMOS transistor and NchMOS transistor connected in series between a power supply voltage and a constant voltage; and a third capacitor, wherein the input signal of the inverter circuit is given through the third capacitor to the gate of a transistor for which one terminal of a current path is connected to the constant voltage, between these transistors. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は水晶振動子を用いた発振回路に関する。  The present invention relates to an oscillation circuit using a crystal resonator.

従来の発振回路の構成を図3に示す。発振回路は、PchMOSトランジスタ2とNchMOSトランジスタ3とが高電位電源(電源電圧)と低電位電源(接地電位)との間で直列接続し構成されるインバータ回路と、該インバータ回路の入出力端子間に接続された水晶振動子1及び帰還抵抗4とを有し、インバータ回路の入力端は第1の容量6を介して低電位電源と接続され、インバータ回路の出力端は第2の容量7を介して低電位電源と接続されている。かかる発振回路の構成は、例えば特開2004−80650に記載されている。  The configuration of a conventional oscillation circuit is shown in FIG. The oscillation circuit includes an inverter circuit configured by connecting a PchMOS transistor 2 and an NchMOS transistor 3 in series between a high potential power supply (power supply voltage) and a low potential power supply (ground potential), and an input / output terminal of the inverter circuit The inverter 1 is connected to a low-potential power source via a first capacitor 6, and the output terminal of the inverter circuit is connected to a second capacitor 7. Via a low-potential power supply. The configuration of such an oscillation circuit is described in, for example, Japanese Patent Application Laid-Open No. 2004-80650.

特開2004−80650JP 2004-80650 A

従来の発振回路では、インバータ回路が電源電圧と接地電位間に接続されるような電源電圧を印加する形式であったため、電源電圧の変動に起因して発振特性の変動が大きかった。さらに発振振幅が大きく、水晶振動子に流れる電流が大きいため異常発振が出易い問題があった。  In the conventional oscillation circuit, since the inverter circuit is configured to apply a power supply voltage such that the inverter circuit is connected between the power supply voltage and the ground potential, fluctuations in oscillation characteristics are large due to fluctuations in the power supply voltage. Furthermore, there is a problem that abnormal oscillation is likely to occur because the oscillation amplitude is large and the current flowing through the crystal resonator is large.

このような発振特性の変動を低減する手段として、インバータ回路の接続される高電位電源を、電源電圧ではなく定電圧回路を用いて定電圧にすることが考えられる。しかしながら、該定電圧はその動作上、インバータ回路に用いられているPchMOSトランジスタ2のしきい値とNchMOSトランジスタ3のしきい値との和以上に設定しなければいけないため、低電圧で安定発振させるのが困難であった。  As a means for reducing such fluctuations in oscillation characteristics, it is conceivable to use a constant voltage circuit instead of the power supply voltage for the high potential power supply connected to the inverter circuit to a constant voltage. However, since the constant voltage must be set to be equal to or higher than the sum of the threshold value of the PchMOS transistor 2 and the threshold value of the NchMOS transistor 3 used in the inverter circuit in its operation, stable oscillation is performed at a low voltage. It was difficult.

上記課題を解決するために、本発明の発振回路は、インバータ回路と、前記インバータ回路に並列に接続された帰還抵抗と、前記帰還抵抗の一端と電源との間に接続された第1の容量と、前記帰還抵抗の他端と電源との間に接続された第2の容量とを有しており、前記インバータに水晶振動子を並列に接続することにより発振出力を生成する発振回路において、前記インバータ回路は、電源電圧と定電圧との間に直列に接続されたPchMOSトランジスタおよびNchMOSトランジスタと、第3の容量とを有し、前記トランジスタのうち前記定電位に電流通路の一端が接続された方のトランジスタのゲートには前記第3の容量を介してインバータ回路の入力信号が与えられる。  In order to solve the above problems, an oscillation circuit according to the present invention includes an inverter circuit, a feedback resistor connected in parallel to the inverter circuit, and a first capacitor connected between one end of the feedback resistor and a power source. And a second capacitor connected between the other end of the feedback resistor and a power source, and an oscillation circuit that generates an oscillation output by connecting a crystal resonator in parallel to the inverter, The inverter circuit includes a PchMOS transistor and an NchMOS transistor connected in series between a power supply voltage and a constant voltage, and a third capacitor, and one end of a current path is connected to the constant potential of the transistors. The input signal of the inverter circuit is supplied to the gate of the other transistor through the third capacitor.

また、前記発振回路は定電圧回路により生成される電圧で駆動されることを特徴とする。 The oscillation circuit is driven by a voltage generated by a constant voltage circuit.

また、前記発振回路は、前記インバータ回路の出力と前記帰還抵抗との間に直列に接続された出力抵抗を有することを特徴とする。 Further, the oscillation circuit has an output resistor connected in series between the output of the inverter circuit and the feedback resistor.

本発明によれば、発振インバータ回路のPchMOSトランジスタ又はNchMOSトランジスタのゲートを容量を介して信号が入力されることにより、低電圧からの発振開始が可能となる。
また、発振回路を定電圧回路で駆動することにより、高安定、低消費電流を可能とする。
更に、インバータ回路の出力と前記帰還抵抗との間に直列に接続された出力抵抗を有することにより、安定発振が可能となる。
According to the present invention, it is possible to start oscillation from a low voltage by inputting a signal to the gate of the PchMOS transistor or NchMOS transistor of the oscillation inverter circuit via the capacitor.
Further, driving the oscillation circuit with a constant voltage circuit enables high stability and low current consumption.
Furthermore, stable oscillation is possible by having an output resistor connected in series between the output of the inverter circuit and the feedback resistor. Furthermore, stable oscillation is possible by having an output resistor connected in series between the output of the inverter circuit and the feedback resistor.

また、本発明によれば、PchMOSトランジスタのゲートをカップリングしているため、低電圧からの安定発振が可能となる。さらに、発振振幅が小さいため、水晶振動子に流れる電流が少なく、出力抵抗を接続することでさらなる水晶電流の削減を可能とし、異常発振が起こり難い発振回路となる。  According to the present invention, since the gate of the PchMOS transistor is coupled, stable oscillation from a low voltage is possible. Furthermore, since the oscillation amplitude is small, the current flowing through the crystal resonator is small, and by connecting an output resistor, the crystal current can be further reduced, and an oscillation circuit in which abnormal oscillation hardly occurs is obtained.

以下、本発明の好適な実施の形態を添付図面を参照し説明する。図1は本発明の第1の実施の形態に係わる発振回路を示している。発振回路は、インバータ回路と、該インバータ回路の入出力端子間に接続された水晶振動子21及び帰還抵抗24とを有し、インバータ回路の入力端は第1の容量26を介して低電位電源と接続され、インバータ回路の出力端は抵抗素子25、第2の容量27を介して低電位電源と接続されている。出力抵抗25は、帰還回路の位相の安定化および水晶振動子21に印加される振幅レベルの減少のために用いられている。  Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an oscillation circuit according to the first embodiment of the present invention. The oscillation circuit includes an inverter circuit, a crystal resonator 21 and a feedback resistor 24 connected between the input and output terminals of the inverter circuit, and an input terminal of the inverter circuit is a low potential power source via a first capacitor 26. The output terminal of the inverter circuit is connected to the low potential power source via the resistance element 25 and the second capacitor 27. The output resistor 25 is used for stabilizing the phase of the feedback circuit and reducing the amplitude level applied to the crystal resonator 21.

本実施の形態の発振回路におけるインバータ回路は、高電位(定電位Vref)と低電位電源(接地電位)との間で直列接続し構成されるPchMOSトランジスタ22とNchMOSトランジスタ23とを有し、PchMOSトランジスタ22が接続される高電位は、定電位回路を用いて生成される定電位(Vref)が供給される。更に、そのソースが定電位(Vref)に接続されドレインとゲートが共通接続されたPchMOSトランジスタ28と、一端がPchMOSトランジスタ28のドレインに接続され他端が低電位電源に接続された抵抗素子29と、一端がPchMOSトランジスタ28のドレインに接続され他端がPchMOSトランジスタ22のゲートに接続された抵抗素子11と、PchMOSトランジスタ22のゲートと第1の容量26との間に接続された第3の容量10とを有する。  The inverter circuit in the oscillation circuit of the present embodiment includes a PchMOS transistor 22 and an NchMOS transistor 23 configured in series between a high potential (constant potential Vref) and a low potential power supply (ground potential). The high potential to which the transistor 22 is connected is supplied with a constant potential (Vref) generated using a constant potential circuit. Further, a PchMOS transistor 28 whose source is connected to a constant potential (Vref) and whose drain and gate are commonly connected, and a resistance element 29 whose one end is connected to the drain of the PchMOS transistor 28 and whose other end is connected to a low potential power source. The resistance element 11 having one end connected to the drain of the PchMOS transistor 28 and the other end connected to the gate of the PchMOS transistor 22, and a third capacitor connected between the gate of the PchMOS transistor 22 and the first capacitor 26. 10 and.

PchMOSトランジスタ28及び抵抗素子29は、PchMOSトランジスタ22のゲートバイアス電圧を印加するための素子であり、第3の容量10はインバータのバイアス回路とPchMOSトランジスタ22のゲートをAC的に分離するためのものである。  The PchMOS transistor 28 and the resistance element 29 are elements for applying the gate bias voltage of the PchMOS transistor 22, and the third capacitor 10 is for AC separation of the bias circuit of the inverter and the gate of the PchMOS transistor 22. It is.

PchMOSトランジスタ22のゲートには、PchMOSトランジスタ28及び抵抗素子29で決定されるバイアス電圧を中心に、カップリング容量10を介して入力される信号が印加される。従って、PchMOSトランジスタ28及び抵抗素子29で決定されるバイアス電圧を適正に選択することにより、インバータ回路に印加される電圧が低い場合でも、PchMOSトランジスタ22のしきい値に影響されず、NchMOSトランジスタ23のしきい値+αの電圧で発振開始することができる。さらに、発振回路を定電圧で動作させることにより、低電圧動作かつ発振特性の電源電圧依存性が少ない発振回路の構成が可能となる。  A signal input via the coupling capacitor 10 is applied to the gate of the PchMOS transistor 22 with a bias voltage determined by the PchMOS transistor 28 and the resistance element 29 as a center. Therefore, by appropriately selecting the bias voltage determined by the Pch MOS transistor 28 and the resistance element 29, the Nch MOS transistor 23 is not affected by the threshold value of the Pch MOS transistor 22 even when the voltage applied to the inverter circuit is low. Oscillation can be started at a voltage of the threshold value + α. Further, by operating the oscillation circuit at a constant voltage, it is possible to configure the oscillation circuit with low voltage operation and less oscillation power supply voltage dependency.

図2は本発明の第2の実施の形態に係わる発振回路であり、インバータ回路のNchMOSトランジスタのゲートをカップリングする場合の回路例である。
発振回路は、インバータ回路と、該インバータ回路の入出力端子間に接続された水晶振動子31及び帰還抵抗34とを有し、インバータ回路の入力端は第1の容量36を介して高電位電源と接続され、インバータ回路の出力端は抵抗素子35、第2の容量37を介して高電位電源と接続されている。 The oscillation circuit has an inverter circuit, a crystal oscillator 31 and a feedback resistor 34 connected between the input / output terminals of the inverter circuit, and the input end of the inverter circuit is a high-potential power supply via a first capacitance 36. The output end of the inverter circuit is connected to the high potential power supply via the resistance element 35 and the second capacitance 37. 出力抵抗35は、帰還回路の位相の安定化および水晶振動子31に印加される振幅レベルの減少のために用いられている。 The output resistor 35 is used to stabilize the phase of the feedback circuit and reduce the amplitude level applied to the crystal oscillator 31. FIG. 2 shows an oscillation circuit according to the second embodiment of the present invention, which is a circuit example in the case of coupling the gate of an NchMOS transistor of an inverter circuit. FIG. 2 shows an oscillation circuit according to the second embodiment of the present invention, which is a circuit example in the case of coupling the gate of an NchMOS transistor of an inverter circuit.
The oscillation circuit includes an inverter circuit, a crystal resonator 31 and a feedback resistor 34 connected between the input and output terminals of the inverter circuit, and the input terminal of the inverter circuit is a high potential power source via a first capacitor 36. The output terminal of the inverter circuit is connected to a high potential power source via a resistance element 35 and a second capacitor 37. The output resistor 35 is used for stabilizing the phase of the feedback circuit and reducing the amplitude level applied to the crystal unit 31. The oscillation circuit includes an inverter circuit, a crystal resonator 31 and a feedback resistor 34 connected between the input and output terminals of the inverter circuit, and the input terminal of the inverter circuit is a high potential power source via a first capacitor 36. The output terminal of the inverter circuit is connected to a high potential power source via a resistance element 35 and a second capacitor 37. The output resistor 35 is used for stabilizing the phase of the feedback circuit and reducing the amplitude level applied to the crystal unit 31 ..

本実施の形態の発振回路におけるインバータ回路は、高電位電源(電源電位)と低電位電源(定電位)との間で直列接続し構成されるPchMOSトランジスタ32とNchMOSトランジスタ33とを有し、NchMOSトランジスタ33が接続される低電位は、定電位回路を用いて生成される定電位(Vref)が供給される。更に、そのソースが定電位(Vref)に接続されドレインとゲートが共通接続されたNchMOSトランジスタ38と、一端がNchMOSトランジスタ38のドレインに接続され他端が高電位電源に接続された抵抗素子39と、一端がNchMOSトランジスタ38のドレインに接続され他端がNchMOSトランジスタ33のゲートに接続された抵抗素子41と、NchMOSトランジスタ33のゲートと第1の容量36との間に接続された第3の容量40とを有する。  The inverter circuit in the oscillation circuit according to the present embodiment includes a Pch MOS transistor 32 and an Nch MOS transistor 33 configured in series between a high potential power source (power source potential) and a low potential power source (constant potential). The low potential to which the transistor 33 is connected is supplied with a constant potential (Vref) generated using a constant potential circuit. Further, an NchMOS transistor 38 whose source is connected to a constant potential (Vref) and whose drain and gate are commonly connected, and a resistance element 39 whose one end is connected to the drain of the NchMOS transistor 38 and whose other end is connected to a high potential power source. A resistance element 41 having one end connected to the drain of the Nch MOS transistor 38 and the other end connected to the gate of the Nch MOS transistor 33, and a third capacitor connected between the gate of the Nch MOS transistor 33 and the first capacitor 36. 40.

NchMOSトランジスタ38及び抵抗素子39は、NchMOSトランジスタ33のゲートバイアス電圧を印加するための素子であり、第3の容量40はインバータのバイアス回路とNchMOSトランジスタ33のゲートをAC的に分離するためのものである。  The Nch MOS transistor 38 and the resistance element 39 are elements for applying the gate bias voltage of the Nch MOS transistor 33, and the third capacitor 40 is for separating the bias circuit of the inverter and the gate of the Nch MOS transistor 33 in an AC manner. It is.

NchMOSトランジスタ33のゲートには、NchMOSトランジスタ38及び抵抗素子39で決定されるバイアス電圧を中心に、第3の容量40を介して入力される信号が印加される。従って、NchMOSトランジスタ38及び抵抗素子39で決定されるバイアス電圧を適正に選択することにより、インバータ回路に印加される電圧が低い場合でも、PchMOSトランジスタ32のしきい値+αの電圧で発振開始することができる。さらに、発振回路を定電圧で動作させることにより、低電圧動作かつ発振特性の電源電圧依存性が少ない発振回路の構成が可能となる。  A signal input via the third capacitor 40 is applied to the gate of the Nch MOS transistor 33 with a bias voltage determined by the Nch MOS transistor 38 and the resistance element 39 as a center. Therefore, by appropriately selecting the bias voltage determined by the Nch MOS transistor 38 and the resistance element 39, even when the voltage applied to the inverter circuit is low, the oscillation starts at the voltage of the threshold value + α of the Pch MOS transistor 32. Can do. Further, by operating the oscillation circuit at a constant voltage, it is possible to configure the oscillation circuit with low voltage operation and less oscillation power supply voltage dependency.

上記実施の形態では、インバータ回路を構成するPchMOSトランジスタ又はNchMOSトランジスタの一方のみを容量を介して信号を入力させたが、両方のトランジスタに適用することも可能である。 In the above embodiment, the signal is input to only one of the PchMOS transistor and the NchMOS transistor constituting the inverter circuit through the capacitor. However, the present invention can be applied to both transistors.

本発明の第1の実施の形態に係わる発振回路を示す回路図である。 1 is a circuit diagram showing an oscillation circuit according to a first embodiment of the present invention. 本発明の第2の実施の形態に係わる発振回路を示す回路図である。 It is a circuit diagram which shows the oscillation circuit concerning the 2nd Embodiment of this invention. 従来技術のおける発振回路の一般的な構成を示した回路図である。 It is the circuit diagram which showed the general structure of the oscillation circuit in a prior art.

符号の説明Explanation of symbols

1、21、31:水晶振動子
2、22、32:PchMOSトランジスタ
3、23、33:NchMOSトランジスタ
4、24、34:帰還抵抗
25、35:出力抵抗
6、26、36:第1の容量
7、27、37:第2の容量
10、40:第3の容量、
1, 21, 31: Crystal resonators 2, 22, 32: Pch MOS transistors 3, 23, 33: Nch MOS transistors 4, 24, 34: Feedback resistor 25, 35: Output resistors 6, 26, 36: First capacitor 7 , 27, 37: second capacity 10, 40: third capacity,

Claims (3)

  1. インバータ回路と、前記インバータ回路に並列に接続された帰還抵抗と、前記帰還抵抗の一端と電源との間に接続された第1の容量と、前記帰還抵抗の他端と電源との間に接続された第2の容量とを有し、前記インバータに水晶振動子を並列に接続することにより発振出力を生成する発振回路において、前記インバータ回路は、電源電圧と定電圧との間に直列に接続されたPchMOSトランジスタおよびNchMOSトランジスタと、第3の容量とを有し、前記トランジスタのうち前記定電位に電流通路の一端が接続された方のトランジスタのゲートには前記第3の容量を介してインバータ回路の入力信号が与えられることを特徴とする発振回路。  An inverter circuit, a feedback resistor connected in parallel to the inverter circuit, a first capacitor connected between one end of the feedback resistor and a power source, and a connection between the other end of the feedback resistor and a power source An oscillation circuit that generates an oscillation output by connecting a crystal resonator in parallel to the inverter, the inverter circuit being connected in series between a power supply voltage and a constant voltage A PchMOS transistor and an NchMOS transistor, and a third capacitor, of which one end of a current path is connected to the constant potential, the gate of the transistor is connected to the inverter via the third capacitor. An oscillation circuit characterized by being provided with an input signal of the circuit.
  2. 前記発振回路は定電圧回路により生成される電圧で駆動されることを特徴とする請求項1記載の発振回路。 2. The oscillation circuit according to claim 1, wherein the oscillation circuit is driven by a voltage generated by a constant voltage circuit.
  3. 前記発振回路は、前記インバータ回路の出力と前記帰還抵抗との間に直列に接続された出力抵抗を有することを特徴とする請求項1記載の発振回路。 2. The oscillation circuit according to claim 1, wherein the oscillation circuit has an output resistor connected in series between an output of the inverter circuit and the feedback resistor.
JP2005380816A 2005-12-06 2005-12-06 Oscillation circuit Withdrawn JP2007159077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005380816A JP2007159077A (en) 2005-12-06 2005-12-06 Oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005380816A JP2007159077A (en) 2005-12-06 2005-12-06 Oscillation circuit

Publications (1)

Publication Number Publication Date
JP2007159077A true JP2007159077A (en) 2007-06-21

Family

ID=38242799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005380816A Withdrawn JP2007159077A (en) 2005-12-06 2005-12-06 Oscillation circuit

Country Status (1)

Country Link
JP (1) JP2007159077A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010171644A (en) * 2009-01-21 2010-08-05 Oki Semiconductor Co Ltd Constant current driven oscillating circuit
JP2014155184A (en) * 2013-02-13 2014-08-25 Seiko Npc Corp Integrated circuit for oscillation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010171644A (en) * 2009-01-21 2010-08-05 Oki Semiconductor Co Ltd Constant current driven oscillating circuit
JP2014155184A (en) * 2013-02-13 2014-08-25 Seiko Npc Corp Integrated circuit for oscillation

Similar Documents

Publication Publication Date Title
DE60318060T2 (en) Ringoscillator with frequency stabilization
US8766616B2 (en) Comparator, control circuit of switching regulator using the same, switching regulator, and electronic equipment
US6646469B2 (en) High voltage level shifter via capacitors
US6091307A (en) Rapid turn-on, controlled amplitude crystal oscillator
JP3957019B2 (en) DC-DC converter control circuit
US7683730B2 (en) Differential crystal oscillator circuit with peak regulation
US20040135567A1 (en) Switching regulator and slope correcting circuit
JP2009146130A (en) Dropper type regulator
JP4167255B2 (en) Oscillator start-up control circuit
US9093952B2 (en) Semiconductor device and control method thereof
JP2009239971A (en) Piezoelectric oscillator
JP3610556B1 (en) Constant voltage power supply
JP4259485B2 (en) Piezoelectric oscillation circuit
JP2005323413A (en) Overcurrent detection circuit and power supply comprising it
US7786777B2 (en) Circuit arrangement and method for the provision of a clock signal with an adjustable duty cycle
US6710669B2 (en) Voltage controlled oscillator
KR100814142B1 (en) Class d amplifier with start-up click noise elimination
JP2004086750A (en) Band gap circuit
US6515522B2 (en) Drive circuit of capacitive load and integrated circuit for driving capacitive load
US6133801A (en) Crystal oscillation circuit
US7307465B2 (en) Step-down voltage output circuit
US5126695A (en) Semiconductor integrated circuit device operated with an applied voltage lower than required by its clock oscillator
KR101059720B1 (en) Amplitude Level Control Circuit for Oscillator
US8106718B2 (en) GM-boosted differential drain-to-source feedback colpitts voltage controlled oscillator
US8098057B2 (en) Constant voltage circuit including supply unit having plural current sources

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081126

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110628

A761 Written withdrawal of application

Effective date: 20110818

Free format text: JAPANESE INTERMEDIATE CODE: A761