JP5296125B2 - Low power consumption circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact low-power consumption circuit that stably starts while minimizing an increase in current during start operation. <P>SOLUTION: The low-power consumption circuit includes: a first oscillation transistor P31; a second oscillation transistor N31 having a drain terminal connected to a drain terminal of the first oscillation transistor P31; a first capacity C2; a piezoelectric oscillator Q1 having one electrode connected to the first capacity C2 and having the other electrode connected to a connection node between the first oscillation transistor P31 and the second oscillation transistor N31; a feedback resistance circuit Z3 having one electrode connected to the piezoelectric oscillator Q1 and having the other electrode connected to a gate terminal of the first oscillation transistor P31; a first amplitude limiting element P32 having a first terminal connected to a gate terminal VP1 of the first oscillation transistor P31 and having a second terminal connected to the connection node; and a second amplitude limiting element N32 having a second terminal connected to a gate terminal VN1 of the second oscillation transistor N31 and having a first terminal connected to the connection node. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a low power consumption circuit, and more particularly to a low power consumption oscillation circuit and a low power consumption bias circuit that supplies a DC bias to drive the oscillation circuit.

  In a low power consumption IC (low power consumption circuit) typified by a watch or the like, reducing the current consumption to the limit leads to an extension of the battery life and produces great added value. For this reason, the current flowing in the low power consumption IC is set to a very small value such as several nA to several hundred nA.

  Patent Document 1 discloses a bias voltage generation circuit including a bias voltage generation circuit that generates a bias voltage and an error voltage, a current output unit that generates a bias current, and a startup current supply unit that supplies the startup current to the bias voltage generation circuit. An apparatus is disclosed. Here, the bias voltage generation circuit includes a balanced current detector and a power supply current controller. According to the bias current generator described in Patent Document 1, the potential difference between the bias voltage and the error voltage generated when the balance of the balanced current detector is lost due to fluctuations in the power supply voltage VDD or the like is fed back to the power supply current controller. Therefore, since the power supply current control unit controls the current supplied to the balanced current detection unit so that the balanced current detection unit is always in a balanced state, the bias voltage is supplied from the current output unit even if the power supply voltage VDD fluctuates. The bias current can be kept at a value that is always constant. Therefore, even when the power supply voltage VDD is lowered, a stable bias current can be supplied.

  However, in the conventional bias current generator (bias circuit) as described in Patent Document 1, in order to set the bias circuit in a desired operation state when the power is turned on, it is generally provided with a start mode in which the start current flows. Is. In other words, each node of each transistor constituting the bias circuit is set in a dynamic state by the start mode, and then is changed to a stable state in which a desired current flows in each transistor by setting the steady mode. For this reason, in the conventional bias current generator (bias circuit), there are transistors through which a current several to several tens of times that in the steady state flows in the startup mode. In the case of a circuit including a current mirror-connected transistor group, a current that is several times to several tens of times the steady state flows through a plurality of transistors. Further, in the conventional bias circuit, if the bias circuit includes a drive circuit that operates as a current source, the current of the entire drive circuit increases. In a low power consumption IC such as a watch, Problems such as expediting battery consumption occur.

  An example of a drive circuit driven by a bias circuit is a crystal oscillation circuit as disclosed in Patent Document 2. In such a conventional crystal oscillation circuit, if the drive current is set to a very small value such as several nA to several hundred nA, a time of several seconds to 10 seconds is required until the voltage required for oscillation is stabilized. It becomes necessary. If the time from the battery insertion to the start of oscillation is slow, a test time is required, resulting in an increase in manufacturing cost and a problem that it is difficult to distinguish from a failure when replacing the battery. A clock IC or the like has a specification that defines an oscillation start time and cannot satisfy this specification.

JP 2001-273046 A Japanese Patent Laid-Open No. 7-7325

  An object of the present invention is to provide a small-sized low power consumption circuit that can suppress a current increase during start-up operation to a minimum and can perform a stable start-up operation.

  Aspects of the present invention are: (a) a first oscillation transistor in which a first main current terminal is connected to a first control power supply; and (b) a second main current terminal is connected to a second main current terminal of the first oscillation transistor. And a second oscillation transistor having a channel conductivity type opposite to the first oscillation transistor, the first main current terminal being connected to a second control power source having a potential different from that of the first control power source, and (c) one electrode being a second electrode. A first capacitor connected to the control terminal of the oscillation transistor; and (d) the other electrode of the first capacitor is connected to one electrode, and the other electrode is connected to a connection node between the first oscillation transistor and the second oscillation transistor. A piezoelectric vibrator, (e) a feedback resistor circuit in which one electrode is connected to the other electrode of the piezoelectric vibrator, and the other electrode is connected to the control terminal of the first oscillation transistor; Terminal to connect the second oscillation transistor An amplitude limiting element having a second terminal connected to the control terminal of the transistor, the first oscillation transistor and the second oscillation transistor form an oscillation amplifier, and a connection node between the first oscillation transistor and the second oscillation transistor It is a low power consumption circuit having an oscillation circuit as an output node of this oscillation amplifier.

  According to the present invention, it is possible to provide a small-sized low power consumption circuit that can suppress a current increase during a start-up operation to a minimum and can perform a stable start-up operation.

It is a figure which shows the structure of the low power consumption circuit (bias circuit) based on the 1st Embodiment of this invention. It is the figure which showed the relationship between the starting resistance and bias current of the low power consumption circuit (bias circuit) which concerns on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram showing an example of a drive circuit of a low power consumption circuit (bias circuit) according to the first embodiment shown in FIG. 1. FIG. 2 is a circuit diagram showing an oscillation circuit serving as a drive circuit for the low power consumption circuit (bias circuit) according to the first embodiment shown in FIG. 1. 5A is a circuit diagram showing an example of a feedback resistor circuit used in the oscillation circuit shown in FIG. 4, and FIG. 5B is a circuit diagram showing another example of the feedback resistor circuit of the oscillation circuit shown in FIG. FIG. 5C is a circuit diagram showing still another example of the feedback resistor circuit of the oscillation circuit of FIG. 5 is an equivalent circuit representation of the oscillation amplifier of the oscillation circuit shown in FIG. 4 and its peripheral circuits. It is a circuit diagram which shows the oscillation circuit as another example of the drive circuit of the low power consumption circuit (bias circuit) based on 1st Embodiment. It is a figure which shows the structure of the low power consumption circuit (bias circuit) based on the 2nd Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (bias circuit) which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (bias circuit) based on the 4th Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (bias circuit) based on the 5th Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (oscillation circuit) which concerns on the 6th Embodiment of this invention. It is a figure which shows the example of the operation | movement waveform from power activation to oscillation stabilization about the oscillation circuit of the comparative example which is not provided with an amplitude limiting element. It is a figure which shows the example of the operation waveform from the power activation to the oscillation stabilization about the low power consumption circuit (oscillation circuit) concerning the 6th Embodiment of this invention. It is an example of the operation | movement waveform in the oscillation stable state of the low power consumption circuit (oscillation circuit) which concerns on the 6th Embodiment of this invention, when the voltage of a 1st control power supply is comparatively high. It is an example of the operation waveform in the oscillation stable state of the low power consumption circuit (oscillation circuit) which concerns on the 6th Embodiment of this invention, when the voltage of a 1st control power supply is comparatively low. It is a figure which shows the structure of the low power consumption circuit (oscillation circuit) which concerns on the 7th Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (bias circuit and oscillation circuit) which concerns on the 8th Embodiment of this invention. It is a figure which shows the example of the operation waveform in the oscillation stable state of the oscillation circuit of the low power consumption circuit which concerns on 8th Embodiment shown in FIG. It is a figure which shows the structure of the low power consumption circuit (oscillation circuit) which concerns on the 9th Embodiment of this invention. It is a figure which shows the structure of the low power consumption circuit (bias circuit and oscillation circuit) based on the 10th Embodiment of this invention.

  Next, first to tenth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the following first to tenth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is a component part. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the technical scope described in the claims.

(First embodiment)
As shown in FIG. 1, the low power consumption circuit according to the first embodiment of the present invention includes a current mirror circuit M1 supplied with a voltage from a first main power supply VDD, and an output terminal of the current mirror circuit M1. A bias dividing circuit R12 comprising a series circuit of a first dividing resistor R1 having one end connected to the first dividing resistor R2, a second dividing resistor R2 having one end connected to the first dividing resistor R1, and a control terminal at one end of the first dividing resistor R1 A first transistor N1 having a second main current terminal connected to the other end of the second dividing resistor R2 and a first main current terminal connected to a second main power supply (GND power supply) having a potential different from that of the first main power supply VDD; The same channel as the first transistor N1, in which the control terminal is connected to the other end of the second dividing resistor R2, the second main current terminal is connected to the input end of the current mirror circuit M1, and the first main current terminal is connected to the second main power supply GND. Including a conductive second transistor N2 A bias circuit. The bias circuit applies a first dividing resistor R1 the starting current I _ST to a connection node between the second dividing resistor R2 at startup. In the present specification, the “first main current terminal” means a terminal (electrode) which is either an emitter terminal or a collector terminal in a bipolar transistor (BJT). In a field effect transistor (FET) and a static induction transistor (SIT), it means a terminal (electrode) which is either a source terminal or a drain terminal. The “second main current terminal” is a terminal (electrode) that is either an emitter terminal or a collector terminal that is not the first main current terminal in the BJT, and the first main current terminal in the FET or SIT. It means a terminal (electrode) that is either a source terminal or a drain terminal that should not be used. That is, if the first main current terminal is an emitter terminal, the second main current terminal is a collector terminal, and if the first main current terminal is a source terminal, the second main current terminal is a drain terminal. The “control terminal” is a terminal for controlling a current flowing between the first main current terminal and the second main current terminal, and specifically, a terminal having a region or structure of a Schottky junction structure or an insulated gate structure. Means. For example, FET and SIT mean a gate terminal or gate structure, and BJT means a base terminal. As is well known, the “channel conductivity type” of a transistor includes a p-channel type and an n-channel type that are opposite channel conductivity types. In the description of the low power consumption circuit according to the first embodiment, the first transistor N1 and the second transistor N2 having the same channel conductivity type as the first transistor N1 are described as nMOS transistors. It is not limited.

As shown in FIG. 1, the current mirror circuit M1 is composed of a pair of a pMOS transistor P1 and a pMOS transistor P2 having a channel conductivity type opposite to that of the nMOS transistor. The first main current terminals (source terminals) of the pMOS transistor P1 and the pMOS transistor P2 are connected to the VDD power source. When the low power consumption circuit (bias circuit) is started, in order to apply the starting current I _ST to the connection node between the first divided resistor R1 and the second divided resistor R2, the first divided resistor R1 and the second divided resistor R2 PMOS transistor P3 having a drain terminal connected to the connection node (connection point) and a source terminal connected to the VDD power supply (first main power supply). Further, a gate terminal is connected to the other end of the second dividing resistor R2, which is the other end of the bias dividing circuit R12, a drain terminal is connected to the input terminal I3IN of the drive circuit CT1, and a source is connected to the GND power supply (second main power supply). An nMOS transistor N3 having a terminal connected is provided.

In the low power consumption circuit according to the first embodiment, when the activation signal ST = VDD level, a non-operating state in which I ₁ = I ₂ = I ₃ = 0, a desired current flows, and the driving circuit CT1 is constant. a bias circuit that can take two states of the operating state for supplying a current output I _3. In order to bring the bias circuit into a desired operation state when the power is turned on, a start mode is required in which the start signal ST = GND level, the nMOS transistor N1 and the nMOS transistor N2 are turned on, and I ₁ and I ₂ are flown. By setting the VDD level to the steady mode, a desired constant current flows through I ₁ , I ₂ , and I ₃ , transitions to a stable state, and a constant current output I ₃ is supplied to the drive circuit CT 1.

Here, the channel widths of the pMOS transistor P1, the pMOS transistor P2, the nMOS transistor (first transistor) N1, the nMOS transistor (second transistor) N2, and the nMOS transistor N3 are set to W _P1 , W _P2 , W _N1 , W _N2 , W _N , respectively. _N3 and the channel lengths are L _P1 , L _P2 , L _N1 , L _N2 , and L _N3 , respectively. Also, the drain terminal current characteristic ln (I _ds ) with respect to the gate terminal voltage in the weak inversion region of the MOS transistor is 1 / K, and the drain terminal current when the gate terminal voltage of the nMOS transistor is V _g1 and V _{g2. Are} I _d1 and I _d2 respectively.
1 / K = {ln (I _d1 ) −ln (I _d2 )} / (V _g1 −V _g2 ) (1)
or,
L _P1 = L _P2 (2)
L _N1 = L _N2 = L _N3 (3)
age,
R1 + R2 = R12 (4)
Then, in the operation state of ST = VDD level, I ₁ , I ₂ , and I ₃ are stabilized by generating the next current independent of VDD.

I ₁ = I _1D = (1 / R12) × K · ln {(I ₁ / I ₂ ) · (W _N2 / W _N1 )} (5)
I ₂ = (W _P2 / W _P1 ) × I _1D (6)
I ₃ = (W _N3 / W _N2 ) × I ₂ (7)
Therefore,
I ₁ · R 12 = K · ln {(I ₁ / I ₂ ) · (W _N2 / W _N1 )} (8)
When the start signal ST = GND level,
I ₁ = I _1D + I _ST = I ₂ × (W _P1 / W _P2 ) + I _ST (9)
So,
I ₁ / I ₂ = W _P1 / W _P2 + I _ST / I ₂ (10)
or,
I ₁・ R12 ＝ I _1D・ R12 ＋ I _ST・ R2 (11)
Therefore, if this is substituted into equation (8),
I ₁ · R 12 = K · ln {(I ₁ / I ₂ ) · (W _N2 / W _N1 )} (12)
I _1D · R 12 + I _ST · R 2 = K · ln {(W _P1 / W _P2 + I _ST / I ₂ ) · (W _N2 / W _N1 )}
(13)
(W _P1 / W _P2 + I _ST / I ₂ ) × W _N2 / W _N1 = exp {(I _1D · R 12 + I _ST · R 2) / K}
(14)
(W _P1 / W _P2 ) × (W _N2 / W _N1 ) × (1 + I _ST / I _1D ) = exp {(I _1D · R 12 + I _ST · R 2) / K} (15)
Substituting W _P1 , W _P2 , W _N1 , W _N2 , K, R 12, R 2, and I _ST into equation (15) gives I _1D, and substituting this into equation (6) gives I ₂ .

As an example, W _P1 / W _P2 = 2, W _N2 / W _N1 = 2, K = 40 mV, R12 = 500 kΩ, I _ST = 0.5 μA, and a plot of the relationship between the second divided resistor R2 and I _1D As shown in FIG. The resistance value R12 of the bias divider circuit is a parameter that determines the output current of the bias circuit, and is therefore a fixed value. As the second divider resistor R2 increases:
R1 = R12-R2 (16)
And R1 shall be reduced. As shown in FIG. 2, I _1D decreases as the resistance value R2 of the second divided resistor increases. Since it can be considered that I _ST = 0A in the steady mode, I _1D = about 110 nA from the equation (15). In the start-up mode, when a current _equal to or higher than the steady mode is supplied to I _1D , V _N2 rises, the bias circuit becomes a dynamic state, and a stable operation state is reliably transitioned after the start-up mode is released. If the resistance value R2 of the second divided resistor is increased unnecessarily, V _N2 cannot be sufficiently increased, and there is a concern that the non-operating state of I ₁ = I ₂ = I ₃ = 0 is restored after the start-up mode is canceled. In order to set I _1D to about 110 nA or more in the steady mode, it is necessary to set the resistance value to be about R 2 = 130 kΩ or less in consideration of resistance variation. In the low power consumption circuit according to the first embodiment of the present invention, the resistance value R12 of the bias dividing circuit is divided into the first dividing resistor R1 and the second dividing resistor R2, and the starting current I is connected to the connection node (connection point). By applying _ST , it is possible to select an optimum resistance value R2 of the second divided resistor that is not influenced by the order of the resistance value R12 of the bias dividing circuit that determines the bias current.

As a reference example, consider the case where the resistance value R2 of the second divided resistor is 0Ω in the above equation (15). Substituting R2 = 0Ω into equation (15) results in I _1D = about 210 nA in the reference example. On the other hand, when the resistance value R2 = 130 kΩ of the second divided resistor is selected using the low power consumption circuit according to the first embodiment of the present invention, it becomes about 115 nA. This can be improved and can be suppressed to a value closer to the steady mode.

-Example of drive circuit-
FIG. 3 shows an example of the drive circuit CT1 driven by the bias circuit shown in FIG. It constitutes a voltage follower circuit for outputting impedance conversion of V _IN Type V _OUT constant current output I ₃ of the bias circuit. In the bias circuit of the reference example of R2 = 0Ω, when I ₃ increases in the start mode, I ₄ and I ₅ connected in the current mirror also increase at the same ratio, so that the entire current consumption of the drive circuit increases. Become. However, in the case of the bias circuit of the low power consumption circuit according to the first embodiment of the present invention, it is possible to minimize the increase in I ₃ as described above, and in particular, it features low power consumption such as battery driving. In such applications, it is possible to reduce battery consumption and increase the added value of the product.

-Other examples of drive circuits-
4 is another example of the drive circuit CT1 driven by the bias circuit shown in FIG. 1, and includes a first oscillation transistor P31 having a first main current terminal (source terminal) connected to the first control power supply VDD, The second main current terminal (drain terminal) is connected to the second main current terminal (drain terminal) of the first oscillation transistor P31, and the first main current terminal (source terminal) is connected to the second control power supply GND. The second oscillation transistor N31 having the same channel conductivity type as the one transistor N1, the first capacitor C2 having one electrode connected to the control terminal (gate terminal) of the second oscillation transistor N31, and the other electrode of the first capacitor C2 Piezoelectric vibrator Q1 connected to one electrode, the other electrode connected to the connection node of first oscillation transistor P31 and second oscillation transistor N31, and one electrode connected to the other electrode of piezoelectric vibrator Q1 The feedback resistor circuit Z3 having the other electrode connected to the control terminal (gate terminal) of the first oscillation transistor P31, the second main current terminal (drain terminal) and the control terminal (gate terminal) are connected, and this control terminal The first transistor N1 having the (gate terminal) connected to the control terminal (gate terminal) of the second oscillation transistor N31 and the drive transistor N33 of the same channel conductivity type are driven directly or indirectly with the output current of the bias circuit. This is a Colpitts oscillation circuit applied to the second main current terminal (drain terminal) of the transistor N33. As shown in FIG. 4, the drive circuit CT1 has a second capacitor having one electrode connected to the control terminal (gate terminal) of the first oscillation transistor P31 and the other electrode connected to the other electrode of the first capacitor C2. C1 is further provided. Specifically, as the piezoelectric vibrator Q1, an example using a quartz vibrator is shown here, but lithium niobate (LiNbO ₃ ), lithium tantalate (LiTaO ₃ ), lithium tetraborate (Li ₂ B) Other piezoelectric crystals such as ₄ O ₇ ), potassium niobate (KNbO ₃ ) and langasite (La ₃ Ga ₅ SiO ₁₄ ), and piezoelectric ceramics such as lead titanate ceramics may be used. In addition, a case where a p-channel MOS transistor (pMOS transistor) is used as the second oscillation transistor N31 as the first oscillation transistor P31, an n-channel MOS transistor (nMOS transistor) is used as the second oscillation transistor N31, and an nMOS transistor is used as the drive transistor N33. It is not limited to these.

That is, the drive circuit CT1 shown in FIG. 4 has a pMOS transistor (first oscillation transistor) P31 and V _N4 having gate terminals V _P4 and V _N4 between VDD (first control power supply) and GND (second control power supply). the nMOS transistor (second oscillation transistor) N31 to be connected in series, a current I ₆ with folded _{I 3} in a current mirror circuit M2, the gate terminal and the drain terminal to the nMOS transistor (drive transistor) N33 connected to V _N4 Apply. One electrode of the crystal resonator (piezoelectric resonator) Q1 and V _P4 and V _N4 are connected by the second capacitor C1 and the first capacitor C2, respectively, to be _XIN, and the other electrode of the crystal resonator (piezoelectric resonator) Q1 Is connected to the drain terminal connection node (connection point) of the pMOS transistor (first oscillation transistor) P31 and the nMOS transistor (second oscillation transistor) N31, and is X _OUT . Further, a connection between V _P4 and X _OUT in the feedback resistor circuit Z3, X _IN, X _OUT constitute a crystal oscillation circuit that respectively connect the oscillator capacitors C3, C4 between GND (second control power).

The feedback resistance circuit Z3 of the drive circuit CT1 shown in FIG. 4 includes a resistance element R22 as shown in FIG. 5A, a MOS transmission gate comprising a pMOS transistor P71 and an nMOS transistor N71 as shown in FIG. 5B. The circuit includes a differential amplifier or the like including pMOS transistors P72, P73, P74 and nMOS transistors N72, N73 as shown in FIG. In the drive circuit (quartz oscillator) CT1 shown in FIG. 4, when the operating current _{I 3} increases, I ₆ also increases.

FIG. 6 shows a second capacitor C1, a first capacitor C2, a pMOS transistor (first oscillation transistor) P31, an nMOS transistor (second oscillation transistor) N31, and an nMOS transistor (drive transistor) N33 in the drive circuit CT1 shown in FIG. The oscillation amplifier portion composed of the feedback resistor circuit Z3 is shown as an electrical schematic diagram. In FIG. 6, V _P4 and V _N4 are biased by a voltage source (Rp, VGP) and a voltage source (Rn, VGN) each including an impedance component. When I ₆ increases, the output impedances Rp and Rn of the voltage source decrease, and the cut-off frequency of the high-pass filter formed by the second capacitor C1, the output impedance Rp, the first capacitor C2 and the output impedance Rn increases. The cutoff frequency can not fully convey the amplitude of the X _IN is not set smaller than the desired oscillation frequency in V _P4, V _N4. Therefore, when the cut-off frequency increases due to an increase in current during the start-up mode, the apparent gain of the oscillation amplifier A1 is lowered, resulting in a problem that oscillation cannot be performed. In many cases, the activation signal ST uses a system that counts the clock output from the oscillation circuit and releases it after a desired time has elapsed. In such a system, a fatal problem occurs that the oscillation does not start and the system does not operate in the startup mode. To avoid this problem, the second capacitor C1 and the first capacitor C2 need to be set large in order to lower the cut-off frequency. However, the current increase in the startup mode is several times to several tens of times that in the steady state. Therefore, it is necessary to set the capacitor capacity to several tens of times. This increases the chip area and increases the manufacturing cost. Further, when trying to make _IST smaller, it is necessary to increase the ON resistance by increasing the channel length of the pMOS transistor P3 shown in FIG. 1 to increase the chip area.

  According to the low power consumption circuit according to the first embodiment of the present invention, it is possible to provide an optimum circuit configuration that avoids the above-described problems without increasing the chip area.

-Further examples of drive circuits-
FIG. 7 shows still another example of the drive circuit CT1 driven by the bias circuit shown in FIG. In Figure 7, it is obtained by the X _IN and V _P4 abolished second capacitor C1 of the driving circuit CT1 shown in FIG. 4 and short-circuit X _IN. Even in this case, an effect equivalent to the effect described in FIG. 4 can be obtained.

(Second Embodiment)
As shown in FIG. 8, the low power consumption circuit according to the second embodiment of the present invention includes an nMOS transistor N3 of the low power consumption circuit according to the first embodiment shown in FIG. The bias circuit is configured to output the current supply I ₃ ′ from the VDD (first main power supply) side to the drive circuit CT1 by configuring the pMOS transistor P2 and the current mirror circuit M4.

  According to the low power consumption circuit (bias circuit) according to the second embodiment, it is necessary to increase the output constant current as in the low power consumption circuit according to the first embodiment described in FIG. It is possible to provide a bias circuit that can be minimized and can perform a stable start-up operation without increasing the chip size. Further, according to the low power consumption circuit according to the second embodiment, it is possible to reduce the current consumption of the entire semiconductor integrated circuit at the time of start-up, and it is possible to reduce the consumption of the battery serving as the power source. In addition, the driving circuit such as an oscillation circuit with improved start-up reliability can be mounted with a smaller chip size, and a constant voltage circuit with less voltage change at start-up can be provided. The same effect as that of the low power consumption circuit according to the embodiment can be obtained.

(Third embodiment)
As shown in FIG. 9, the low power consumption circuit according to the third embodiment of the present invention includes the pMOS transistor P1, the pMOS transistor P2, the low power consumption circuit according to the first embodiment shown in FIG. This is a bias circuit in which the pMOS transistor P3 is changed to a pnp transistor B1, a pnp transistor B2, and a pnp transistor B3.

  According to the low power consumption circuit (bias circuit) according to the third embodiment, it is necessary to increase the output constant current as in the low power consumption circuit according to the first embodiment described in FIG. It is possible to provide a bias circuit that can be minimized and can perform a stable start-up operation without increasing the chip size. Further, according to the low power consumption circuit according to the third embodiment, it is possible to reduce the current consumption of the entire semiconductor integrated circuit at the time of start-up, and it is possible to reduce the consumption of the battery serving as the power source. In addition, the driving circuit such as an oscillation circuit with improved start-up reliability can be mounted with a smaller chip size, and a constant voltage circuit with less voltage change at start-up can be provided. The same effect as that of the low power consumption circuit according to the embodiment can be obtained.

(Fourth embodiment)
As shown in FIG. 10, the low power consumption circuit according to the fourth embodiment of the present invention is a bias circuit having a polarity opposite to that of the low power consumption circuit according to the first embodiment shown in FIG. The VDD power supply is the second main power supply, and the GND power supply is the first main power supply. That is, the low power consumption circuit (bias circuit) according to the fourth embodiment of the present invention includes a current mirror circuit M3 to which a voltage from the first main power supply GND is supplied, as shown in FIG. A bias dividing circuit R12 comprising a series circuit of a first dividing resistor R1 having one end connected to the output end of the mirror circuit M3 and a second dividing resistor R2 having one end connected to the first dividing resistor R1, and a first dividing resistor R1 And a second main current terminal connected to the other end of the second dividing resistor R2, and a first main current terminal connected to a second main power supply (VDD power supply) having a potential different from that of the first main power supply GND. A control terminal is connected to the other end of the first transistor P1, the second dividing resistor R2, a second main current terminal is connected to the input end of the current mirror circuit M3, and a first main current terminal is connected to the second main power supply GND. Second transistor of the same channel conductivity type as one transistor P1 A bias circuit including a transistor P2. The bias circuit applies a first dividing resistor R1 the starting current I _ST to a connection node between the second dividing resistor R2 at startup. In the description of the low power consumption circuit according to the fourth embodiment, the first transistor P1 and the second transistor P2 having the same channel conductivity type as the first transistor P1 are described as pMOS transistors. It is not limited.

As shown in FIG. 10, the current mirror circuit M3 is composed of a pair of an nMOS transistor N1 and an nMOS transistor N2 having a channel conductivity type opposite to that of the pMOS transistor. The first main current terminals (source terminals) of the nMOS transistor N1 and the nMOS transistor N2 are connected to the first main power supply (GND power supply). Furthermore, this start-up low power circuit (bias circuit), in order to apply the starting current I _ST to the first dividing resistor R1 to a connection node between the second dividing resistor R2, a first dividing resistor R1 and the second dividing An nMOS transistor N3 having a drain terminal connected to a connection node (connection point) of the resistor R2 and a source terminal connected to a first main power supply (GND power supply) is provided. Further, the gate terminal is connected to the other end of the second dividing resistor R2 which is the other end of the bias dividing circuit R12, the drain terminal is connected to the input terminal I3IN of the drive circuit CT1, and the source is supplied to the second main power supply (VDD power supply). A pMOS transistor P3 having a terminal connected is provided.

That is, the low power consumption circuit according to the fourth embodiment is configured such that the pMOS transistor P1, the pMOS transistor P2, and the pMOS transistor P3 of the low power consumption circuit according to the first embodiment shown in FIG. The nMOS transistor N1, the nMOS transistor N2, and the nMOS transistor N3 of the low power consumption circuit according to the first embodiment shown in FIG. 1 are replaced with the pMOS transistor P1, replacing the transistor N1, the nMOS transistor N2, and the nMOS transistor N3, respectively. , PMOS transistor P2, and pMOS transistor P3, and V _P1 of the low power consumption circuit according to the first embodiment shown in FIG. 1 is set to V _N1 , and V _N1 and V _N2 are set to V _P1 and V _P2 , respectively. Corresponding to the replaced bias circuit, start-up mode with start signal ST = VDD level And then, and the steady mode activation signal ST = GND level.

  According to the low power consumption circuit (bias circuit) according to the fourth embodiment, it is necessary to increase the output constant current as in the low power consumption circuit according to the first embodiment described in FIG. It is possible to provide a bias circuit that can be minimized and can perform a stable start-up operation without increasing the chip size. Further, according to the low power consumption circuit according to the fourth embodiment, it is possible to reduce the current consumption of the entire semiconductor integrated circuit at the time of start-up, and it is possible to reduce the consumption of the battery serving as the power source. In addition, the driving circuit such as an oscillation circuit with improved start-up reliability can be mounted with a smaller chip size, and a constant voltage circuit with less voltage change at start-up can be provided. The same effect as that of the low power consumption circuit according to the embodiment can be obtained.

(Fifth embodiment)
As shown in FIG. 11, the low power consumption circuit according to the fifth embodiment of the present invention comprises a drive circuit CT1 of FIG. 8 as a series connection circuit of a resistance element R4 and a pnp transistor B4, and a bias circuit. Is a bias circuit configured to output a constant voltage V _OUT by applying a constant current output I _{3 ′} from the resistor element R4.

According to the low power consumption circuit (bias circuit) according to the fifth embodiment, an effect of suppressing the increase in _{VOUT to} the minimum necessary even in the startup mode can be obtained. Further, according to the low power consumption circuit according to the fifth embodiment, as in the low power consumption circuit according to the first embodiment described in FIG. Therefore, it is possible to provide a bias circuit capable of stable start-up operation without increasing the chip size. Further, according to the low power consumption circuit according to the fifth embodiment, it is possible to reduce the current consumption of the entire semiconductor integrated circuit at the time of startup, thereby reducing the consumption of the battery serving as the power source. Further, the same effect as the low power consumption circuit according to the first embodiment can be obtained, such as providing a constant voltage circuit with little voltage change at the time of startup.

(Sixth embodiment)
As shown in FIG. 12, the low power consumption circuit according to the sixth embodiment of the present invention includes a first oscillation transistor P31 having a first main current terminal (source terminal) connected to a first control power supply VDD, The second main current terminal (drain terminal) is connected to the second main current terminal (drain terminal) of the first oscillation transistor P31, and the first main current terminal (source terminal) has a potential different from that of the first control power supply VDD. 2 a second oscillation transistor N31 having a channel conductivity type opposite to that of the first oscillation transistor P31 connected to the control power supply GND, and a first capacitor C2 having one electrode connected to a control terminal (gate terminal) of the second oscillation transistor N31. The other electrode of the first capacitor C2 is connected to one electrode, the other electrode is connected to the connection node of the first oscillation transistor P31 and the second oscillation transistor N31, and one electrode is piezoelectric. Connected to the other electrode of Doko Q1, and the other electrode and the feedback resistor circuit Z3 connected to the control terminal (gate terminal) of the first oscillation transistor P31, the control terminal of the first oscillation transistor P31 (gate terminal) V _P1 The first terminal is connected to the first node, the second terminal is connected to the connection node, the second terminal is connected to the control terminal (gate terminal) V _N1 of the second oscillation transistor N31, and the connection node is connected to the connection node. The first oscillation transistor P31 and the second oscillation transistor N31 constitute an oscillation amplifier A1, and a connection node is connected to an output node X _{OUT of the} oscillation amplifier A1. Colpitts type oscillation circuit. As shown in FIG. 12, this Colpitts oscillation circuit has a first electrode connected to the control terminal (gate terminal) of the first oscillation transistor P31 and the other electrode connected to the other electrode of the first capacitor C2. It further includes two capacitors C1.

  Specifically, as the piezoelectric vibrator Q1, here, an example using a crystal vibrator is shown, but other piezoelectric crystals such as lithium niobate and langasite, and piezoelectric ceramics such as lead titanate ceramics are used. Also good. In addition, a case where a p-channel MOS transistor (pMOS transistor) is used as the second oscillation transistor N31 as the first oscillation transistor P31, an n-channel MOS transistor (nMOS transistor) is used as the second oscillation transistor N31, and an nMOS transistor is used as the drive transistor N33. It is not limited to these. The first amplitude limiting element P32 has a control terminal (gate terminal) and a second main current terminal (drain terminal) connected to the control terminal (gate terminal) of the first oscillation transistor P31, and is connected to the output node of the oscillation amplifier A1. A pMOS transistor connected to the first main current terminal (source terminal) is used, and the control terminal (gate terminal) and the second main current terminal are connected to the control terminal (gate terminal) of the second oscillation transistor N31 as the second amplitude limiting element N32. Although the case where an nMOS transistor in which (drain terminal) is connected and the first main current terminal (source terminal) is connected to the output node of the oscillation amplifier A1 is illustrated, it is not limited thereto. In FIG. 12, the pMOS transistor serving as the first amplitude limiting element P32 is a so-called so-called “first oscillation transistor P31” having a control terminal (gate terminal) connected to a control terminal (gate terminal) and a second main current terminal (drain terminal). In the nMOS transistor as the second amplitude limiting element N32, which is “diode connection”, the control terminal (gate terminal) and the second main current terminal (drain terminal) are connected to the control terminal (gate terminal) of the second oscillation transistor N31. Each of the diode-connected configurations functions as a diode. Therefore, a connection node between the control terminal (gate terminal) of the first amplitude limiting element (pMOS transistor) P32 and the second main current terminal (drain terminal) is the “first” of the first amplitude limiting element (pMOS transistor) P32. The first main current terminal (source terminal) of the first amplitude limiting element (pMOS transistor) P32 is the “second terminal” of the first amplitude limiting element (pMOS transistor) P32. Similarly, the connection node between the control terminal (gate terminal) of the second amplitude limiting element (nMOS transistor) N32 and the second main current terminal (drain terminal) is the “second” of the second amplitude limiting element (nMOS transistor) N32. The first main current terminal (source terminal) of the second amplitude limiting element (nMOS transistor) N32 is the “first terminal” of the second amplitude limiting element (nMOS transistor) N32.

As shown in FIG. 12, the low power consumption circuit (oscillation circuit) according to the sixth embodiment further connects the second main current terminal (drain terminal) and the control terminal (gate terminal), and the second The main current terminal is connected to the control terminal (gate terminal) of the second oscillation transistor N31, and the DC bias voltage is applied to the control terminal (gate terminal) of the second oscillation transistor N31. The same channel conductivity type as the second oscillation transistor N31 Drive transistor N33. Although the case where an nMOS transistor is used as the drive transistor N33 is illustrated, the present invention is not limited to this. Further, the oscillation circuit shown in FIG. 12 includes an oscillation capacitor C3 and an oscillation capacitor C4 respectively connected between both ends X _IN and X _OUT of a crystal resonator (piezoelectric resonator) Q1 and a GND power source (second control power source). The drive transistor (nMOS transistor) N33 is provided with a bias circuit (IC1, M2) for applying a constant current. The bias circuit (IC1, M2) includes a constant current source IC1 and a current mirror circuit M2.

  The feedback resistance circuit Z3 includes a resistance element R22 as shown in FIG. 5 (a), a MOS transmission gate circuit comprising a pMOS transistor P71 and an nMOS transistor N71 as shown in FIG. 5 (b), and FIG. 5 (c). What is necessary is just to comprise by the differential amplifier etc. which consist of pMOS transistor P72, P73, P74 and nMOS transistor N72, N73 which were shown.

In the low power consumption circuit according to the sixth embodiment of the present invention, the nMOS transistor (second oscillation transistor) N31 has a voltage V _N1 applied to its gate terminal as a DC bias voltage and a crystal oscillator ( The oscillation amplitude from the piezoelectric vibrator Q1 is applied through the first capacitor C2. pMOS transistor to the gate terminal V _P1 (first oscillation transistor) P31, the voltage of the output X _OUT of the oscillator amplifier via a feedback resistor circuit Z3 is fed back VDD- | V _thP | voltage near occurs DC bias voltage And the oscillation amplitude from the crystal resonator (piezoelectric resonator) Q1 is applied via the second capacitor C1 in the same manner as the nMOS transistor N1. Accordingly oscillator amplifier A1 is to operate as an inverting amplifier X _OUT VDD- | V _thP | outputting the amplified waveform around the voltage near the X _IN inverted phase to maintain the oscillation.

Here, V _P1 is affected by parasitic capacitance when starting oscillation such as when power is turned on.
V _P1 <X _OUT − | V _thP | (17)
If a, pMOS transistor (first amplitude limiting element) P32 acts as turning off the V _P1 increases the pMOS transistor (first oscillation transistor) P31 with lowering the ON and X _OUT. Similarly,
X _OUT + V _thN <V _N1 (18)
If a, nMOS transistors (the second amplitude limiting element) N32 acts as turning off the nMOS transistor (second oscillation transistor) N31 lowering the V _N1 with increasing the on-and X _OUT. Therefore, the time when the oscillation stabilization voltage V _P1 becomes a voltage near VDD− | V _thP |, V _N1 becomes a voltage near GND + V _thN , and X _OUT becomes a voltage near VDD− | V _thP | The oscillation start time can be shortened.

FIG. 13 shows, as a comparative example, VDD, X _OUT from power-on to oscillation stabilization of an oscillation circuit that does not include the pMOS transistor (first amplitude limiting element) P32 and the nMOS transistor (second amplitude limiting element) N32 in FIG. , V _P1 , V _N1 of the operation waveforms of the nodes are shown in FIG. 14 as VDD, X _OUT , V _P1 , V _N1 from the power-on to the oscillation stabilization of the oscillation circuit according to the sixth embodiment of the present invention. An example of an operation waveform of each node is schematically shown. In the comparative example shown in FIG. 13, the stability of V _P1 is slow and X _OUT rises to the VDD power supply (first control power supply), and the oscillation stabilization time is long. On the other hand, in the oscillation circuit according to the sixth embodiment of the present invention shown in FIG. 14, in the period (1) shown near the left end of the time axis, between V _P1 and X _OUT ,
X _OUT − | V _thP | <V _P1 (19)
Thus, it can be seen that the rise of V _{P1 and} the fall of X _OUT are accelerated and the stabilization time is short.

In the low power consumption circuit (oscillation circuit) according to the sixth embodiment of the present invention, the X _OUT amplitude in the oscillation stable state is limited to the range of V _N1 −V _thN to V _P1 + | V _thP |. . FIG. 15 shows that | V _thP | and V _thN are equal and VDD (voltage of the first control power supply) is relatively high, for example, pMOS transistor (first oscillation transistor) P31, nMOS transistor (second oscillation transistor) N31 V The operation waveforms of the nodes V _P1 , V _N1 , and X _OUT in the oscillation stable state when the sum of the absolute values of _th is higher, the pMOS transistor (first amplitude limiting element) P32, and the nMOS transistor (second amplitude limiting element) Each waveform of I _ds , | I _dsP2 | and I _dsN2 of N32 is shown. In the figure, when X _OUT −V _P1 at the timing when V _P1 is low and X _OUT is high is ΔV1, the pMOS transistor (first amplitude limiting element) P32 is intermittently turned on at the timing of | V _thP | <ΔV1. _dsP2 | is generated. As a result, V _P1 cannot fall any further and the on state of the pMOS transistor (first oscillation transistor) P31 is limited. Therefore, the rise of X _OUT is also restricted and the upper limit of amplitude is restricted.

16, as in FIG. 15, | V _thP | and V _thN are equal and VDD (voltage of the first control power supply) is relatively low. For example, pMOS transistor (first oscillation transistor) _{P 31} , nMOS transistor (second oscillation) Transistor) Each waveform is shown when it is lower than the sum of absolute values of _Vth of N31. In the figure, the high X _OUT is V _N1 is a [Delta] V2 to V _N1 -X _OUT at low timing, nMOS transistor N32 with the timing of the V _thN <[Delta] V2 is generated intermittently ON and I _dsn2. As a result, V _N1 cannot rise any further, and the on state of the nMOS transistor (second oscillation transistor) N31 is limited. Therefore, the amplitude limit is also lowered in the X _OUT limit is restricted.

In the above description, the case where VDD (the voltage of the first control power supply) is relatively high and the case where it is relatively low has been described. However, VDD (first control power supply), pMOS transistor (first oscillation transistor) P31, nMOS transistor (second When the sum of the absolute values of V _th of the oscillation transistor N31 is equal, the operation shown in FIG. 15 and the operation shown in FIG. 16 may occur simultaneously. When | V _thP | and V _thN are unbalanced, VDD (first control power supply), pMOS transistor (first oscillation transistor) P31, and nMOS transistor (second oscillation transistor) N31 V _th Regardless of the relationship of the sum of the absolute values, the operation shown in FIG. 15, the operation shown in FIG. 16, or the operation shown in FIG. 15 and the operation shown in FIG.

Under these conditions, limits the ON state of the pMOS transistor (first oscillation transistor) P31 in the on state and the nMOS transistor (second oscillation transistor) N31, and the amplitude of the X _OUT is limited, the oscillation maintaining properties secure Is done. As a result, the operating current consumption of the oscillation circuit can be reduced by several tens of percent. In an IC for a watch or the like, the ratio of the operating current consumption of the oscillation circuit to the total operating current consumption of the IC is very high. Therefore, the reduction of the operating current consumption of the oscillation circuit leads to the reduction of the operating current consumption of the entire IC. In addition, the pMOS transistor (first amplitude limiting element) P32 and the nMOS transistor (second amplitude limiting element) N32 can be formed in the same size as a general transistor used in the oscillation circuit, which affects the chip size. Does not affect. Further, the pMOS transistor (first amplitude limiting element) P32 and the nMOS transistor (second amplitude limiting element) N32 are respectively connected to the pMOS transistor (first oscillation transistor) P31 and the nMOS transistor (second oscillation transistor) N31 or the channel length or channel. By designing the widths to be uniform, it is possible to make the voltages to be turned on uniform, and an easy design can be performed.

  As described above, according to the low power consumption circuit (oscillation circuit) according to the sixth embodiment of the present invention, the oscillation start time after battery insertion can be shortened, the test time can be shortened, and the manufacturing cost can be reduced. It is possible to avoid troubles such as mistakes when replacing batteries. Further, the operating current consumption of the oscillation circuit can be reduced without increasing the chip size, the operating current consumption of the entire IC can be reduced, the battery life can be greatly extended, and the added value of the product can be increased.

(Seventh embodiment)
As shown in FIG. 17, the low power consumption circuit according to the seventh embodiment of the present invention is a diode instead of the pMOS transistor P32 of the low power consumption circuit (oscillation circuit) shown in FIG. This is an oscillation circuit using D1 and using a diode D2 as the second amplitude limiting element instead of the nMOS transistor N32 of FIG. That is, in the low power consumption circuit (oscillation circuit) shown in FIG. 12, the pMOS transistor as the first amplitude limiting element P32 is a diode in which the control terminal (gate terminal) and the second main current terminal (drain terminal) are short-circuited. The nMOS transistor as the second amplitude limiting element N32 has a diode-connected configuration in which the control terminal (gate terminal) and the second main current terminal (drain terminal) are short-circuited, both functioning as a diode. Therefore, even if the diodes D1 and D2 equivalent to these diode connections are replaced, the same operation as the low power consumption circuit (oscillation circuit) shown in FIG. 12 is possible.

That is, in the low power consumption circuit (oscillation circuit) according to the seventh embodiment, the first terminal (cathode terminal) is connected to the control terminal (gate terminal) V _P1 of the first oscillation transistor P31, and the connection node (output) The first amplitude limiting element (diode) D1 having a second terminal (anode terminal) connected to the node _XOUT and the second terminal (anode terminal) connected to the control terminal (gate terminal) V _N1 of the second oscillation transistor N31 and, except for and a connection node (output node) X _OUT second amplitude limiting element which connects the first terminal (cathode terminal) to (diode) D2, the sixth embodiment shown in FIG. 12 Since the configuration is the same as that of the low power consumption circuit, redundant description is omitted.

However, in the low power consumption circuit (oscillation circuit) according to the seventh embodiment, the threshold value | V _thP | of the pMOS transistor (first amplitude limiting element) P32 in the description of the operation in FIG. (First amplitude limiting element) The forward voltage V _f of D1 is replaced, and the threshold voltage V _thN of the nMOS transistor (second amplitude limiting element) N32 in FIG. 12 is equal to the forward voltage V of the diode (second amplitude limiting element) D2. Replaced by _f .

  According to the low power consumption circuit (oscillation circuit) according to the seventh embodiment, the oscillation start time at the time of oscillation start-up can be shortened similarly to the low power consumption circuit (oscillation circuit) according to the sixth embodiment. In addition, the test time can be shortened and the manufacturing cost can be reduced, and troubles such as mistakes can be avoided during battery replacement. Furthermore, the operating current consumption of the oscillation circuit can be reduced without increasing the chip size, the operating current consumption of the entire IC can be reduced, the battery life can be extended, and the added value of the product can be increased.

(Eighth embodiment)
In the low power consumption circuit according to the eighth embodiment of the present invention, the output VREG of the regulator circuit (bias circuit) REG1 shown on the left side of FIG. 18 is connected to the first control power supply of the oscillation circuit shown on the right side of FIG. The output VREG is a low power consumption circuit configured to be supplied to the oscillation circuit as the voltage of the “first control power supply”. The oscillation circuit shown on the right side of FIG. 18 has substantially the same configuration as that of the oscillation circuit according to the sixth embodiment shown in FIG.

  The regulator circuit (bias circuit) REG1 shown on the left side of FIG. 18 includes a current mirror circuit M1 composed of a pMOS transistor pair and having a source terminal connected to the VDD power supply, and a resistance element R2 having one end connected to the output terminal of the current mirror circuit M1. The nMOS transistor N1 has a gate terminal connected to one end of the resistor element R2, a drain terminal connected to the GND power source and a source terminal connected to the GND power source, a gate terminal connected to the other end of the resistor element R2, and a drain terminal connected to the input terminal of the current mirror circuit M1. An nMOS transistor N2 having a source terminal connected to the GND power supply, an nMOS transistor N57 having a gate terminal connected to the other end of the resistor element R2, a source terminal connected to the GND power supply, and a gate terminal and a drain terminal connected to the drain terminal of the nMOS transistor N57. PMOS transistor P58 having a source terminal connected to output VREG and , A pMOS transistor P57 having a source terminal connected to the VDD power source and a drain terminal connected to the output VREG, a connection node (connection point) between the gate terminal and the drain terminal of the pMOS transistor P58 as a positive input, and one end of a resistor R2 as a negative input, A differential circuit DA1 having an output connected to the gate terminal of the pMOS transistor P57 is provided.

  The low power consumption circuit according to the eighth embodiment of the present invention includes an nMOS transistor N4 having a gate terminal connected to the other end of the resistance element R2 of the regulator circuit (bias circuit) REG1 and a source terminal connected to the GND power supply. In place of the constant current source IC1 of the low power consumption circuit (oscillation circuit) shown in FIG. 12, a constant current is supplied to the drive transistor (nMOS transistor) N33 of the oscillation circuit shown on the right side of FIG.

In low-power circuit according to the eighth embodiment, the output VREG of the regulator circuit (bias circuit) REG1, the voltage of the sum of the potentials of V _GS of V _GS and the pMOS transistor P58 of the nMOS transistor N1 is output , | V _thP | + V _thN is obtained as an output voltage. Usually, in an oscillation circuit for a watch or the like, the operating current is set to be smaller, so that the actual VREG voltage (the voltage of the first control power supply) is lower than | V _thP | + V _thN . In this state, as shown in FIG. 19, the operation state shown in FIG. 15 and the operation state shown in FIG. 16 occur simultaneously, and X _OUT ensures a minimum amplitude that does not impair the oscillation sustaining characteristics, and the operation current consumption The oscillation amplitude can be made optimal without increasing the frequency.

(Ninth embodiment)
As shown in FIG. 20, the low power consumption circuit according to the ninth embodiment of the present invention is an oscillation circuit corresponding to a circuit in which the pMOS transistor (first amplitude limiting element) P32 is omitted from the oscillation circuit shown in FIG. Circuit. The rest is substantially the same as the oscillation circuit shown in FIG. 12, and thus redundant description is omitted. However, the low power consumption circuit (oscillation circuit) shown in FIG. 20 can expect only the effect shown in FIG. However, when VDD (the voltage of the first control power supply) is limited to a relatively low state, as in the oscillation circuit shown in FIG. 12, the oscillation start time at the start of oscillation can be shortened, and the test time can be reduced. The manufacturing cost can be reduced by shortening, and troubles such as mistaken mistakes when replacing the battery can be avoided. Furthermore, the operating current consumption of the oscillation circuit can be reduced without increasing the chip size, the operating current consumption of the entire IC can be reduced, the battery life can be extended, and the added value of the product can be increased.

20 illustrates the case where the pMOS transistor (first amplitude limiting element) P32 is deleted, but the circuit configuration in which only the nMOS transistor (second amplitude limiting element) N32 is deleted from the oscillation circuit shown in FIG. When the voltage of the VDD power supply is relatively high, as in the oscillation circuit shown in FIG. 12, the oscillation start time at the start of oscillation can be shortened, the test time can be shortened, the manufacturing cost can be reduced, and the battery can be replaced. Troubles such as mistakes can be avoided. Furthermore, the operating current consumption of the oscillation circuit can be reduced without increasing the chip size, the operating current consumption of the entire IC can be reduced, the battery life can be extended, and the added value of the product can be increased.

(Tenth embodiment)
The low power consumption circuit according to the tenth embodiment of the present invention includes a regulator circuit (bias circuit) REG1 shown on the left side of FIG. 18 in the low power consumption circuit according to the eighth embodiment, and the left side of FIG. Is switched to the regulator circuit (bias circuit) REG2, and the output VREG of the regulator circuit (bias circuit) REG2 is used as the “second control power supply”, and the first main current terminal (second main transistor N31) constituting the oscillation amplifier A1 ( This is an example of supply to the source terminal.

  In the circuit configuration shown in FIG. 21, as in the low power consumption circuit shown in FIG. 18, the oscillation start time at the start of oscillation of the right oscillation circuit can be shortened, the test time can be shortened and the manufacturing cost can be reduced. Troubles such as mistakes can be avoided during replacement. Furthermore, the operation current consumption of the oscillation circuit can be reduced without increasing the chip size, and the effects such as the reduction of the operation current consumption of the entire IC, the extension of the battery life, and the enhancement of the added value of the product can be expected. .

(Other embodiments)
As described above, the present invention has been described according to the first to tenth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, embodiments, and operational techniques will be apparent to those skilled in the art.

   For example, in the fourth embodiment of the present invention, an example of a circuit having a polarity opposite to that of the low power consumption circuit according to the first embodiment is shown, but the first to tenth embodiments show the example. The circuit configuration is such that the p-type and n-type transistors are reversed and the voltage relationship between the second main power source and the first main power source is reversed, or the voltage relationship between the second control power source and the first control power source is reversed. Even so, it can be understood from the above description that the same effect can be obtained.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

C1 ... second capacitor C2 ... first capacitor D1 ... diode (first amplitude limiting element)
D2: Diode (second amplitude limiting element)
M1, M2, M3, M4 ... Current mirror circuit N1 ... nMOS transistor (first transistor)
N2 ... nMOS transistor (second transistor)
N31 ... nMOS transistor (second oscillation transistor)
N32 ... nMOS transistor (second amplitude limiting element)
N33 ... nMOS transistor (drive transistor)
P31 ... pMOS transistor (first oscillation transistor)
P32 ... pMOS transistor (first amplitude limiting element)
Q1 ... Piezoelectric vibrator (quartz crystal vibrator)
R1: First division resistor R12: Bias division circuit (resistance value of the bias division circuit)
R2 ... Second divided resistor Z3 ... Feedback resistor circuit

Claims (4)

A first oscillation transistor having a first main current terminal connected to a first control power supply;
The first oscillation transistor, wherein a second main current terminal is connected to a second main current terminal of the first oscillation transistor, and the first main current terminal is connected to a second control power supply having a potential different from that of the first control power supply. A second oscillation transistor opposite in channel conductivity type,
A first capacitor having one electrode connected to a control terminal of the second oscillation transistor;
A second capacitor having one electrode connected to the control terminal of the first oscillation transistor and the other electrode connected to the other electrode of the first capacitor;
A piezoelectric vibrator in which the other electrode of the first capacitor is connected to one electrode, and the other electrode is connected to a connection node of the first oscillation transistor and the second oscillation transistor;
A feedback resistor circuit in which one electrode is connected to the other electrode of the piezoelectric vibrator and the other electrode is connected to a control terminal of the first oscillation transistor;
A first amplitude limiting element having a first terminal connected to a control terminal of the first oscillation transistor and a second terminal connected to the connection node ;
A second amplitude limiting element having a first terminal connected to the connection node and a second terminal connected to a control terminal of the second oscillation transistor, wherein the first oscillation transistor and the second oscillation transistor oscillate; An amplifier is configured, and the connection node is an output node of the oscillation amplifier ,
At the time of oscillation start-up, the potential of the control terminal of the second oscillation transistor is the potential of the second control power supply, and after oscillation start-up, the oscillation amplitude from the piezoelectric vibrator is applied to the control terminal of the second oscillation transistor. Applied through the capacity,
Wherein the control terminal of the first oscillation transistor, the output voltage of said oscillator amplifier via the feedback resistor circuit is fed back, the oscillation amplitude from the piezoelectric vibrator is applied through the second capacitor Rukoto A low power consumption circuit. A drive transistor having a first main current terminal connected to the second control power supply, and a control terminal and a second main current terminal both connected to the control terminal of the second oscillation transistor;
2. The low power consumption circuit according to claim 1, wherein a potential of the second control power source is applied to a control terminal of the second oscillation transistor via the driving transistor at the time of oscillation start. 3. The low power consumption circuit according to claim 1, wherein each of the first and second amplitude limiting elements has its own control terminal and its second main current terminal connected to each other. 2. The first amplitude limiting element and the second amplitude limiting element are arranged such that at least one of a channel length and a channel width is aligned with the first oscillation transistor and the second oscillation transistor, respectively. 4. The low power consumption circuit according to any one of 3 above.

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