JP6320048B2 - Oscillator circuit - Google Patents

Description

  The present invention relates to an oscillation circuit using a constant voltage circuit that outputs a voltage corresponding to the sum of threshold voltages of an NMOS transistor and a PMOS transistor as a constant voltage.

  Conventionally, when trying to operate a CMOS circuit at a low power, it is desirable to operate in a power supply voltage region where no through current flows. For example, | Vtp | + Vtn (= ΣVth), which is a voltage just before the through current starts to flow, is used as the power supply voltage. A circuit that generates the reference voltage of ΣVth is described in Patent Document 1. 4 and 5 are outlines of the reference voltage generating circuit and the constant voltage circuit disclosed in Patent Document 1. FIG. Vtp and Vtn represent threshold voltages (Vth) of the PMOS transistor and NMOS transistor used in the CMOS circuit, respectively.

  The reference voltage generating circuit shown in FIG. 4 includes a constant current source 101 having one end connected to the positive power supply VDD, a PMOS transistor 103 having a source electrode connected to the constant current source 101, and a drain electrode and a gate electrode connected to each other. The NMOS transistor 105 has a drain electrode connected to the drain electrode of the PMOS transistor 103, a gate electrode connected to the drain electrode, and a source electrode grounded (GND). Both transistors are connected in series. An output node 107 for outputting the output voltage Vreg is connected between the constant current source 101 and the PMOS transistor 103.

Here, when a power supply voltage is supplied between GND and VDD, both the PMOS transistor 103 and the NMOS transistor 105 connect the gate electrode and the drain electrode, so that VDS = VGS (VDS is the voltage between the drain electrode and the source electrode, VGS is a voltage between the gate electrode and the source electrode). For example, when the set current value of the constant current source 101 is set so that the PMOS transistor 103 and the NMOS transistor 105 operate near the threshold voltage Vth, the VDS of the PMOS transistor 103 and the NMOS transistor 105 are approximately Vtp and Vtn, respectively. . Therefore, Vreg is approximately | Vtp | + Vtn (= ΣVth), and Vreg is approximately equal to the sum ΣVth of the threshold voltages of the PMOS transistor 103 and the NMOS transistor 5. Further, by arbitrarily setting the current value of the constant current source 101, it is also possible to adjust the VDS and therefore Vreg of the PMOS transistor 103 and the NMOS transistor 105.
The constant voltage circuit shown in FIG. 5 generates a power supply for driving the oscillation circuit. The constant voltage circuit includes a reference voltage generation circuit 100 and an impedance conversion unit 200, and a desired output voltage generated by the reference voltage generation circuit 100. (Vreg) is converted to a low impedance by the impedance conversion unit 200 and supplied to the oscillation circuit 300.
Patent Document 2 discloses a crystal oscillation circuit in which an input voltage can follow fluctuations in an amplification region of an oscillation inverter and can oscillate reliably in a short time. In this oscillation circuit, an inverter for driving the crystal unit is connected in parallel with the crystal unit, a resistor for setting the operating point to the amplification region of the inverter is connected in parallel with the crystal unit, and a constant current source is connected. Connected in series to the inverter as a power supply, provided a capacitor on the input side of the inverter, provided another capacitor on the output side of the inverter, connected one end to the input side of the inverter and the other end between the inverter and the constant current source Another capacitor is provided. The output of the oscillation CMOS inverter is input to an accompanying circuit (logic circuit) such as a waveform shaping inverter or a frequency dividing circuit.

JP-A-8-305453 JP-A-6-177646

  As described in FIG. 5 for explaining the aforementioned Patent Document 1, a voltage of the sum of the absolute value of the threshold voltage of the PMOS transistor and the threshold voltage of the NMOS transistor | Vtp | + Vtn (= ΣVth) is generated, If the CMOS inverter for oscillation and the logic circuit in the subsequent stage are operated using the voltage, it is possible to reduce power consumption. However, in this case, the logic circuit is not affected by the through current and can reduce the power consumption. However, when this voltage is directly supplied to the CMOS inverter for oscillation, the voltage (reference voltage) depends on the temperature characteristic of the threshold voltage Vth. There is a problem that the oscillation amplitude is increased and the power consumption is extremely increased particularly when the temperature is lowered, especially when the temperature is low.

Accordingly, when both the logic circuit and the oscillation CMOS inverter are reduced in power consumption and the constant voltage circuit described in Patent Document 1 is used, a constant current generation circuit is separately provided, and the current of the oscillation CMOS inverter is There was a need to control.
In addition, the constant voltage circuit described in Patent Document 1 has a problem of influence on the reference voltage output due to fluctuations in the power supply voltage, and as it is, a reference voltage (ΣVth) generation circuit for reducing power consumption, that is, However, there is a problem in using it as a constant voltage generating circuit.
The present invention has been made under such circumstances, and is an oscillation circuit that suppresses the influence of fluctuations in power supply voltage and the temperature characteristics of the transistor, and achieves both low power consumption of the oscillation CMOS inverter and the subsequent logic circuit. I will provide a.

In one embodiment of the present invention, an oscillation unit including an inverter circuit in which a current is controlled by a constant current source provided in a current path and a vibrator is connected between input and output, and a reference voltage is input to a non- inverting input terminal, It has a voltage follower configuration in which its output is directly fed back to the inverting input terminal without passing through other elements, and an operational amplifier that outputs a predetermined constant voltage, and the reference voltage is obtained using the voltage output from the operational amplifier as a power source. and a reference voltage generating circuit to be generated, the reference voltage generating circuit includes a reference voltage transistor which is one type of MOS transistors either of the N-type or P-type to the current path, of the reference voltage transistor A voltage corresponding to a threshold voltage is generated as the reference voltage, and the operational amplifier is configured to change the current flowing through the reference voltage transistor by the current mirror effect. A current mirror connection portion to the constant current source that is generated in the current source, and an offset transistor that is a MOS transistor of a type different from the type of the reference voltage transistor of N type or P type is connected to the inverting input side A current mirror transistor which is a MOS transistor of the N-type or P-type that matches the type of the reference voltage transistor, and which corresponds to the threshold voltage of the offset transistor. Output the voltage corresponding to the sum of the threshold voltage of the reference voltage transistor and the threshold voltage of the offset transistor as the constant voltage, and the constant voltage as the power supply of the oscillation unit. The oscillation circuit is characterized by being used.

In addition, according to one embodiment of the present invention, in the above-described oscillation circuit, the reference voltage generation circuit further includes a resistance element having one end connected to the inverting input terminal and the other end connected to the non-inverting input terminal. The reference voltage transistor has a diode connection in which a drain terminal is connected to the resistance element, a source terminal is connected to a ground potential, and a gate terminal and a drain terminal are connected to each other, A voltage generated between a drain terminal and a source terminal of the reference voltage transistor due to a current flowing through the reference voltage transistor is generated as the reference voltage.

With such a configuration, the oscillating unit supplies the current supplied as it is, and the logic circuit in the subsequent stage can reduce the current consumption without being influenced by the through current. Furthermore, a semiconductor constant voltage source circuit composed of a reference voltage generation circuit and an operational amplifier can operate from a low voltage while using a self-bias configuration in which the output generated by the reference voltage generation circuit is used as its own power supply voltage. Highly stable constant voltage can be output.

1 is a block diagram of an oscillation circuit according to Embodiment 1. FIG. FIG. 3 is a circuit diagram illustrating details of the oscillation circuit according to the first embodiment. The circuit diagram which shows the detail of the starting circuit which concerns on FIG. The circuit diagram of the conventional reference voltage generation circuit. The circuit diagram of the conventional constant voltage circuit.

    Hereinafter, embodiments of the invention will be described with reference to examples.

The oscillation circuit according to the first embodiment will be described with reference to FIGS.
In this embodiment, a crystal oscillator is configured by externally attaching a crystal resonator to an IC chip in which an oscillation circuit is built.
As shown in FIG. 1, the oscillation circuit includes a reference voltage generation circuit 10, an operational amplifier 20 in the subsequent stage, an oscillation unit 30 in the subsequent stage of the operational amplifier, a constant current source 40 that controls the current in the oscillation unit 30, and the oscillation circuit. And a CMOS logic circuit 40 at the rear stage. For this logic circuit, an inverter, a frequency divider, or the like is used. The signal of the oscillation circuit is output to the outside through the logic circuit 50.
The reference voltage generation circuit 10 and the operational amplifier 20 constitute a semiconductor constant voltage source circuit and output a constant voltage. That is, the semiconductor constant voltage source circuit 1 has a configuration in which a reference voltage corresponding to Vtn is input to a non-inverting input terminal (+), and its output is fed back to the inverting input terminal (−). The operational amplifier 20 outputs Vtn + | Vtp |), and the reference voltage generation circuit 10 generates the reference voltage using the voltage (Vtn + | Vtp |) output from the operational amplifier 20 as a power source.

As will be described later in detail, the reference voltage generation circuit 10 includes an NMOS transistor in its current path, generates a voltage (Vtn) corresponding to the threshold voltage of the NMOS transistor as the reference voltage, and the operational amplifier 20 An offset PMOS transistor is included in the current path on the inverting input side (−). By having an offset voltage corresponding to the absolute value of the threshold voltage of the offset PMOS transistor, the threshold voltage of the NMOS transistor ( A voltage corresponding to the sum of the absolute value (| Vtp |) of the threshold voltage of the offset PMOS transistor and the offset PMOS transistor is output as a constant voltage (Vtn + | Vtp |).
As shown in FIG. 2, the reference voltage generation circuit 10 includes a resistor R1 and an NMOS transistor N1. One end of the resistor R1 is connected to the output end of the activation circuit 60, and the other end is connected to the drain of the NMOS transistor N1. The source of the NMOS transistor N1 is connected to the ground (GND) potential, and the gate and the drain are connected (diode connection). In the reference voltage generation circuit 10, a voltage (Vtn) corresponding to the threshold voltage of the NMOS transistor N1 is generated as a reference voltage. This reference voltage (Vtn) is input to the operational amplifier 20 from the non-inverting input terminal IN (+).

The operational amplifier 20 to which the reference voltage (Vtn) generated by the reference voltage generation circuit is input includes PMOS transistors P2, P3, and P4, NMOS transistors N2, N3, and N4, a resistor R2, and a capacitor C, and further for offset. A current mirror connection unit 21 including a PMOS transistor P1, a PMOS transistor P6, and an NMOS transistor N9 is provided.
The sources of the PMOS transistors P2-P4 of the operational amplifier 20 are connected to the power supply voltage Vdd, and the source of the NMOS transistor N2 is grounded (GND). The gate and drain of the PMOS transistor P2 are connected, and the drain is connected to the drain of the NMOS transistor N3. The PMOS transistor P3 has a gate connected to the gate of the PMOS transistor P2, and a drain connected to the drain of the NMOS transistor N4.

The operational amplifier 20 has a voltage follower configuration, the non-inverting input terminal IN (+) is connected to the gate of the NMOS transistor N4, and the inverting input terminal IN (−) is connected to the gate of the NMOS transistor N3. The source of the NMOS transistor N4 is connected to the drain of the NMOS transistor N2. The source of the NMOS transistor N2 is grounded (GND), and the gate is connected to a signal line connecting the gate of the NMOS transistor N9 and the gate / drain of the NMOS transistor N1.
The inverting input terminal IN (−) is connected to a signal line connecting the output terminal OUT and one end of the resistor R1 constituting the reference voltage generating circuit 10, and the non-inverting input terminal IN (−) is connected to the resistor R1. Connected to the other end.

The PMOS transistor P4 has a drain connected to the signal line connecting the output terminal OUT and one end of the resistor R1, and a gate connected to the midpoint of the drain of the PMOS transistor P3 and the drain of the NMOS transistor N4. A resistor R2 and a capacitor C connected in series are connected between the drain of the PMOS transistor P4.
The current mirror connection portion 21 provided in the operational amplifier 20 is one of the features of this embodiment, and includes a current mirror circuit including an NMOS transistor N1, an NMOS transistor N9, a PMOS transistor P6, and a PMOS transistor P7, and an NMOS. The reference current flowing through the transistor N1 is supplied to the subsequent constant current source 40 by the current mirror effect. The NMOS transistor N9 has a gate connected to the gate / drain of the NMOS transistor N1, a source grounded, and a drain connected to the gate / drain of the PMOS transistor P6. At this time, the gate of the NMOS transistor N2 is connected to the gate of the NMOS transistor N9 and the gate / drain of the NMOS transistor N1. The gate and drain of the PMOS transistor P6 are connected to the gate of the PMOS transistor P7 constituting the constant current source 40, and the source is connected to a signal line connecting the output terminal OUT and one end of the resistor R1.

A self-biased circuit such as a semiconductor constant voltage source circuit is stable even when no current flows in the circuit. In a state where no current flows, the circuit is in an off state. In this state, the circuit is activated by the activation circuit in order to prevent it from resting. In the starting circuit 60 shown in FIG. 1, the current generated by the current source is sent to the resistor R1 of the reference voltage generating circuit 10 through a current mirror circuit composed of NMOS transistors N6 and N7 to start it.
The starting circuit 60 is composed of a PMOS transistor P5, NMOS transistors N6, N7, N8 and a resistor R3. The NMOS transistor N6 has a gate and drain connected, and a drain connected to the power supply voltage Vdd via the resistor R3. The NMOS transistor N7 has a drain connected to the power supply voltage Vdd, a gate connected to the gate of the NMOS transistor N6, and a source connected to the reference voltage generation circuit 10. The PMOS transistor P5 has a gate / drain connected and a source connected to the source of the NMOS transistor N6. The NMOS transistor N8 has a gate / drain connected and a source grounded.

In this way, the current flowing through the reference voltage generation circuit 10 can be supplied to the constant current source 40 via the current mirror circuit of the current mirror connection unit 21.
In response to the current supplied from the reference voltage generation circuit 10, the constant current source 40 drives a CMOS inverter of the oscillation unit 30, and the CMOS inverter is connected to a crystal resonator (not shown) in parallel with the CMOS inverter. Drive). Furthermore, the constant voltage generated by the semiconductor constant voltage source circuit 1 is used as a power source for a logic circuit 50 such as another CMOS inverter or a frequency divider circuit.
This embodiment has another feature in that the offset PMOS transistor P1 is incorporated in the operational amplifier 20. The PMOS transistor P1 has a source connected to the source of the NMOS transistor N3, a gate and a drain connected, and a gate and a drain connected to the drain of the NMOS transistor N2 and the source of the NMOS transistor N4.

As described above, the operational amplifier includes the offset PMOS transistor P1 in the current path on the inverting input side (−). Therefore, the semiconductor constant voltage source circuit outputs, as a constant voltage, a voltage corresponding to the sum of absolute values of the threshold voltage Vtn of the NMOS transistor N1 of the reference voltage generation circuit 10 and the threshold voltage Vtp of the offset PMOS transistor P1. To do. The generated constant voltage can be operated from a low voltage, and a stable voltage can be obtained.
Further, when driving the oscillating unit, the current supplied to the oscillating unit becomes the current consumption as it is, and the logic circuit in the subsequent stage can reduce the current consumption without the influence of the through current.

Next, Example 2 will be described. In this embodiment, the PMOS transistor used in the first embodiment is changed to an NMOS transistor, and the NMOS transistor is changed to a PMOS transistor. Its configuration is as shown in paragraph 0008.
In such a semiconductor constant voltage source circuit, as in the first embodiment, the operational amplifier is provided with an offset NMOS transistor in the current path on the inverting input side (−). Therefore, a voltage corresponding to the sum of the threshold voltage Vtp of the PMOS transistor of the reference voltage generation circuit and the threshold voltage Vtn of the NMOS transistor for offset is output as a constant voltage. The generated constant voltage can be operated from a low voltage, and a stable voltage can be obtained.
Further, when driving the oscillating unit, the current supplied to the oscillating unit becomes the current consumption as it is, and the logic circuit in the subsequent stage can reduce the current consumption without the influence of the through current.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor constant voltage source circuit 10 ... Reference voltage generation circuit 20 ... Operational amplifier 21 ... Current mirror connection part 30 ... Oscillation part 40 ... Constant current source 50 ... Logic circuit 60 ... Starting circuit

Claims (2)

An oscillation unit including an inverter circuit in which a current is controlled by a constant current source provided in a current path and a vibrator is connected between input and output ;
An operational amplifier that has a voltage follower configuration in which a reference voltage is input to the non- inverting input terminal and the output is directly fed back to the inverting input terminal without passing through other elements, and outputs a predetermined constant voltage;
A reference voltage generation circuit that generates the reference voltage using a voltage output from the operational amplifier as a power source;
The reference voltage generation circuit includes a reference voltage transistor, which is one of N-type and P-type MOS transistors, in its current path, and a voltage corresponding to a threshold voltage of the reference voltage transistor is the reference voltage Generate as voltage ,
The operational amplifier has a current mirror connection part to the constant current source that causes the current flowing through the reference voltage transistor to be generated in the constant current source by a current mirror effect, and the reference voltage of N type or P type An offset transistor which is a MOS transistor of a type different from the transistor type is included in the current path on the inverting input side, and a current mirror transistor which is a MOS transistor of the N type or P type which matches the type of the reference voltage transistor A voltage corresponding to the sum of the threshold voltage of the reference voltage transistor and the threshold voltage of the offset transistor by having an offset voltage corresponding to the threshold voltage of the offset transistor included in the current mirror connection portion Is output as the constant voltage, and the constant voltage is used as the power source of the oscillation unit. An oscillation circuit characterized by being used.   The reference voltage generation circuit further includes a resistance element having one end connected to the inverting input terminal and the other end connected to the non-inverting input terminal in its current path,
  The reference voltage transistor has a diode connection in which a drain terminal is connected to the resistance element, a source terminal is connected to a ground potential, and a gate terminal and a drain terminal are connected to each other,
  A voltage generated between a drain terminal and a source terminal of the reference voltage transistor due to a current flowing through the reference voltage transistor through the resistance element is generated as the reference voltage.
  The oscillation circuit according to claim 1.

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