JP6320047B2 - Constant voltage source circuit - Google Patents

Description

  The present invention relates to a constant voltage source circuit that outputs a voltage corresponding to the sum of threshold voltages of an NMOS transistor and a PMOS transistor as a constant voltage.

  Conventionally, when trying to operate a CMOS circuit at a low power, it is desirable to operate in a power supply voltage region where no through current flows. For example, | Vtp | + Vtn (= ΣVth), which is a voltage just before the through current starts to flow, is used as the power supply voltage. A circuit that generates the reference voltage of ΣVth is described in Patent Document 1. 4 and 5 are outlines of the reference voltage generating circuit and the constant voltage circuit disclosed in Patent Document 1. FIG. Vtp and Vtn are the threshold voltages (Vth) of the PMOS transistor and NMOS transistor used in the CMOS circuit, respectively.

  The reference voltage generating circuit shown in FIG. 4 includes a constant current source 101 having one end connected to the positive power supply VDD, a PMOS transistor 103 having a source electrode connected to the constant current source 101, and a drain electrode and a gate electrode connected to each other. The NMOS transistor 105 has a drain electrode connected to the drain electrode of the PMOS transistor 103, a gate electrode connected to the drain electrode, and a source electrode grounded (GND). Both transistors are connected in series. An output node 107 for outputting the output voltage Vreg is connected between the constant current source 101 and the PMOS transistor 103.

Here, when a power supply voltage is supplied between GND and VDD, both the PMOS transistor 103 and the NMOS transistor 105 connect the gate electrode and the drain electrode, so that VDS = VGS (VDS is the voltage between the drain electrode and the source electrode, VGS is a voltage between the gate electrode and the source electrode). For example, when the set current value of the constant current source 101 is set so that the PMOS transistor 103 and the NMOS transistor 105 operate near the threshold voltage Vth, the VDS of the PMOS transistor 103 and the NMOS transistor 105 are approximately Vtp and Vtn, respectively. . Therefore, Vreg is approximately | Vtp | + Vtn (= ΣVth), and Vreg is approximately equal to the sum ΣVth of the threshold voltages of the PMOS transistor 103 and the NMOS transistor 5. Further, by arbitrarily setting the current value of the constant current source 101, it is possible to adjust the VDS of the PMOS transistor 103 and the NMOS transistor 105, that is, Vreg.
The constant voltage circuit shown in FIG. 5 generates a power supply for driving the oscillation circuit. The constant voltage circuit includes a reference voltage generation circuit 100 and an impedance conversion unit 200, and a desired output voltage generated by the reference voltage generation circuit 100. (Vreg) is converted into a low impedance by the impedance converter 200 and supplied to the oscillation circuit 300.

JP-A-8-305453

In a circuit that generates a reference voltage, a power supply voltage (Vdd) is generally used for the power supply. However, when the power supply voltage fluctuates, the generated reference voltage (Vreg) is also affected. In particular, when | Vtp | + Vtn is set to a low voltage of about 1 V in order to reduce current consumption in the CMOS circuit, even if the reference voltage (Vreg) varies due to a minute variation of the power supply voltage (Vdd), The effect is relatively large.
As a countermeasure against fluctuations in the power supply voltage (Vdd), a so-called self-bias configuration in which the output (reference voltage Vreg) generated in the reference voltage circuit is used as the self power supply voltage can be considered. However, when using the output voltage as its own power supply voltage, it is necessary to convert the output voltage to a voltage higher than the output voltage when feedback is performed. There is a problem that the circuit becomes complicated, such as being required by adding one stage, and the current consumption increases.
The present invention has been made under such circumstances, and can operate from a low voltage while having a self-bias configuration in which the output generated in the reference voltage circuit is used as its own power supply voltage, and is a highly stable constant voltage. A semiconductor constant voltage source circuit is provided.

One embodiment of the present invention has a voltage follower configuration in which a reference voltage is input to a non-inverting input terminal and the output is directly fed back to the inverting input terminal without passing through other elements, and outputs a predetermined constant voltage. And a reference voltage generating circuit that generates the reference voltage using a voltage output from the operational amplifier as a power source, and the reference voltage generating circuit is an N-type or P-type MOS transistor The reference voltage transistor is included in the current path, and a voltage corresponding to the threshold voltage of the reference voltage transistor is generated as the reference voltage. The operational amplifier is an N type or a P type of the reference voltage transistor. and Nde including a current path of the offset transistor inverting input MOS transistors of different types and the threshold of the offset transistor By having an offset voltage corresponding to the voltage, the semiconductor constant voltage and outputs a voltage corresponding to the sum of the threshold voltage and the threshold voltage of the offset transistor of the reference voltage transistor as the constant voltage Source circuit.

One embodiment of the present invention is the above-described semiconductor constant voltage source circuit, wherein the reference voltage generation circuit includes a resistance element having one end connected to the inverting input terminal and the other end connected to the non-inverting input terminal. The reference voltage transistor further includes a diode connection in which a drain terminal is connected to the resistance element, a source terminal is connected to a ground potential, and a gate terminal and a drain terminal are connected to each other. A voltage generated between the drain terminal and the source terminal of the reference voltage transistor due to the current flowing through the reference voltage transistor via the reference voltage transistor is generated as the reference voltage.

It is possible to operate from a low voltage while using a self-bias configuration in which the output generated in the reference voltage circuit is used as its own power supply voltage, and a highly stable constant voltage can be output.

1 is a block diagram of a semiconductor constant voltage source circuit according to a first embodiment. 1 is a circuit diagram showing details of a semiconductor constant voltage source circuit according to Embodiment 1. FIG. The circuit diagram which shows the detail of the starting circuit which concerns on FIG. The circuit diagram of the conventional reference voltage generation circuit. The circuit diagram of the conventional constant voltage circuit.

    Hereinafter, embodiments of the invention will be described with reference to examples.

The first embodiment will be described with reference to FIGS.
As shown in FIG. 1, the semiconductor constant voltage source circuit 1 has a configuration in which a reference voltage (Vtn) is input to a non-inverting input terminal (+) and an output (Vtp) is fed back to the inverting input terminal (−). An operational amplifier 20 that outputs a predetermined constant voltage (Vtn + Vtp), and a reference voltage generation circuit 10 that generates the reference voltage using the voltage (Vtn + Vtp) output from the operational amplifier 20 as a power source.
As will be described later in detail, the reference voltage generation circuit 10 includes an NMOS transistor in its current path, generates a voltage (Vtn) corresponding to the threshold voltage of the NMOS transistor as the reference voltage, and the operational amplifier 20 The PMOS transistor for offset is included in the current path on the inverting input side (−), and by having an offset voltage corresponding to the threshold voltage of this PMOS transistor for offset, the threshold voltage (Vtn) of the NMOS transistor A voltage corresponding to the sum of absolute values (| Vtp |) of threshold voltages of the offset PMOS transistors is output as a constant voltage (Vtn + | Vtp |).

As shown in FIG. 2, the reference voltage generation circuit 10 includes a resistor R1 and an NMOS transistor N1. One end of the resistor R1 is connected to the output end of the starter circuit 30, and the other end is connected to the drain of the NMOS transistor N1. The source of the NMOS transistor N1 is connected to the ground (GND) potential, and the gate and the drain are connected (diode connected). In the reference voltage generation circuit 10, a voltage (Vtn) corresponding to the threshold voltage of the NMOS transistor N1 is generated as a reference voltage. This reference voltage (Vtn) is input to the operational amplifier 20.
The operational amplifier 20 to which the reference voltage (Vtn) generated by the reference voltage generation circuit 10 is input includes PMOS transistors P2, P3, P4, NMOS transistors N2, N3, N4, N5, a resistor R2, and a capacitor C. An offset PMOS transistor P1 is provided.

  The sources of the PMOS transistors P2-P4 of the operational amplifier 20 are connected to the power supply voltage Vdd, and the sources of the NMOS transistors N2, N5 are grounded (GND). The gate and drain of the PMOS transistor P2 are connected, and the drain is connected to the drain of the NMOS transistor N3. The PMOS transistor P3 has a gate connected to the gate of the PMOS transistor P2, and a drain connected to the drain of the NMOS transistor N4.

  The operational amplifier 20 has a voltage follower configuration, the non-inverting input terminal IN (+) is connected to the gate of the NMOS transistor N4, and the inverting input terminal IN (−) is connected to the gate of the NMOS transistor N3. The source of the NMOS transistor N4 is connected to the drain of the NMOS transistor N2. The source of the NMOS transistor N2 is grounded (GND), and the gate is connected to a signal line connecting the output terminal OUT of the operational amplifier 20 and the gate / drain of the NMOS transistor N1 constituting the reference voltage generation circuit 10. In this signal line, an NMOS transistor N5 is provided between the output terminal OUT and the gate of the NMOS transistor N2, the gate is connected to the gate of the NMOS transistor N2, the drain is connected to the output terminal OUT, and the source is connected. Grounded (GND).

The inverting input terminal IN (−) is connected to a signal line connecting the output terminal OUT and one end of the resistor R1 constituting the reference voltage generation circuit 10, and the non-inverting input terminal IN (+) is connected to the resistor R1. Connected to the other end.
The PMOS transistor P4 has a drain connected to the signal line connecting the output terminal OUT and one end of the resistor R1, and a gate connected to the midpoint of the drain of the PMOS transistor P3 and the drain of the NMOS transistor N4. A resistor R2 and a capacitor C connected in series are connected between the drain of the PMOS transistor P4.

  The starter circuit 30 includes a PMOS transistor P5, NMOS transistors N6, N7, N8, and a resistor R3. The NMOS transistor N6 has a gate and drain connected, and a drain connected to the power supply voltage Vdd via the resistor R3. The NMOS transistor N7 has a drain connected to the power supply voltage Vdd, a gate connected to the gate of the NMOS transistor N6, and a source connected to the reference voltage generation circuit 10. The PMOS transistor P5 has a gate / drain connected and a source connected to the source of the NMOS transistor N6. The NMOS transistor N8 has a gate / drain connected and a source grounded. A self-biased circuit such as a semiconductor constant voltage source circuit is stable even when no current flows in the circuit. In a state where no current flows, the circuit is in an off state. In this state, the circuit is started up by a start-up circuit to prevent it from being stopped. The current generated by the current source of the starting circuit 30 is sent to the reference voltage generating circuit 10 via a current mirror circuit composed of NMOS transistors N6 and N7 and is started.

This embodiment is characterized in that the offset PMOS transistor P1 is incorporated in the operational amplifier 20. The PMOS transistor P1 has a source connected to the source of the NMOS transistor N3, a gate and a drain connected, and a gate and a drain connected to the drain of the NMOS transistor N2 and the source of the NMOS transistor N4.
As described above, the operational amplifier includes the offset PMOS transistor P1 in the current path on the inverting input side (−). Therefore, the semiconductor constant voltage source circuit outputs a voltage corresponding to the sum of the threshold voltage Vtn of the NMOS transistor N1 of the reference voltage generation circuit 10 and the threshold voltage Vtp of the offset PMOS transistor P1 as a constant voltage. The generated constant voltage can be operated from a low voltage, and a stable voltage can be obtained.

Next, Example 2 will be described. In this embodiment, the PMOS transistor used in the first embodiment is changed to an NMOS transistor, and the NMOS transistor is changed to a PMOS transistor. Its configuration is as shown in paragraph 0008.
In such a semiconductor constant voltage source circuit, as in the first embodiment, the operational amplifier is provided with an offset NMOS transistor in the current path on the inverting input side (−). Therefore, a voltage corresponding to the sum of the threshold voltage Vtp of the PMOS transistor of the reference voltage generation circuit and the threshold voltage Vtn of the NMOS transistor for offset is output as a constant voltage. The generated constant voltage can be operated from a low voltage, and a stable voltage can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor constant voltage source circuit 10 ... Reference voltage generation circuit 20 ... Operational amplifier 30 ... Starting circuit

Claims (2)

An operational amplifier that has a voltage follower configuration in which a reference voltage is input to the non-inverting input terminal and the output is directly fed back to the inverting input terminal without passing through other elements, and outputs a predetermined constant voltage;
A reference voltage generation circuit that generates the reference voltage using a voltage output from the operational amplifier as a power source;
The reference voltage generation circuit includes a reference voltage transistor , which is one of N-type and P-type MOS transistors, in its current path, and a voltage corresponding to a threshold voltage of the reference voltage transistor is the reference voltage Generate as voltage,
The operational amplifier, N-type or are Nde including a current path of the offset transistor inverting input MOS transistors of a different type than the type of the reference voltage transistor of the P-type, corresponding to the threshold voltage of the offset transistor A semiconductor constant voltage source circuit characterized in that a voltage corresponding to the sum of the threshold voltage of the reference voltage transistor and the threshold voltage of the offset transistor is output as the constant voltage.   The reference voltage generation circuit further includes a resistance element having one end connected to the inverting input terminal and the other end connected to the non-inverting input terminal in its current path,
  The reference voltage transistor has a diode connection in which a drain terminal is connected to the resistance element, a source terminal is connected to a ground potential, and a gate terminal and a drain terminal are connected to each other,
  A voltage generated between a drain terminal and a source terminal of the reference voltage transistor due to a current flowing through the reference voltage transistor through the resistance element is generated as the reference voltage.
  The semiconductor constant voltage source circuit according to claim 1.

Images