KR101506579B1 - Class ab amplifier having bias stabilizing circuit - Google Patents

Abstract

The present invention enables negative feedback of current information flowing through two output transistors in alternate operation in a push-pull manner so that a stable bias is maintained which stably maintains a bias current regardless of which of the two output transistors is inactive And to a class AB amplifier that maintains.

Description

CLAST AB AMPLIFIER HAVING BIAS STABILIZING CIRCUIT < RTI ID = 0.0 >

The present invention enables negative feedback of current information flowing through two output transistors in alternate operation in a push-pull manner so that a stable bias is maintained which stably maintains a bias current regardless of which of the two output transistors is inactive And to a class AB amplifier that maintains.

An amplifier that amplifies a signal is a basic block that is commonly used in electronic circuits. However, as a result of efforts to reduce power consumption as well as the development of portable electronic devices, AB Various modifications of the class amplifier have been used, and in particular, they have been developed as efficient amplifiers with lower operating voltages

An AB class amplifier amplifies an input signal to constitute an output section that supplies current to a load in the form of two output drive elements and operates alternately but does not completely shut off an output drive element that is not operated, So that it operates without delay in the next cycle. This is to prevent crossover distortion occurring when switching from the blocking state to the operating state. Such an AB class amplifier will be described with reference to FIG.

FIG. 1 is a circuit diagram of a conventional class AB amplifier. Since the main feature of the present invention is a bias circuit, only the circuit portion will be described in detail, and other circuit portions will be briefly described. Ib2, Ib3, Ib4) are abbreviated.

The class AB amplifier according to the prior art shown in Fig. 1 includes a driving voltage generating section 1, an output section 2, a bias circuit section 3, and an input stage 4.

The input stage 4 converts the voltage difference between the input voltage signal Vip and the input voltage signal Vin input through the two terminals into a single current signal and applies it to the input signal Iin of the driving voltage generator 1 Circuit which is composed of PMOS transistors M21 and M22 in differential structure and M23, M24 and M25 which are NMOS transistors, respectively, to generate an input signal Iin converted into a single current signal, And a single conversion unit.

M21, and M22, it is assumed that the sources of M21 and M22 are coupled, the input voltage signal Vip is input to the gate of M21, the input voltage signal Vin is input to the gate of M2, And a current is supplied from the current source Ib3 connected to the power supply voltage VDD. Accordingly, the drain currents of M21 and M22 fluctuate in accordance with the voltage level difference between the input voltage signals Vip and Vin.

M23, M24, and M25, M23 is configured to supply a reference voltage Vref, which is preset in the same manner as M8, to the driving voltage generating unit 1, and supplies a current source connected to the HIGH level power supply voltage VDD And a drain is connected to the current source Ib4 to receive a current from the current source Ib4. In the case of M24, the drain is connected to the source of M23 and the drain of M22, the source is connected to the LOW level power supply voltage GND, and the gate is connected to the drain of M23. In the case of M25, the gate is connected to the drain of M23 in the same manner as the gate of M24, the drain is connected to the sources of M8 and M9 mutually coupled in the drive voltage generator 1 and also to the drain of M21, It is connected to the LOW level power supply voltage GND.

The input stage 4 configured as described above changes the input signal Iin applied to the driving voltage generator 1 according to the voltage level difference between the input voltage signals Vip and Vin and outputs the driving voltage Va, Vb). For example, when Vip > Vin, the input signal Iin is increased because M21 flows less current than M22, and conversely, when Vip < Vin, M21 flows more current than M22. The input signal Iin of the drive voltage generator 1 is changed in accordance with the voltage level difference between the input voltage signals Vip and Vin so that the drive voltages Va and Vb of the drive voltage generator 1 ) Is generated.

The driving voltage generating section 1 includes M8 and M9 which are NMOS transistors. The driving voltage generating section 1 receives the input signal Iin of the input stage (not shown) commonly to the sources of M8 and M9 and receives the HIGH level power supply voltage VDD A bias voltage Vc is applied to the gate of M8 and a negative feedback voltage Vc is applied to the gate of M9 through the bias circuit 3. The current source Ib1 and Ib2 connected to the current source Ib1 and Ib2 are connected to the drain, It can accommodate the bias of the AB amplifier.

Here, the drain voltage of M8 is generated as a voltage signal corresponding to the LOW level signal in the input signal Iin as the LOW level drive voltage Va and applied to the gate of M1 of the output section 2, and the drain voltage of M9 is And is generated as a voltage signal corresponding to the HIGH level signal among the input signal Iin as the HIGH level driving voltage Vb and is applied to the gate of M2 of the output section 2. [

The output unit 2 is composed of M1 made of PMOS and M2 made of NMOS and each drain is connected to the output terminal Vout and the source of M1 is connected to the HIGH level power supply VDD and the source of M2 is set to the LOW level power supply voltage The gate of M1 is connected to the drain of M8 of the driving voltage generating unit 1 and the LOW level driving voltage Va is applied thereto and the gate of M2 is connected to the drain of M9 of the driving voltage generating unit 1. [ And a HIGH level driving voltage Vb is applied. M1 and M2 are alternately operated by the drive voltages Va and Vb so that the current flows to the load through the output terminal Vout when M1 is operated and the current flows to the output terminal Vout ), The PUSH-PULL output flowing from the load is made.

When the transistor M1 operates, the transistor M2 enters a non-operating state. In this case, the non-operation of the transistor M2 maintains the conduction state by applying the HIGH level driving voltage Vb at a voltage slightly higher than the threshold voltage To this end, the current flowing during the non-operation of M2 is negatively fed back and applied to the gate of M9 of the driving voltage generator 1 as the negative feedback voltage Vc. This is because, as a characteristic of the class AB amplifier, it is possible to prevent crossover distortion when switching the M2 to a normal turn-on operation state by maintaining the turn-on state with a slight current, It is to reduce power.

The bias circuit section 3 is composed of a current mirror section 3-1, a feedback current generating section 3-2 and a current-voltage converting section 3-3 and corresponds to a current flowing in M2 of the output section 2 To the M2 gate of the driving voltage generating section 1. The driving voltage generating section 1 generates the negative feedback voltage Vc.

The current mirror unit 3-1 is composed of M3 made of NMOS like M2, and mirrors the current of M2. To this end, M3 and M2 are connected together by their gates and their sources are connected together so that a current proportional to the drain-source current of M2 is copied to the drain-source current of M3.

M4 and M5 each have a source connected to the HIGH level power supply voltage VDD and the gates connected to each other, and M4 and M5 are connected to each other. The feedback current generator 3-2 includes three PMOS transistors M4, M5 and M6. And the drain of M4 is connected to the drain of M3. Thus, the current mirrored by M3 is re-mirrored to M5 while flowing through M4, where the re-mirrored current is supplied to the current-voltage conversion unit 3-3.

At this time, M6 is provided between the M5 and the current-to-voltage converter (3-3) and interrupts the re-mirroring current to be supplied to the current-voltage converter (3-3) when the M1 is operated. The source is connected to the drain of M5, the drain is connected to the current-voltage converting portion 3-3, and the gate is connected to the gate of M1. That is, when the LOW level driving voltage Va which is the gate voltage of M1 is LOW, M1 operates. At this time, M6 is also turned on so that a current mirrored by M2 to M3, M4 and M5 is outputted to the current- .

The current-to-voltage conversion unit 3-3 converts the mirror current of M2 by M3, M4 and M5 into a voltage signal to generate a negative feedback voltage Vc and applies a negative feedback voltage Vc to the gate of M9. The current-to-voltage conversion unit 3-3 is composed of NMOS M7, and has a circuit such that a drain and a gate are commonly connected to a drain of M6 and a source is connected to a ground (GND).

The bias circuit portion 3 configured as described above is configured to have a bias current of M3 and M4 (hereinafter referred to as &quot; bias current I3 &quot;) by using a current flowing in the non- And M5, and transmits it to M7. However, when M1 operates and M2 does not operate, it is transmitted to M7 to be negative feedback. When M2 is operating, that is, when M1 is in the non-operating state, the LOW level driving voltage Va, which is the gate voltage of M1, is HIGH, so that M6 is turned off so that the current mirroring current of M2 is not transmitted to M7.

When the current of M2 is increased due to factors such as load variation in the non-operating state, the current supplied to M7 is mirrored by M3, M4 and M5, and the drain voltage of M7, that is, the feedback voltage Vc, . Here, since M8 and M9 constituting the driving voltage generating section 1 are differential structures, and the gate of M8 is applied with the reference voltage Vref and the gate of M9 is applied with the negative feedback voltage Vc, When the negative feedback voltage Vc becomes larger than the reference voltage Vref due to the increase of the non-operating current, the gate voltage of M1 becomes higher and the gate voltage of M2 becomes lower. As a result, the bias currents of M1 and M2 become small.

On the other hand, if the current decreases in the non-operation state of the transistor M2 and the negative feedback voltage Vc decreases, the gate voltage of the transistor M1 becomes lower and the gate voltage of the transistor M2 becomes higher. As a result, the bias current flowing in the output becomes large.

As described above, the bias circuit unit 3 has a negative feedback structure, so that the bias current of M2 of the output unit 2 is stabilized.

However, the conventional class AB amplifier described with reference to FIG. 1 transfers the current information of M2 to M7, but does not transmit the current information of M1, which is a half bias control circuit. That is, when M1 does not operate normally due to some factor and there is a problem, it can not detect it, and since the current information of M1 is not transmitted, the ripple of the negative feedback voltage Vc becomes large, And the distortion is also increased.

Furthermore, there is also a problem that the current of M2 is transmitted only when M1 operates.

SUMMARY OF THE INVENTION [0008] Accordingly, it is an object of the present invention to provide a method and apparatus for supplying a stable bias current, regardless of the direction in which a push-pull type output current flows in order to solve the problems and disadvantages of the prior art, And to provide a class AB amplifier that maintains a constant bias to maintain a constant bias that minimizes crossover distortion due to stable operation even when the driving is not performed regardless of variations.

According to an aspect of the present invention, there is provided a method of driving a semiconductor device including a first output transistor and a second output transistor connected in a push-pull manner and alternately operated according to a driving voltage applied to each gate, An output unit 2; A voltage corresponding to the bias current is negatively fed back by using the current of the output transistor that is inactive among the first output transistor and the second output transistor as a bias current so that the biased HIGH level driving voltage with respect to the HIGH level of the input signal, A driving voltage generator (1) for generating a biased LOW level driving voltage for a LOW level and applying the same to the gates of the first output transistor and the gates of the second output transistor in a one-to-one manner to operate alternately; And a bias circuit unit (10) for generating a negative feedback voltage corresponding to a bias current of the non-operational output transistor and transmitting the negative feedback voltage to the driving voltage generation unit (1) The bias circuit unit 10 includes a current mirror unit 11 for mirroring currents of the first and second output transistors, respectively; A current comparator (12) for comparing the currents of the first and second output transistors to select an inactive output transistor; A current selector (13) for selecting a mirror current of the output transistor selected by the current comparator (12); And a current-to-voltage conversion unit (14) for converting the selected mirror current into a voltage signal and negative feedback to the driving voltage generation unit (1).

The driving voltage generating section 1 applies a first input transistor which applies a preset reference voltage to the gate and a drain voltage to the LOW level driving voltage and a second input transistor which applies a negative feedback voltage to the gate and a drain voltage to a HIGH level driving voltage And a current source is provided between each of the drains and the HIGH level power supply voltage, and an input current is commonly applied to the sources.

The first output transistor and the second output transistor of the output section 2 are connected in a push-pull manner between a preset high level power supply voltage and a ground voltage, with the LOW level power supply voltage of the power supply voltage being a ground voltage .

The current comparator 12 includes a PMOS transistor having a source connected to a HIGH level power supply voltage and a gate connected to a LOW level driving voltage, an NMOS transistor having a source connected to a LOW level power supply voltage, And the drains of the two transistors are connected to each other to select a selected voltage, and an output transistor which is not operated according to the magnitude of the selected voltage is selected.

The current selector 13 includes two transistors to which the selected voltage is applied to the gate so that either one of the transistors is operated in accordance with the magnitude of the selected voltage and the mirror current of the non- (14).

When the mirror current of the output transistor to be pulled out from the load is transferred to the first and second output transistors, the current selector 13 mirrors the mirror current again and transmits the mirror current to the current / voltage converter 14 .

And a filter unit 15 for smoothing the negative feedback voltage between the current-to-voltage conversion unit 14 and the driving voltage generation unit 1.

According to the present invention configured as described above, a transistor that operates in an alternating manner in the output unit is selected to select a non-operating transistor, and the current flowing in the selected transistor is negatively fed back by determining it as a bias current. It deals with all the current information flowing in two transistors and constant feedback is applied across the whole area amplifying the input signal, thereby suppressing the ripple of the negative feedback, stabilizing the bias current of the output current, prevent.

Further, the present invention prevents the output current from being distorted due to stable bias, and minimizes crossover distortion.

1 is a circuit diagram of a class AB amplifier according to the prior art;
2 is a circuit diagram of a class AB amplifier that maintains a stable bias according to an embodiment of the present invention;
3 is a graph of voltage and current waveforms of a class AB amplifier maintaining a stable bias according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that, in the drawings, the same reference numerals are used to denote the same or similar components in other drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 2 is a circuit diagram of a class AB amplifier that maintains a stable bias according to an embodiment of the present invention, and FIG. 3 is a graph of voltage and current waveforms of a class AB amplifier that maintains a stable bias according to an embodiment of the present invention .

The class AB amplifier that maintains a stable bias according to an embodiment of the present invention includes an input stage (I) for converting a voltage difference of an input voltage signal input through two terminals into a single current signal to generate an input signal Iin A driving voltage generating unit 1 for receiving the input signal Iin from the input stage 4 to generate a driving voltage, an output unit 2 for amplifying and outputting the driving voltage, And a bias circuit unit (10) for negatively feeding a voltage corresponding to the bias current in the output unit (2) in order to apply a bias current to the output current and stabilize the bias current.

First, the driving voltage generating unit 1 and the output unit 2 are the same as those described with reference to the class AB amplifier according to the related art shown in FIG. 1 in the background art of the present invention. However, The bias circuit portion 10 will be described in more detail with reference to the background art. The input stage 4 for applying the input signal Iin to the driving voltage generating unit 1 can be constructed by referring to the input stage 4 in FIG. 1 to explain the background art of the present invention. Are not shown in detail, and explanations thereof are omitted.

The output unit 2 includes a first output transistor M1 formed by a PMOS transistor and a second output transistor M2 formed by an NMOS transistor and supplies an output current to the load in a push-pull manner . That is, the first output transistor Ml and the second output transistor M2 are connected between a preset HIGH level power supply voltage and a LOW level power supply voltage to alternately operate. For example, In this case, the output current through the output terminal flows toward the load, and then the output from the load is alternately repeated.

Here, the operation of the first output transistor Ml and the second output transistor M2 is a turn-on state to perform the amplifying operation.

As opposed to the operation, the non-operation means not to shut off the output transistor, but to maintain the turn-on state to such a degree that a slight current flows. Thus, the first and second output transistors M1 and M2 are alternately operated, and the non-operating transistor conducts a small amount of current for the class AB amplifying operation. This non-operating state is a key feature of the Class AB amplifying operation that prevents crossover distortion from occurring when switching to the operating state. In a real class AB amplifier, when the output transistor is deactivated, it is applied to the gate with a voltage slightly higher than the threshold voltage to cause a very low current, i.e., a bias current, to flow between the drain and the source. In a non-operating state, a driving voltage greater than a voltage applied to the gate is applied in an operating state to cause a current corresponding to the driving voltage to flow to the output transistor to be output. Here, it is a well known technology that the high and low voltages of PMOS and NMOS are opposite to each other.

1, a drain of the first output transistor Ml and a drain of the second output transistor Ml are coupled to an output terminal Vout, A source of the transistor M1 is connected to the HIGH level power supply voltage VDD and a source of the second output transistor M2 is connected to the LOW level power supply voltage GND. The gate of the first output transistor M1 and the gate of the second output transistor M2 are respectively supplied with the driving voltage from the driving voltage generator 1 and the first output transistor M1 and the second transistor M2 ) Alternately operate to provide the output current in a push-pull manner to the load.

The output current is either PUSH or pulled depending on the magnitude of the first output current IM1 flowing through the first output transistor M1 and the second output current IM2 flowing through the second output transistor M2 If the first output current IM1 is larger than the second output current IM2, the push current is obtained, and if the first output current IM1 is larger than the second output current IM2, the push current becomes the pull current.

Here, the class AB amplifier according to the embodiment of the present invention uses the preset HIGH level power supply voltage VDD and the LOW level power supply voltage GND while setting the LOW level power supply voltage GND as the ground voltage . Accordingly, the output voltage becomes a voltage swinging between the HIGH level power supply voltage VDD and the ground voltage.

The driving voltage generating unit 1 generates a driving voltage by applying a bias voltage to the driving voltage generating unit 1 so that the voltage corresponding to the bias current of the output signal is negatively fed back to generate a biased LOW level driving voltage Va versus the LOW level of the input signal, Level driving voltage Vb and applies it to the output section 2. [ A terminal for outputting the LOW level drive voltage Va and the HIGH level drive voltage Vb is connected to the gate of the first output transistor Ml and the second output transistor M2 provided in the output section 2 in a one- The first output transistor M1 and the second output transistor M2 are alternately operated in accordance with the application of the driving voltage so that the output signal through the output terminal Vout is applied to the load by the push- PULL).

Here, the LOW level driving voltage Va is a waveform representing the LOW signal information of the input signal, and the HIGH level driving voltage Vb is a waveform representing the HIGH signal information of the input signal.

According to a specific embodiment, the driving voltage generator 1 is configured to connect the first input transistor M8 and the second input transistor M9, which are respectively constituted by NMOS transistors, in a differential structure. Then, a predetermined reference voltage Vref is applied to the gate of the first input transistor M8, a negative feedback voltage corresponding to the bias current of the output current is applied to the gate of the second input transistor M9, Is coupled in circuit to couple the source of the input transistor M8 and the source of the second input transistor M9 to apply the input current Iin to amplify. The drain of the first input transistor M8 and the drain of the second input transistor M9 are respectively connected to the current sources Ib1 and Ib2 connected to the HIGH level power supply voltage VDD.

The driving voltage generator 1 configured as described above outputs the LOW level driving voltage Va through the drain of the first input transistor M8 and the HIGH level driving voltage V1 through the drain of the second input transistor M9, (Vb). The LOW level drive voltage Va and the HIGH level drive voltage Vb with respect to the input current Iin are formed by the waveforms shown in Fig.

As shown in FIG. 2, the class AB amplifier according to the embodiment of the present invention includes a bias circuit unit 10 as compared with the prior art shown in FIG.

The bias circuit part 10 selects the non-operating output transistor among the first and second output transistors M1 and M2 constituting the output part 2 and selects the output transistor that is not in operation and flows between the drain- And detects the current as a bias current, converts the current into a voltage corresponding to the bias current, and feeds back the voltage to the gate of the second input transistor M9 of the output unit 2. For this purpose, the current mirror unit 11, A current selection section 12, a current selection section 13, a current-voltage conversion section 14, and a filter section 15.

The current mirror unit 11 mirrors the output current IM1 of the first output transistor M1 and the output current IM2 of the second output transistor M2 of the output unit 2, To this end, it includes M14 composed of a PMOS transistor and M3 composed of an NMOS transistor. Here, mirroring is to copy current proportional to the output current.

M14 is of the same PMOS type as the first output transistor M1 and has a source connected to the source of the first output transistor M1 and a gate connected to the gate of the first output transistor M1, I.e., mirror, the current proportional to the current IMl of the transistor M1.

M3 is of the same NMOS type as the second output transistor M2 and has a source connected to the source of the second output transistor M2 and a gate connected to the gate of the second output transistor M2, I.e., mirror, the current proportional to the current IM2 of the transistor M1.

M14 and M3 are selected by the current selecting unit 13 and only one of the mirror currents is transmitted to the current-voltage converting unit 14. [ In the prior art shown in FIG. 1, only the second output transistor M2 is mirrored only by M3. In the present invention, the first output transistor M1 is also mirrored by M14.

The current comparator 12 compares the current of the first output transistor M1 with the current of the second output transistor M2 to select an inactive output transistor. According to an embodiment of the present invention, an output transistor which is not operated with a voltage level is selected. To this end, a PMOS transistor M12 and an NMOS transistor M13 are coupled to each other to connect the drains to each other, (Vd), which is a selection criterion of the voltage Vd. M12 connects the source to the source of the first output transistor (M1) and the gate to the gate of the first output transistor (M1), M13 connects the source to the source of the second output transistor (M2) To the gate of the second output transistor (M2). Since the source of the first output transistor Ml is connected to the HIGH level power supply voltage, the source of M12 is also connected to the HIGH level power supply voltage, and the source of the second output transistor M2 is connected to the LOW level power supply voltage. The source is also connected to the LOW level power supply voltage.

Accordingly, the M12 receives the LOW level driving voltage Va in the same manner as the first output transistor M1, and the M13 receives the HIGH level driving voltage Vb in the same manner as the second output transistor M2, If the first output transistor M1 is operated and the second output transistor M2 is not operated in accordance with the driving voltage, the current IM1 of the first output transistor M1 becomes the current IM2 and M12 are turned on so that the selection voltage Vd becomes the HIGH level power supply voltage VDD and the first output transistor M1 is inactive and the second output transistor M2 is in operation. The current IM2 of the two output transistor M2 becomes larger than the current IM1 of the first output transistor M1 and the transistor M13 is turned on so that the selection voltage Vd becomes the ground voltage GND.

That is, when the selection voltage Vd becomes the HIGH level power supply voltage VDD, the second output transistor M2 is in the inactive state, and when the selection voltage Vd becomes the ground voltage GND, So that the mirror current of the non-operating output transistor in the current selecting section 13 can be applied to the current-voltage converting section 14. [

The current selector 13 selects the mirror current of the output transistor selected by the current comparator 12 from the current mirror 11 and transfers the selected mirror current to the current / voltage converter 14, Two transistors M10 and M11 which apply a voltage Vd to the respective gates are provided so that only one of the transistors is turned on depending on the magnitude of the selection voltage Vd.

Referring to FIG. 2, a NMOS transistor M10 and a PMOS transistor M11 are provided. In the M10, a source is connected to a drain of M13 of the current mirror unit 11 so that a selection voltage Vd becomes a high level power supply voltage VDD. And the mirror current IM2 'of the second output transistor M2 is allowed to flow through the drain, and M11 connects the source to the drain of M14 of the current mirror portion 11 to turn on the selection voltage Vd And turns on to allow the mirror current IM1 'of the first output transistor M2 to flow to the drain when the ground voltage is GND.

Since the drain of M11 is connected to the current-voltage switching unit 14, the mirror current IM1 'of the first output transistor M2 is set such that the first output transistor M1 is inactive and the selection voltage Vd is grounded And is transmitted to the current-voltage switching unit 14 as M11 is turned on under the condition that the voltage becomes the voltage (GND).

However, since the mirror current IM2 'of the second output transistor M2 flows from M10 to M3 of the mirror portion 11, it is not directly transmitted to the current-voltage switching portion 14, but the second output transistor M2 The mirror current IM2 'is mirrored once again and is transferred to the current-to-voltage conversion unit 14. This is because the second output transistor M2 pulls the current from the load PULL and flows to the ground GND so that the mirror current of this current also flows to the ground GND. 2, a PMOS transistor M4 having a source connected to a HIGH level power supply voltage and a gate and a drain coupled to the drain of M10 is provided between the HIGH level power supply voltage VDD and the drain of M10, To flow the mirror current IM2 'of the second output transistor M2. M5, which is a PMOS transistor for mirroring the current of M4, that is, M5, which has a gate connected to the gate of M4, a source connected to the HIGH level power supply voltage VDD and a drain connected to the current- So that the current IM2 '' obtained by mirroring the mirror current IM2 'of the second output transistor M2 is transmitted to the current-voltage conversion unit 14. [

The current-to-voltage conversion unit 14 converts the mirror current received from the current selection unit 13 into a voltage signal to be fed back to the driving voltage generation unit 1. The current-to-voltage converting unit 14 includes an NMOS transistor M7 which combines a drain and a gate to receive a mirror current transmitted from the current selecting unit 13 and a source connected to a ground voltage GND. Thus, a voltage corresponding to the mirror current is generated in the drain of M7.

The filter unit 15 is provided between the current-voltage conversion unit 14 and the driving voltage generation unit 1 to smooth the voltage of the drain of M7 constituting the current-voltage conversion unit 14 to generate a negative feedback voltage (Vc) and applies it to the gate of the second input transistor (M9) of the driving voltage generating section (1). This is because the output current of the output unit 2 changes according to the input signal and the mirror current also changes, so that it is smoothed and negative feedback is performed to a constant voltage.

The operation of the present invention configured as described above will be described with reference to FIG.

3 is a signal waveform graph in the case where the input current Iin of sin waveform is applied to the driving voltage generator 1. Fig.

The LOW level driving voltage Va and the HIGH level driving voltage Vb are in the HIGH state because the 0 to t1 section, the t2 to T3 section and the t4 to T5 section are the HIGH level periods of the input current Iin. The HIGH level drive voltage Vb reflecting the HIGH level signal of the first output transistor M1 is varied in accordance with the input current Iin of this section and the LOW level drive voltage Va varies the first output transistor M1 in the non- A state in which a bias current, which is a current, can flow).

That is, the output current IM2 flows to the second output transistor M2 by the HIGH level drive voltage Vb which varies according to the HIGH level waveform of the input current Iin. The output current IM2 at this time is a pull current which absorbs the current from the load, and the output voltage Vout becomes an inverted waveform when compared with the input current.

On the other hand, since the first output transistor M1 is in the non-operating state, only the current corresponding to the bias current flows. At this time, since the current IM1 of the first output transistor M1 is smaller than the current IM2 of the second output transistor, the selection voltage Vd becomes the ground voltage GND and the transistor M11 is turned on, The mirror current IM1 'of the first output transistor M1 obtained by mirroring with the M14 of the current mirror circuit 11 is supplied to the current-voltage conversion section 14. [

the low level driving voltage Va and the high level driving voltage Vb are in the LOW state while the t1 to t2 and t3 to t4 sections are the LOW level periods of the input current Iin. The LOW level drive voltage Va varies in accordance with the input current Iin in this interval and the HIGH level drive voltage Vb changes the second output transistor M2 in the non-operation state A state in which the in-bias current can flow).

That is, the output current IM1 flows to the first output transistor Ml by the LOW level drive voltage Va that varies according to the LOW level waveform of the input current Iin. The output current IM1 at this time is a push (PUSH) current for supplying a current to the load.

On the other hand, since the second output transistor M2 is in the non-operating state and only the current corresponding to the bias current smaller than the current flowing in the first output transistor IM1 flows, the selection voltage Vd becomes the HIGH level power supply voltage M10 is turned on. Accordingly, the mirror current IM2 'of the second output transistor M2 obtained by mirroring with M3 of the current mirror unit 11 is mirrored by M5 that flows through M4 and M10 and mirrors the current of M4, And supplied to the current-to-voltage conversion unit 14 with a current IM2 ''.

Since the voltage corresponding to the bias current of the output current is negatively fed to the entire input current Iin as described above, the negative feedback voltage Vc, which is fed back to the driving voltage generator 1, is stably fed without ripple And the bias current is stabilized. Then, the negative feedback voltage Vc is further stabilized by the filter section 15. [ Thus, the distortion of the output current can be minimized.

As described above, according to the present invention, the first output transistor M1 and the second output transistor M2 are alternately operated according to the level (i.e., size) of the input current Iin to output in a push- 1 which does not completely turn off the output transistor in the operating state but flows a slight current (i.e., bias current) but negatively feeds back the output current only when the second output transistor M2 is not in operation It is possible to suppress the ripple of the negative feedback voltage Vc and stabilize the bias current by negatively feeding the output current even during the non-operation of the first output transistor Ml as compared with the prior art, Can be output without amplification.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, . &Lt; / RTI &gt; Accordingly, such modifications are deemed to be within the scope of the present invention, and the scope of the present invention should be determined by the following claims.

1: driving voltage generating unit 2: output unit
3: bias circuit part 3-1: current mirror part
3-2: bias current generating unit 3-3: current-voltage converting unit
4: Input stage
10: bias circuit part 11: current mirror part
12: current comparison unit 13: current selection unit
14: current-voltage conversion unit 15: filter unit
M1: first output transistor M2: second output transistor
M8: first input transistor M9: second input transistor
Va: LOW level driving voltage Vb: HIGH level driving voltage
Vc: negative feedback voltage Vd: selection voltage
Vref: Reference voltage
VDD: HIGH level power supply voltage GND: LOW level power supply voltage (ground voltage)

Claims (7)

The first output transistor and the second output transistor are connected in a push-pull manner between the HIGH level power supply voltage and the LOW level power supply voltage and alternately operated according to the driving voltage applied to each gate to output the output signal An output unit 2 for outputting;
A voltage corresponding to the bias current is negatively fed back by using the current of the output transistor that is not in the first output transistor and the second output transistor as the bias current so that the HIGH level driving voltage biased with respect to the HIGH level of the input signal, A driving voltage generator (1) for generating a LOW level driving voltage biased with respect to a LOW level and applying the same to the gates of the first output transistor and the gates of the second output transistor in a one-to-one manner to operate alternately;
A bias circuit unit 10 for generating a negative feedback voltage corresponding to a bias current of the non-operating output transistor and transmitting the generated negative feedback voltage to the driving voltage generating unit 1;
And a second input terminal connected to the second input terminal,
The bias circuit unit (10)
A current mirror unit 11 for mirroring currents of the first and second output transistors, respectively;
A current comparator (12) for comparing the currents of the first and second output transistors to select an inactive output transistor;
A current selector (13) for selecting a mirror current of the output transistor selected by the current comparator (12); And
A current-to-voltage converter 14 for converting the selected mirror current into a voltage signal and negative feedback to the driving voltage generator 1;
And a second input terminal connected to the second input terminal of the second amplifier. The method according to claim 1,
The driving voltage generator (1)
A first input transistor for applying a predetermined reference voltage to the gate and a drain voltage for the LOW level driving voltage, and a second input transistor for applying a negative feedback voltage to the gate and a drain voltage to a HIGH level driving voltage, And a current source is provided between each of the drains and the HIGH level power supply voltage, and an input current is commonly applied to the source. The class AB amplifier maintains a stable bias. 3. The method of claim 2,
The first output transistor and the second output transistor of the output section 2 are connected in a push-pull manner between a preset high level power supply voltage and a ground voltage, with the LOW level power supply voltage of the power supply voltage being a ground voltage A class AB amplifier that maintains a stable bias characteristic of the Harmonic. 4. The method according to any one of claims 1 to 3,
The current comparator (12)
A PMOS transistor having a source connected to a HIGH level power supply voltage and a gate connected to a LOW level driving voltage, an NMOS transistor having a source connected to a LOW level power supply voltage and a gate connected to a HIGH level driving voltage,
The drains of the two transistors are connected to each other to select the selected voltage, and when the selected voltage becomes the HIGH level power supply voltage, the second output transistor is selected as the inactive transistor. When the selected voltage becomes the LOW level power supply voltage, A class AB amplifier that maintains a stable bias, characterized by selecting non-operating output transistors. 5. The method of claim 4,
The current selector (13)
A transistor that is turned on when a HIGH level power supply voltage is applied to the gate and causes the mirror current of the second output transistor to flow to the current-voltage conversion unit 14; And a transistor for causing the mirror current of the transistor to flow to the current-to-voltage conversion section (14). By applying the selection voltage to the gates of both transistors, one of the transistors is operated by the selection voltage, To the current-to-voltage conversion unit (14). 5. The method of claim 4,
The current selector (13)
And when the mirror current of the output transistor to be pulled out from the load is transferred among the first and second output transistors, the mirror current is mirrored again and transferred to the current-to-voltage converter (14). Class AB amplifier. The method of claim 3,
And a filter unit (15) for smoothing the negative feedback voltage between the current-voltage conversion unit (14) and the driving voltage generation unit (1).

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