WO2012137670A1

WO2012137670A1 - Load current detection circuit

Info

Publication number: WO2012137670A1
Application number: PCT/JP2012/058455
Authority: WO
Inventors: 明宏中原; 相馬　治
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2011-04-05
Filing date: 2012-03-29
Publication date: 2012-10-11
Also published as: JP5666694B2; JPWO2012137670A1

Abstract

Provided is a technique for accurately detecting a load current even when the load current falls rapidly or the like. A load current detection circuit is equipped with: a load current generation circuit for generating a load current; a sense current generation circuit for generating an initial sense current; a sense current control circuit for changing the initial sense current according to a fluctuation in the load current; and a compensation current generation circuit for causing a compensation current for compensating the amount of change in the initial sense current to be supplied to an output node. The initial sense current includes a first current supplied to a first input port, and a second current supplied to a power supply port of a resistance element. The compensation current generation circuit supplies a current in the same amount as the first current to the output node as a compensation current.

Description

Load current detection circuit

The present invention relates to a current detection circuit, and more particularly to a load current detection circuit for detecting a load current flowing in the load circuit.

2. Description of the Related Art A technique for monitoring a current flowing through a load (hereinafter referred to as a load current) and determining a load state based on a change in the load current is known (see, for example, Patent Documents 1 and 2). FIG. 1 is a circuit diagram showing a configuration of a current detection circuit described in Patent Document 1. In FIG. The current detection circuit described in Patent Document 1 includes a power field-effect semiconductor component 101 for detecting a load current and another field-effect semiconductor component 102. The drain terminals and gate terminals of both

semiconductor components

101 and 102 are connected to each other. A resistor 105 is connected in series to the source terminal of the semiconductor component 102 via a controllable resistor 106. The other terminal of the resistor 105 is connected to a fixed voltage. By the action of the resistor 106, the drain-source voltages of the

semiconductor components

101 and 102 are adjusted to be equal.

Patent Document 2 discloses a technique for significantly reducing power loss associated with current detection, performing current detection constantly, and detecting current stably and with high accuracy. FIG. 2 is a circuit diagram showing a configuration of the current detection circuit described in Patent Document 2. As shown in FIG. In the technique disclosed in Patent Document 2, the power transistor 211 and the current detection transistor 212 are commonly supplied with the power supply voltage Vcc and the switch signal S1. A buffer circuit 200 is provided so that an idling current Iidl is supplied to the output node of the current detection transistor 212, and the output voltages of both transistors are virtually the same voltage. Thus, the buffer circuit 200 is always operated as a class A amplifier circuit.

JP-A-8-334534 JP 2005-249518 A

The circuits shown in FIGS. 1 and 2 are generally called high-side switches, and supply current to a load connected to the GND side via a switch connected to the power supply side. In such a high-side switch, a plurality of loads may be driven by one switch. The current detection circuit detects the disconnection state of the plurality of loads by detecting the load current. When the load connected to the switch is disconnected, the load current decreases rapidly. Even in such a case, a technique for accurately detecting the load current is required.

In Patent Documents 1 and 2, as a method for detecting a load current, a small transistor (semiconductor component 102 or current detection) having a similar structure to an output MOSFET (power semiconductor component 101 or power transistor 211) for driving a load is disclosed. A technique for connecting the transistor 212) in parallel with the output MOSFET is disclosed. In the techniques described in Patent Documents 1 and 2, when the load current is small, the accuracy of detecting the load current may be reduced. The present invention provides a technique for accurately detecting a load current even when the load current decreases rapidly.

The load current detection circuit is provided between the power supply and the load circuit, and is arranged in parallel with the load current generation circuit for generating the load current to be supplied to the load circuit in response to the control signal, and for controlling the load current generation circuit. A sense current generation circuit that generates an initial sense current in response to a signal, a sense current control circuit that monitors a change in the load current and changes the initial sense current in response to the change in the load current, and a load current fluctuation An output node that receives a current for detection; a sense resistor that converts a current flowing into the output node into a voltage; and a compensation current generation circuit that supplies a compensation current that compensates for a change in the initial sense current to the output node. To do.
Here, the sense current control circuit generates a resistance element provided between the output terminal of the sense current generation circuit and the output node, and a resistance value control signal for controlling the resistance value of the resistance element. With a bowl. The computing unit includes a first input terminal connected to the output terminal of the sense current generation circuit and a second input terminal connected to the output terminal of the load current generation circuit. The initial sense current includes a first current supplied to the first input terminal and a second current supplied to the power supply terminal of the resistive element, and the compensation current generation circuit has the same amount as the first current. Current is supplied to the output node as a compensation current.

In the present invention, it is possible to detect the load current with high accuracy even when the load current rapidly decreases.

FIG. 1 is a circuit diagram showing a configuration of a current detection circuit described in Patent Document 1. In FIG. FIG. 2 is a circuit diagram showing a configuration of the current detection circuit described in Patent Document 2. As shown in FIG. FIG. 3 is a block diagram illustrating a configuration when the load current detection circuit 10 of the present embodiment is applied to an electronic control system of an automobile. FIG. 4 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the first embodiment. FIG. 5 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the first embodiment. FIG. 6 is a circuit diagram illustrating the configuration of a load current detection circuit of a comparative example. FIG. 7 is a graph showing the ratio between the load current and the sense current (sense ratio). FIG. 8 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the second embodiment. FIG. 9 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the third embodiment. FIG. 10 is a circuit diagram illustrating the configuration of the constant voltage circuit 57. FIG. 11 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the fourth embodiment.

Description of embodiment

Hereinafter, embodiments will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

[First Embodiment]
FIG. 3 is a block diagram illustrating a configuration when the load current detection circuit 10 of the present embodiment is applied to an electronic control system of an automobile. The electronic control system includes an electronic control unit 1, a battery power source 3, and a load circuit 2 including a plurality of loads. The load circuit 2 includes, for example, a load circuit 2-1, a load circuit 2-2, and a load circuit 2-n. The electronic control unit 1 includes a power semiconductor device 4, a power supply IC 5, a microcomputer 6, a stabilization capacitor 7 a, a stabilization capacitor 7 b, and a Zener diode 8. The stabilization capacitor 7a stabilizes between the power supply terminal VDD and the GND terminal. The zener diode 8 clamps the voltage against the dump surge.

As shown in FIG. 3, the electronic control unit 1 is connected to a battery power source 3 provided outside thereof. The battery power supply 3 supplies a power supply voltage to the power supply IC 5 and the power semiconductor device 4 of the electronic control unit 1. The power supply IC 5 creates a stabilized voltage based on the voltage supplied from the battery power supply 3 and supplies the power supply voltage to the microcomputer 6. A stabilization capacitor 7b is connected between the output terminal of the power supply IC 5 and the GND terminal. The power semiconductor device 4 is connected to a microcomputer 6. In addition, a load circuit 2-1, a load circuit 2-2, and a load circuit 2-n are connected to the output terminal OUT of the power semiconductor device 4. The power semiconductor device 4 is controlled to be turned on / off in response to an input signal IN from the microcomputer 6, and supplies power to the load circuit 2-1, load circuit 2-2,... Load circuit 2-n. To control.

Further, the power semiconductor device 4 includes a load current detection circuit 10. The load current detection circuit 10 causes a sense current proportional to the current flowing through the load circuit 2-1, the load circuit 2-2, and the load circuit 2-n to flow through the IS terminal. The sense resistor 9 connected to the IS terminal converts the sense current into a sense voltage. The voltage is input to the A / D converter of the microcomputer 6. The microcomputer 6 can determine the magnitude of the load current by reading the voltage at the IS terminal.

For example, if at least one of the load circuit 2-1, the load circuit 2-2,..., The load circuit 2-n is disconnected, the current output to the IS terminal decreases, and the IS voltage accordingly decreases. The microcomputer 6 can determine the disconnection of the load circuit 2-1, the load circuit 2-2,..., The load circuit 2-n according to the change in the IS voltage. The microcomputer 6 can notify the user of the disconnection.

Load circuit 2-1, load circuit 2-2... When the load circuit 2-n is a low power load, the current flowing through each is small. For example, a case where the load circuit 2-1, the load circuit 2-2,..., The load circuit 2-n are all 5 W lamps and are driven by a battery voltage of 12V will be described below. In this case, each steady current is about 0.4A. Further, in a normal state where all loads are connected, 1.2 A (= 0.4 A × 3) is obtained. If one load is disconnected, it becomes 0.8A. Moreover, it will be set to 0.4 A when two are disconnected. Therefore, the electronic control unit 1 needs to detect a low current. The load current detection circuit 10 mounted on the electronic control unit 1 of this embodiment has improved detection accuracy for low load current. Therefore, it is possible to accurately detect whether one load is disconnected or whether two loads are disconnected.

FIG. 4 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the present embodiment. The load current detection circuit 10 includes an output MOSFET 11 as a load current generation circuit, a sense MOSFET 12 as a sense current generation circuit, a sense current control circuit 13, a sense resistor 14 (corresponding to the sense resistor 9), and a compensation current supply circuit. 15. The sense current control circuit 13 includes a P-channel MOSFET 21 as a resistive element, an operational amplifier 22 as an arithmetic unit, a level shift circuit 23, and a level shift circuit 24. The level shift circuit 23 is provided with a diode 25 and a sense current side current source 26. The level shift circuit 24 is provided with a diode 27 and a load current side current source 28. The compensation current supply circuit 15 includes a compensation current side current source 31, a P-channel MOSFET 32, and a control terminal 33.

The drain of the output MOSFET 11 is connected to the power supply terminal 16, and the source of the output MOSFET 11 is connected to a fixed voltage (for example, GND) via the load (load circuit) 2. The source of the output MOSFET 11 is connected to the anode of the diode 27 via the node N3. The gate of the output MOSFET 11 is connected to the gate of the sense MOSFET 12. The gate of the output MOSFET 11 is connected to the gate control terminal 18 via the resistor 19.

The drain of the sense MOSFET 12 is connected to the power supply terminal 16, and the source of the sense MOSFET 12 is connected to the anode of the diode 25 via the node N4. The source of the sense MOSFET 12 is connected to the source of the P-channel MOSFET 21 through the node N4.

The cathode of the diode 25 is connected to one end of the sense current side current source 26. The cathode of the diode 27 is connected to one end of the load current side current source 28. The other end of the current source (sense current side current source 26, load current side current source 28) is connected to a fixed voltage. Further, the cathode of the diode 25 is connected to the inverting input terminal of the operational amplifier 22, and the cathode of the diode 27 is connected to the non-inverting input terminal of the operational amplifier 22. The circuit constituted by the diode 25, the sense current side current source 26, the diode 27, and the load current side current source 28 provides a function as a level shift circuit for appropriately setting the input terminal voltage of the operational amplifier 22. ing. The output terminal of the operational amplifier 22 is connected to the gate of the P-channel MOSFET 21.

The drain of the P-channel MOSFET 21 is connected to the output node N1 through the connection node N2. A sense resistor 14 is connected between the output node N1 and the fixed voltage (ground terminal 17). The source of the P-channel MOSFET 32 is connected to the power supply terminal 16. The drain of the P-channel MOSFET 32 is connected to one end of the compensation current side current source 31. The gate of the P-channel MOSFET 32 is connected to the control terminal 33. The other end of the compensation current side current source 31 is connected to the output node N1 via the connection node N2. In the load current detection circuit 10 of the present embodiment, the same current value is set for the compensation current side current source 31, the sense current side current source 26, and the load current side current source 28.

A control signal is supplied to the gate terminal 18 from a booster circuit (not shown) such as a charge pump. The control terminal 33 is supplied with a low level / high level signal from a control circuit (not shown). When a low level signal is input to the gate terminal 18, the output MOSFET 11 is off and power is not supplied to the load circuit 2. At this time, a high level signal is supplied to the control terminal 33, and the compensation current side current source 31 does not output a current to the output node N1. Also, no current flows through the sense MOSFET 12. Therefore, no sense current is output from the sense MOSFET 12 to the output node N1.

When a high level signal is input to the gate terminal 18, the output MOSFET 11 and the sense MOSFET 12 are turned on. Thereby, the load current is supplied to the load circuit 2 via the node N3. Further, a current flows through the sense MOSFET 12, the diode 25, the P-channel MOSFET 21, and the sense resistor 14. The sense current control circuit 13 includes a level shift circuit 23 including a diode 25 and a sense current side current source 26, and a level shift circuit 24 including a diode 27 and a load current side current source 28. Is provided. The level shift circuit supplies, as an inverting input of the operational amplifier 22, a voltage that is lower than the source of the sense MOSFET 12 by the forward voltage (VF) of the diode 25. Further, a voltage that is reduced by the forward voltage (VF) of the diode 27 from the source of the output MOSFET 11 is supplied as a non-inverting input of the operational amplifier 22.

Here, it is assumed that the drain-source voltage in the sense MOSFET 12 is larger than the drain-source voltage of the output MOSFET 11. In that case, a voltage for controlling the P-channel MOSFET 21 to a higher resistance is supplied to the input terminal of the operational amplifier 22. The current through the sense MOSFET 12 is adjusted until the difference between the input voltages to the input terminal of the operational amplifier 22 becomes zero, that is, the drain-source voltages of the output MOSFET 11 and the sense MOSFET 12 are equal. This means that a current that is always fixedly proportional to the load current flows through the sense resistor 14 in a regulated and steady state regardless of the load size of the load circuit 2. That is, when the load current changes during the operation, for example, due to a partial short circuit or due to a failure of any of the loads connected in parallel, the drain-source voltage in the output MOSFET 11 increases or decreases, In accordance with the change, the resistance value of the P-channel MOSFET 21 is controlled to decrease or increase, and the voltage difference at the input terminal of the operational amplifier 22 becomes zero.

A precondition for the proportionality between the current through the output MOSFET 11 and the current through the sense MOSFET 12 is that the Id-Vds characteristic curves of the respective MOSFETs are similar to each other. The current passing through the sense MOSFET 12 as the initial sense current Isense is proportional to the current flowing through the output MOSFET 11. The sense resistor 14 converts the current passing through the sense MOSFET 12 into a voltage proportional to the load current with reference to the ground point (ground terminal 17). This voltage is taken from the output node N1. Similarity between the output MOSFET 11 and the sense MOSFET 12 can be easily achieved by configuring the output MOSFET 11 and the sense MOSFET 12 using unit cells having the same structure. By setting the ratio of the number of cells of the sense MOSFET 12 and the number of cells of the output MOSFET 11 to, for example, 1: 1000, a sense current corresponding to the ratio of the number of cells can be obtained.

Here, let us consider the phenomenon in which the load current decreases due to the disconnection of the load. At this time, the current passing through the output MOSFET 11 decreases. As a result, the current through the sense MOSFET 12 also decreases. Of the current passing through the sense MOSFET 12 (initial sense current Isense), the first current I1 flows to the sense current side current source 26, and a large error is caused in the current (second current I2) output to the sense terminal (output node N1). There was to give.

First current I1 = 10 μA from the sense current side current source 26,
Fourth current I4 = 10 μA by the load current side current source 28,
Output MOSFET 11 current = 0.1 A,
When the current of the sense MOSFET 12 = 0.1 A / 1000 = 0.1 mA,
Load current (fifth current I5) = (current Iout flowing in the output MOSFET 11) − (fourth current I4 of the load current side current source 28) ≈0.1 A
Current flowing into the P-channel MOSFET 21 (second current I2) = (current Isense flowing in the sense MOSFET 12) − (first current I1 of the sense current side current source 26) = 90 μA.

The load current detection circuit 10 of the present embodiment includes a compensation current supply circuit 15, and the compensation current supply circuit 15 supplies (compensates) the current (10 μA) of the compensation current side current source 31 to the output node N1. is doing. for that reason,
Sense current = (current Isense flowing in the sense MOSFET 12) − (first current I1 of the sense current side current source 26) + (third current I3 of the compensation current side current source 31) = 100 μA = current flowing in the sense MOSFET 12 (initial sense) Current Isense)
It becomes. That is, the third current of the compensation current side current source 31 is equal to the first current I1 of the sense current side current source 26, and compensates for a change caused by the first current I1 of the sense current side current source 26.

FIG. 5 is a circuit diagram illustrating a specific circuit configuration of the load current detection circuit 10 of the present embodiment. In the following, in order to facilitate understanding of the present invention, a configuration and operation different from the load current detection circuit 10 of FIG. 4 will be described in detail. Further, in the circuit diagram illustrated in FIG. 5, the same members as those of the circuit illustrated in FIG. 4 are denoted by the same reference numerals in principle, and repeated description thereof is omitted.

In the load current detection circuit 10 shown in FIG. 5, the sense current side current source 26, the load current side current source 28, and the compensation current side current source 31 are constituted by a depletion type MOSFET. The depletion type N-channel MOSFET 26 a corresponds to the sense current side current source 26. The depletion type N-channel MOSFET 28 a corresponds to the load current side current source 28. The depletion type N-channel MOSFET 31 a corresponds to the compensation current side current source 31. The load current detection circuit 10 includes a diode 41, a diode 42, a diode 43, a resistor 44, and a capacitor 45.

The diode 41 is disposed between the power supply terminal 16 and the inverting input terminal of the operational amplifier 22. The diode 42 is disposed between the power supply terminal 16 and the non-inverting input terminal of the operational amplifier 22. The anode of the diode 43 is connected to the node N4, and the cathode is connected to the node N3. The resistor 44 is connected between the output terminal of the operational amplifier 22 and the gate of the P-channel MOSFET 21. One end of the capacitor 45 is connected to the gate of the P-channel MOSFET 21 and the other end is connected to the ground line.

The drain of the depletion type N-channel MOSFET 28 a is connected to the cathode of the diode 27. The drain of the depletion type N-channel MOSFET 26 a is connected to the cathode of the diode 25. The source and gate of the depletion type N-channel MOSFET 28a and the source and gate of the depletion type N-channel MOSFET 26a are each connected to a fixed voltage (GND). The depletion type N-channel MOSFET 31a has a drain connected to the power supply terminal 16 via the P-channel MOSFET 32, and a gate and a source connected to the output node N1 via the connection node N2.

In the load current detection circuit 10 of the present embodiment, as shown in FIG. 5, the sense current side current source 26, the load current side current source 28, and the compensation current side current source 31 are constituted by depletion type MOSFETs. . The depletion type N-channel MOSFET 26a, the depletion type N-channel MOSFET 28a, and the depletion type N-channel MOSFET 31a each operate as a transistor exhibiting constant current characteristics. Therefore, by making each transistor size the same, the constant current values can be made equal.

The sense current in the load current detection circuit 10 of FIG. 5 is a current as shown by the following equation.
Sense current = (current flowing in the sense MOSFET 12) − (current of the depletion type N-channel MOSFET 26a) + (current of the depletion type N-channel MOSFET 31a) = current flowing in the sense MOSFET 12, and the load current is similar to the circuit illustrated in FIG. The detection accuracy can be improved.

FIG. 5 discloses a specific circuit configuration for realizing the load current detection circuit 10. Similar to the load current detection circuit 10 illustrated in FIG. 4, an error in the sense current is canceled by adding the same amount of current as the sense current shunted to the level shift circuit to the output node N1 via the connection node N2. It is possible. As a result, the sense ratio (the ratio between the load current and the sense current) can be improved over the low load current region.

[Comparative Example] FIG. 6 is a circuit diagram showing a comparative example of this embodiment. The load current detection circuit 310 is a circuit when the above-described load current detection circuit 10 is not provided with the compensation current supply circuit 15. Referring to FIG. 6, the load current detection circuit 310 includes a power supply terminal 316, a gate terminal 318, an output node N301, an output MOSFET (load current generation circuit) 311, a sense MOSFET (sense current generation circuit) 312, a load resistor 302, and a sense. A resistor 314, a diode 341, a diode 342, a diode 325, a diode 327, a diode 343, a current source 326, a current source 328, an operational amplifier (arithmetic unit) 322, a P-channel MOSFET 321, a resistor 319, a resistor 344, and a capacitor 345 are provided. . The connection of each element of the load current detection circuit 310 is the same as that of the load current detection circuit 10 described above.

Here, the operation of the load current detection circuit 310 will be briefly described. When a low level signal is input to the gate terminal 318, the output MOSFET 311 is off and no power is supplied to the load resistor 302. When a high level signal is input to the gate terminal 318, the output MOSFET 311 is on and power is supplied from the power supply terminal 316 to the load resistor 302.

The output MOSFET 311 and the sense MOSFET 312 are connected in parallel, and the operational amplifier 322 controls the resistance of the P-channel MOSFET 321 so that the source voltages of the output MOSFET 311 and the sense MOSFET 312 are equal. As a result, a current (sense current) proportional to the load is output to the output node N301. The sense resistor 314 converts the sense current into a sense voltage. The microcomputer 6 can determine the current flowing through the load by reading the sense voltage.

Since the source voltage of the output MOSFET 311 is close to the voltage of the power supply terminal 316 in the ON state, the input terminal of the operational amplifier 322 passes through a level shift circuit composed of a diode 325, a diode 327, a current source 326, and a current source 328. The source of the output MOSFET 311 and the source of the sense MOSFET 312 are connected.

When the current flowing through the output MOSFET 311 is small, the sense current flowing through the sense MOSFET 312 is also reduced proportionally. At this time, part of the sense current flows to the current source 326 constituting the level shift circuit, so that the sense current output to the output node N301 decreases. The load current flowing through the load is similarly reduced by the current source 328. However, the effect is small compared to the sense current. For example,
Current source 326 = 10 μA,
Current source 328 = 10 μA,
Output MOSFET 311 current = 0.1 A,
If the current of the sense MOSFET 312 = 0.1 A / 1000 = 0.1 mA,
Load current = (current flowing in the output MOSFET 311) − (current of the current source 328) ≈0.1 A
Sense current = (current flowing in sense MOSFET 312− (current of current source 326)) = 90 μA.

FIG. 7 is a graph showing the ratio of the load current to the sense current (sense ratio) with the load current as a parameter. When the load current is plotted on the horizontal axis and the sense ratio (load current / sense current) is plotted on the vertical axis, the dotted line 47 in FIG. 7 indicates the ratio of the load current to the sense current (sense ratio) of the load current detection circuit 310. Represents. In the case of the configuration like the load current detection circuit 310, the sense current becomes small at a low load current, and the sense ratio increases. For this reason, the load current detection accuracy deteriorates.

In the load current detection circuit 10 of the present embodiment, a change in the sense current due to the shunt can be compensated by supplying the output node N1 with the same amount of current as the shunt to the level shift circuit. As a result, the load current detection accuracy can be improved over the low load current region. A solid line 46 in FIG. 7 is a graph showing a ratio (sense ratio) between the load current and the sense current of the load current detection circuit 10 described above. As shown in FIG. 7, the load current detection circuit 10 can obtain a constant sense ratio up to a low load current. That is, highly accurate current detection can be performed.

[Second Embodiment]
The second embodiment will be described below. FIG. 8 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the second embodiment. In the following embodiments, in order to facilitate understanding, configurations and operations different from the load current detection circuit 10 of the first embodiment will be described in detail. In the circuit diagram illustrated in FIG. 8, the same members of the circuit illustrated in the first embodiment are denoted by the same reference numerals in principle, and the repeated description thereof is omitted.

Referring to FIG. 8, in the load current detection circuit 10 of the second embodiment, the sense current side current source 26 and the load current side current source 28 are enhanced MOSFETs (enhancement type N channel MOSFET 26b, enhancement type N channel MOSFET 28b). It consists of The configuration shown in the load current detection circuit 10 of FIG. 8 is superior in matching of the constant current characteristics than the constant current source of the first embodiment, and can detect the load current with higher accuracy.

As described above, in the load current detection circuit 10 of the second embodiment, the N-channel MOSFET 26b and the N-channel MOSFET 28b are enhancement type. As shown in FIG. 8, the drain of the enhancement type N-channel MOSFET 26 b is connected to the cathode of the diode 25, and the drain of the enhancement type N-channel MOSFET 28 b is connected to the cathode of the diode 27. Further, the sources of the enhancement type N-channel MOSFET 26b and the enhancement type N-channel MOSFET 28b are respectively connected to a fixed voltage.

The gates of the enhancement type N-channel MOSFET 26b and the enhancement type N-channel MOSFET 28b are connected to the bias circuit 15a. The bias circuit 15 a includes an N channel transistor 51 and an N channel transistor 55. The bias circuit 15 a includes a P channel MOSFET 32, a P channel transistor 52, a P channel transistor 53, and a P channel transistor 54. The drain and gate of the N channel transistor 51 are connected in common to the gate of the enhancement type N channel MOSFET 26b and the gate of the enhancement type N channel MOSFET 28b. Thereby, the bias circuit 15a biases the gate of the enhancement type N-channel MOSFET 26b and the gate of the enhancement type N-channel MOSFET 28b. The drain and gate of the N channel transistor 51 are connected to the drain of the P channel transistor 52.

The P channel transistor 52 is connected to the power supply terminal 16 via the P channel MOSFET 32. The gate of the P channel transistor 52 is connected to the gate of the P channel transistor 53. The gate of the P channel transistor 52 is connected to the drain of the N channel transistor 55.

The source of the P channel transistor 54 is connected to the power supply terminal 16. The N-channel transistor 55 is supplied with a fixed voltage at its gate and source. In the present embodiment, the N-channel transistor 55 is a depletion type, exhibits a constant current characteristic by this connection, and provides a function as a current source.

The P channel transistor 54 and the P channel transistor 52 constitute a current mirror. The current mirror causes the constant current of the N channel transistor 55 to flow through the N channel transistor 51. The N-channel transistor 51, the enhancement type N-channel MOSFET 26b, and the enhancement type N-channel MOSFET 28b constitute a current mirror. The current mirror causes a current of the same amount as that of the N-channel transistor 51 to flow through the enhancement-type N-channel MOSFET 26b and the enhancement-type N-channel MOSFET 28b. That is, a constant current determined by the N-channel transistor 55 flows through the N-channel transistor 51, the enhancement-type N-channel MOSFET 26b, and the enhancement-type N-channel MOSFET 28b.

A P-channel transistor 53 is further connected between the P-channel MOSFET 32 and the output node N1. The source of the P channel transistor 53 is connected to the drain of the P channel MOSFET 32. The drain of the P-channel transistor 53 is connected to the output node N1. The gate of the P channel transistor 53 is connected to the gate of the P channel transistor 54.

As described above, the P channel transistor 54 and the P channel transistor 53 constitute a current mirror. Therefore, the same current as the constant current flowing through the N channel transistor 55 flows through the P channel transistor 53. That is, the constant current of the N channel transistor 55 is added at the output node N1. From the above, the sense current is
Sense current = (current flowing through the sense MOSFET 12) − (current of the enhancement type N-channel MOSFET 26b) + (current of the P-channel transistor 53) = current flowing through the sense MOSFET 12, and is the same as the load current detection circuit 10 of the first embodiment. , Load current detection accuracy is improved.

As described above, the method of configuring the constant current source with the current mirror configuration has better relative accuracy than using the depletion type current source. A method of making a constant current circuit using a current mirror circuit using an enhancement type N-channel MOSFET 26b and an enhancement type N-channel MOSFET 28b constituted by enhancement type transistors is higher than obtaining a constant current using a depletion type N-channel transistor. Accurate constant current characteristics can be obtained. Therefore, more accurate load current detection can be performed as compared with the load current detection circuit 10 illustrated in FIG.

[Third Embodiment]
The third embodiment of the present invention will be described below. FIG. 9 is a circuit diagram illustrating the configuration of the load current detection circuit 10 according to the third embodiment of the invention. In the following embodiments, in order to facilitate understanding of the present invention, configurations and operations different from the load current detection circuit 10 of the first and second embodiments will be described in detail. In the circuit diagram illustrated in FIG. 9, the same members of the circuits illustrated in the first and second embodiments described above are denoted by the same reference numerals in principle, and repeated description thereof is omitted.

The compensation current supply circuit 15b of the load current detection circuit 10 according to the third embodiment further includes P for the bias circuit 15a (compensation current supply circuit 15) of the load current detection circuit 10 (FIG. 8) according to the second embodiment. A channel transistor 56 and a constant voltage circuit 57 are provided. The sources of the N channel transistor 55, the N channel transistor 51, the enhancement type N channel MOSFET 26b, and the enhancement type N channel MOSFET 28b are connected to the output of the constant voltage circuit 57. In the configuration of the load current detection circuit 10 of the third embodiment, the matching of the constant current characteristics is superior to that of the constant current source of the second embodiment, and more accurate load current detection is possible.

In the following, in order to clarify the difference from the second embodiment and facilitate understanding, explanations other than the changed parts will be omitted. In the following description, the drain of the P channel transistor 53 is referred to as a node Na, the output of the constant voltage circuit 57 is referred to as a node Nb, and the drain of the P channel transistor 52 is referred to as a node Nc.

As shown in FIG. 9, the constant voltage circuit 57 is connected between the power supply voltage terminal 16 and the fixed voltage terminal (GND), and outputs a constant voltage between them to the node Nb. In the present embodiment, it is assumed that the constant voltage circuit 57 outputs a voltage of VBB-6V (the voltage of the power supply terminal 16 is VBB) to the node Nb.

FIG. 10 is a circuit diagram illustrating the configuration of the constant voltage circuit 57. 10 has a Zener diode 61, an N channel transistor 62, an N channel transistor 63, a P channel transistor 64, a power supply terminal 16, and a fixed voltage (ground) terminal 17. The cathode of the Zener diode 61 is connected to the power supply voltage terminal 16. The anode of the Zener diode 61 is connected to the drain of the N-channel transistor 62. In the constant voltage circuit 57 of the load current detection circuit 10 of the third embodiment, it is assumed that the Zener diode 61 has a breakdown voltage of 6V.

The N channel transistor 62 serves as a current source that determines the operating current of the Zener diode 61. In the constant voltage circuit 57 of the load current detection circuit 10 of the third embodiment, the N-channel transistor 62 is a depletion type, and the drain, source, and gate are respectively connected to the anode of the Zener diode 61, the fixed voltage, and the fixed voltage. Used as a current source.

The N-channel transistor 63 serves as a pull-up element for the node Nb that is the output of the constant voltage circuit 57. In the constant voltage circuit 57 of the load current detection circuit 10 of the third embodiment, the N-channel transistor 63 is a depletion type. The drain of the N channel transistor 63 is connected to the power supply terminal 16. The source of the N channel transistor 63 is connected to the node Nb. The gate of the N channel transistor 63 is connected to the node Nb. The N channel transistor 63 is used as a constant current source.

The P channel transistor 64 is an enhancement type and serves as an output buffer for the node Nb. The drain of the P-channel transistor 64 is connected to a fixed voltage (ground terminal 17). The source of the P channel transistor 64 is connected to the node Nb. The gate of the P channel transistor 64 is connected to the anode of the Zener diode 61.

The voltage of 6V as viewed from the power supply terminal 16 is output to the anode of the Zener diode 61. Assuming that the threshold voltage of the P-channel transistor 64 is Vtp2 and the voltage of the power supply terminal 16 is VBB, a voltage of VBB-6V + Vtp2 is output to the node Nb.

In the load current detection circuit 10 (FIG. 9) of the second embodiment described above, the drain of the P-channel transistor 53 is connected to the output node N1. In the load current detection circuit 10 of the third embodiment, a P-channel transistor 56 is connected between the P-channel transistor 53 and the output node N1. The source of the P channel transistor 56 is connected to the node Na. The drain of the P-channel transistor 56 is connected to the output node N1. The gate of the P channel transistor 56 is connected to the node Nb.

In the second embodiment described above, the sources of the N-channel transistor 55, the N-channel transistor 51, the enhancement-type N-channel MOSFET 26b, and the enhancement-type N-channel MOSFET 28b are connected to a fixed voltage (substantially the GND voltage). It was. In the load current detection circuit 10 of the third embodiment, the sources of the N-channel transistor 55, the N-channel transistor 51, the enhancement type N-channel MOSFET 26b, and the enhancement type N-channel MOSFET 28b are connected to the output (node Nb) of the constant voltage circuit 57. It is connected.

Furthermore, in the second embodiment, the P-channel transistor 54 and the P-channel transistor 53 constitute a current mirror. If the channel modulation effect of the P-channel transistor 54 and the P-channel transistor 53 constituting the current mirror is large, the current mirror accuracy is deteriorated. The channel modulation effect is the slope of the saturation current with respect to the drain-source voltage.

In the second embodiment, when the load current is small, the drain voltage of the P-channel transistor 53 decreases to near a fixed voltage. Therefore, the channel modulation effect of the P channel transistor 54 and the P channel transistor 53 constituting the current mirror is increased, and the accuracy of the current mirror of the P channel transistor 54 and the P channel transistor 53 may be deteriorated.

In contrast, in the load current detection circuit 10 of the third embodiment, the P-channel transistor 56 operates as a source follower. Therefore, the voltage at node Na is about node Nb + Vtp (Vtp: threshold voltage of P channel transistor 56). That is, the drain (node Na) of the P-channel transistor 53 does not drop greatly to the fixed voltage side. The voltage of the drain (node Nc) of the P-channel transistor 52 is about node Nb + Vtn (Vtn: threshold voltage of the N-channel transistor 51). Therefore, when Vtp and Vtn are substantially equal, the node Na and the node Nc have substantially the same voltage. As a result, the currents flowing through the P channel transistor 53 and the P channel transistor 52 have substantially the same value.

Therefore, the current of the current source (enhancement type N-channel MOSFET 26b) of the level shift circuit is
The current of the current source of the level shift circuit = the current of the N-channel transistor 51 = the current of the P-channel transistor 53, and the current of the P-channel transistor 53 is equal to the current of the P-channel transistor 52. Therefore, the current of the current source of the level shift circuit is added at the output node N1. Therefore, the current sense ratio is improved.

[Fourth Embodiment]
The fourth embodiment will be described below. FIG. 11 is a circuit diagram illustrating the configuration of the load current detection circuit 10 of the fourth embodiment. In the following embodiments, in order to facilitate understanding, configurations and operations different from the load current detection circuit 10 of the first to third embodiments will be described in detail. Also, in the circuit diagram illustrated in FIG. 11, the same members as those of the circuits illustrated in the first to third embodiments are denoted by the same reference numerals in principle, and the repetitive description thereof is omitted.

The compensation current supply circuit 15c of the load current detection circuit 10 of the fourth embodiment further includes an operational amplifier 58 in addition to the compensation current supply circuit 15b of the load current detection circuit 10 (FIG. 9) of the third embodiment. Further, the load current detection circuit 10 of the fourth embodiment is different from the third embodiment in the connection of the P-channel transistor 56. The load current detection circuit 10 of the fourth embodiment is superior to the constant current characteristic matching of the constant current source of the third embodiment, and can detect a load current with higher accuracy.

Referring to FIG. 11, the operational amplifier 58 has a non-inverting terminal and an inverting terminal connected to the node Nc and the node Nb, respectively. The output terminal of the operational amplifier 58 is connected to the gate of the P channel transistor 56. The operational amplifier 58 controls the resistance value of the P-channel transistor 56 so that the voltages at the node Na and the node Nc are equal.

When (the voltage of the node Na> the voltage of the node Nc), since the low level signal is applied to the gate of the P channel transistor 56, the P channel transistor 56 becomes more conductive and lowers the voltage of the node Na. . Conversely, when (the voltage at the node Na <the voltage at the node Nc), a high level signal is applied to the gate of the P-channel transistor 56, so that the P-channel transistor 56 becomes more non-conductive and the node Na Increase the voltage. Such a feedback operation works, and the node Na and the node Nc are kept at the same voltage.

As a result, the drain-source voltage of the P-channel transistor 53 is equal to the drain-source voltage of the P-channel transistor 52, and a highly accurate current mirror characteristic can be obtained. That is, as for the currents of the P-channel transistor 53 and the P-channel transistor 52, an equal current that is more matched than the load current detection circuit 10 of the third embodiment flows. Therefore, the current of the current source (enhancement type N-channel MOSFET 26b) of the level shift circuit is
The current of the current source of the level shift circuit = the current of the N-channel transistor 51 = the current of the P-channel transistor 53, and the current of the P-channel transistor 53 is equal to the current of the P-channel transistor 52. At the output node N1, the current of the current source of the level shift circuit is added, and the current sense ratio is improved.

The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

This application claims priority based on Japanese Patent Application No. 2011-083450 filed on Apr. 5, 2011, the entire disclosure of which is incorporated herein.

Claims

A load current generating circuit provided between a power supply and a load circuit, generating a load current in response to a control signal and supplying the load current to the load circuit;
A sense current generating circuit provided in parallel to the load current generating circuit and generating an initial sense current in response to the control signal; and the initial sense current includes a first current and a second current; Current is supplied to the output node,
A sense current control circuit that changes the first current in response to a change in the load current;
A compensation current generating circuit connected to the power supply and supplying a current having the same value as the second current to the output node as a compensation current;
A load current detection circuit comprising: a sense resistor that converts a sum of the first current supplied to the output node and the compensation current into a voltage.
The load current detection circuit according to claim 1,
The compensation current generation circuit includes:
A switch,
A compensation current side current source for supplying the compensation current to the output node when the switch is turned on;
The sense current control circuit includes:
A series combination of a first diode and a sense current side current source connected to the sense current generation circuit;
A resistive element provided between the sense current generating circuit and the output node;
A first input terminal; a second input terminal connected to the load current generation circuit; and an arithmetic unit that controls a resistance value of the resistive element. The first diode, the sense current side current source, The node between is connected to the first input terminal,
The compensation current side current source is:
A load current detection circuit in which the same current value as that of the sense current side current source is set.
The load current detection circuit according to claim 2,
The compensation current side current source is:
A load current detection circuit that is arranged between the switch and the output node and supplies the compensation current to the output node.
In the load current detection circuit according to claim 2 or 3,
The sense current control circuit further includes:
A series connection of a second diode and a load circuit side current source connected to the load current generation circuit;
A node between the second diode and the load circuit side current source is connected to the second input terminal,
The load circuit side current source is:
A load current detection circuit in which the same current value as that of the compensation current side current source is set.
The load current detection circuit according to claim 4,
Each of the sense current side current source and the compensation current side current source includes a depletion type transistor of the same size. Load current detection circuit.
The load current detection circuit according to claim 4,
Each of the sense current side current source and the compensation current side current source includes an enhancement type transistor of the same size and connected in a current mirror. Load current detection circuit.
In the load current detection circuit according to any one of claims 1 to 6,
The sense current generation circuit includes:
A load current detection circuit that generates a current proportional to a current flowing through the load current generation circuit as the initial sense current.