TWI351019B - Methods for transferring frame data, and for transferring image data and timing control modules - Google Patents

Methods for transferring frame data, and for transferring image data and timing control modules

Info

Publication number
TWI351019B
TWI351019B TW096101740A TW96101740A TWI351019B TW I351019 B TWI351019 B TW I351019B TW 096101740 A TW096101740 A TW 096101740A TW 96101740 A TW96101740 A TW 96101740A TW I351019 B TWI351019 B TW I351019B
Authority
TW
Taiwan
Prior art keywords
transferring
methods
timing control
control modules
image data
Prior art date
Application number
TW096101740A
Other languages
English (en)
Other versions
TW200729150A (en
Inventor
Huan Hsin Li
Yu Hsi Ho
Yao Jen Hsieh
Original Assignee
Au Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Au Optronics Corp filed Critical Au Optronics Corp
Publication of TW200729150A publication Critical patent/TW200729150A/zh
Application granted granted Critical
Publication of TWI351019B publication Critical patent/TWI351019B/zh

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/16Determination of a pixel data signal depending on the signal applied in the previous frame
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00Parallel handling of streams of display data
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/123Frame memory handling using interleaving
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00Aspects of the architecture of display systems
    • G09G2360/12Frame memory handling
    • G09G2360/128Frame memory using a Synchronous Dynamic RAM [SDRAM]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Dram (AREA)
TW096101740A 2006-01-18 2007-01-17 Methods for transferring frame data, and for transferring image data and timing control modules TWI351019B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76012606P 2006-01-18 2006-01-18
US11/644,214 US20070165015A1 (en) 2006-01-18 2006-12-22 Efficient use of synchronous dynamic random access memory

Publications (2)

Publication Number Publication Date
TW200729150A TW200729150A (en) 2007-08-01
TWI351019B true TWI351019B (en) 2011-10-21

Family

ID=38701045

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096101740A TWI351019B (en) 2006-01-18 2007-01-17 Methods for transferring frame data, and for transferring image data and timing control modules

Country Status (4)

Country Link
US (1) US20070165015A1 (zh)
JP (1) JP2007213055A (zh)
CN (1) CN100446084C (zh)
TW (1) TWI351019B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109410828A (zh) * 2018-11-29 2019-03-01 宗仁科技(平潭)有限公司 Led点光源驱动方法、系统及控制器

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008009227A (ja) * 2006-06-30 2008-01-17 Toshiba Corp 画像データ出力装置及び液晶表示装置
US8384832B2 (en) * 2009-12-29 2013-02-26 Intersil Americas Inc. Systems and methods for partitioned color, double rate video transfer
US8310885B2 (en) 2010-04-28 2012-11-13 International Business Machines Corporation Measuring SDRAM control signal timing
CN101964171B (zh) * 2010-09-16 2013-05-22 深圳市明微电子股份有限公司 一种数据传输方法
TWI740705B (zh) 2020-11-05 2021-09-21 友達光電股份有限公司 顯示裝置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3948141B2 (ja) * 1998-09-24 2007-07-25 富士通株式会社 半導体記憶装置及びその制御方法
JP2002091823A (ja) * 2000-09-19 2002-03-29 Victor Co Of Japan Ltd 画像表示装置に使用されるメモリ制御装置
US6795079B2 (en) * 2001-02-15 2004-09-21 Sony Corporation Two-dimensional buffer pages
US7038691B2 (en) * 2001-02-15 2006-05-02 Sony Corporation Two-dimensional buffer pages using memory bank alternation
US6791557B2 (en) * 2001-02-15 2004-09-14 Sony Corporation Two-dimensional buffer pages using bit-field addressing
US6891545B2 (en) * 2001-11-20 2005-05-10 Koninklijke Philips Electronics N.V. Color burst queue for a shared memory controller in a color sequential display system
JP3945328B2 (ja) * 2002-07-12 2007-07-18 ソニー株式会社 画像処理装置及び画像処理方法
JP4719429B2 (ja) * 2003-06-27 2011-07-06 株式会社 日立ディスプレイズ 表示装置の駆動方法及び表示装置
JP2005049665A (ja) * 2003-07-30 2005-02-24 Nec Plasma Display Corp 映像信号処理回路、表示装置及びその映像信号処理方法
US20050052386A1 (en) * 2003-08-28 2005-03-10 Su-Hyun Kwon Method of processing image signals for improved image quality
KR20050050885A (ko) * 2003-11-26 2005-06-01 삼성전자주식회사 신호 처리 장치 및 방법
US7525548B2 (en) * 2005-11-04 2009-04-28 Nvidia Corporation Video processing with multiple graphical processing units

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109410828A (zh) * 2018-11-29 2019-03-01 宗仁科技(平潭)有限公司 Led点光源驱动方法、系统及控制器

Also Published As

Publication number Publication date
TW200729150A (en) 2007-08-01
US20070165015A1 (en) 2007-07-19
CN101013567A (zh) 2007-08-08
CN100446084C (zh) 2008-12-24
JP2007213055A (ja) 2007-08-23

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees