TWI350582B - High current semiconductor power device soic package - Google Patents

High current semiconductor power device soic package

Info

Publication number
TWI350582B
TWI350582B TW096135002A TW96135002A TWI350582B TW I350582 B TWI350582 B TW I350582B TW 096135002 A TW096135002 A TW 096135002A TW 96135002 A TW96135002 A TW 96135002A TW I350582 B TWI350582 B TW I350582B
Authority
TW
Taiwan
Prior art keywords
power device
high current
semiconductor power
current semiconductor
soic package
Prior art date
Application number
TW096135002A
Other languages
English (en)
Other versions
TW200818438A (en
Inventor
Sun Ming
Zhang Xiaotian
Shi Lei
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/544,453 external-priority patent/US7759775B2/en
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW200818438A publication Critical patent/TW200818438A/zh
Application granted granted Critical
Publication of TWI350582B publication Critical patent/TWI350582B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
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    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
TW096135002A 2006-10-06 2007-09-19 High current semiconductor power device soic package TWI350582B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/544,453 US7759775B2 (en) 2004-07-20 2006-10-06 High current semiconductor power device SOIC package

Publications (2)

Publication Number Publication Date
TW200818438A TW200818438A (en) 2008-04-16
TWI350582B true TWI350582B (en) 2011-10-11

Family

ID=39422986

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096135002A TWI350582B (en) 2006-10-06 2007-09-19 High current semiconductor power device soic package

Country Status (3)

Country Link
CN (2) CN101174602B (zh)
HK (1) HK1115937A1 (zh)
TW (1) TWI350582B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9041170B2 (en) * 2013-04-02 2015-05-26 Infineon Technologies Austria Ag Multi-level semiconductor package
JP6325975B2 (ja) * 2014-12-19 2018-05-16 新光電気工業株式会社 リードフレーム、半導体装置
DE102015101674B4 (de) 2015-02-05 2021-04-29 Infineon Technologies Austria Ag Halbleiterchipgehäuse mit Kontaktstiften an kurzen Seitenrändern
US10325878B2 (en) * 2016-06-30 2019-06-18 Kulicke And Soffa Industries, Inc. Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
CN109727943A (zh) * 2019-02-27 2019-05-07 无锡新洁能股份有限公司 一种具有低热阻的半导体器件封装结构及其制造方法
CN110164832A (zh) * 2019-05-31 2019-08-23 无锡电基集成科技有限公司 大电流半导体功率器件
CN110164831A (zh) * 2019-05-31 2019-08-23 无锡电基集成科技有限公司 利于焊接的大电流半导体功率器件及其制造方法
CN215266282U (zh) * 2021-04-14 2021-12-21 苏州汇川技术有限公司 一种功率半导体器件的封装结构

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114750A (en) * 1996-10-01 2000-09-05 International Rectifier Corp. Surface mount TO-220 package and process for the manufacture thereof

Also Published As

Publication number Publication date
HK1115937A1 (en) 2008-12-12
CN101794760A (zh) 2010-08-04
CN101794760B (zh) 2012-05-23
CN101174602B (zh) 2011-10-05
CN101174602A (zh) 2008-05-07
TW200818438A (en) 2008-04-16

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