TWI345295B - Chip stacked package structure and applications thereof - Google Patents

Chip stacked package structure and applications thereof Download PDF

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Publication number
TWI345295B
TWI345295B TW96115393A TW96115393A TWI345295B TW I345295 B TWI345295 B TW I345295B TW 96115393 A TW96115393 A TW 96115393A TW 96115393 A TW96115393 A TW 96115393A TW I345295 B TWI345295 B TW I345295B
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substrate
wafer
package structure
active surface
stacked package
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TW96115393A
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TW200843078A (en
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Chun Ying Lin
Yu Tang Pan
Shih Wen Chou
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Chipmos Technology Inc
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Priority to TW96115393A priority Critical patent/TWI345295B/zh
Priority to US11/872,205 priority patent/US7696629B2/en
Publication of TW200843078A publication Critical patent/TW200843078A/zh
Priority to US12/713,333 priority patent/US20100155929A1/en
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Publication of TWI345295B publication Critical patent/TWI345295B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

1345295 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體封裝結構，且特別是有關於 一種堆疊封裝結構。 【先前技術】 隨著電子產品功能與應用之需求的急遽增加，封裝技術 亦朝著高密度微小化、單晶片封裝到多晶片封裝、二維尺度 到三維尺度的方向發展。其中系統化封裝技術（System In Package)係一種可整合不同電路功能晶片的較佳方法，利用 表面黏著（Surface Mount Technology ; SMT)製程將不同的晶 片堆疊整合於同一基板上，藉以有效縮減封裝面積。具有體 積小、高頻、高速、生產週期短與低成本之優點。 請參照第4圖，第4圖係根據一習知的晶片堆疊封裝結 構400所繪示的結構剖面圖。晶片堆疊封裝結構400包括基 板410、第一晶片420、第二晶片430以及複數條打線440 和450。其中第一晶片420固設於基材410上，並藉由打線 440與基材410電性連接。第二晶片430堆疊於第一晶片420 上，且藉由打線450與基板410電性連接。 然而，由於疊設於上層的晶片，例如第二晶片430，必 須遷就下層晶片（第一晶片420)的打線（打線440)配置，因此 上層晶片（第二晶片430)尺寸必須小於下層晶片。因此也限制 了晶片堆疊的數量與彈性。又因為上層晶片的尺寸較小，必 須延長打450的配線長度並擴大其線弧，方能使其與基材410 5 1345295 電性連接。當後續進行壓模製程時，該些被延長的打線容易 受到沖移，而出現短路的現象，影響製程良率。 «月參照第5圖，苐5圖係根據另一種晶片堆疊封裝結構 500所繪示的結構剖面圖。晶片堆疊封裝結構5〇〇包括基板 510、第一晶片520、第二晶片530、複數條打線54〇和55〇 以及位於第一晶片 560。其中第一晶片 520和第二晶片53〇之間的虛擬晶片 520疊5又於基板51〇上，並藉由打線540
使第-銲塾570與基材51〇電性連接;虛擬晶片疊設於第 一晶片520上；第二晶片則疊設於虛擬晶片56〇上，並藉由打 線550使第二銲塾580與基材51〇 t性連接。藉由尺寸小於 第-晶片520的虛擬晶片56〇的設置，不僅可在第一晶片52〇 和第二晶片530之間’提供^夠的佈線㈣與線弧高度，以 容納打線540’而且不會限制上層晶片(第二晶片53〇)的堆疊 尺寸。因此第二晶片53〇之尺寸實質等於第—晶片52〇之尺 寸。
二而虛擬晶片的設置，不僅會增加晶片堆疊的厚度，且 徒增製程成本，更限制了裝結構微小化與高密度的趨勢。 因此有需要提供一種良率古 〜 艮旱间、製程低廉且不會限制封裝 被度的晶片堆疊封裝結構。 【發明内容】 本發明的一目的在提供— #、笛B '、種日日片堆疊封裝結構包括：基 材、第一晶片、圖案化線路 _ 第一日日片以及封膠樹脂。其 第表面與相對的第二表面，且第-晶片位於 6

Claims (1)

  1. 十、申請專利範園： 1. 一種晶片堆疊封裝結構，包括： -基材，該基材具有一第一表面與相對的第二表面； -第-晶片，位於該基材之該第一表面上，該第一晶片 具有-第-主動面與—相對的第—晶背，其中該第一主動面 係面對該基材，並與該基材電性連接； 一圖案化線路層，直接形成於該第一晶背之一表面上， 並藉由至少一打線與該基材電性連結； 一第二晶片，位於該圖案化線路層上，具有一第二主動 面以及配置於該第二主動面上的至少一第二銲墊，其中該第 二主動面與該第-晶背具有相同之—尺寸，且該第二鮮塾與 該圖案化線路層電性連接，再經由該打線與該基材電性連接. 以及 ’ 一封膠樹脂（molding compound)，填充於該基材、該第 晶片、該圖案化線路層及該第二晶片之間。 2.如申請專利範圍第1項所述之堆疊封裝結構，其中該 基材係導線架（Lead Frame)、印刷電路板（priming 士㈣ Board)或晶粒承載器（Carrier)。 3.如申請專利範圍第1項所述之堆疊封裝結構，更包 括：複數個外部連接端子，配置於該基材之該第二表面。 4‘如申請專利範圍第3項所述之堆疊封襞結構，其中該 丄 有複數個第—銲塾’並由複數個凸塊，將該些 、墊固者並電性連接於該基材。 -底5膠^?請專利範圍第4項所述之堆疊封I結構，更包括 …匕覆於《凸塊，並將該第—晶片 定於該基材之上。 #主動面固 Α材6呈右如申請專利範圍第1項所述之堆疊封裝結構，其中該 =具有一貫穿開口’將該第-晶片之部分第-主動面暴露 凸塊，將該 .巾請專利_第6項所述之堆疊封裝結構，立中該 第一主動面具有複數個第一鮮墊，並藉由複數個 些第一銲墊固著並電性連接於該基材。 8.如申請專利範圍第7項所述之堆疊封裝結構，更包括 一底膠包覆於該些凸塊，並將該第—主動面固^於該基材。 9·如申請專職圍第8項所狀堆疊封裝 -臟片配置於該第一主動面上，並經由該貫穿開： 延伸。 10·如申請專利範圍第6項所述之堆疊封褒結構，其中 該第-主動面具有複數個第—銲墊，並藉由穿過該貫穿開口 19 [2010军11月i ο曰修正替換頁丨 的至少一打線電性連接至該基材。 U.如申請專利範圍第6項所述之堆疊封裝結構，更包 括一散熱鳍片配置於該第一主動面上，並經由該貫穿開口向 外延伸。 =12.如申請專利範圍第丨項所述之堆疊封裝結構，其中 該圖案化線路層係—重佈線路層（RediStribUti〇n-Layer， …專利範圍第1項所述之堆疊封裝結構，其中 該乂此第包括複數條導線，且每—該些導線之一端與 背之邊緣延伸之-者匹配並電性連接H難該第一晶 如中請專利範圍第！項所述之堆疊封裝結 一k些第二銲墊係藉由一 八 線路層電性連接。 ㉜衣次》電凸塊與該圖案化 面 处日日日片堆疊封裝結構的製造方法，. 基材’縣材具有―卜表面與相對的第 表 於該基材之第一表面配置一第一 對該基材的一第一主 日曰 吏該第一晶片面 主動面與該基材電性連接； 20 1345295 函月10日修正替換頁丨 於該第一晶片相對於該第一主動面的一第一晶背上，直 接形成-圖案化線路層於該第-晶背之一表面上:曰其中該圖 案化線路層包括至少-導線’與欲堆疊於該圖案化線路層上 的一第二晶片之至少一第二銲墊電性匹配； 形成至少-打線’藉以f性連結該圖案化線路層與該其 材； 、/土 於該圖案化線路層上配置該第二晶片，並使該第二鲜塾 電性連接至該導線，再經由該打線與該基材電性連接，其令 該第二晶片之-第二主動面與該第一晶背具有相同之二 寸；以及 使用一封膠體封裝該基材、該第一日 層及該第二晶片。 “、該圖案化線路 16·如中料職Μ 15韻収堆㈣裝結構的製 造方法，其巾該提供該基材之步驟，包括：於該基材 表面’配置複數個外部連接端子。 一 、17.如申請專利範圍第15項所述之堆疊封_ 方法’其中於該基材上配置該第—晶片之步驟包括：& 形成複數個凸塊，將位於該第_主動面之複數 墊’電性連接於該基材；以及 卸 採用—底膠包覆於該些凸塊。 18.如巾請專·圍第15項所述之堆疊㈣結構的製 21 1345295 扭替換頁I 造方法，其中提供該基材之步驟更包括：於該基材中形成一 貫穿開口’用以將一部分的該第一主動面暴露出來。 止19.如申請專利範圍第18項所述之堆疊封裝結構的製 造方法，其中於該基材上配置該第一晶片之步驟包括： 形成複數個凸塊，將位於該第一主動面之複數個第一銲 塾’電性連接於該基材；以及 採用一底膠包覆於該些凸塊。 2〇.如申請專利範圍第 造方法，更包括：於該第一 由該貫穿開口向外延伸。 19項所述之堆疊封裝結構的製 主動面上配置-散軸片，並經
    诰太、土 好丄 ’、”丨心〜$豐封裝結構 法，其中於該基材上配置該第一晶 日日6之步驟包括： 將該第一晶片固設於該基材之第一 篦一士么 表面’並使位於該 第-主動面之複數個第一銲墊，由 以及 Λ貝牙開口暴露出來； 在至一第一銲墊上形成至少—打線 ’以電性連接至該基材。 穿過該貫穿開
    22.如申請專利範圍第 造方法，更包括：於該第一 由該貫穿開口向外延伸。 18項所述之堆疊封裝結構的製 主動面上配置-散熱鰭片，並經 22
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