TW200843078A - Chip stacked package structure and applications thereof - Google Patents

Abstract

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned conductive layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip having a first active surface and an opposite first back surface is electrically connected to the first surface of the substrate serving as a flip chip. The patterned conductive layer set on the first back surface is electrically connected to the substrate via a bonding wire. The second chip set on the patterned conductive layer has a plurality of second pads formed on a second active surface thereof and eclectically connected to the patterned conductive layer.

Description

200843078 IX. Description of the Invention: [Technical Field] The present invention is (iv) a semiconductor package structure, and particularly relates to a stacked package structure. [Prior Art] With the rapid increase in the demand for electronic product functions and applications, packaging technology is also moving toward high-density miniaturization, single-chip packaging to multi-chip packaging, and two-dimensional scale production to three-dimensional scale. The systemized packaging technology (s:em two package) is a preferred method for integrating different circuit function chips, and the surface mount technology (SMT) process is used to integrate different wafer stacks on the same substrate, thereby effectively reducing the number of wafers. Package area. It has the advantages of small volume, high frequency, high speed, short production cycle and low cost. 4 is a cross-sectional view of a structure according to a conventional wafer stack package structure 400. The wafer stack package structure 4 includes a substrate 410, a first wafer 420, a second wafer 43A, and a plurality of wires 44. The first wafer 420 is fixed on the substrate and electrically connected to the substrate 41 by wire bonding 440. The second wafer 43 is stacked on the first wafer 42A and electrically connected to the substrate 410 by the bonding wires 450. However, since the wafer stacked on the upper layer, for example, the second wafer 43A, the wire bonding (wire bonding 44〇) configuration of the lower wafer (first wafer 42A) must be moved, so that the upper wafer (second wafer 430) must be smaller in size than the lower layer. Wafer. This also limits the number and flexibility of the wafer stack. Moreover, because the size of the upper layer wafer is small, it is necessary to extend the wiring length of the 450 and expand the line arc to electrically connect it to the substrate 41〇200843078. When the subsequent molding process is performed, the extended wire is easily subjected to the displacement, and a short circuit occurs, which affects the process yield. The whistle is shown in Figure 5, which is a cross-sectional view of the structure depicted in another wafer stack package structure 500. The wafer stack package structure 5 includes a substrate 510, a first wafer 520, a second wafer 530, and a plurality of wires 540 and 550.

And a dummy wafer 560 between the first wafer 52A and the second wafer 53A. The first wafer 520 is stacked on the substrate 51, and the first pad 570 is electrically connected to the substrate 510 by wire bonding 54; the dummy wafer 56 is stacked on the first wafer 520; the second wafer is The dummy pad 56 is stacked on the dummy wafer 56, and the second pad is connected to the second pad by the 2 550. By the arrangement of the dummy wafer 56A having a size smaller than that of the wafer 520, it is possible to provide not only a sufficient wiring space and a line arc height between the first wafer and the first wafer 53G, but also a size of 53 〇). Therefore, the size of the second wafer 53 is substantially equal to the size of the first wafer. However, the arrangement of the dummy wafer not only increases the thickness of the wafer stack, but also increases the manufacturing cost, and further limits the trend of miniaturization and high density of the package. Therefore, there is a need to provide a wafer stack (four) structure that records g, sets a yield, and has a low process and does not limit the package density. SUMMARY OF THE INVENTION An object of the present invention is to provide a material, a first wafer, a (4) wiring layer, and a package structure including a first surface and a phase = two-day sheet and a sealant resin. a first surface of the first wafer, and the first wafer is located at the first surface of the substrate, and the first wafer has a first active surface and an opposite first crystal first active surface facing the substrate, and is covered with the substrate. The bonding method is electrically connected. The patterned circuit is layered on the back of the button and electrically connected to the substrate by at least _ lines. The second wafer is located on the patterned circuit layer, and has a second main surface and at least one second soldering surface disposed on the second active surface, wherein the second soldering pad is electrically connected to the patterned circuit layer, and then It is electrically secreted with the substrate. The sealant resin is filled on the substrate, the __ wafer, the patterned circuit layer and the second wafer, and finally a plurality of external terminals are formed on the second surface of the substrate. Preferably, the external terminals are, for example, The solder balls are electrically connected to other external circuits by the external terminals. Still another object of the present invention is to provide a wafer stack package structure, the method comprising the steps of: first providing a substrate, wherein the substrate has a first surface and an opposite second surface, the first of the substrates The first wafer is disposed on the surface to electrically connect the first active surface of the first wafer facing the substrate to the substrate in a flip chip manner. Then, a patterned circuit layer is formed on the first crystal back of the first wafer with respect to the first active surface, so that the patterned circuit layer includes at least one wire for the second layer to be stacked above the patterned circuit layer. At least one second pad of the wafer is electrically matched. At least a strip line is formed to electrically connect the patterned wiring layer and the substrate. A second wafer is disposed on the patterned circuit layer, and the second pad is electrically connected to the wire, and then electrically connected to the substrate via the wire. The encapsulant is used to encapsulate the substrate m. The patterned circuit layer and the second wafer are formed, and then a plurality of external terminals are formed on the second surface of the substrate. Preferably, the external terminals are, for example, solder balls. The external terminals are electrically connected to other external circuits. According to the embodiment described above, the technical feature of the present invention is to form a patterned circuit layer on the crystal back of the underlying wafer of the flip chip stack, so that the wiring of the patterned circuit layer and the upper layer stacked thereon are subsequently formed. The pads of the wafer are electrically matched. Then, the upper layer wafer is flip-chip stacked on the patterned circuit layer. By patterning the wiring of the wiring layer, the bonding positions of the pads of the upper wafer are redistributed to be dispersed to the edge of the upper wafer, and the patterned wiring layer is electrically connected to the substrate by wire bonding. Thereby, in the prior art, the problem that the length of the wire bonding wire of the upper layer wafer and the substrate is electrically connected and the wire arc is excessively large is solved. Therefore, the technical advantages provided by the present invention can solve the problem that the conventional wafer stacking structure has a high yield seal and a low package density. [Embodiment] The above and other objects, features, advantages and embodiments of the present invention will become more apparent. Referring to Fig. 1, a first embodiment is a wafer stack package structure according to a first preferred embodiment of the present invention! Schematic diagram of the 〇〇. The cymbal stacking package structure 1 includes a substrate 1 第一 1 , a first wafer 1 , a patterned wiring layer 105 , a second wafer 107 , and a sealant resin 12 . First, a substrate 1 is provided, and the substrate 101 has a first surface 116 and a second surface 117 with respect to the first surface 116. Further, the second surface of the substrate has a plurality of external connection terminals U1. In a preferred embodiment of the invention, the substrate 101 is comprised of a lead frame, a printing drucit board, or a die carrier. In the present embodiment, the base material 200843078 is a printed circuit board made of, for example, a BT or FR4 circuit board or a read circuit board. $ 疋 电路 circuit 116 = the first crystal of the crystal - 1102 is bonded to the first surface of the substrate 101

The second wafer 102 is electrically connected to the substrate by the first active surface 103 facing the substrate 101. In the embodiment, the first wafer 102 further has a blood-first active opposite first crystal back 104, and the first active surface 103 has a plurality of solder pads 115, and by a plurality of bumps 113, These first bead 15 / / substrate 101 are electrically connected. In addition, after the first wafer is overlaid on the substrate ιοί, it further includes coating the bump (1) with a primer, and thereby fixing the first active sl〇3 to the substrate ι〇ι first Surface Μ0 Next, a patterned wiring layer 105 is formed on the crystal back 104 of the first wafer 102, and the patterned wiring layer is still electrically connected to the substrate 101 by at least one bonding wire 1〇6. The patterned circuit layer 1〇5 is a Redistribution-Layer (RDL). And the patterned circuit layer 1〇5 includes a plurality of wires, such as wires 1〇5& and 105b, and one end of each wire (for example, wire l〇5a) is designed to be stacked on the patterned circuit layer 105. One of the second pads 107 of the second wafer 107 is electrically matched, and the other end extends to other positions of the first crystal back 104, for example, to the edge of the first crystal back 1〇4, and then the second The wafer 107 is electrically connected to the patterned wiring layer 105 by flip chip bonding. The second wafer 107 has a second active surface 108 and a second bonding pad 1〇9 disposed on the second active surface 108, wherein each of the second bonding pads 109 is formed by a ball or a conductive bump 11 The wires 200843078 105a or 105b of the circuit layer 1〇5 are electrically connected. In the #杏杏办丨々 a „ ^ 牧 ... in his household, court example, the patterned circuit layer 105 can be used to match the wiring pattern of different wafers to change the wiring pattern. At least one second pad of the second wafer 1G7 Just one of the wires of the patterned wiring layer 105, such as the wire 1, may be fused or secreted, so when the second wafer 107 having the same size as the first wafer 102 and the first wafer H) 2 are stacked on each other, patterning The wire of the circuit layer 1 () 5 can redistribute the second pad 1 〇 9 which is originally close to the center of the second wafer 107 to be dispersed to the

The other positions of the two wafers 107 are, for example, dispersed to the edges of the second crystal, and the second pads 109 are electrically connected to the substrate 1〇1 via the bonding wires 106. Thereafter, the substrate 1〇1, the first wafer 1〇2, the patterned wiring layer 105, and the second wafer 107 are packaged using a sealing resin 12〇, and the sealing resin 12〇 is filled on the substrate 101 and the first wafer. 102. Between the patterned circuit layer 1〇5 and the second wafer 1〇7. Finally, a plurality of external terminals ι are formed on the second surface 117 of the substrate, and the external terminals may preferably be, for example, solder balls. With these external terminals Hi, the wafer stack package structure 100 can be electrically connected to other external circuits. Fig. 2 is a cross-sectional view showing a wafer stack package structure 2'' according to a second preferred embodiment of the present invention. The wafer stack package structure 2 includes a substrate 2〇1, a first wafer 2〇2, a patterned wiring layer 2〇5, a second wafer 2〇, and a sealant resin 22〇. A substrate 201 is first provided having a first surface 218 and a second surface 219 opposite the first surface 218. In a preferred embodiment of the invention, base #201 is preferably constructed of a leadframe, printed circuit board or die carrier. In the present embodiment, the substrate 2〇1 is a die carrier, and the material thereof is, for example, a crucible or an FR4 circuit board or other flexible circuit board. 200843078 Next, a through opening 217 is formed in the substrate 201. The first wafer 202 is then flip-chip bonded to the first surface 218 of the substrate 201, so that the first active surface 203 of the first wafer 202 facing the substrate 201 is electrically connected to the substrate 201. In this embodiment, the first wafer 202 has a first crystal back 204 opposite to the first active surface 203, and the first active surface 203 has a plurality of first pads 215, and the first pads 215 are borrowed. The plurality of bumps 213 are fixed and electrically connected to the first surface 218 of the substrate 201. In addition, in the preferred embodiment of the present invention, the wafer stack package structure 200 further includes a primer 214 for covering the plurality of bumps 213, thereby fixing the first active surface 203 of the first wafer 202 to the substrate. The first surface 218 of 201. Since the substrate 201 has a through opening 217, a portion of the first active surface 203 is exposed through the through opening 217 of the substrate 201. In a preferred embodiment of the present invention, a heat dissipation fin 216 is formed on the first active surface 203 to extend outward through the through opening 217, thereby increasing the heat dissipation effect of the wafer stack package structure 200. . Then, a patterned circuit layer 205 is formed on the first crystal back 204 of the first wafer 202, and is electrically connected to the substrate 201 by at least one wire 206, wherein the patterned circuit layer 205 is a redistributed circuit layer, and The patterned wiring layer 205 includes a plurality of wires, such as wires 205a and 205b, and one end of each wire (e.g., wire 205a) is designed to be used in a second wafer 207 to be stacked on the patterned wiring layer 205. One of the pads 209 is electrically matched, and the other end extends to other locations of the first crystal back 204, for example, to the edge of the first crystal back 204. The second wafer 207 is electrically connected to the patterned layer 11 200843078 via layer 205 in a flip chip bonding manner. The second wafer 207 has a second active surface 208 and a second bonding pad 209 disposed on the second active surface 208. The at least one second bonding pad 209 is formed by solder balls or conductive bumps 210 and the patterned wiring layer 205. The wires 205a or 205b are electrically connected. In other embodiments, the patterned wiring layer 205 can change the wiring pattern in conjunction with the pad configuration of the different wafers. Thereafter, the substrate 201, the first wafer 202, the patterned wiring layer 205, and the second wafer 207 are encapsulated using the encapsulating resin 220, and the encapsulating resin 220 is filled in the substrate 201, the first wafer 202, and the patterned wiring layer 205. And between the second wafer 207. Finally, a plurality of external terminals 211 are formed on the second surface 219 of the substrate 201. These external terminals 211 may preferably be, for example, solder balls. With these external terminals 211, the wafer stack package structure 200 can be electrically connected to other external circuits. Since at least one second pad 209 of the second wafer 207 is electrically matched with one of the wires of the patterned wiring layer 205, such as the wires 205a or 205b, when the second wafer 207 having the same size as the first wafer 202 is When the first wafers 202 are stacked on each other, the wires of the patterned wiring layer 205 can reroute the second pads 209 originally adjacent to the center of the second wafer 207 to be dispersed to other locations of the second wafer 207, for example, to the second. The second pad 209 and the substrate 201 are electrically connected to each other via the wire 206, and the port is electrically connected to the substrate 201. Referring to FIG. 3, the third drawing is drawn according to the third preferred embodiment of the present invention. A cross-sectional view of the wafer stack package structure 300 is shown. The wafer stack package structure 300 includes a substrate 301, a first wafer 302, a patterned wiring layer 305, a second wafer 307, and a sealant resin 320. 12 200843078 A substrate 301 is first provided having a first surface 316 and a second surface 319 opposite the first surface 316. In a preferred embodiment of the invention, substrate 301 is preferably constructed of a leadframe, printed circuit board or die carrier. In the present embodiment, the substrate 3〇1 is a die carrier, such as a 疋BT or FR4 circuit board or other flexible circuit board. A through opening 317 is then formed on the substrate 301. The first wafer 302 is then flip-chip bonded to the first surface 316 of the substrate 3〇1 to make the first wafer.

The first active surface 3〇3 facing the substrate 301 is electrically connected to the substrate 3〇1. In this embodiment, the first wafer 302 further has a first crystal back 304 opposite to the first active surface 3() 3, and a portion of the first active surface 3〇3 is worn by the substrate 3〇. The opening 317 is exposed. The first wafer 3〇2 has a plurality of first fresh slabs 315, and the first active surface is located in a region exposed through the cleavage jaws. The first fresh (four) 5 is electrically connected to the substrate 301 by a wire 318 passing through the through opening 317. Then, a patterned wiring layer 305' is formed on the first crystal back 3〇4 of the first wafer 302 and electrically connected to the substrate 3〇1 by at least one bonding wire 3〇6. The patterned circuit layer 305 is a redistributed circuit layer. And the patterned circuit layer 3〇5 includes a plurality of wires, such as wires 3G5a and ·, and the end of each wire (for example, wire milk a) is judged and (i) is disposed on the patterned circuit layer 305. The second pads of the two wafers 307 are electrically matched, and the other ends extend to other positions of the first crystal back, for example, to the edges of the first crystal backs 3〇4. The second crystal layer 305 is further disposed. The second sheet 307 is electrically connected to the patterned line 3 by flip chip bonding. The second sheet 307 has a second active surface 308 and a second bonding pad 309 disposed on an active surface 308 of the 13200843078, wherein at least one second The solder pads are electrically connected to the wires 3〇5a or 3〇5b of the patterned circuit layer 3〇5 by solder balls or conductive bumps 310. In other embodiments, the patterned wiring layer 305T changes the wiring pattern with a pad configuration that is a different wafer. Thereafter, the base material 3〇1, the first wafer 302, the patterned circuit layer 305, and the first wafer 307 are packaged using a sealant tree 320, and the sealant resin 320 is filled in the substrate 3〇1, the first wafer. 302, between the patterned circuit layer 305 and the second wafer 3〇7. Finally, a plurality of external terminals 3ΐ, which are formed on the second surface 319 of the substrate 301, are formed. F% sub-311 is more affordable, such as tin balls. These external terminals 311 b can be electrically connected to other external circuits by the chip stack package structure 3 . Since at least one second pad 3〇9 of the second wafer 307 is electrically matched with one of the wires of the patterned wiring layer 305, such as the wires 3〇5a or 3〇讣, when having the same with the first wafer 3〇2 When the second wafers 3 of the same size and the first wafers 302 are stacked on each other, the wires of the patterned wiring layer 3〇5 can reroute the second pads 3〇9 originally close to the center of the second wafer 307 to be dispersed to The other locations of the second wafer 307 are, for example, dispersed to the edges of the second wafer, and the second pads 3〇9 are electrically connected to the substrate 3〇1 via the bonding wires 306. Thereby, not only the wire length and the line arc for electrically connecting the upper layer wafer and the substrate are shortened, but also the pad design of different upper layer wafers can be used to change the wiring in the patterned circuit layer to improve the process of the stacked package. elasticity. By eliminating the need for virtual wafers, stack thickness and process cost can be significantly reduced while increasing package density. According to the embodiments described above, the technical feature of the present invention is to form a patterned circuit layer on the crystal back of the underlying wafer of the overlay wafer stack 200843078, so that the wiring of the patterned circuit layer and the upper layer stacked thereon are subsequently formed. The pads of the wafer are matched. Then, the upper wafer is flip-chip stacked on the patterned wiring layer. By patterning the wiring of the wiring layer, the bonding positions of the pads of the upper wafer are redistributed to be dispersed to the edges of the upper wafer, and the patterned wiring layer is electrically connected to the substrate by wire bonding. & Therefore, with the technical advantages provided by the present invention, the problem of low yield seal and low package density of the conventional wafer stacked package structure can be solved. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The above and other objects, features, advantages and embodiments of the present invention will become more apparent. The detailed description of the drawings is as follows:

Fig. 1 is a schematic cross-sectional view showing the first stack of the wafer stack of the first embodiment of the present invention, which is not shown in the example of the first embodiment of the present invention. 2 is a cross-sectional view of a package structure 200 in accordance with a second preferred embodiment of the present invention. Figure 3 is a schematic cross-sectional view of a third stack of package structures 300 in accordance with the present invention. ~ "The wafer stack shown in the column is shown in Figure 4 according to a conventional g-field structure profile. 15 illustrated by the Feng-Fracture Structure 400 2008. 2008.78 Figure 5 is depicted in accordance with another wafer-stack package structure 500 Structural section view.

[Main component symbol description] 100: wafer stack package structure 102: first wafer 104: first crystal back 105a: wire 106: wire 108: second active surface 110: bump 113: bump 115: first pad 117 : Substrate second surface 200 : wafer stack package structure 202 : first wafer 204 : first crystal back 205a · wire 206 : wire 208 : second active surface 210 : bump 213 : bump 215 : first pad 217: through opening 101: substrate 103 • first active surface 105: patterned wiring layer 105b = wire 107: second wafer 109: second pad 111: external connection terminal 114: primer 116: substrate first Surface 120: sealant 201: substrate 203: first active surface 205: patterned wiring layer 205b • wire 207: second wafer 209: second pad 211: external connection terminal 214: primer 216: heat sink fin 218 : substrate first surface 16 200843078

219: second surface 220 of the substrate: 300: wafer stack package structure 301: 302: first wafer 303: 304: first crystal back 305: 305a: wire 305b 306: wire 307: 308: second active surface 309 : 310 : bump 311 · · 313 : bump 314 : 315 : first pad 316 : 317 : through opening 318 : 319 : second surface of the substrate 320 : 400 : wafer stack package structure 410 : 420 : first Wafer 430: 440: wire 450: 510: substrate 520: 530: second wafer 540: 550: wire 560 · · 570 : 塾 580 : sealing resin substrate first active surface patterned circuit layer: wire second wafer Second solder pad external connection terminal primer substrate first surface wire sealing resin substrate second wafer wire first wafer wire virtual wafer worship 17

Claims (1)

200843078 X. Patent Application Range: 1 . A wafer stack package structure comprising: a substrate having a -first surface and an opposite second surface; a first wafer, the first surface of the substrate The first wafer: has a first-active surface and an opposite first crystal back, wherein the first active surface faces the substrate and is electrically connected to the substrate; - patterned circuit layer Forming on the first crystal back, and electrically connecting to the substrate by at least one wire; a second wafer on the patterned circuit layer, having a second active surface: and being disposed in the second At least one second soldering pad on the active surface, wherein the first soldering is electrically connected to the patterned circuit layer, and then electrically connected to the substrate via the bonding wire; and a molding compound is filled Between the substrate, the first wafer, the patterned wiring layer, and the second wafer. 2. The stacked package structure of claim 1, wherein the substrate is a lead frame, a printed circuit board, or a die carrier (CarHer). 3. The stacked package structure of claim 2, further comprising: a plurality of external connection terminals disposed on the second surface of the substrate. 4. The stacked package structure according to claim 3, wherein the first active surface has a plurality of first pads, and the plurality of bumps are fixed, and the 18 200843078 first pads are fixed and electrically Sexually attached to the substrate. 5. If the application package (4) includes the stacked package structure, the method further includes: a primer is applied to the bumps, and the first active surface of the first wafer is fixed on the substrate. 6. The stacked package of claim 1, wherein the substrate has a through opening, and the part of the first active surface of the wafer is exposed. 7. The stacked package structure as described in claim 6 of the patent application, and the main = (four) number of first radiances ' and by a plurality of bumps:: will: Electrically connected to the substrate. 8. The stacked package as described in claim 7 - the primer is coated on the bumps, and the first active surface is fixed and the second active surface is covered by the stack (four). Further, the extension includes: "the sheet is disposed on the active surface of the brother" and is externally arranged through the through opening, and the stacked package structure described in the sixth item is fully occupied. The active-active surface has a plurality of first pads. And at least one dozen of wires are electrically connected to the substrate. ^贝牙开1口<:S 19 200843078 η · The package structure described in claim 6 of the patent application, further comprising: a heat fin disposed on the first active surface and passing through the through opening 2: The stacked package structure as described in claim 4, wherein the patterned circuit layer is a redistributed line I (RediStribution_L:, RDL). J. The stacked package structure as described in item 1 of the patent scope of Zhongqing, the straight middle case, including a plurality of wires, and the ends of each of the wires: the pads are matched and electrically connected, and the other ends Then it extends for the edge. Not 曰曰 14· If you apply for a patent scope 帛! The first crystal back has the same one of the second active surface; The stacked package structure described in each of the materials of the first item, wherein the second electrode is electrically connected by a tin-line layer. The conductive bump and the patterned seed wafer package are packaged. The manufacturing method of the structure includes: · face; the substrate has the first - and the opposite second table 20 200843078 on the first side of the substrate; ^ a _ a material of a m, 'set a brother a wafer for electrically connecting the M-filament surface of the first wafer surface material to the substrate; wherein: the first wafer is formed into a patterned circuit layer with respect to a first crystal back of the first active surface The patterned circuit layer includes at least one wire electrically matched with the solder pad to be stacked on the patterned circuit layer; #一形成 at least-wired' to electrically connect the patterned circuit layer and the substrate 1 arranging the second wafer on the patterned circuit layer, and electrically connecting the second zinc pad to the ground (4), electrically bonding the substrate, and packaging the substrate with a sealant. The first wafer, the patterned wiring layer, and the second wafer. ▲ 17· # The method for manufacturing a stacked package structure as described in the patent application, wherein the step of providing the substrate comprises: arranging a plurality of external connection terminals on the second surface of the substrate. The method for manufacturing a stacked package structure according to Item 16, wherein the step of disposing the first wafer on the substrate comprises: forming a plurality of bumps, and electrically connecting a plurality of first soldering pads on the first active surface And the method of manufacturing the stacked package structure according to claim 16 of the invention, wherein the step of providing the substrate is further improved. The method of manufacturing a stacked package structure according to claim 19, wherein the substrate is formed in the substrate, the through-opening is used to expose a portion of the first active surface. The step of disposing the first wafer includes: forming a plurality of bumps to electrically connect the plurality of first electrodes on the first active surface to the substrate; and coating the substrate with a primer The method of manufacturing the stacked package structure as described in claim 2, further comprising: disposing a heat dissipation fin on the first active surface, and extending outward from the through opening The method for manufacturing a stacked package structure according to claim 19, wherein the step of disposing the first wafer on the substrate comprises: fixing the first wafer to the first of the substrate a surface of the plurality of first pads on the first active surface exposed by the through openings; and forming at least one wire on the at least one first pad, electrically connected through the through opening The substrate of the stacked package structure described in claim 19, further comprising: disposing a heat dissipating fin on the first active surface, and Extend outside. ^ 22