TWI343123B - Vertical nanotube semiconductor device structures and methods of forming the same - Google Patents
Vertical nanotube semiconductor device structures and methods of forming the same Download PDFInfo
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- TWI343123B TWI343123B TW094100109A TW94100109A TWI343123B TW I343123 B TWI343123 B TW I343123B TW 094100109 A TW094100109 A TW 094100109A TW 94100109 A TW94100109 A TW 94100109A TW I343123 B TWI343123 B TW I343123B
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- 239000002071 nanotube Substances 0.000 title claims description 46
- 239000004065 semiconductor Substances 0.000 title claims description 46
- 238000000034 method Methods 0.000 title claims description 31
- 239000004020 conductor Substances 0.000 claims description 30
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- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 19
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
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- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Carbon And Carbon Compounds (AREA)
Description
1343123 玖、發明說明: 【發明所屬之技術領域】 本發明係有關於半導趙元件製造,且特別是關於 合奈米管成為一兀件單元之垂直半導體元件結構(例如 效電晶體及電容器),以及製造該垂直半導體元件結構的 法。 【先前技術】 傳統的場效電晶體(FET)為熟悉的傳統元件,其通巧 結合至積想電路(IC)晶片的複雜電路内,而作為一基^ 構區塊。- IC晶片可容載有數千至數百$的而 及其他像是電阻器及電容器而由各導想線徑所互聯的系 疋件可藉改變在—區隔—源極及_汲極之通道區域户 通道的電阻來操作纟FET。從源極經由該通道而流至分 之載子係正比於該電阻的變異度。電子會負責各η ^ Τ内的通道傳導,而在各P通道FET裡,電洞會負$ 通道内的傳導。FET的輸出電流可藉由將-電壓施加方 位在該源極與兮· 變 ,,'及極間之通道區域上的靜電耦接閘極ί 薄型閘極介電質可將該閘極絕緣於該通道區域< 極電壓的微,]、_ . 變化可造成從該源極流到該汲極之電流ό 大變異度。 FET可分猫^ , 成水平架構及垂直架構。水平FET之i 係以平行於i k 、、形成有該等FET之基材水平面的方向t 極流向汲極。而&丄 ^ 而垂直FET之載子則以垂直於齊上形成a 結 場 方 係 建 以 動 之 極 道 該 改 閘 極 子 源 該 3 等 FET « ll fet 基材垂直面的方向由踝極流向汲極。由於垂 ,通道長度與微影設備及方法所解析之最小特徵尺 :’因此可使垂I FET之通道長度短於水平FETe因 輪出功率。’ 可快迷切換並保有較高之電 ,奈米管係奈米等級之高深究比碳原子柱趙,用於形 :型(hybrid)元件。碳奈米管可因該等導體形式而有效率 一電且因其半導體形式而作為一半導體。&已利用一 —半導體碳奈米管將水平FET製作為一通道區域,並且 , 表面上而延伸於一黃金源極與一黃金汲極間之碳 未管的相對端形成歐姆接觸點…閉極係經界定於位在 :奈求管底之下的基材内,且通常是在該源極與該汲極 ,基材之一乳化曝出表面可於該經復蓋之閘極與該 …’管間界定出-閉極介電質<這種水平FET應可靠地 :於同時由於該碳奈米管之小維度,所耗損之電力應明 嚴”矽基元件。水平FET現已藉由-原子力顯微鏡來操 :-碳奈米管、或從一组散置之奈米管一致地£放一: =的方式在實驗室條件下成功地構建完成。然而, =成這種水平FET元件結構的方法與大量製造技術並 因此’所需者係一種結合一或多個半導體碳奈米管做 道區域且滿足大量製造技術之垂直FET結構。 【發明内容 直 寸 此 源 成 地 單 在 奈 該 之 碳 切 顯 縱 這 不 為 4 1343123 根據本發明之原理,係提出一種垂直半導體元件結構, 其包含一界定出一大致水平平面之基材;一自該基材垂直 地凸出之閘極;以及至少一經過該閘極,而在相對之第〜 與第二端間垂直地延伸的半導體奈米管。一可經置放在至 少一半導體奈米管之上的閘極介電質將該至少一半導體奈 米管電性絕緣於該閘極。一源極係電性麵接於該至少一半 導體奈米管的第一端,而一汲極則是電性耦接於該至少_ 半導體奈米管的第二端。
在本發明另一態樣裡,係提.供一種形成一半導體元件結 構之方法,包含於一基材上形成一導體板,然後成長出至 少一半導體奈米管,此者自該導體板而在一電性耦接於該 導體板之第一端與一第二自由端間大致垂直地延伸。該方 法更包含藉一閘極介電質電性絕緣該至少一半導體奈米 管,並形成一電性絕緣、且疊置在該導體板上之閘極,使 至^半導體奈米管經該閘極而垂直地延伸。一接觸點孫
以電性耦接於該至少一半導體奈米管之第二端且電性絕緣 於該閘極的方式形成。 各半導體奈米管界定出—場效電晶體之一通道區域該 電晶體具有一藉由對該閉極施加一控制電壓而予以調控的 通道#符於本發明原理,該源極與該汲極間之通道區域 的長度是Μ開極之垂直尺寸或厚度所界定,而不受半導 ,,製程裡用以於傳統場效電晶肖内形成通道區域的傳 統微影處理的限制β 根據本發明原理,一半導艘元件結構包含一界定出一大 1343123 致水平平面之基材、—經置放於該基材上之導 板’以及自該第一平板垂直a出之至少一奈米管 米管可具有一導體分子結構或一半導體分子結構 性麵接於該第一平板 '經垂直定位於該第一平板 管上者係第-平& ’此者係藉由-介電層而絕 一平板及該碳奈米管。 在本發明另一態樣中’係提出一種形成一半導 構之方法,其中包含於-基材上形成-導體第一 成長至少一自該第一平板所大致垂直地延伸之夺 者係電性耗接於該第-平板。該方法更包含包繞 管並將該第一平板覆蓋以-介電〗,且形成一疊 -平板上之第二平,此者係藉由該介電層而電 各奈米管及該第一平板。 【實施方式】 本發明係有關於垂直場效電晶體(FET),其係 米管作為半導體材料而為通道區域,當施加一電 電耦接閘極時,可於一源極與一汲極之間提供一 體線徑。根據本發明原g,於該源極與該汲極間 域的長度,是由該閘極之厚度所界定(其大致等於 的長度),且與具解析度限制之微影處理無關。該 不需個別地操控以置放於一源極與一》及極間,且 決一或多個隨機分佈於元件表面上之奈米管是否 源極與汲極。 睹第一乎 ^各個奈 ,且係電 及該奈米 緣於該第 體元件結 爭板,並 米管,此 各個奈米 置於該第 性絕緣於 運用碳奈 壓於一靜 選擇性導 之通道區 該奈米管 碳奈米管 亦無須取 一致對齊 6 見參照於第1圓,-適於幫助該等碳奈米管14成長 =劑材料的催化劑塾〗。在一絕緣基材12之區域上: 、平板10之圖案的一部分。$等碳奈米管14係經定 ::催化劑& 10大致垂直朝上延伸。該絕緣基材12 形成於—晶圓(未圖示)上,該晶圓係由任何適當半導體 料j包含但不限於矽(Si)及坤化鍺(GaAs),所組成者, 上可形成-絕緣基材12,例如矽氧化物。肖催化劑墊 的可藉任何傳統沉積技術將催化材料之毯復層沉積於絕 層12上的方式形成’其包含但不限於利用適當之先趨 (如金屬南化物及金屬羰基物)之化學氣相沉積(CVD)、濺 以及物理氣相沉積(PVD),接著使用一標準微影與負蝕 製程來圖案化該毯覆層。。該催化劑墊内的催化劑材 為任一種在適於促進奈米管成長之化學反應條件下暴露 適當反應劑時可成核並幫助碳奈米管14成長之材料。 如’適當的催化劑材料包含但不限於鐵、鉑、鎳、鈷、 等材料各者的化合物,以及此等材料各者之合金,像是 屬梦化物β 碳奈米管14可藉由任何適當成長或沉積技術而成長 該催化劑墊10上。在一本發明具體實施例中,碳奈米 14是利用任何適當氣態或氣化的碳基反應劑(該等反應 包含但不限於一氧化碳(CO)、乙烯(C2H4)、甲烷(CH4)、 炔(C2H4)、乙炔及氨(NH3)的混合物、乙炔及氮(N2)的混 物、乙炔及氫(H2)的混合物、二甲苯(C6H4(CH3)2)以及二 苯及二茂鐵(Fe(C5H5)2)的混合物),在適合於促進在形成 之 成 位 可 材 其 10 緣 物 鍍 刻 料 於 例 此 金 於 管 劑 乙 合 甲 該 7 1343123
參考。本發明亦涵蓋奈米管14可由除碳外、特徵在於具有 能量間隙與半導體特性之材料所組成。 在此所用之「水平」乙詞係經界定如一與該絕緣基材 12及該底置晶圓之傳統平面或表面相平行的平面無論其 指向為何。該「垂直」係指垂直於即如前定義之水平者。 像是「之上」、「高於」、「底下」、「邊側」(即如側壁)、「高 於」、Γ低於」、「其頂」、「其底」等詞係參照於該水平平面 所定義。 現參照第2圖,一薄型介電層20係完整均勻地沉積於 該催化劑塾10及該絕緣基材12之上。該介電層2〇可利用 四乙氧基矽烷(TEOS)作為矽先趨物來源,藉由一低壓化學 氣相沉積(LPCVD)製程沉積之二氧化矽(Si〇2)所組成。該介 電層20亦石著其各自之高度或長度而塗覆於該等碳奈米 管14之各者的外部。許多除該TEOS基氧化物以外的材料 亦可使用’只要能確保電性隔離即可。各碳奈米管1 4上的 9 1343123 【圊式簡單說明】 本發明原理連同前文之發明說明在參照本說明書及其 附加圖式之各具體實施例後,將可獲得最佳之領會,其中: 第1圖係一具經垂直成長於一經圖案化導體催化劑墊 上之碳奈米管的基材局部之截面視圖。 第2圖係一類似於第1圓而在後績製造階段内的載面視 圖。 • 第3圖係一類似於第2圖而在後續製造階段内的載面視 圖。 第4圖係一類似於第3圖而在後續製造階段内的截面視 圖。 — 第5圖係一類似於第4圖而在後續製造階段内的截面視 圖。 第6圖係一類似於第5圖而在後續製造階段内的載面視 圖。 第7圖係一類似於第6圖而在後續製造階段内的截面視 ^圖。 第8圖係一類似於第7圖而在後續製造階段内的截面視 圖a 第9圖係一根據本發明一替代性具體實施例,類似於第 2圖而在後續製造階段内的截面視圖。 第1 0圖係一類似於第9圖而在後績製造階段内的截面 視圖。 15
Claims (1)
1343123 年月日修正替換頁 mi. 1 9 拾、申請專利範圍: 1. 一種用以形成一半導體元件結構之方法,其至少包含下 列步驟: 於一基材上形成一導體墊;
自該導體墊大致垂直地延伸成長至少一半導體奈米管 於一電性耦接於該導體墊之第一端與一第二自由端之間; 施加一第一絕緣層於該導體墊與該至少一半導體奈米 管上,以致該第一絕緣層之一部分於該至少一半導體奈米 管上界定一閘極介電質; 施加一導體層於該第一絕緣層與該至少一半導體奈米 管上; 圖案化該導體層以形成一閘極,該閘極係藉由該第一絕 緣層而電性絕緣於該導體墊,並以該至少一半導體奈米管 疊置在導體墊上,該至少一半導體奈米管垂直延伸通過該 閘極中之一孔,並藉由該閘極介電質而電性絕緣於該閘 極;以及
形成一接觸點,其係電性耦接於該至少一半導體奈米管 之第二端,且電性絕緣於該閘極。 2.如申請專利範圍第1項所述之方法,其中該電性絕緣於 該至少一半導體奈米管的步驟包含: 將該至少一半導體奈米管包繞於該閘極介電質内。 3.如申請專利範圍第1項所述之方法,其中形成該接觸點 17 1343123 >rm 至少包含下列步驟: 從該至少一半導體奈米管之自由端移除該閘極介電 質;以及 提供一金屬特徵以作為該接觸點。 4. 如申請專利範圍第3項所述之方法,其更包含下列步 驟: 於該閘極上形成一第二絕緣層;以及 φ 縮钱(recessing)該第二絕緣層與該閘極介電質以曝出 該至少一半導體奈米管之自由端。 5. 如申請專利範圍第1項所述之方法,其中該至少一半導 ’ 體奈米管係一碳奈米管,且該導體墊係由一適於成長碳奈 米管之催化劑材料所形成,且成長該至少一半導體奈米管 更包含如下步驟: 在有效將碳原子併入該具一半導體分子結構之碳奈米 管的條件下,將該導體墊曝露於一含碳反應劑。
6. 如申請專利範圍第1項所述之方法,其中成長該至少一 半導體奈米管更包含如下步驟: 藉由一化學氣相沉積技術成長該至少一半導體奈米管。 7. 如申請專利範圍第1項所述之方法,其中該至少一半導 體奈米管之自由端係凸出至一構成該接觸點之金屬内。 18 1343123
8.如申請專利範圍第1項所述之方法,其中該至少一半導 體奈米管特徵在於經排置之碳原子。 9.如申請專利範圍第1項所述之方法,其中該至少一半導 體奈米管界定出一具有一通道之場效電晶體的通道區域, 該通道係由施加於該閘極之一控制電壓所調控。
10.如申請專利範圍第1項所述之方法,其中形成該接觸點 包含: 自該至少一半導體奈米管之第二端部分移除該閘極介 電質以曝露該至少一半導體奈米管之第二端。 11.如申請專利範圍第10項所述之方法,更包含: 提供一金屬特徵以作為該接觸點,該接觸點電性耦接於 該至少一半導體奈米管之第二端。
12.如申請專利範圍第1項所述之方法,其中該至少一半導 體奈米管可界定出一具一通道之場效電晶體的通道區域, 可藉由施加一控制電壓至該閘極來調控流經該通道之電 流。 13. —種用以形成一半導體元件結構之方法,其包含下列 步驟: 19 1343123 替換頁 於一基材上形成一第一導體板; 自該第一導體板大致垂直地延伸成長至少一電性耦接 於該第一導體板之奈米管; 以一介電層覆蓋該至少一奈米管與該第一導體板,以致 該至少一奈米管係包繞於該介電層中且該至少一奈米管之 一前尖端係由該介電層之一部分所覆蓋;及 於該介電層上沉積一導電材料之一毯覆層,該毯覆層藉 由該介電層與該至少一奈米管及該第一導體板電性絕緣。
14.如申請專利範圍第13項所述之方法,其中該至少一奈 米管具有一導體分子結構。 15.如申請專利範圍第13項所述之方法,其中該至少一奈 米管具有一半導體分子結構。 16.如申請專利範圍第13項所述之方法,更包括:
平坦化該毯覆層之導電材料至一高於該至少一碳奈米 管由介電質覆蓋的前尖端之深度。 17.如申請專利範圍第16項所述之方法,更包括: 於該毯覆層之平坦化導電材料上形成一第二導體板。 20 1343123 - -.......... < 正替換頁 第今φ丨扣|。1號專利案丨6畔I月修正 柒、指定代表圖: (一) 、本案指定代表圖為:第1圖。 (二) 、本代表圖之元件代表符號簡單說明: 10 催化劑 墊 12 絕緣基材 14 複奈米 管 16 前尖端 18 接附端 捌、本案若有化學式時,請揭示最能顯示發明 特徵的化學式:
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- 2005-01-03 TW TW094100109A patent/TWI343123B/zh not_active IP Right Cessation
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- 2005-01-13 JP JP2006550156A patent/JP2007520072A/ja active Pending
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CN1914746A (zh) | 2007-02-14 |
US7691720B2 (en) | 2010-04-06 |
RU2342315C2 (ru) | 2008-12-27 |
US20080227264A1 (en) | 2008-09-18 |
TW200527667A (en) | 2005-08-16 |
KR20060127105A (ko) | 2006-12-11 |
US20050167655A1 (en) | 2005-08-04 |
JP2011258969A (ja) | 2011-12-22 |
EP1708960A1 (en) | 2006-10-11 |
RU2006130861A (ru) | 2008-03-10 |
IL177125A0 (en) | 2006-12-10 |
CN100580971C (zh) | 2010-01-13 |
JP5511746B2 (ja) | 2014-06-04 |
WO2005076381A1 (en) | 2005-08-18 |
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