TWI343108B - Structure of integrated active component within substrate and manufacturing method of the same - Google Patents

Structure of integrated active component within substrate and manufacturing method of the same Download PDF

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TWI343108B
TWI343108B TW096105520A TW96105520A TWI343108B TW I343108 B TWI343108 B TW I343108B TW 096105520 A TW096105520 A TW 096105520A TW 96105520 A TW96105520 A TW 96105520A TW I343108 B TWI343108 B TW I343108B
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layer
circuit
circuit layer
dielectric layer
substrate structure
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TW096105520A
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TW200834851A (en
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Chien Hao Wang
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1343108 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種内埋主動晶片基板構造與其製法，尤其 是一種高散熱性之内埋主動晶片基板構造與其製法。 【先前技術】1343108 IX. Description of the Invention: [Technical Field] The present invention relates to a buried active wafer substrate structure and a method for fabricating the same, and more particularly to a high heat dissipation embedded active wafer substrate structure and a method for fabricating the same. [Prior Art]

近年來可揭式電子產品日益普及，例如：筆記型電腦、行 動電話、個人數位助理（pers〇nal Digital Assistant，PDA)與數位 相機等，為了達到消費者對產品外型輕薄短小的要求，電子產 品内之相關組件皆需滿足多功能、尺寸微型化等設計要求。 就電子產品中之晶片封裝體而言，為了滿足電子產品多功 月匕與回速问頻運异的需求，基板上必須增加主動元件的數量， 並且在達到尺寸微型化之要求的同時，亦需具備良好的散熱能 力。如此一來，將使得晶片封裝體中之電路與元件密度增加， 進而導致電磁干擾與雜訊增加，使電子產品可靠度降低。 而習知技術之半導體封裝方法，其半導體晶片係放置在基板 之上1致晶片封裝體的體積大小無法有效縮小，且因半導體晶 曰；η速運二時會產生熱效應等問題’散熱性不佳將導致半導體 =片的可靠度下降。因此，有必要提出—種新穎之半導體晶片封 裝結構與方法以解決上述問題。 【發明内容】 本發明之主要目的在提供-種内埋主動晶片基板結構與 其製造方法’其可提高祕㈣構之料性與料祕板結構 6 1343108 層122，該第二介電層120覆蓋該第一電路層ι16，該第三介電層122覆蓋 該第二電路層118(步驟S214)。 如第II圖，以雷射鑽孔方式分別在該第二介電層12〇與第三介電 層122上形成複數個孔洞124,以暴露出該第一電路層116與該第二電路層 118上之相應電路（步驟S216)。 如第1J圖，在該第二介電層12〇之孔洞丨24中填入金屬以形成—第 -垂直導通層126,該第二垂直導通層126無第—電路層⑽之相應電路 達成電性連接；在該第三介電層122之孔洞124中填入金屬以形成一第三 垂直導通層13G，該第二垂直導通層130與該第二電路層us之相應電路達 成電性連接。接著，形成-第三電路層128於該第二介電層⑽上，該第 三電路層128與該第二垂直導通層126之相應電路達成電性連接；形成— 第四電路層132於該第三介電層122上，該第四電路層132與該第三垂直 導通層13G之相應電路達成電性連接，其中該第三電路層128與第四電路 層132可以電鍍方式形成（步驟S218)。 如第1K圖，形成一銲錫遮罩134覆蓋該第三電路層128與第四電路 層132 ’並暴露出該第三電路層128與第四電路層132之部份電路，且於裸 露之該第三電路層128與第四電路層132之部份電路上設置銲錫136(步驟 S220)。 依據第2圖所示步驟S200至S212及其相關說明，可構成兩 層電路結構’因該半導體晶片已埋人該兩層電路結構之基板中， 相較於先前技藝，其在尺寸上已大幅縮小，且具有良好之散熱效 9 1343108 果。再者，於步驟S216至S218中，亦可以在該第一電路層116 與第三電路層128或該第二電路層128與第四電路層132之間設 置額外之半導體晶片，使本發明之結構更具產業應用之彈性。 本發明確已符合創作專利申請之要件，爰依法提出專利申 請。惟上所述者，僅本發明之較佳實施例而已，當不能以此限定 本發明實施之範圍，故：凡依本發明申請專利範圍及創作說明書 所作之簡單的等效變化與修飾，其皆應仍屬本發明專利涵蓋之範 圍内。 【圖式簡單說明】 第1A至1K圖係依據本發明實施例之内埋晶片基板結構製程示 意圖。 第2圖係本發明之内埋晶片基板結構製程流程圖。 【主要元件符號說明】 100 基板 101 第一金屬層 102 第二金屬層 104 第三金屬層 106 第一垂直導通層 108 半導體晶片 110 電性接點 112 散熱黏著層 1343108 114 第一介電層 116 第一電路層 118 第二電路層 120 第二介電層 122 第三介電層 124 孔洞 126 第二垂直導通層 128 第三電路層 130 第三垂直導通層 132 第四電路層 134 銲錫遮罩 136 銲錫In recent years, the popularity of electronic products has become more and more popular, such as notebook computers, mobile phones, personal digital assistants (PDAs) and digital cameras. In order to meet the requirements of consumers for thin and light products, electronic The relevant components in the product must meet the design requirements of multi-function, size miniaturization. In the case of a chip package in an electronic product, in order to meet the demand for multi-function and reciprocal speed of electronic products, the number of active components must be increased on the substrate, and at the same time as the miniaturization of the size is required, Need to have good heat dissipation. As a result, the density of circuits and components in the chip package is increased, which leads to an increase in electromagnetic interference and noise, which reduces the reliability of the electronic product. In the semiconductor packaging method of the prior art, the semiconductor chip is placed on the substrate, and the size of the chip package cannot be effectively reduced, and the semiconductor wafer is immersed in the semiconductor wafer; Jia will lead to a decrease in the reliability of the semiconductor=sheet. Therefore, it is necessary to propose a novel semiconductor wafer package structure and method to solve the above problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide an embedded active wafer substrate structure and a method for fabricating the same that can improve the material structure of the secret structure and the structure of the material layer 6 1343108, and the second dielectric layer 120 covers The first circuit layer ι16 covers the second circuit layer 118 (step S214). As shown in FIG. 2, a plurality of holes 124 are formed in the second dielectric layer 12 and the third dielectric layer 122 by laser drilling to expose the first circuit layer 116 and the second circuit layer. The corresponding circuit on 118 (step S216). As shown in FIG. 1J, a metal is filled in the hole 24 of the second dielectric layer 12 to form a first vertical conduction layer 126. The second vertical conduction layer 126 has no corresponding circuit of the first circuit layer (10). The metal is filled in the hole 124 of the third dielectric layer 122 to form a third vertical conductive layer 13G. The second vertical conductive layer 130 is electrically connected to the corresponding circuit of the second circuit layer us. Then, a third circuit layer 128 is formed on the second dielectric layer (10), and the third circuit layer 128 is electrically connected to the corresponding circuit of the second vertical conductive layer 126; forming a fourth circuit layer 132. On the third dielectric layer 122, the fourth circuit layer 132 and the corresponding circuit of the third vertical conduction layer 13G are electrically connected, wherein the third circuit layer 128 and the fourth circuit layer 132 can be formed by electroplating (step S218). ). As shown in FIG. 1K, a solder mask 134 is formed to cover the third circuit layer 128 and the fourth circuit layer 132' and expose a portion of the circuit of the third circuit layer 128 and the fourth circuit layer 132, and is exposed. Solder 136 is disposed on a part of the circuits of the third circuit layer 128 and the fourth circuit layer 132 (step S220). According to steps S200 to S212 and related descriptions shown in FIG. 2, a two-layer circuit structure can be formed. In the substrate in which the semiconductor wafer is buried in the two-layer circuit structure, the size is greatly increased compared with the prior art. Reduced, and has a good heat dissipation effect 9 1343108. Furthermore, in steps S216 to S218, an additional semiconductor wafer may be disposed between the first circuit layer 116 and the third circuit layer 128 or the second circuit layer 128 and the fourth circuit layer 132, so that the present invention The structure is more flexible in industrial applications. The invention has indeed met the requirements for the creation of a patent application, and has filed a patent application according to law. The foregoing is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and the equivalent equivalents and modifications made by the scope of the invention and the description of the invention are All should remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1K are diagrams showing the construction process of a buried wafer substrate according to an embodiment of the present invention. 2 is a flow chart showing the process of constructing a buried wafer substrate of the present invention. [Main component symbol description] 100 substrate 101 first metal layer 102 second metal layer 104 third metal layer 106 first vertical conduction layer 108 semiconductor wafer 110 electrical contact 112 heat dissipation adhesive layer 1343108 114 first dielectric layer 116 a circuit layer 118 second circuit layer 120 second dielectric layer 122 third dielectric layer 124 hole 126 second vertical conduction layer 128 third circuit layer 130 third vertical conduction layer 132 fourth circuit layer 134 solder mask 136 solder

Claims (1)

1343108 ： ,1343108 : , 2010年11月30日修正替換頁Corrected replacement page on November 30, 2010 十、申請專利範圍： 1. 一種内埋晶片基板結構，其包含： 一基板’該基板具有-第-電路層、—第二電路層及—垂直導通層， 該垂直導通層用以在垂直方向電性連接該第—電路層與第二電路層之相 應電路；X. Patent application scope: 1. A buried wafer substrate structure, comprising: a substrate having a - first circuit layer, a second circuit layer and a vertical conduction layer, wherein the vertical conduction layer is used in a vertical direction Electrically connecting the corresponding circuit of the first circuit layer and the second circuit layer; 一介電層’係形成於該第-電路賴第二電路層之間，該垂直導通 層内埋於該介電層中； 一半_晶片’其位於該第-電路層與第二電路層之間朗埋於該 介電層中’該半«晶片具有-上表面及一下表面，該半導體晶片之上 表面具有複數個電性接點用以連接該第一電路層之相應電路；以及 一具有散熱效果之黏著層，其形成於該半導體晶片之下表面，且該 黏著層將該半導體晶片黏著於該第二電路層上。a dielectric layer is formed between the first circuit and the second circuit layer, the vertical conductive layer is buried in the dielectric layer; and the half-wafer is located at the first circuit layer and the second circuit layer Between the dielectric layer and the lower surface, the upper surface of the semiconductor wafer has a plurality of electrical contacts for connecting the corresponding circuits of the first circuit layer; An adhesive layer for dissipating heat is formed on a lower surface of the semiconductor wafer, and the adhesive layer adheres the semiconductor wafer to the second circuit layer. 2.如申請專利範圍第1項所述之内埋晶片基板結構，其中該第一電路層與 該垂直導通層係由銅金屬形成。 其中該第二電路層係 其中該介電層係以塗 其中該介電層厚度實 其中該垂直導通層厚 3. 如申請專利範圍第1項所述之内埋晶片基板結構 由鎳與銅金屬形成。 4. 如申請專利範圍第1項所述之内埋晶片基板結構 佈方式形成。 5. 如申請專利範圍第1項所述之内埋晶片基板結構 質上相等於該垂直導通層厚度。 6. 如申請專利範圍第1項所述之内埋晶片基板結構 12 1343108 ___ 2010年η月3〇日修正替換頁 度約為100" m。 厂二....... . 7.如申請專利範圍第1項所述之内埋晶片基板結構，其中該‘耳庠^^| 30 /z m 至 50 ν m。 8.如申請專利範圍第1項所述之内埋晶片基板結構，其中該第一電路層係 以電鍍方式形成。 9.- 種内埋晶片基板結構之製造方法，該方法包含以下步驟： 提供一具有三層金屬層之基板，該三層金屬層依序為第一金屬層、 第二金屬層與第三金屬層； 對該第一金屬層進行蝕刻以形成一第一垂直導通層， 並暴露出部份第二金屬層； 设置-半導體晶片於該第二金屬層上，該半導體晶片之上表面具有 復數個電性接點’該料體晶狀下表面具有—散絲著層，將該半導 體晶片黏著於該第二金屬層上； 形成-第-介電層覆蓋該第__垂直導通層與該半導體晶片； 平整化該第-介電層以暴露出該電性接點與該第一垂直導通層之表 面，以及 形成-第-電路層於該第-介電層上，使該半導體晶片上之電 點瓣-蝴爾職㈠败城 1〇·如申請專利範嶋_述之7 一金屬層軸蝴，陳蝴__ 為鋼金屬層。 所一贪屬層係 13 11. 如申請專利範圍第9項所述之内埋晶片基板結構之製造方法，•中’該第 一介電層係以塗佈方式形成。 12. 如申請專利範圍第9項所述之内埋晶片基板結構之製造方法，其中該第 一電路層係以電鍍方式形成。 13. 如申請專利範圍第9項所述之内埋晶片基板結構之製造方法，另包括以 下步驟： 對該第二金屬層與第三金屬層進行蝕刻以形成一第二電路層，該第 二電路層與相應之該第一垂直導通層電性連接； 分別形成一第二介電層與一第三介電層，該第二介電層覆蓋該第一 電路層，該第三介電層覆蓋該第二電路層； 分別對該第二介電層與第三介電層進行鑽孔，以暴露出該第一電路 層與該第二電路層上之相應電路； 在該第二介電層之孔洞中填入金屬以形成一第二垂直導通層，該第 二垂直導通層與該第一電路層之相應電路達成電性連接； 在該第三介電層之孔洞中填入金屬以形成一第三垂直導通層，該第 三垂直導通層與該第二電路層之相應電路達成電性連接； 形成一第三電路層於該第二介電層上，該第三電路層與該第二垂直 導通層之相應電路達成電性連接； 形成一第四電路層於該第三介電層上，該第四電路層與該第三垂直 導通層之相應電路達成電性連接； 形成一銲錫遮罩於該第三電路層之表面，以暴露出該第三電路層之 13431082. The embedded wafer substrate structure of claim 1, wherein the first circuit layer and the vertical conductive layer are formed of copper metal. Wherein the second circuit layer is characterized in that the dielectric layer is coated with a thickness of the dielectric layer, wherein the vertical conductive layer is thick. 3. The buried wafer substrate structure according to claim 1 is made of nickel and copper metal. form. 4. The embedded wafer substrate structure is formed as described in claim 1 of the patent application. 5. The embedded wafer substrate as described in claim 1 is structurally equivalent in thickness to the vertical conductive layer. 6. Buried wafer substrate structure as described in item 1 of the patent application. 12 1343108 ___ 2010 November 3rd modified replacement page degree is about 100" m. The second embodiment of the invention relates to the embedded wafer substrate structure according to the first aspect of the invention, wherein the 'ears 庠^^| 30 /z m to 50 ν m. 8. The embedded wafer substrate structure of claim 1, wherein the first circuit layer is formed by electroplating. 9. A method of fabricating a buried wafer substrate structure, the method comprising the steps of: providing a substrate having three metal layers, the first metal layer, the second metal layer and the third metal being sequentially The first metal layer is etched to form a first vertical conductive layer, and a portion of the second metal layer is exposed; and a semiconductor wafer is disposed on the second metal layer, the upper surface of the semiconductor wafer has a plurality of layers An electrical contact 'the crystalline lower surface of the material body has a -filament layer, the semiconductor wafer is adhered to the second metal layer; forming a -first dielectric layer covering the first vertical conduction layer and the semiconductor Wafering; planarizing the first dielectric layer to expose the electrical contact and the surface of the first vertical conductive layer, and forming a -first circuit layer on the first dielectric layer to make the semiconductor wafer Electric point flap - Butterfly job (a) defeated city 1 〇 · If you apply for a patent Fan _ _ 7 a metal layer shaft butterfly, Chen __ is a steel metal layer. A greedy layer system 13 11. The method of manufacturing a buried wafer substrate structure according to claim 9, wherein the first dielectric layer is formed by coating. 12. The method of fabricating a buried wafer substrate structure according to claim 9, wherein the first circuit layer is formed by electroplating. 13. The method of fabricating a buried wafer substrate structure according to claim 9, further comprising the steps of: etching the second metal layer and the third metal layer to form a second circuit layer, the second The circuit layer is electrically connected to the corresponding first vertical conductive layer; respectively forming a second dielectric layer and a third dielectric layer, the second dielectric layer covering the first circuit layer, the third dielectric layer Covering the second circuit layer; respectively drilling the second dielectric layer and the third dielectric layer to expose corresponding circuits on the first circuit layer and the second circuit layer; The holes of the layer are filled with metal to form a second vertical conduction layer, and the second vertical conduction layer is electrically connected to the corresponding circuit of the first circuit layer; the hole of the third dielectric layer is filled with metal Forming a third vertical conduction layer, the third vertical conduction layer and the corresponding circuit of the second circuit layer are electrically connected; forming a third circuit layer on the second dielectric layer, the third circuit layer and the Corresponding circuit of the second vertical conduction layer achieves electrical Forming a fourth circuit layer on the third dielectric layer, the fourth circuit layer and the corresponding circuit of the third vertical conduction layer are electrically connected; forming a solder mask on the surface of the third circuit layer To expose the third circuit layer 1343108 部份電路；以及 形成一銲錫遮罩於該第四電路層之表面，以暴露出該第四電路層之 部份電路 14. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第二介電層與第三介電層係以塗佈方式形成。 15. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第三電路層與第四電路層係以電鍍方式形成。 16. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第三電路層與第四電路層係由銅金屬形成。 17. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第二介電層與第三介電層之孔洞係以蝕刻方式形成。 18. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第二垂直導通層與第三垂直導通層係由銅金屬填入相對應之孔洞形成。a part of the circuit; and forming a solder mask on the surface of the fourth circuit layer to expose a portion of the circuit of the fourth circuit layer. 14. Manufacturing of the embedded wafer substrate structure according to claim 13 The method wherein the second dielectric layer and the third dielectric layer are formed by coating. 15. The method of fabricating a buried wafer substrate structure according to claim 13, wherein the third circuit layer and the fourth circuit layer are formed by electroplating. 16. The method of fabricating a buried wafer substrate structure according to claim 13, wherein the third circuit layer and the fourth circuit layer are formed of copper metal. 17. The method of fabricating a buried wafer substrate structure according to claim 13, wherein the holes of the second dielectric layer and the third dielectric layer are formed by etching. 18. The method of fabricating a buried wafer substrate structure according to claim 13, wherein the second vertical conductive layer and the third vertical conductive layer are formed by filling a corresponding hole with copper metal. ^9月11日费寻替換頁 19. 如申請專利範圍第13項所述之内埋晶片基板結構之製造方法，其中該 第二介電層與第三介電層之孔洞係以雷射鑽孔方式形成。 15The manufacturing method of the embedded wafer substrate structure according to claim 13 , wherein the holes of the second dielectric layer and the third dielectric layer are laser drilled The hole pattern is formed. 15
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