200834851 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種内埋主動晶片基板構造與其製法，尤其 是一種高散熱性之内埋主動晶片基板構造與其製法。 【先前技術】 近年來可攜式電子產品日益普及，例如：筆記型電腦、行 動電話、個人數位助理（Personal Digital Assistant，PDA)與數位 相機等，為了達到消費者對產品外型輕薄短小的要求，電子產 品内之相關組件皆需滿足多功能、尺寸微型化等設計要求。 就電子產品中之晶片封裝體而言，為了滿足電子產品多功 能與高速高頻運算的需求，基板上必須增加主動元件的數量， 並且在達到尺寸微型化之要求的同時，亦需具備良好的散熱能 力。如此一來，將使得晶片封裝體中之電路與元件密度增加， 進而導致電磁干擾與雜訊增加，使電子產品可靠度降低。 而習知技術之半導體封裝方法，其半導體晶片係放置在基板 之上，導致晶片封裝體的體積大小無法有效縮小，且因半導體晶 片於高速運算時會產生熱效應等問題，散熱性不佳將導致半導體 晶片的可靠度下降。因此，有必要提出一種新穎之半導體晶片封 裝結構與方法以解決上述問題。 【發明内容】 本發明之主要目的在提供一種内埋主動晶片基板結構與 其製造方法，其可提高該基板結構之散熱性與縮小該基板結構 6 200834851 之體積。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buried active wafer substrate structure and a method of fabricating the same, and more particularly to a highly heat-dissipating embedded active wafer substrate structure and a method of fabricating the same. [Prior Art] In recent years, portable electronic products have become more and more popular, such as notebook computers, mobile phones, personal digital assistants (PDAs) and digital cameras, in order to meet the requirements of consumers for thin and light products. The relevant components in the electronic product must meet the design requirements of multi-function, size miniaturization. In the case of chip packages in electronic products, in order to meet the needs of multi-function and high-speed high-frequency operation of electronic products, the number of active components must be increased on the substrate, and the requirements for miniaturization of the size must be met. Cooling capacity. As a result, the density of circuits and components in the chip package is increased, which leads to an increase in electromagnetic interference and noise, which reduces the reliability of the electronic product. In the semiconductor packaging method of the prior art, the semiconductor chip is placed on the substrate, which causes the size of the chip package to be effectively reduced, and the semiconductor chip is thermally affected during high-speed operation, and the heat dissipation is poor. The reliability of semiconductor wafers is degraded. Therefore, it is necessary to propose a novel semiconductor wafer package structure and method to solve the above problems. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a buried active wafer substrate structure and a method of fabricating the same that can improve the heat dissipation of the substrate structure and reduce the volume of the substrate structure 6 200834851.
本發明之内埋主動晶片基板構造主要包含_基板、—介電層 一半導體晶片及—具有散熱效果之黏著層。該基板具有-第—電路層/一 第二電繼-崎_，纖_树姆師峨辦 -電路層與第二電簡之相應該介電層係形成於鄕—電路層與第 二電路層之間。該半導體晶片位於該第—電路層與第二電路層之間，料 有-上表面及-下表面，該半導體晶片之上表面具有複數個電性接點: 連接該第-電路層之相應。雜絲形成於該轉體晶片之下表面， 用以將該半導體晶片黏著於該第二層上，並增加該基板構造之散熱 效果。 相較於μ技術，本發杨晶片基板構造可大幅縮 小半導體晶片封裝之體積尺寸，且具有良好之散熱效果。另外， 本發明之内埋主動晶片基板構造亦可以在各電路層之間設置額 外之半導體晶片，使本發明之結構更具產業應用之彈性。 【實施方式】 第1Α至1Κ圖為本發明之内埋晶片基板結構之製程示意圖，第2 圖則為相應之製造方法流程圖。如第u圖，首先提供一金屬基板 100，其包括一第一金屬層m、—第二金屬層1〇2與一第三金屬 層104,其中該第一銅金屬層101與第三金屬層1〇4可由銅金屬形 成，該第二金屬層102可由鎳金屬形成（步驟S2⑽）。 如第1B圖，經由蝕刻該第一金屬層1〇1形成一第一蚕直導通 層106,其厚度約為i〇0/zm，並暴露出該第二金屬層1〇2(步驟 7 200834851 S202)。 • 如第1C圖，將一半導體晶片108藉由一散熱黏著層112黏著 , 於該第二金屬層102之裸露部份，該半導體晶片108其表面具有 複數個電性接點110。該半導體晶片108厚度约為30〜50# m(步驟 S204)。 如第1D圖，以塗佈方式形成一第一介電層114覆蓋於該第一 垂直導通層106、該半導體晶片108及該第二金屬層102之裸露部 _ 份之上（步驟S206)。 如第1E圖，對該第一介電層114進行平整化（Leveling)製 .程以暴露出該半導體晶片108之電性接點110與第一垂直導通層 106之上表面。此時，該第一介電層114所剩下之厚度約等於該第一垂 直導通層106之厚度（步驟S208)。 如第1F圖，以電鍍方式形成一第一電路層116於該第一介電 層114上，該第一電路層116電性連接相應之垂直導通層106及 ® 該半導體晶片108上之電性接點110。該第一電路層116可由銅金 屬形成（步驟S210)。 請參考第1G圖，對該第二金屬層102與第三金屬層104進行蝕刻以 形成一第二電路層118,該第二電路層118與相應之第一垂直導通層106形 成電性連接。該第二電路層118形成於該半導體晶片108下表面之部 份可增加散熱之效果（步驟S212)。 如第1H圖，以塗佈方式分別形成一第二介電層120與一第三介電 8 200834851 層122 ’該第二介電層120覆蓋該第一電路層116，該第三介電層122覆蓋 該第二電路層118(步驟S214)。 如第II圖，以雷射鑽孔方式分別在該第二介電層12〇與第三介電 層122上形成複數個孔洞124，以暴露出該第一電路層ιΐ6與該第二電路層 118上之相應電路（步驟S216)。 如第ij @，在該第二介電層120之孔洞124中填入金屬以形成一第 〆爱直^η層126’該第_垂直導通層126與該第_電路層H6之相應電路 # 遠成電性連接，在該第三介電層122之孔洞124中填人金屬以形成一第三 蜜直W層m該第二垂直導通層伽與該第二電路層118之相應電路達 成電性連接。接著，形成—第三電路層128於該第二介電請上，該第 〆路層128與該弟二垂直導通層126之相應電路達成電性連接丨形成— 第四電路層132於該第=介齋 導通層說相她四軸132與該第三垂直 132可&連接’射鱗三電闕⑽與第叫路 廣132了以"鍍方式形成（步驟S218)。 # 如第1Κ圖，开^ mm 、'锡遮罩134覆蓋該第三電路層128與第四電路 慮132 5並暴路出該繁=哈 岭 '層128與第四電路層132之部份電路，且於裸 露之該第三電路層128巖 歹、稞 s22〇)。 X $ 132之部份電路上設置銲錫136(步驟 依據第2圖所示步驟§綱至 層電路結構，因該半 及，、相關說明，可構成兩 相較於先前技藝，其在片已埋人該兩層電路結構之基板中， 尺寸上已大幅縮小，且具有良好之散熱效 9 200834851 杲。再者，於步驟S216至S218中，亦可以在該第一電路層116 與第三電路層128或該第二電路層128與第四電路層132之間設 置額外之半導體晶片，使本發明之結構更具產業應用之彈性。 本發明確已符合創作專利申請之要件，爰依法提出專利申 請。惟上所述者，僅本發明之較佳實施例而已，當不能以此限定 本發明實施之範圍，故：凡依本發明申請專利範圍及創作說明書 所作之簡單的等效變化與修飾，其皆應仍屬本發明專利涵蓋之範 圍内。 【圖式簡單說明】 第1A至1〖圖係依據本發明實施例之内埋晶片基板結構製程示 意圖。 第2圖係本發明之内埋晶片基板結構製程流程圖。 【主要元件符號說明】 100 基板 101 第一金屬層 102 第二金屬層 104 第三金屬層 106 第一垂直導通層 108 半導體晶片 110 電性接點 112 散熱黏著層 200834851 114 第一介電層 ^ 116 第一電路層 . 118 第二電路層 120 第二介電層 122 第三介電層 124 孔洞 126 第二垂直導通層 _ 128 第三電路層 130 第三垂直導通層 132 第四電路層 134 銲錫遮罩 136 鲜錫 11The embedded active wafer substrate structure of the present invention mainly comprises a substrate, a dielectric layer, a semiconductor wafer, and an adhesive layer having a heat dissipation effect. The substrate has a -first circuit layer / a second electrical relay - the same circuit layer and a second electrical circuit. The dielectric layer is formed on the circuit layer and the second circuit Between the layers. The semiconductor wafer is located between the first circuit layer and the second circuit layer, and has an upper surface and a lower surface. The upper surface of the semiconductor wafer has a plurality of electrical contacts: a corresponding connection of the first circuit layer. A dummy wire is formed on the lower surface of the rotor wafer to adhere the semiconductor wafer to the second layer and to increase the heat dissipation effect of the substrate structure. Compared with the μ technology, the structure of the wafer substrate of the present invention can greatly reduce the size of the semiconductor chip package and has a good heat dissipation effect. In addition, the embedded active wafer substrate structure of the present invention can also provide additional semiconductor wafers between the circuit layers, making the structure of the present invention more flexible for industrial applications. [Embodiment] Figs. 1 to 1 are schematic views showing a process of a buried wafer substrate structure of the present invention, and Fig. 2 is a flow chart of a corresponding manufacturing method. As shown in FIG. 5, a metal substrate 100 is first provided, which includes a first metal layer m, a second metal layer 1〇2 and a third metal layer 104, wherein the first copper metal layer 101 and the third metal layer 1〇4 may be formed of copper metal, and the second metal layer 102 may be formed of nickel metal (step S2(10)). As shown in FIG. 1B, a first silkworm conductive layer 106 is formed by etching the first metal layer 1〇1 to a thickness of about i〇0/zm, and the second metal layer 1〇2 is exposed (step 7 200834851). S202). • As shown in FIG. 1C, a semiconductor wafer 108 is adhered by a heat dissipation adhesive layer 112 having a plurality of electrical contacts 110 on the surface of the exposed portion of the second metal layer 102. The semiconductor wafer 108 has a thickness of about 30 to 50 #m (step S204). As shown in FIG. 1D, a first dielectric layer 114 is formed over the first vertical via layer 106, the semiconductor wafer 108, and the bare portion of the second metal layer 102 by coating (step S206). As shown in FIG. 1E, the first dielectric layer 114 is leveled to expose the electrical contacts 110 of the semiconductor wafer 108 and the upper surface of the first vertical via layer 106. At this time, the thickness of the first dielectric layer 114 is approximately equal to the thickness of the first vertical conductive layer 106 (step S208). As shown in FIG. 1F, a first circuit layer 116 is formed on the first dielectric layer 114 by electroplating, and the first circuit layer 116 is electrically connected to the corresponding vertical conduction layer 106 and the electrical property on the semiconductor wafer 108. Contact 110. The first circuit layer 116 may be formed of copper metal (step S210). Referring to FIG. 1G, the second metal layer 102 and the third metal layer 104 are etched to form a second circuit layer 118. The second circuit layer 118 is electrically connected to the corresponding first vertical conductive layer 106. The portion of the second circuit layer 118 formed on the lower surface of the semiconductor wafer 108 can increase the effect of heat dissipation (step S212). As shown in FIG. 1H, a second dielectric layer 120 and a third dielectric layer 8 200834851 layer 122 are formed by coating, and the second dielectric layer 120 covers the first circuit layer 116. The third dielectric layer 122 covers the second circuit layer 118 (step S214). As shown in FIG. 2, a plurality of holes 124 are formed in the second dielectric layer 12 and the third dielectric layer 122 by laser drilling to expose the first circuit layer ι6 and the second circuit layer. The corresponding circuit on 118 (step S216). For example, in the ij @, the hole 124 of the second dielectric layer 120 is filled with metal to form a first 〆 直 layer 126 ′ the first vertical conduction layer 126 and the corresponding circuit of the _ circuit layer H6. The metal is filled in the hole 124 of the third dielectric layer 122 to form a third honey straight W layer. The second vertical conductive layer 380 is electrically connected to the corresponding circuit of the second circuit layer 118. Sexual connection. Then, a third circuit layer 128 is formed on the second dielectric layer, and the third circuit layer 128 is electrically connected to the corresponding circuit of the second vertical conduction layer 126. The fourth circuit layer 132 is formed in the first circuit layer 132. = Jie Zhai conduction layer said that her four axes 132 and the third vertical 132 can be & connected 'square three electric sputum (10) and the first road wide 132 formed by " plating method (step S218). #如第一图, open ^ mm, 'tin mask 134 covers the third circuit layer 128 and the fourth circuit considers 132 5 and violently exits the portion of the complex = haling' layer 128 and the fourth circuit layer 132 The circuit is exposed to the third circuit layer 128, 歹2222). Solder 136 is disposed on part of the circuit of X $ 132 (the steps are based on the step § to the layer circuit structure shown in Figure 2, because the half and the related descriptions can constitute two phases compared to the prior art, which is buried in the film In the substrate of the two-layer circuit structure, the size has been greatly reduced, and the heat dissipation effect is good. 9 200834851 再 In addition, in steps S216 to S218, the first circuit layer 116 and the third circuit layer may also be used. 128 or an additional semiconductor wafer is disposed between the second circuit layer 128 and the fourth circuit layer 132, so that the structure of the present invention is more flexible in industrial application. The invention has indeed met the requirements of the patent application, and the patent application is filed according to law. The foregoing is a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. All of them should still be within the scope of the present invention. [Simplified Schematic Description] FIGS. 1A to 1 are schematic diagrams showing the structure of a buried wafer substrate according to an embodiment of the present invention. FIG. 2 is a view of the present invention. Flow chart of the structure of the embedded wafer substrate structure [Description of main component symbols] 100 substrate 101 first metal layer 102 second metal layer 104 third metal layer 106 first vertical conduction layer 108 semiconductor wafer 110 electrical contact 112 heat dissipation Layer 200834851 114 first dielectric layer ^ 116 first circuit layer. 118 second circuit layer 120 second dielectric layer 122 third dielectric layer 124 hole 126 second vertical conduction layer _ 128 third circuit layer 130 third vertical Conduction layer 132 fourth circuit layer 134 solder mask 136 fresh tin 11